Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing an initial substrate having an etching hard mask and a planarization material layer on the etching hard mask; performing a photolithography process on the planarization material layer to form a patterned planarization layer; etching the etching hard mask using the patterned planarization layer as a mask to form a patterned etching hard mask layer; and etching the initial substrate using the patterned etching hard mask layer as a mask to form a target pattern. This approach can improve the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are widely used; therefore, as the density and integration of semiconductor devices increase, the feature size of transistors is also becoming smaller and smaller.

[0003] Photolithography is a commonly used patterning method and one of the most critical technologies in semiconductor manufacturing. With the continuous miniaturization of semiconductor process nodes, self-aligned multiple patterning (SAMP) has become a favored patterning method in recent years. It involves depositing material on both sides of a pre-defined pattern to form sidewalls, and then using sidewall image transfer technology to transfer the pattern. This method can increase the pattern density formed on the wafer surface and further reduce the pitch between adjacent patterns, thus enabling the fabrication of small-sized patterns. This technology is commonly used for line / space formation. Specifically, SADP (Self-aligned Double Patterning) can increase the pattern density by 2 times, and SAQP (Self-aligned Quadruple Patterning) can increase the density by 4 times. SAMP requires only one photolithography step, eliminating mask position errors caused by multiple photolithography steps and offering significant cost advantages. Currently, this technology is widely used in 10nm-level process technology.

[0004] However, existing semiconductor structures still suffer from poor performance. Summary of the Invention

[0005] The problem solved by this invention is to provide a method for forming a semiconductor structure to improve the photolithography process window, thereby further improving the device density and structural performance of the formed semiconductor.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] An initial substrate is provided, on which an etched hard mask and a planarization material layer are located;

[0008] A photolithography process is performed on the planarization material layer to form a patterned planarization layer;

[0009] The patterned planarization layer is used as a mask to etch the etch hard mask, forming a patterned etch hard mask layer;

[0010] The initial substrate is etched using the patterned etch hard mask layer as a mask to form the target pattern.

[0011] Optionally, before forming the patterned planarization layer, the method further includes: performing a material modification process on a portion of the planarization material layer to form a retained area of ​​the planarization material layer, wherein the planarization material layer located on the side of the retained area is a non-retained area; after forming the patterned planarization layer, the method further includes removing the planarization layer corresponding to the non-retained area to form the patterned planarization layer.

[0012] Optionally, the step of performing a material modification process on a portion of the planarized material layer includes:

[0013] A first spin-coated material layer is formed on the planarized material layer;

[0014] A first anti-reflection coating (ARC) layer is formed on the first spin-coated material layer;

[0015] A patterned mask layer is formed on the first antireflective material layer;

[0016] The first antireflective material layer and the first spin-coated material layer are sequentially etched using the patterned mask layer to form a patterned first antireflective layer and a first spin-coated layer;

[0017] A material modification process is performed on the planarization material layer using a patterned first swirl coating, a first anti-reflection layer, and a first mask layer as masks to form a retained area of ​​the planarization material layer;

[0018] After performing the material modification process, the patterned first swirl coating, first anti-reflective layer and first mask layer are removed.

[0019] Optionally, the material modification process includes an ion implantation process.

[0020] Optionally, the step of forming a patterned planarization layer includes:

[0021] After performing a material modification process on a portion of the planarization material layer, a bottom mandrel material layer and a plurality of discrete first mandrel layers located on the bottom mandrel material layer are formed on the planarization material layer;

[0022] A first sidewall mask layer is formed to cover the sidewall of the first mandrel layer;

[0023] Remove the first mandrel layer and etch the bottom mandrel material layer using the first sidewall mask layer as a mask to form multiple discrete second mandrel layers;

[0024] Remove the first sidewall mask layer;

[0025] A second sidewall mask layer is formed to cover the sidewall of the second core layer;

[0026] Remove the second core layer and etch the planarization material layer using the second sidewall mask layer as a mask to form a patterned planarization layer;

[0027] Remove the masking layer from the second sidewall.

[0028] Optionally, before forming the bottom mandrel material layer on the planarization material layer, the method further includes forming a first etched hard mask on the planarization material layer.

[0029] Optionally, the material of the first etched hard mask is silicon oxide.

[0030] Optionally, prior to the plurality of discrete first mandrel layers on the bottom mandrel material layer, the method further includes forming a second etched hard mask on the bottom mandrel material layer.

[0031] Optionally, the material of the second etched hard mask is silicon oxide.

[0032] Optionally, the process for removing the planarization layer corresponding to the non-retained areas is a wet etching process.

[0033] Optionally, the dimensions of each of the reserved regions may be the same or different in the fin width direction.

[0034] Optionally, a buffer material layer is also formed between the initial substrate and the etched hard mask.

[0035] Optionally, the planarization material layer is made of amorphous silicon.

[0036] Optionally, the material of the etched hard mask is silicon nitride.

[0037] This invention also provides a semiconductor structure, the semiconductor structure comprising:

[0038] Initial base;

[0039] The initial substrate has an etched hard mask;

[0040] A planarization material layer located on the etched hard mask;

[0041] Multiple discrete second mandrel layers are located on the planarization material layer.

[0042] Optionally, the planarization material layer is made of amorphous silicon.

[0043] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0044] The above-described scheme involves providing an initial substrate with an etch hard mask and a planarization material layer on the etch hard mask; performing photolithography on the planarization material layer to form a patterned planarization layer; etching the etch hard mask using the patterned planarization layer as a mask to form a patterned etch hard mask layer; and etching the initial substrate using the patterned etch hard mask layer as a mask to form the target pattern. Since the planarization material layer is formed on the etch hard mask after it is formed on the initial substrate, the subsequent patterning process of the mask layer can be performed on the planarization material layer with a flat surface. This eliminates the pattern loading effect, increases the photolithography process window, and further improves the density and structural performance of the formed semiconductor device. Attached Figure Description

[0045] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0046] Figures 2 to 15 This is a schematic diagram of the intermediate structure formed by each step of a semiconductor structure formation method in an embodiment of the present invention. Detailed Implementation

[0047] In the back-end of line (BEOL) process of FinFET, self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) is generally used to form the substrate and the discrete fins on the substrate.

[0048] However, in existing self-aligned double patterning or self-aligned quadruple patterning processes, the patterning of the mask layer is performed on a non-planar surface, and the resulting loading effect reduces the performance of the formed semiconductor structure.

[0049] To address the aforementioned issues, the technical method provided in this embodiment of the invention forms a planarization material layer on the etched hard mask after forming an etched hard mask on the initial substrate. This allows the subsequent patterning process of the mask layer to be performed on a flat surface, thereby eliminating the loading effect and improving the performance of the formed semiconductor structure.

[0050] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention is shown. See also... Figure 1 A method for forming a semiconductor structure according to an embodiment of the present invention may specifically include:

[0051] Step S101: Provide an initial substrate having an etched hard mask and a planarization material layer on the etched hard mask;

[0052] Step S102: Perform a photolithography process on the planarization material layer to form a patterned planarization layer;

[0053] Step S103: Etch the etch hard mask using the patterned planarization layer as a mask to form a patterned etch hard mask layer;

[0054] Step S104: Etch the initial substrate using the patterned etched hard mask layer as a mask to form the target pattern.

[0055] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] The following will combine Figures 2 to 15 A method for forming a semiconductor structure according to an embodiment of the present invention will be described in further detail.

[0057] See Figure 2 Provide an initial base of 100.

[0058] In a specific implementation, the initial substrate 100 is used for subsequent etching to form a substrate and fins located on the substrate.

[0059] In this embodiment, the initial substrate 100 is made of silicon. In other embodiments, the initial substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The initial substrate may also be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, or other types of substrates. In still other embodiments, the initial substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer. The first semiconductor layer provides a process foundation for subsequent substrate formation, and the second semiconductor layer provides a process foundation for subsequent fin formation. In other embodiments, the initial substrate may also include other functional layers to be etched, such as a gate material layer.

[0060] See Figure 3 An etched hard mask 110 and a planarization material layer 120 are formed on the initial substrate 100.

[0061] The etching hard mask 110 is used to subsequently form an etching mask for etching the initial substrate 100 to form the target pattern.

[0062] In this embodiment, the material of the etching hard mask 110 is silicon nitride (SiN). In other embodiments, the material of the etching hard mask 110 may also be silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonide (SiOCN), or a combination thereof.

[0063] The process for forming the etched hard mask 110 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal treatment, or combinations thereof.

[0064] The planarization material layer 120 is used to provide a process basis for the subsequent formation of the planarization layer.

[0065] In this embodiment, the planarization material layer 120 is made of amorphous silicon.

[0066] The process for forming the planarization material layer 120 can be atomic layer deposition, chemical vapor deposition, or physical vapor deposition, etc.

[0067] In this embodiment, before forming the etch hard mask 110 on the initial substrate 100, a buffer material layer 105 is formed on the initial substrate 100. The buffer material layer 105 provides a buffering effect during the formation of the etch hard mask 110, which can enhance the adhesion between the initial substrate 100 and the etch hard mask 110, thus avoiding the problem of misalignment when the etch hard mask 110 is formed directly on the initial substrate 100.

[0068] In this embodiment, the material of the buffer material layer 105 is silicon oxide.

[0069] In this embodiment, before forming the planarization material layer 120 on the etch hard mask 110, a step of forming a bottom etch hard mask 111 on the etch hard mask 110 is included. The bottom etch hard mask 111 serves as an etch mask for the etch hard mask 110 and can also provide a buffering effect during the formation of the etch hard mask 110, thereby enhancing the adhesion between the etch hard mask 110 and the planarization material layer 120. Therefore, it can avoid the problem of misalignment when the planarization material layer 120 is formed directly on the etch hard mask 110.

[0070] See Figure 4 A material modification process is performed on a portion of the planarization material layer 120 to form a retained area I of the planarization material layer, and a non-retained area II of the planarization material layer located on the side of the retained area I.

[0071] In this embodiment, the material modification process is an ion implantation process, and the material of the planarization layer 120 is amorphous silicon. Specifically, the ion implantation process can increase the etching selectivity of the ion-implanted regions in the amorphous silicon, so that after the subsequent formation of the patterned planarization layer, the ion-implanted regions in the amorphous silicon can be retained, while the non-ion-implanted regions in the amorphous silicon can be removed.

[0072] In this embodiment, the material of the planarization material layer 120 is amorphous silicon (a-Si).

[0073] The steps of performing a material ion implantation process on a portion of the planarization material layer 120 include: forming a first spin-on coating material layer (not shown in the figure) covering the planarization material layer 120, a first silicon-based anti-reflection coating (Si-ARC) material layer (not shown in the figure) located on the first spin-on coating material layer, and a patterned first mask layer (not shown in the figure) located on the first Si-ARC layer; sequentially etching the first Si-ARC material layer and the first spin-on coating material layer using the patterned first mask layer as a mask to form a patterned first Si-ARC layer and the first spin-on coating layer; performing an ion implantation process on the planarization material layer 120 using the patterned first mask layer, the first Si-ARC layer, and the first spin-on coating layer as masks to form a retained region I of the planarization material layer 120, and a non-retained region II of the planarization material layer 120 that is not subjected to the ion implantation process.

[0074] In this embodiment, the first spin-coated material layer is a spin-on carbon (SOC) material layer.

[0075] It is understood that when performing an ion implantation process on the planarization material layer 120, the number of target patterns (such as fins) formed on each retained region I can be controlled by controlling the size of each retained region I formed in the planarization material layer 120. Therefore, the size of each retained region I in the embodiments of the present invention can be adjusted according to the number of target patterns finally formed, thereby creating target patterns with different degrees of sparseness in the initial substrate corresponding to each retained region I.

[0076] In other embodiments, after forming an etched hard mask and a planarization material layer on the initial substrate, a photolithography process can be directly performed on the planarization material layer to form a patterned planarization layer, without prior material modification of the planarization material layer to form a target pattern with uniform pattern density by etching the initial substrate.

[0077] By forming a planarization material layer 120 on the etched hard mask 110, the film layer formed on the planarization material layer 120 can be formed on the planarization material layer with a flat surface during the subsequent patterning of the planarization material layer 120 to form a patterned planarization layer. This can improve the flatness of the surface of the film layer formed thereon, thereby eliminating the loading effect and improving the morphological quality and dimensional accuracy of the film layer formed on the planarization material layer 120 during the semiconductor structure formation process, thereby improving the performance of the formed semiconductor structure.

[0078] After performing a material modification process on a portion of the planarization material layer 120, a photolithography process is performed on the reserved region I and the non-reserved region II in the planarization material layer 120 to form a patterned planarization layer.

[0079] Figures 5 to 13 This diagram illustrates an intermediate structure formed during the steps of forming a patterned planarization layer according to an embodiment of the present invention. See also... Figures 5 to 13 The steps for forming a patterned planarization layer include:

[0080] See Figure 5 A bottom mandrel material layer 130 is formed on the planarization material layer 120.

[0081] The bottom mandrel material layer 130 provides a process basis for the subsequent formation of a patterned second mandrel layer. The second sidewall mask layer, subsequently formed on the sidewall of the second mandrel layer, serves as a mask for patterning the etched hard mask 110.

[0082] After forming the second sidewall mask layer located on the sidewall of the second core layer, the second core layer also needs to be removed. Therefore, the bottom core material layer 130 is an easily removable material, and the process of removing the second core layer causes minimal damage to other film layers. In this embodiment, the material of the bottom core material layer 130 is amorphous silicon. In other embodiments, the material of the bottom core material layer is silicon nitride. In other embodiments, the material of the bottom core material layer may also be amorphous carbon, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride, silicon carbonitride, or a combination thereof. In other embodiments, the material of the bottom core material layer may also be an organic dielectric layer (ODL) material.

[0083] The process for forming the bottom core material layer 130 can be atomic layer deposition, chemical vapor deposition, or physical vapor deposition, etc.

[0084] In this embodiment, before forming the bottom mandrel material layer 130, the method further includes forming a first etch hard mask 121 on the planarization material layer 120.

[0085] The first etch hard mask 121 is used as an etch mask for subsequent etching of the planarization material layer 120, and can provide a buffer for the bottom mandrel material layer 130 subsequently formed on the first etch hard mask 121.

[0086] In this embodiment, the material of the first etched hard mask 121 is silicon dioxide.

[0087] The process for forming the first etched hard mask 121 is atomic layer deposition, chemical vapor deposition, or atomic layer deposition, etc.

[0088] In this embodiment, after forming the bottom mandrel material layer 130, the step of forming a second etch hard mask 131 on the bottom mandrel material layer 130 is further included.

[0089] The second etch hard mask 131 serves as an etch mask for subsequent etching of the bottom mandrel material layer 130, and can provide a buffer for the top mandrel material layer subsequently formed thereon.

[0090] In this embodiment, the material of the second etching hard mask 131 is silicon dioxide.

[0091] The process for forming the second etched hard mask 131 is atomic layer deposition, chemical vapor deposition, or atomic layer deposition, etc.

[0092] See Figure 6 A plurality of discrete first mandrel layers 140 are formed on the bottom mandrel material layer 130.

[0093] The step of forming multiple discrete first mandrel layers 140 includes: forming a top mandrel material layer on a bottom mandrel material layer 130; forming a second spin-coating material layer (not shown in the figure) covering the top mandrel material layer; a second Si-ARC material layer (not shown in the figure) located on the second spin-coating material layer; and a patterned second mask layer (not shown in the figure) located on the second Si-ARC layer; sequentially etching the second Si-ARC material layer and the second spin-coating material layer using the patterned second mask layer as a mask to form a patterned second Si-ARC layer and a second spin-coating layer; etching the top mandrel material layer using the patterned second mask layer, the second Si-ARC layer, and the second spin-coating layer as masks to form multiple discrete first mandrel layers 140 on the bottom mandrel material layer 130; and removing the patterned second mask layer, the second Si-ARC layer, and the second spin-coating layer after forming the first mandrel layers 140.

[0094] In this embodiment, the material of the second spin-coated material layer is SOC.

[0095] The top mandrel material layer provides the process basis for subsequent etching to form the first mandrel layer. The first sidewall mask layer, which forms the sidewalls of the first mandrel layer, provides the process basis for etching the bottom mandrel material layer 130.

[0096] After forming the second sidewall mask layer located on the sidewall of the first mandrel layer 140, the first mandrel layer 140 also needs to be removed. Therefore, the top mandrel material layer is an easily removable material, and the process of removing the first mandrel layer 140 causes minimal damage to other film layers. In this embodiment, the material of the top mandrel material layer is amorphous silicon. In other embodiments, the material of the top mandrel material layer is silicon nitride. In other embodiments, the material of the top mandrel material layer may also be amorphous carbon, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride, silicon carbonitride, or organic dielectric layer (ODL) materials.

[0097] The process for forming the top core material layer includes atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0098] See Figure 7 A first sidewall mask layer 145 is formed covering the sidewall of the first core layer 140.

[0099] The first sidewall mask layer 145 serves as a mask for subsequent patterning of the bottom mandrel material layer 130.

[0100] The step of forming the first sidewall mask layer 145 includes: forming a first sidewall mask material layer (not shown) that conformally covers the bottom mandrel material layer 130 and the first mandrel layer 140; removing the first sidewall mask material layer covering the bottom mandrel material layer 130 and the first sidewall mask material layer covering the top of the first mandrel layer 140, and retaining only the first sidewall mask material layer covering the sidewall of the first mandrel layer 140 as the first sidewall mask layer 145.

[0101] In this embodiment, to improve the uniformity of the thickness of the first sidewall mask material layer and reduce the difficulty of controlling its thickness, an atomic layer deposition process is used to form the first sidewall mask material layer. In other embodiments, the first sidewall mask material layer can also be formed using a chemical vapor deposition process.

[0102] In this embodiment, the material of the first sidewall mask layer 145 is silicon nitride. Silicon nitride is a commonly used sidewall mask material in SADP processes. Silicon nitride has high hardness and density, and the etching selectivity between silicon nitride and amorphous silicon is relatively large, which can reduce the probability of damage to the first sidewall mask layer 145 during the subsequent removal of the first core layer 140.

[0103] In this embodiment, when a second etched hard mask 131 is also formed on the bottom mandrel material layer 130, the first sidewall mask material layer conformally covers the second etched hard mask 131 and the first mandrel layer 140.

[0104] In this embodiment, an anisotropic blanket dry etch process is used to selectively etch the first sidewall mask material layer along the normal direction of the initial substrate 100 surface, thereby forming the first sidewall mask layer 145 on the sidewall of the first mandrel layer 140.

[0105] See Figure 8 After forming the first sidewall mask layer 145, the first core layer 140 is removed.

[0106] The first mandrel layer 140 is removed to provide a process basis for the subsequent patterning of the bottom mandrel material layer 130.

[0107] In this embodiment, a wet etching process is used to remove the first core layer 140. Specifically, the material of the first core layer 140 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH (Tetra-Methyl Ammonium Hydroxide) solution. In other embodiments, a dry etching process, or a combination of dry and wet etching, can also be used to remove the first core layer 140.

[0108] See Figure 9 The bottom mandrel material layer 130 and multiple discrete second mandrel layers 135 are etched using the first sidewall mask layer 145 as a mask.

[0109] The second mandrel layer 135 provides a base for the subsequent formation of the second sidewall mask layer. In subsequent processes, the second sidewall mask layer is formed on the sidewall of the second mandrel layer 135, and the second sidewall mask layer is used as a patterning material layer 120 to form a patterned planarization layer.

[0110] In this embodiment, the material of the second core layer 135 is amorphous silicon.

[0111] In this embodiment, a second etch hard mask 131 is formed on the bottom core material layer 130 along the direction from the initial substrate 100 to the bottom core material layer 130. Therefore, using the first sidewall mask layer 145 as a mask, the second etch hard mask 131 and the bottom core material layer 130 are etched sequentially using a dry etching process to form a patterned second etch hard mask layer (not shown) and a second core layer 135.

[0112] After forming multiple discrete second core layers 135, the process also includes the step of removing the first sidewall mask layer 145.

[0113] When a second etched hard mask 131 is formed on the bottom mandrel material layer 130, after removing the first sidewall mask layer 145, the step of removing the patterned second etched hard mask layer is also included.

[0114] See Figure 10 A second sidewall mask layer 155 is formed on the sidewall of the second core layer 135.

[0115] The second sidewall mask layer 155 serves as a mask for patterning the planarization material layer 120.

[0116] In this embodiment, the material of the second sidewall mask layer 155 is silicon nitride. A description of the material of the second sidewall mask layer 155 can be found in the preceding description of the first sidewall mask layer 135, and will not be repeated here.

[0117] Specifically, the step of forming the second sidewall mask layer 155 includes: forming a second sidewall mask material layer that conformally covers the second mandrel layer 135 and the planarization material layer 120; removing the second sidewall mask material layer on the top of the second mandrel layer 135 and the planarization material layer 120 using a maskless etching process, and retaining the remaining second sidewall mask material layer on the sidewall of the second mandrel layer 135 as the second sidewall mask layer 155.

[0118] For a detailed description of the steps for forming the second sidewall mask layer 155, please refer to the aforementioned description of forming the first mask sidewall 135, which will not be repeated here.

[0119] See Figure 11 After forming the second sidewall mask layer 155, the second mandrel layer 135 is removed.

[0120] Removing the second mandrel layer 135 provides a process basis for forming the planarization material layer 120 in subsequent drawings.

[0121] In this embodiment, a wet etching process is used to remove the second mandrel layer 135. For a detailed description of the process for removing the second mandrel layer 135, please refer to the corresponding description of the removal of the first mandrel layer 140, which will not be repeated here.

[0122] See Figure 12 The planarization material layer 120 is etched using the second sidewall mask layer 155 as a mask to form a patterned planarization layer 125.

[0123] The planarization layer 125 provides the process basis for patterning the etched hard mask 110.

[0124] The process for forming the patterned planarization layer 125 is a dry etching process. Specifically, using the second sidewall mask layer 155 as a mask, the first etched hard mask 121 and the planarization material layer 120 are sequentially etched using a dry etching process to form a patterned first etched hard mask layer (not shown) and planarization layer 125.

[0125] After forming the patterned planarization layer 125, the process further includes removing the second sidewall mask layer 155 and the first etched hard mask layer. In this embodiment, a wet etching process is used to etch and remove the second sidewall mask layer 155 and the remaining first etched hard mask layer. In other embodiments, a dry etching process can also be used to etch and remove the second sidewall mask layer 155 and the first etched hard mask layer.

[0126] See Figure 13 After forming a patterned planarization layer 125, the planarization layer 125 corresponding to the non-retained region II is removed to form a patterned planarization layer 126.

[0127] The planarization layer 126 provides a process basis for the patterned etching hard mask 110.

[0128] In this embodiment, the process for removing the planarization layer 125 corresponding to the non-retained region II is a wet etching process.

[0129] Since the planarization layer corresponding to the retained region I in the patterned planarization layer 125 has undergone a material modification process, the wet etching process has a higher etching selectivity rate for the planarization layer 125 corresponding to the retained region I than for the planarization layer 125 corresponding to the non-retained region II. This allows for the rapid removal of the planarization layer 125 corresponding to the non-retained region II, while having less impact on the planarization layer 125 corresponding to the retained region I. This helps maintain the morphological quality of the planarization layer 125 corresponding to the retained region I, thereby improving the morphological quality of the formed target pattern.

[0130] It should be noted that the number of discrete planarization layers 126 in the planarization layer 125 corresponding to each retained region I may be the same or at least partially different. This can be controlled by the size of each retained region I formed when performing a material modification process on a portion of the planarization material layer 120, and is not limited here.

[0131] As can be seen from the above description, before the patterned planarization layer 126 is formed, that is, during the process of forming the patterned planarization layer 125, the pattern density of the corresponding film layer is uniform. Therefore, the loading effect caused by the uneven pattern density can be eliminated, thus improving the pattern quality of the corresponding film layer, thereby improving the quality of the final semiconductor structure.

[0132] See Figure 14 The patterned planar layer 126 is used as a mask to etch the etch hard mask 110 to form a patterned etch hard mask layer 115.

[0133] The process for forming the patterned etched hard mask layer 115 is a dry etching process. Specifically, using the patterned planarization layer 126 as a mask, the bottom etched hard mask 111 and the etched hard mask 110 are sequentially etched using a dry etching process to form the patterned etched hard mask layer 111' and the etched hard mask layer 110'.

[0134] See Figure 15 The initial substrate 100 is etched using the patterned etched hard mask layer 111' as a mask to form the target pattern 101.

[0135] In this embodiment, after patterning the initial substrate 100, the remaining initial substrate 100 is used as a substrate 102, the target pattern 102 is a fin, and the fin 101 and the substrate 102 are an integral structure.

[0136] The process for forming the target pattern 101 is a dry etching process. Specifically, using the patterned etched hard mask layer 111' and the etched hard mask layer 110' as masks, the buffer material layer 105 and the initial substrate 100 are sequentially etched using a dry etching process to form the patterned buffer layer 105' and the fin 101, and the remaining initial substrate 100 is used as a substrate 102.

[0137] In other embodiments, when the initial substrate includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the first semiconductor layer is etched. The first semiconductor layer serves as a substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer serves as a fin. Accordingly, the material of the fin can also be different from the material of the substrate.

[0138] Accordingly, embodiments of the present invention also provide a semiconductor structure.

[0139] Please continue reading Figure 11 The semiconductor structure includes: an initial substrate 100; an etched hard mask 105 on the initial substrate; a planarization material layer 120 on the etched hard mask; and a plurality of discrete second core layers 155 on the planarization material layer.

[0140] In this embodiment, the material of the planarization material layer 120 is amorphous silicon.

[0141] In this embodiment, the planarization material layer 120 has a reserved region I and a non-reserved region II located on the side of the reserved region I.

[0142] It is understood that by controlling the size of the retained regions I formed in the planarization material layer 120, the number of target patterns (such as fins) formed on each retained region I can be controlled. Therefore, the size of each retained region I in the embodiments of the present invention can be adjusted according to the number of target patterns finally formed, thereby creating target patterns with different degrees of sparseness in the initial substrate corresponding to each retained region I.

[0143] In other embodiments, the planarization material layer may also have neither reserved nor unreserved regions, in order to form a target pattern with uniform pattern density in a subsequent process by etching the initial substrate.

[0144] In this embodiment, a buffer material layer 105 is further provided between the initial substrate 100 and the etch hard mask 110. The buffer material layer 105 is used to provide a buffering effect when forming the etch hard mask 110, which can enhance the adhesion between the initial substrate 100 and the etch hard mask 110, thus avoiding the problem of misalignment when the etch hard mask 110 is formed directly on the initial substrate 100.

[0145] In this embodiment, a bottom etching hard mask 111 is also provided between the etching hard mask 110 and the planarization material layer 120. The bottom etching hard mask 111 serves as an etching mask for the etching hard mask 110 and can also provide a buffering effect when forming the etching hard mask 110. It can enhance the adhesion between the etching hard mask 110 and the planarization material layer 120, thus avoiding the problem of misalignment when the planarization material layer 120 is formed directly on the etching hard mask 110.

[0146] In this embodiment, a first etch hard mask 121 is also provided between the planarization material layer 120 and the plurality of discrete second mandrel layers 155. The first etch hard mask 121 is used as an etch mask for subsequent etching of the planarization material layer 120, and can provide a buffering effect for the bottom mandrel material layer 130 subsequently formed on the first etch hard mask 121.

[0147] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial substrate is provided, on which an etched hard mask and a planarization material layer are located; A material modification process is performed on a portion of the planarization material layer to form a retained area of ​​the planarization material layer, and the planarization material layer located on the side of the retained area is a non-retained area; A photolithography process is performed on the planarization material layer to form a patterned planarization layer, wherein the step of forming the patterned planarization layer includes: After performing a material modification process on a portion of the planarization material layer, a bottom mandrel material layer and a plurality of discrete first mandrel layers located on the bottom mandrel material layer are formed on the planarization material layer; A first sidewall mask layer is formed to cover the sidewall of the first mandrel layer; Remove the first mandrel layer and etch the bottom mandrel material layer using the first sidewall mask layer as a mask to form multiple discrete second mandrel layers; Remove the first sidewall mask layer; A second sidewall mask layer is formed to cover the sidewall of the second core layer; Remove the second core layer and etch the planarization material layer using the second sidewall mask layer as a mask to form a patterned planarization layer; Remove the masking layer from the second sidewall; Remove the planarization layer corresponding to the non-preserved areas to form a patterned planarization layer; The patterned planar layer is used as a mask to etch the etch hard mask, forming a patterned etch hard mask layer; The initial substrate is etched using the patterned etch hard mask layer as a mask to form the target pattern.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps of performing a material modification process on a portion of the planarized material layer include: A first spin-coated material layer is formed on the planarized material layer; A first antireflective material layer is formed on the first spin-coated material layer; A patterned mask layer is formed on the first antireflective material layer; The first antireflective material layer and the first spin-coated material layer are sequentially etched using the patterned mask layer to form a patterned first antireflective layer and a first spin-coated layer; A material modification process is performed on the planarization material layer using a patterned first swirl coating, a first anti-reflection layer, and a first mask layer as masks to form a retained area of ​​the planarization material layer; After performing the material modification process, the patterned first swirl coating, first anti-reflective layer and first mask layer are removed.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The material modification process includes ion implantation.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The process for removing the planarization layer corresponding to the non-retained areas is a wet etching process.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, A buffer material layer is also formed between the initial substrate and the etched hard mask.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the planarization layer is amorphous silicon.

7. The semiconductor structure formed by the method according to claim 1, characterized in that, include: Initial base; The initial substrate has an etched hard mask; A planarization material layer is located on the etched hard mask, the planarization material layer having a reserved region and a non-reserved region located on the side of the reserved region; Multiple discrete second mandrel layers are located on the planarization material layer.

8. The semiconductor structure according to claim 7, characterized in that, The material of the planarization layer is amorphous silicon.

Images