Method for manufacturing connection hole, semiconductor device, memory and manufacturing method

Abstract

Embodiments of the present application disclose a method for manufacturing a connection hole, a semiconductor device, a memory and a manufacturing method. The method comprises: providing a conductive layer and an insulating layer on the conductive layer; sequentially forming a plurality of intermediate layers and a mask layer on the insulating layer, the mask layer having an opening, and the materials of any two adjacent intermediate layers being different; sequentially forming a via in the plurality of intermediate layers through the opening, and removing the film layer on the intermediate layer where the via is formed after forming each via; forming a connection hole in the insulating layer through the via; and the sizes of the opening, the via and the connection hole are sequentially reduced. The embodiments of the present application can reduce the size of the connection hole, and further reduce the volume of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a connection hole, a semiconductor device, a memory, and a method for fabricating the same. Background Technology

[0002] Currently, the method for fabricating connector holes involves forming a mask layer on an insulating layer, and then etching the connector hole through an opening in the mask layer within the insulating layer. However, due to process limitations, the size of the opening in the mask layer is difficult to further reduce, which in turn makes it difficult to further reduce the size of the resulting connector hole. Summary of the Invention

[0003] This invention provides a method for manufacturing a connector hole, a semiconductor device, a memory, and a manufacturing method thereof, which can reduce the size of the connector hole and thus reduce the volume of the semiconductor device.

[0004] This invention provides a method for manufacturing a connecting hole, comprising:

[0005] A conductive layer is provided, and an insulating layer is located on the conductive layer;

[0006] A plurality of intermediate layers and a mask layer are sequentially formed on the insulating layer, the mask layer having an opening; any two adjacent intermediate layers are made of different materials;

[0007] Through the opening, through holes are sequentially formed in the plurality of intermediate layers, and after each through hole is formed, the film layer on the intermediate layer where the through hole is located is removed.

[0008] A connection hole is formed in the insulating layer through the through hole; the size of the opening, the through hole, and the connection hole decreases in sequence.

[0009] Furthermore, the size of the connecting hole is smaller than a preset size.

[0010] Furthermore, the thickness of each of the intermediate layers is less than or equal to a preset thickness; in the direction from the mask layer toward the insulating layer, the thickness of the plurality of intermediate layers gradually increases, or the thickness of the plurality of intermediate layers is the same.

[0011] Furthermore, the smaller the size of the connecting hole, the more intermediate layers there are.

[0012] Furthermore, the plurality of intermediate layers includes a first intermediate layer, a second intermediate layer, and a third intermediate layer located sequentially between the mask layer and the insulating layer;

[0013] The step of sequentially forming through-holes in the plurality of intermediate layers through the opening, and removing the film layer on the intermediate layer where the through-hole is located when forming each through-hole, includes:

[0014] A first through-hole is formed in the first intermediate layer through the opening, and the mask layer is removed;

[0015] A second through-hole is formed in the second intermediate layer through the first through-hole, and the first intermediate layer is removed;

[0016] A third through-hole is formed in the third intermediate layer through the second through-hole, and the second intermediate layer is removed.

[0017] Furthermore, the first intermediate layer is made of the same material as the third intermediate layer, and the second through-hole includes a first sub-hole and a second sub-hole;

[0018] The step of forming a second through-hole in the second intermediate layer through the first through-hole and removing the first intermediate layer includes:

[0019] The first sub-hole is formed in the second intermediate layer through the first through-hole;

[0020] Remove the first intermediate layer;

[0021] A second sub-hole, communicating with the first sub-hole, is formed in the second intermediate layer through the first sub-hole.

[0022] Furthermore, both the first intermediate layer and the third intermediate layer are made of carbon.

[0023] Further, the step of forming a connection hole in the insulating layer through the through-hole includes:

[0024] The connection hole is formed in the insulating layer through the third through-hole, and the third intermediate layer is removed.

[0025] Furthermore, the second intermediate layer is made of the same material as the insulating layer;

[0026] The step of removing the second intermediate layer is performed simultaneously with the step of forming the connection hole in the insulating layer.

[0027] Furthermore, both the second intermediate layer and the insulating layer are made of oxides.

[0028] Accordingly, the present invention also provides a method for fabricating a semiconductor device, comprising:

[0029] The connection hole is formed in the insulating layer using the above-described method, wherein the insulating layer is located on the conductive layer;

[0030] A connection contact point is formed in the connection hole, and the connection contact point is connected to the conductive layer.

[0031] Accordingly, the present invention also provides a method for manufacturing a memory, including the method for manufacturing the above-mentioned semiconductor device.

[0032] The present invention also provides a semiconductor device, comprising:

[0033] Conductive layer;

[0034] An insulating layer is located on the conductive layer;

[0035] A connecting hole penetrates the insulating layer; the connecting hole is formed by the above-described method for manufacturing a connecting hole.

[0036] The connection point is located in the connection hole and connected to the conductive layer.

[0037] Furthermore, the cross-sectional area of ​​the connecting contact point is smaller than a preset area.

[0038] The present invention also provides a memory, including a memory array structure and a peripheral structure connected to the memory array structure;

[0039] At least one of the memory array structure and the peripheral structure includes the aforementioned semiconductor device.

[0040] The beneficial effects of this invention are as follows: multiple intermediate layers and a mask layer are sequentially formed on an insulating layer, with any two adjacent intermediate layers made of different materials. Through the opening in the mask layer, vias are sequentially formed in the multiple intermediate layers. After each via is formed, the film layer on the intermediate layer where the via is located is removed. Then, a connection hole is formed in the insulating layer through the via. The sizes of the opening, via, and connection hole are sequentially reduced. This reduces the size of the connection hole under the constraints of the opening size and etching depth-to-width ratio in the mask layer, thereby reducing the volume of the semiconductor device and the memory. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A schematic flowchart illustrating a method for manufacturing a connection hole according to an embodiment of the present invention;

[0043] Figures 2a to 2h This is a structural schematic diagram of the method for manufacturing a connecting hole according to an embodiment of the present invention;

[0044] Figure 3aThis is a schematic diagram of the opening of the mask layer in the method for manufacturing the connection hole provided in an embodiment of the present invention;

[0045] Figure 3b This is a schematic diagram of the structure of the first through hole in the first intermediate layer in the method for manufacturing the connecting hole provided in the embodiment of the present invention;

[0046] Figure 3c This is a schematic diagram of the structure of the second through hole in the second intermediate layer in the method for manufacturing the connecting hole provided in the embodiment of the present invention;

[0047] Figure 3d This is a schematic diagram of the structure of the connecting hole in the insulating layer in the method for manufacturing the connecting hole provided in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of a memory provided in an embodiment of the present invention. Detailed Implementation

[0050] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0051] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0054] To reduce the size of the interconnects, a sacrificial layer can be added between the insulating layer and the mask layer to transfer the openings from the mask layer to the sacrificial layer. The interconnects are then etched in the insulating layer through the openings in the sacrificial layer. However, due to limitations in photolithography technology, the size of the openings in the mask layer cannot be further reduced. To further reduce the size of the interconnects, the thickness of the sacrificial layer can be increased. However, due to the aspect ratio of the etching depth, the thickness of the sacrificial layer cannot be too thick, making it difficult to further reduce the size of the openings in the sacrificial layer, and consequently, the size of the interconnects cannot be further reduced.

[0055] Based on this, embodiments of the present invention provide a method for manufacturing a connecting hole. See also Figure 1 This is a flowchart illustrating the method for manufacturing a connection hole provided in an embodiment of the present invention.

[0056] like Figure 1 As shown, this embodiment provides a method for fabricating a connection hole. By filling the connection hole with connection points, the connection points can be applied to a memory. The memory may include a memory array structure and a peripheral structure bonded to the memory array structure. The connection points may be located in the memory array structure or in the peripheral structure. The connection points can also be applied to other devices, and are not specifically limited here.

[0057] The method includes steps 101 to 104, as follows:

[0058] Step 101: Provide a conductive layer and an insulating layer located on the conductive layer.

[0059] In embodiments of the present invention, such as Figure 2aAs shown, conductive layer 1 can be a metal layer, including but not limited to tungsten, cobalt, copper, aluminum, etc. Conductive layer 1 can also be a semiconductor substrate, such as a silicon substrate, or a substrate including other element semiconductors or compound semiconductors.

[0060] An insulating layer 2 is formed on the conductive layer 1 using a thin-film deposition process. The insulating layer 2 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The thin-film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc.

[0061] Step 102: A plurality of intermediate layers and a mask layer are sequentially formed on the insulating layer, wherein the mask layer has an opening; any two adjacent intermediate layers are made of different materials.

[0062] In embodiments of the present invention, such as Figure 2a As shown, a thin-film deposition process is used to sequentially form multiple intermediate layers on the insulating layer 2, such as a first intermediate layer 31, a second intermediate layer 32, and a third intermediate layer 33. Specifically, the third intermediate layer 33 is first formed on the insulating layer 2, then the second intermediate layer 32 is formed on the third intermediate layer 33, and finally the first intermediate layer 31 is formed on the second intermediate layer 32. Multiple intermediate layers can also include other numbers of intermediate layers, such as two or more intermediate layers. The number of intermediate layers can be adjusted according to actual needs and is not specifically limited here.

[0063] If any two adjacent intermediate layers are made of different materials, the etching materials required to etch them will also be different. For example, if the first intermediate layer 31 and the second intermediate layer 32 are made of different materials, the etching materials required to etch the first intermediate layer 31 and the second intermediate layer 32 will also be different; similarly, if the second intermediate layer 32 and the third intermediate layer 33 are made of different materials, the etching materials required to etch the second intermediate layer 32 and the third intermediate layer 33 will also be different. Intermediate layers that are spaced apart can be made of the same or different materials, and the etching materials required to etch them can also be the same or different. For example, the first intermediate layer 31 and the third intermediate layer 33 can be made of the same material, and the etching materials required to etch the first intermediate layer 31 and the third intermediate layer 32 can also be the same.

[0064] The insulating layer 2 is made of a different material than the adjacent intermediate layers, and the materials used to etch the insulating layer 2 and the adjacent intermediate layers are also different. For example, the insulating layer 2 is made of a different material than the third intermediate layer 33, and the etching materials required to etch the insulating layer 2 and the third intermediate layer 33 are also different. The insulating layer 2 and the intermediate layers spaced apart from it can be made of the same or different materials, and the etching materials required to etch the insulating layer 2 and the intermediate layers spaced apart from it can also be the same or different. For example, the insulating layer 2 and the second intermediate layer 32 can be made of the same material, and the etching materials required to etch the insulating layer 2 and the second intermediate layer 32 can also be the same.

[0065] A mask layer 4 is formed on multiple intermediate layers, wherein when the multiple intermediate layers include a first intermediate layer 31, a second intermediate layer 32, and a third intermediate layer 33, the mask layer 4 is located on the first intermediate layer 31. For example... Figure 2a As shown, the mask layer 4 has an opening 40. Specifically, the mask layer 4 includes a hard mask layer 41, an anti-reflection layer 42, and a photoresist layer 43 sequentially located on a plurality of intermediate layers. The hard mask layer 41 can be made of amorphous carbon, and the anti-reflection layer 42 can be made of silicon oxynitride (SiON).

[0066] The photoresist layer 43 has an opening 40. The size of the opening 40 can be determined by considering the photolithography process, the size of the interconnect holes, etc. Alternatively, the size of the opening 40 can be consistent with the size of the mask layer opening required to form the interconnect holes in the prior art. That is, compared with the prior art, this embodiment does not need to reduce the size of the opening in the mask layer. The size of the opening 40 refers to its lateral (i.e., direction A parallel to the upper surface of the conductive layer 1) length or cross-sectional area. Figure 3a As shown, when the cross-section of the opening 40 is circular, the size D1 of the opening 40 can refer to the diameter of the opening 40. For example, the size of the opening 40 can range from 50 nm to 55 nm.

[0067] Step 103: Through the opening, through holes are sequentially formed in the plurality of intermediate layers, and after each through hole is formed, the film layer on the intermediate layer where the through hole is located is removed.

[0068] In this embodiment of the invention, an etching process is used to sequentially form multiple interconnected vias in multiple intermediate layers along direction B of the mask layer 4 toward the insulating layer 2, with each via corresponding to one of the multiple intermediate layers. After a via is formed in each intermediate layer, the film layer on that intermediate layer is removed to avoid affecting the etching of the via in the next intermediate layer. For example, after a via is formed in the topmost intermediate layer (i.e., the intermediate layer adjacent to the mask layer 4), the mask layer 4 is removed. Then, after a via is formed in the next intermediate layer, the topmost intermediate layer is removed, and so on, until a via is formed in the bottommost intermediate layer (i.e., the intermediate layer adjacent to the insulating layer 2), and then the intermediate layer on the bottommost intermediate layer is removed.

[0069] In this embodiment of the invention, the thickness of each intermediate layer can be less than or equal to a preset thickness, wherein the preset thickness is the thickness corresponding to the maximum acceptable aspect ratio determined by the etching process, etching equipment, etc., so as to reduce the difficulty of the process.

[0070] In some embodiments, the thickness of multiple intermediate layers can be the same. In this case, when forming intermediate layers with the same material, the same process parameters can be used, eliminating the need to adjust the process parameters multiple times and reducing the complexity of the process.

[0071] In other embodiments, the thicknesses of the multiple intermediate layers can be different, specifically, in the direction B from the mask layer 4 toward the insulating layer 2, i.e. Figure 2a In the direction from top to bottom, the thickness of multiple intermediate layers gradually increases to gradually reduce the size of the vias in the intermediate layers and ensure the orderly and controllable reduction of the via size. Alternatively, in direction B from the mask layer 4 toward the insulating layer 2, the thickness of intermediate layers of the same material gradually increases. For example, the first intermediate layer 31 and the third intermediate layer 33 are made of the same material, and the thickness of the first intermediate layer 31 is less than the thickness of the third intermediate layer 33.

[0072] Because any two adjacent intermediate layers are made of different materials, each intermediate layer can serve as a stop layer for the previous film layer and as a mask layer for the next film layer. Vias are sequentially formed in multiple intermediate layers to gradually reduce the via size required for etching the connecting holes without reducing the size of the opening 40 of the mask layer 4 or increasing the etching aspect ratio of the intermediate layers. In this embodiment, the size of the multiple vias is smaller than the size of the opening 40, and the size of the multiple vias decreases sequentially in the direction B from the mask layer 4 towards the insulating layer 2. Since the sidewalls of the vias may be inclined, the dimensions of the top (i.e., the side of the via away from the conductive layer 1) and bottom (i.e., the side of the via close to the conductive layer) may be different. In this embodiment, the via size can refer to the maximum size of the via, such as the top size. The top size of the via refers to the lateral (i.e., direction A parallel to the upper surface of the conductive layer 1) length or cross-sectional area of ​​the top of the via. When the cross-section of the via is circular, the via size can refer to the diameter of the top of the via.

[0073] For example, when multiple intermediate layers include a first intermediate layer 31, a second intermediate layer 32, and a third intermediate layer 33, the number of through-holes in the multiple intermediate layers is three. The through-hole formed in the first intermediate layer 31 is the first through-hole, the through-hole formed in the second intermediate layer 32 is the second through-hole, and the through-hole formed in the third intermediate layer 33 is the third through-hole. Step 103, which involves sequentially forming through-holes in the multiple intermediate layers through the opening, and removing the film layer on the intermediate layer where the formed through-hole is located during the formation of each through-hole, includes:

[0074] A first through-hole is formed in the first intermediate layer through the opening, and the mask layer is removed;

[0075] A second through-hole is formed in the second intermediate layer through the first through-hole, and the first intermediate layer is removed;

[0076] A third through-hole is formed in the third intermediate layer through the second through-hole, and the second intermediate layer is removed.

[0077] like Figure 2b As shown, a first via 310 is etched in the first intermediate layer 31 through the opening 40 in the mask layer 4. Since the materials of the first intermediate layer 31 and the second intermediate layer 32 are different, the etching of the first via 310 stops on the upper surface of the second intermediate layer 32 (i.e., the surface of the second intermediate layer 32 facing away from the conductive layer 1), meaning the first via 310 penetrates the first intermediate layer 31. Figure 3b As shown, the size D2 of the first via 310 is smaller than the size D1 of the opening 40 in the mask layer 4. For example, the size of the opening 40 can range from 50nm to 55nm, and the size D2 of the first via 310 can range from 30nm to 35nm.

[0078] After forming the first via 310, the mask layer 4 is removed, and only the first intermediate layer 31 is used as the mask layer for the second intermediate layer 32 to avoid the overall thickness of the mask layer 4 and the first intermediate layer 31 being too thick and affecting the etching of the via in the second intermediate layer 32. Then, the second intermediate layer 32 is etched through the first via 310 in the first intermediate layer 31 to form the second via.

[0079] In one embodiment, the first intermediate layer 31 and the third intermediate layer 33 are made of different materials, allowing the second via to be formed directly in the second intermediate layer 32. Because the second intermediate layer 32 and the third intermediate layer 33 are made of different materials, the etching of the second via stops at the upper surface of the third intermediate layer 33 (i.e., the surface of the third intermediate layer 33 facing away from the conductive layer 1), meaning the second via penetrates the second intermediate layer 32. Then, the first intermediate layer 31 is removed, and the second intermediate layer 32 is used only as a mask layer for the third intermediate layer 33 to prevent the overall thickness of the first and second intermediate layers 31 from being too large and affecting the etching of the via in the third intermediate layer 33. Furthermore, because the first intermediate layer 31 and the third intermediate layer 33 are made of different materials, removing the first intermediate layer 31 will not affect the third intermediate layer 33.

[0080] In another embodiment, the first intermediate layer 31 and the third intermediate layer 33 are made of the same material, for example, both the first intermediate layer 31 and the third intermediate layer 33 are carbon. Since carbon has a relatively fast etching rate, if the second via is formed in the second intermediate layer 32 and then the first intermediate layer 31 is removed, the third intermediate layer 33 will be etched simultaneously through the second via while the first intermediate layer 31 is being removed. This results in uncontrollable etching in the third intermediate layer 33, meaning that a via of the required size cannot be formed in the third intermediate layer 33. Therefore, in this embodiment, the second via can be etched in two stages, meaning the second via includes a first sub-via and a second sub-via.

[0081] Specifically, the step of forming a second through-hole in the second intermediate layer through the first through-hole and removing the first intermediate layer includes:

[0082] The first sub-hole is formed in the second intermediate layer through the first through-hole;

[0083] Remove the first intermediate layer;

[0084] A second sub-hole, communicating with the first sub-hole, is formed in the second intermediate layer through the first sub-hole.

[0085] like Figure 2c As shown, through the first through-hole 310 in the first intermediate layer 31, the first sub-hole 321 is first etched in the second intermediate layer 32. The first sub-hole 321 does not penetrate the second intermediate layer 32, that is, the depth of the first sub-hole 321 is less than the thickness of the second intermediate layer 32. Then, as... Figure 2d As shown, removing the first intermediate layer 31, while still separating the first intermediate layer 31 and the third intermediate layer 33 via the second intermediate layer 32, does not affect the third intermediate layer 33. After removing the first intermediate layer 31, as... Figure 2e As shown, through the first sub-hole 321, the second sub-hole 322 is etched in the second intermediate layer 32, and the etching of the second sub-hole 322 stops at the upper surface of the third intermediate layer 33. The first sub-hole 321 and the second sub-hole 322 are connected to form a second through-hole 320 that penetrates the second intermediate layer 32.

[0086] like Figure 3c As shown, the size D3 of the second via 320 is smaller than the size D2 of the first via 310. When the size of the first via 310 is in the range of 30nm to 35nm, the size of the second via 320 can be in the range of 15nm to 20nm.

[0087] Then, as Figure 2fAs shown, a third through-hole 330 is etched in the third intermediate layer 33 through the second through-hole 320 in the second intermediate layer 32. Since the third intermediate layer 33 is made of a different material than the insulating layer 2, the etching of the third through-hole 330 stops at the upper surface of the insulating layer 2 (i.e., the surface of the insulating layer 2 facing away from the conductive layer 1), meaning the third through-hole 330 only penetrates the first intermediate layer 31. The size of the third through-hole 330 is smaller than the size of the second through-hole 320.

[0088] Step 104: A connecting hole is formed in the insulating layer through the through hole; the size of the opening, the through hole, and the connecting hole decreases in sequence.

[0089] In one embodiment, the second intermediate layer 32 is made of a different material than the insulating layer 2. After forming the third via 330 in the third intermediate layer 33, the second intermediate layer 32 is removed first, and the third intermediate layer 33 is used only as a mask layer for the insulating layer 2 to avoid the overall thickness of the second intermediate layer 32 and the third intermediate layer 33 being too thick and affecting the etching of the connection hole in the insulating layer 2. Then, the connection hole is etched in the insulating layer 2 through the third via 330 in the third intermediate layer 33, and the third intermediate layer 33 is removed.

[0090] In another embodiment, the second intermediate layer 32 is made of the same material as the insulating layer 2, for example, both the second intermediate layer 32 and the insulating layer 2 are oxides such as silicon oxide. Since oxides such as silicon oxide have a slow etching rate, simultaneously etching the second intermediate layer 32 and the insulating layer 2 allows for the formation of connection holes of the required size in the insulating layer 2, and simplifies the fabrication process. Therefore, as... Figure 2g As shown, in this embodiment, while removing the second intermediate layer 32, the connection hole 20 is etched in the insulating layer 2 through the third through-hole 330. For example... Figure 2h As shown, after etching the connecting hole 20, the third intermediate layer 33 is removed.

[0091] The size of the connecting hole 20 is smaller than the size of the third through hole 330. Because the sidewalls of the connecting hole 20 may be inclined, the dimensions of the top (i.e., the side of the connecting hole 20 facing away from the conductive layer 1) and the bottom (i.e., the side of the connecting hole 20 close to the conductive layer) of the connecting hole 20 may be different. In this embodiment, the size of the connecting hole 20 can refer to its maximum size, such as the top size. The top size of the connecting hole 20 refers to the transverse (i.e., direction A parallel to the upper surface of the conductive layer 1) length or cross-sectional area of ​​the top of the connecting hole 20. Figure 3d As shown, when the cross-section of the connecting hole 20 is circular, the dimension D4 of the connecting hole 20 can refer to the diameter of the top of the connecting hole 20.

[0092] The size of the connection hole 20 can be smaller than a preset size, which refers to the smallest connection hole size that can be formed in the prior art through the existing mask layer opening. For example, when the size of the mask layer opening is in the range of 50nm to 55nm, the smallest connection hole size that can be formed in the prior art is in the range of 20nm to 26nm. Therefore, the preset size in this embodiment is 20nm, and the size of the connection hole 20 formed in this embodiment is less than 20nm.

[0093] In this embodiment, multiple intermediate layers are provided between the mask layer 4 and the insulating layer 2, and vias are sequentially formed in these intermediate layers. This allows for a gradual reduction in the size of the vias without changing the size of the opening 40 in the mask layer 4 or increasing the etching aspect ratio of the intermediate layers. Consequently, a smaller (i.e., smaller than a preset size) connecting hole 20 is etched into the insulating layer 2. It should be noted that the smaller the size of the connecting hole 20, the more intermediate layers are required.

[0094] After forming the connection hole 20 in the insulating layer 2 and removing the third intermediate layer 33, as follows Figure 4 As shown, the connecting holes 20 can be filled with connecting contact points 5 to allow for the subsequent formation of other conductive layers on the insulating layer 2, enabling these other conductive layers to be electrically connected to the conductive layer 1 through the connecting contact points 5. Connecting contact points 5 may include, but are not limited to, tungsten, cobalt, copper, aluminum, etc.

[0095] The method for fabricating a connection hole provided in this invention involves sequentially forming multiple intermediate layers and a mask layer on an insulating layer. Any two adjacent intermediate layers are made of different materials. Through an opening in the mask layer, vias are sequentially formed in the multiple intermediate layers. After each via is formed, the film layer on the intermediate layer containing the via is removed. Then, a connection hole is formed in the insulating layer through the via. This sequentially reduces the size of the opening, via, and connection hole, thereby reducing the size of the connection hole and consequently the volume of the semiconductor device and the memory.

[0096] This invention also provides a method for fabricating a semiconductor device, comprising:

[0097] The connection hole is formed in the insulating layer using the method for fabricating the connection hole in the above embodiment, wherein the insulating layer is located on the conductive layer;

[0098] A connection contact point is formed in the connection hole, and the connection contact point is connected to the conductive layer.

[0099] like Figure 4As shown, after forming the connection hole 20 in the insulating layer 2, the connection contact point 5 can be filled in the connection hole 20 so that other conductive layers can be formed on the insulating layer 2 subsequently, and the other conductive layers can be electrically connected to the conductive layer 1 through the connection contact point 5. The connection contact point 5 includes, but is not limited to, tungsten, cobalt, copper, aluminum, etc.

[0100] The semiconductor device fabrication method provided in this embodiment of the invention can achieve the beneficial effects that the connection hole fabrication method in the above embodiment can achieve, and will not be described in detail here.

[0101] This invention also provides a method for manufacturing a memory, including the method for manufacturing a semiconductor device as described in the above embodiments.

[0102] The method for manufacturing a memory provided in this embodiment of the invention can achieve the beneficial effects that the method for manufacturing semiconductor devices in the above embodiments can achieve, and will not be described in detail here.

[0103] See Figure 4 The present invention also provides a semiconductor device, including a conductive layer 1, an insulating layer 2, a connecting hole 20, and a connecting contact point 5.

[0104] The conductive layer 1 can be a semiconductor substrate, such as a silicon substrate, or a substrate containing other elemental semiconductors or compound semiconductors. The conductive layer 1 can also be a metal layer, including but not limited to tungsten, cobalt, copper, aluminum, etc.

[0105] The insulating layer 2 is located on the conductive layer 1, and the insulating layer 2 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0106] The connecting hole 20 penetrates the insulating layer 2, and the connecting hole 20 is formed by the connecting hole manufacturing method described in the above embodiment, which will not be elaborated here. In this embodiment, the size of the connecting hole 20 is smaller than the preset size.

[0107] The connecting contact point 5 is located in the connecting hole 20 and is connected to the conductive layer 1. Because the size of the connecting hole 20 is smaller than the preset size, the cross-sectional area of ​​the connecting contact point 5 (i.e., the cross-sectional area of ​​the connecting contact point 5 in direction A) is smaller than the preset area.

[0108] The semiconductor device may also include other conductive layers located on the insulating layer 2, such that the other conductive layers are connected to the conductive layer 1 through the connecting contact point 5.

[0109] This embodiment reduces the size of the semiconductor device by reducing the cross-sectional area of ​​the connecting contact 5, while maintaining the same number of connecting contact 5.

[0110] See Figure 5This is a schematic diagram of the memory structure provided in an embodiment of the present invention.

[0111] like Figure 5 As shown, the memory includes a memory array structure 100 and a peripheral structure 200 connected to the memory array structure 100. The memory array structure 100 can be a non-volatile memory array structure, such as NAND flash memory, NOR flash memory, etc.

[0112] Specifically, the memory array structure 100 may include a substrate 101 and a stacked layer 102 located on the substrate 101. The stacked layer 102 includes a plurality of vertically alternating gate layers 103 and interlayer insulating layers 104. Here, "vertical" refers to the direction perpendicular to the upper surface of the substrate 101. The number of stacked gate layers 103 and interlayer insulating layers 104 is not limited, for example, 48 layers, 64 layers, etc. The memory array structure 100 may also include a memory channel structure 105 that extends vertically through the stacked layer 102 and into the substrate 101. The memory channel structure 105 may include a vertically extending channel layer (not shown in the figure) and a memory dielectric layer (not shown in the figure) disposed around the periphery of the channel layer.

[0113] The peripheral structure 200 may include devices such as CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.

[0114] Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. At least one of the memory array structure 100 and the peripheral structure 200 may include the semiconductor device in the above embodiments, which will not be described in detail here.

[0115] The storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms. For example, the peripheral structure 200 is located below the storage array structure 100, i.e., the PUC (periphery under core array) architecture, or the peripheral structure 200 and the storage array structure 100 are set up side by side, i.e., the PNC (periphery near core array) architecture, etc. No specific limitation is made here.

[0116] The memory provided in this embodiment of the invention can reduce the size of the memory by reducing the cross-sectional area of ​​the contact points.

[0117] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a connecting hole, characterized in that, include: A conductive layer is provided, and an insulating layer is located on the conductive layer; A plurality of intermediate layers and a mask layer are sequentially formed on the insulating layer, the mask layer having an opening; the plurality of intermediate layers include a first intermediate layer, a second intermediate layer, and a third intermediate layer sequentially located between the mask layer and the insulating layer, and any two adjacent intermediate layers are made of different materials; A first through-hole is formed in the first intermediate layer through the opening, and the mask layer is removed; A second through-hole is formed in the second intermediate layer through the first through-hole, and the first intermediate layer is removed; A third through-hole is formed in the third intermediate layer through the second through-hole, and the second intermediate layer is removed; A connecting hole is formed in the insulating layer through the third through hole, and the third intermediate layer is removed; the size of the opening, the first through hole, the second through hole, the third through hole and the connecting hole decreases in sequence.

2. The method for manufacturing a connecting hole according to claim 1, characterized in that, The size of the connecting hole is smaller than the preset size.

3. The method for manufacturing a connecting hole according to claim 1, characterized in that, The thickness of each of the intermediate layers is less than or equal to a preset thickness; the thickness of the plurality of intermediate layers gradually increases in the direction from the mask layer toward the insulating layer, or the thickness of the plurality of intermediate layers is the same.

4. The method for manufacturing a connecting hole according to claim 1, characterized in that, The smaller the size of the connecting hole, the more intermediate layers there are.

5. The method for manufacturing a connecting hole according to claim 1, characterized in that, The first intermediate layer is made of the same material as the third intermediate layer, and the second through-hole includes a first sub-hole and a second sub-hole; The step of forming a second through-hole in the second intermediate layer through the first through-hole and removing the first intermediate layer includes: The first sub-hole is formed in the second intermediate layer through the first through-hole; Remove the first intermediate layer; A second sub-hole, communicating with the first sub-hole, is formed in the second intermediate layer through the first sub-hole.

6. The method for manufacturing a connecting hole according to claim 5, characterized in that, Both the first intermediate layer and the third intermediate layer are made of carbon.

7. The method for manufacturing a connecting hole according to claim 1, characterized in that, The step of forming a connection hole in the insulating layer through the through hole includes: The connection hole is formed in the insulating layer through the third through-hole, and the third intermediate layer is removed.

8. The method for manufacturing a connecting hole according to claim 7, characterized in that, The second intermediate layer is made of the same material as the insulating layer; The step of removing the second intermediate layer is performed simultaneously with the step of forming the connection hole in the insulating layer.

9. The method for manufacturing a connecting hole according to claim 8, characterized in that, Both the second intermediate layer and the insulating layer are made of oxides.

10. A method for fabricating a semiconductor device, characterized in that, include: A connection hole is formed in an insulating layer using the method for fabricating a connection hole as described in any one of claims 1 to 9, wherein the insulating layer is located on a conductive layer; A connection contact point is formed in the connection hole, and the connection contact point is connected to the conductive layer.

11. A method for manufacturing a memory, characterized in that, Including the method for manufacturing a semiconductor device as described in claim 10.

12. A semiconductor device, characterized in that, include: Conductive layer; An insulating layer is located on the conductive layer; The connection hole penetrates the insulating layer; The connecting hole is formed by the method for manufacturing a connecting hole as described in any one of claims 1 to 9; The connection point is located in the connection hole and connected to the conductive layer.

13. The semiconductor device according to claim 12, characterized in that, The cross-sectional area of ​​the connecting contact point is less than the preset area.

14. A memory, characterized in that, It includes a storage array structure and peripheral structures connected to the storage array structure; At least one of the memory array structure and the peripheral structure includes the semiconductor device as described in claim 12 or 13.

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