Resistance test structure and method of manufacturing the same

Abstract

The application relates to a resistance test structure and a manufacturing method thereof. The resistance test structure comprises: a semiconductor substrate comprising an active region; a test transistor structure formed based on the active region and comprising a test gate; a conductive connection structure electrically connected with each test gate and a test port; and a test hole structure located between the test transistor structure and the conductive connection structure and connected with the conductive connection structure and the test gate. The application can effectively improve the accuracy of contact hole resistance test.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a resistance testing structure and its fabrication method. Background Technology

[0002] Contact holes are a common structure in semiconductor architectures. They are typically formed by filling the contact hole with conductive material. The resistance of the contact hole structure has a significant impact on device performance. Therefore, the resistance of the contact hole structure (contact hole resistance) is usually tested during the device fabrication process.

[0003] Currently, with the increasing demands on device performance, there is an urgent need to improve the accuracy of contact hole resistance testing. Summary of the Invention

[0004] Based on this, embodiments of this application provide a resistance testing structure and its fabrication method. This resistance testing structure and its fabrication method can improve the accuracy of contact hole resistance testing.

[0005] A resistance testing structure, characterized in that it comprises:

[0006] Semiconductor substrate, including the active region;

[0007] A test transistor structure is formed based on the active region and includes a test gate;

[0008] A conductive connection structure is electrically connected to each of the aforementioned test gates and test ports;

[0009] A test hole structure is located between the test transistor structure and the conductive connection structure, and is connected to the conductive connection structure and the test gate.

[0010] In one embodiment, the resistance test structure further includes a dielectric layer covering each test transistor structure, a test contact hole is formed in the dielectric layer, the test contact hole structure is located in the test contact hole, and the conductive connection structure connects the test contact hole structure and the dielectric layer.

[0011] In one embodiment, the resistance test structure includes a plurality of test transistor structures, wherein the test gates of each test transistor structure are spaced apart and connected in series through a conductive interconnect structure to form a test circuit.

[0012] In one embodiment, the test gates of each of the test transistor structures are of the same size.

[0013] In one embodiment, the test gate of each test transistor structure includes n block unit resistors, where n is a positive integer, and two test hole structures are formed on the test gate of each test transistor structure. The expression for the resistance of the test hole structure is:

[0014] R = [U / I - (N / 2) * n * Rs] / N,

[0015] Wherein, U is the voltage applied across the test circuit, I is the current in the test circuit, N is the number of test hole structures, and Rs is the resistance value of the block unit resistor.

[0016] In one embodiment, a plurality of the test transistor structures are arranged in an array.

[0017] In one embodiment, the test gate comprises a polysilicon layer.

[0018] In one embodiment, the conductive connection structure is formed in the same layer as the test hole structure.

[0019] A method for fabricating a resistance test structure includes:

[0020] A substrate is provided, the substrate including a semiconductor substrate and a test transistor structure, the semiconductor substrate including an active region, the test transistor structure being formed based on the active region and including a test gate;

[0021] A test hole structure and a conductive connection structure are formed. The conductive connection structure is electrically connected to each of the test gates and test ports. The test hole structure is located between the test transistor structure and the conductive connection structure, and is connected to the conductive connection structure and the test gate.

[0022] In one embodiment, the substrate further includes a dielectric layer that covers the test transistor structure.

[0023] Before forming the test hole structure and the conductive connection structure, the method further includes:

[0024] A test contact hole is formed within the dielectric layer, and the test contact hole is used to form a test hole structure.

[0025] In one embodiment, the test contact hole extends into the test gate.

[0026] In one embodiment, the formation of the test hole structure and the conductive connection structure includes:

[0027] Deposition is performed within the test contact hole and on the surface of the dielectric layer to form the test hole structure and the conductive connection structure.

[0028] In one embodiment, the formation of the test hole structure and the conductive connection structure includes:

[0029] A test hole structure is formed within the test contact hole;

[0030] A conductive connection structure is formed on the surface of the test hole structure and the surface of the dielectric layer.

[0031] In one embodiment, the substrate further includes a functional transistor structure.

[0032] In one embodiment,

[0033] While forming test contact holes in the dielectric layer, functional contact holes are also formed in the dielectric layer.

[0034] While forming a test hole structure within the test contact hole, a contact hole structure is also formed within the functional contact hole.

[0035] The aforementioned resistance test structure and its fabrication method involve setting up a test transistor structure and forming a test hole structure on the test gate of the test transistor structure. This allows the test environment of the test hole structure to more closely resemble its actual operating environment. Therefore, when using the resistance test structure of this application to test the contact hole resistance, other factors that may affect the contact hole resistance can be simulated, resulting in a measured contact hole resistance (resistance of the test hole structure) that is closer to its resistance value under actual operating conditions, thereby improving test accuracy. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a three-dimensional structural diagram of a resistance testing structure provided in one embodiment;

[0038] Figure 2 This is a schematic diagram of the planar structure of the resistance testing structure provided in one embodiment;

[0039] Figure 3 This is a schematic diagram of a block unit resistance provided in one embodiment;

[0040] Figure 4 A flowchart of a method for fabricating a resistance test structure provided in one embodiment;

[0041] Figures 5 to 9 This is a cross-sectional structural diagram illustrating the fabrication process of the resistance testing structure provided in one embodiment, wherein... Figures 5 to 7 This is a front view. Figures 8 to 9 This is a side view;

[0042] Figures 10 to 13 This is a cross-sectional structural diagram of the fabrication process of the resistance test structure provided in another embodiment.

[0043] Figure 14 This is a cross-sectional schematic diagram of the resistance test structure provided in another embodiment.

[0044] Explanation of reference numerals in the attached figures:

[0045] Explanation of reference numerals in the attached figures: 100-semiconductor substrate, 110-active region, 111-source, 112-drain, 200-test transistor structure, 210-test gate, 211-polysilicon layer, 212-metal barrier layer, 213-metal layer, 220-gate dielectric layer, 300-conductive connection structure, 400-test via structure, 500-dielectric layer, 500a-test contact via, 700-patterned photoresist layer. Detailed Implementation

[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of exemplary embodiments (and intermediate structures) of this application, thereby contemplating variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. However, embodiments of this application should not be limited to the specific shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the structures shown in the figures are substantially schematic, and their shapes do not represent the actual shape of the device and do not limit the scope of this application.

[0052] In one embodiment, see Figure 1 as well as Figure 2 A resistance testing structure is provided, including: a semiconductor substrate, a test transistor structure 200, a conductive connection structure 300, and a test hole structure 400.

[0053] The semiconductor substrate may include, but is not limited to, a silicon substrate. The semiconductor substrate includes an active region 110, which may be a P-type active region or an N-type active region.

[0054] The test transistor structure 200 is formed based on the active region 110. As an example, the test transistor structure 200 can be a bipolar complementary oxide semiconductor (CMOS) structure. Of course, the test transistor structure 200 can also be other types of transistor structures, such as N-type oxide semiconductor (NMOS) structures, P-type oxide semiconductor (PMOS) structures, etc.

[0055] The test transistor structure 200 includes a test gate 210. Furthermore, the test transistor structure 200 may also include a gate dielectric layer 220, located between the test gate 210 and the active layer 110. As an example, the gate dielectric layer 220 may be an oxide layer. The source 111 and drain 112 of the test transistor structure 200 are formed within the active layer 110 on both sides of the gate dielectric layer 220 through processes such as ion implantation. The active layer 110 between the source 111 and drain 112 constitutes the conductive channel region of the transistor structure 200.

[0056] To improve testing accuracy, the number of test transistor structures 200 can be set to multiple. Alternatively, the number of test transistor structures 200 can be set to one; there is no limitation on this.

[0057] The conductive connection structure 300 is electrically connected to each test gate 210 and test port (not shown).

[0058] As an example, the material of the conductive connection structure 300 can be a metallic material.

[0059] When there are multiple test transistor structures 200, each test transistor structure 200 is electrically connected through a conductive connection structure 300. Simultaneously, some conductive connection structures 300 (such as...) Figure 1 The conductive connection structure 300 located at the beginning and end of the series circuit is electrically connected to the test gate 210 at one end, and can be used to electrically connect to the test port (not shown) at the other end, which can be used to apply the test voltage.

[0060] The test hole structure 400 is located between the test transistor structure 200 and the conductive connection structure 300, and the test hole structure 400 is connected to both the conductive connection structure 300 and the test gate 210, thereby realizing the electrical connection between the conductive connection structure 300 and the test gate 210.

[0061] As an example, the material of the test hole structure 400 can be a metallic material.

[0062] In this embodiment, by setting up a test transistor 200 structure and forming a test hole structure 400 on the test gate 210 of the test transistor structure 200, the test environment of the test hole structure 400 can be closer to its real working environment. Therefore, when testing the contact hole resistance using the resistance test structure of this embodiment, other factors that may affect the contact hole resistance can be simulated, thereby making the measured contact hole resistance (resistance of the test hole structure 400) closer to its resistance value in the real working environment, thus improving the test accuracy.

[0063] In one embodiment, see Figure 13 as well as Figure 12 The resistance test structure also includes a dielectric layer 500 covering each test transistor structure 200, within which test contact holes 500a are formed. Specifically, the test contact holes 500a may be located only within the dielectric layer 500, or they may extend into a portion of the test gate 210, with the test hole structure 400 formed within the test contact holes 500a of the dielectric layer 500. Therefore, the test hole structure 400 may not extend into the interior of the test gate 210, or it may extend from the surface of the dielectric layer 500 away from the test gate 210 into a portion of the test gate 210.

[0064] The conductive connection structure 300 connects the test hole structure 400 and the dielectric layer 500. At this time, the conductive connection structure 300 and the test hole structure 400 can be the same structure formed in the same layer, or they can be different structures formed in different layers. There is no restriction on this.

[0065] In one embodiment, a functional contact hole is also formed within the dielectric layer 500, and a contact hole structure is formed within the functional contact hole. Specifically, the functional contact hole may be located only within the dielectric layer 500, or it may extend into a portion of the test gate 210. The test hole structure 400 is formed within the test contact hole 500a of the dielectric layer 500. The functional contact hole and the test contact hole 500a may have the same size, thereby making the functional contact hole and the contact hole structure 400 have the same size. This allows the resistance value of the contact hole obtained by measuring the resistance of the test hole structure 400 to be closer to the actual resistance value of the contact hole structure formed within the functional contact hole.

[0066] In one embodiment, the test gate 210 may include a heavily doped polysilicon layer 211, etc. Specifically, the test gate 210 may include an N-type polysilicon layer or a P-type polysilicon layer.

[0067] It should be understood that the test gate 210 may consist of only a polysilicon layer, or it may also include other film layers.

[0068] When the test gate 210 may consist of only a polysilicon layer, the test via structure 400 contacts the polysilicon layer.

[0069] When the test gate 210 also includes other film layers, please refer to Figure 14 As an example, in addition to the polysilicon layer 211, the test gate 210 may also include a metal barrier layer 212 (such as a titanium nitride layer) and a metal layer 213 (such as a tungsten metal layer). In this case, the test hole structure 400 can contact the metal layer 213.

[0070] In one embodiment, see Figure 1 The resistance test structure includes multiple test transistor structures 200, and the test gates 210 of each test transistor structure 200 are spaced apart.

[0071] Meanwhile, the test gates 210 of each test transistor structure 200 are connected in series through the conductive interconnect structure 300 to form a test circuit.

[0072] When testing the contact hole resistance using this embodiment, the resistance on the conductive connection structure 300 can be ignored. The total resistance of the circuit is calculated based on the voltage U across the series circuit and the current I in the test circuit. Then, the total resistance of each test gate 210 is obtained by subtracting the total resistance of the circuit from the total resistance of the circuit. Finally, the resistance of each test hole structure 400 is calculated by dividing the total resistance of each test hole structure 400 by the number of test hole structures 400.

[0073] Of course, in other embodiments, the test circuit for the contact hole resistance is not limited to a series circuit, and there is no limitation in the comparison here.

[0074] In one embodiment, the test gates 210 of each test transistor structure 200 have the same size. This facilitates the layout design and fabrication of each test gate 210. At the same time, the resistance of each test gate 210 is the same, which makes it easier to obtain the total resistance of each test gate 210 and thus facilitates the calculation of the contact hole resistance.

[0075] In one embodiment, the test gate 210 of each test transistor structure 200 includes n block unit resistors, where n is a positive integer.

[0076] The square unit resistance is a resistor with a square cross-section and a square side length of a preset length, forming a square gate structure. When the material of the test gate 210 is polysilicon, the square unit resistance is the resistance of the square polysilicon.

[0077] For example, please refer to Figure 3The square unit resistor is a resistor with a square cross-section and a side length of F in the form of a square gate structure. The test gate 210 in the figure includes 4 square unit resistors.

[0078] The resistance value Rs of the unit sheet resistor is fixed, which facilitates the calculation of the resistance value of each test gate 210. Specifically, the resistance value of the test gate 210 is equal to the product of the number n of the unit sheet resistors and the resistance value Rs of the unit sheet resistors.

[0079] In this embodiment, each test transistor structure 200 may also have two test hole structures formed on its test gate 210.

[0080] Specifically, two test hole structures 400 can be formed at both ends of each test gate 210. The two test hole structures 400 can contact two conductive connection structures 300 respectively, so that each test gate 210 is connected in series through the conductive connection structures 300.

[0081] Meanwhile, the other end of the conductive connection structure 300 connecting the first test hole structure 400 of the series circuit is connected to a test port, and the other end of the conductive connection structure 300 connecting the last test hole structure 400 of the series circuit is connected to another test port. At this time, the series test circuit is connected to the positive and negative terminals through the two test ports respectively, so that the series circuit can obtain a voltage U. As an example, the voltage U can be 1V.

[0082] At this point, one test gate 210 corresponds to two test via structures 400. Therefore, when the number of test via structures is N, the number of test gates 210 is N / 2. Thus, the total resistance of all test gates 210 is (N / 2)*n*Rs.

[0083] Therefore, the expression for the resistance of the test hole structure is:

[0084] R = [U / I - (N / 2) * n * Rs] / N.

[0085] Where U is the voltage applied across the test circuit, I is the current in the test circuit, N is the number of test hole structures, and Rs is the resistance value of the block unit resistor.

[0086] It is understandable that when the test gate is an N-type polysilicon layer, Rs is the sheet resistance of the N-type polysilicon, and when the test gate is a P-type polysilicon layer, Rs is the sheet resistance of the P-type polysilicon.

[0087] In one embodiment, the individual test transistor structures 200 can be arranged in an array. In this case, the length of the resistance test structure can be reduced, and the concentration of the resistance test structure can be improved.

[0088] In one embodiment, see Figure 13 The conductive connection structure 300 and the test hole structure 400 are formed in the same layer. That is, the conductive connection structure 300 and the test hole structure 400 are formed simultaneously in the same process step.

[0089] At this point, on the one hand, the number of process steps can be reduced. On the other hand, since the conductive connection structure 300 and the test hole structure 400 are located in the same continuous film layer, the conductive connection structure 300 and the test hole structure 400 can be better electrically connected.

[0090] Of course, in other embodiments, the test hole structure 400 and the conductive connection structure 300 may also be different layer structures. In this case, their materials may be the same or different.

[0091] In one embodiment, a resistance test structure is provided, including: a semiconductor substrate, a test transistor structure 200, a dielectric layer 500, a test hole structure 400, and a conductive connection structure 300.

[0092] The semiconductor substrate includes multiple active regions 110. Each active region 110 includes a conductive channel region between a source 111 and a drain 112.

[0093] The test transistor structure 200 is formed based on the active region 110. Each test transistor structure 200 formed on the active region 110 also includes a test gate 210 and a gate dielectric layer 220. The test gate 210 of each test transistor structure 200 includes n block unit resistors, where n is a positive integer.

[0094] The dielectric layer 500 covers each test transistor structure 200. Multiple test contact holes 500a are formed within the dielectric layer 500. Specifically, the test contact holes 500a may be located only within the dielectric layer 500, or they may extend into a portion of the test gate 210. Test hole structures 400 are formed within the test contact holes 500a of the dielectric layer 500.

[0095] The test hole structure 400 within each test contact hole 500a is used to achieve electrical connection between each test gate 210 and the conductive connection structure 300. The conductive connection structure 300 and the test hole structure 400 can be formed in the same layer or in different layers.

[0096] Multiple conductive connection structures 300 are used to connect the various test transistor structures 200 in series, forming a series test circuit. In this case, each adjacent test transistor structure 200 is electrically connected through a conductive connection structure 300. Simultaneously, the conductive connection structures 300 also electrically connect the test ports on both sides of the series test circuit. The test ports are used to apply a test voltage to the series test circuit.

[0097] In one embodiment, see Figure 4 Furthermore, a method for fabricating a resistance testing structure is provided, comprising the following steps:

[0098] Step S100: A substrate is provided, comprising a semiconductor substrate and a test transistor structure 200. The semiconductor substrate includes an active region 110. The test transistor structure 200 is formed based on the active region 110 and includes a test gate 210. (See also...) Figure 5 .

[0099] In step S300, a test via structure 400 and a conductive connection structure 300 are formed. The conductive connection structure 300 is electrically connected to each test gate 210 and the test port. The test via structure 100 is located between the test transistor structure 200 and the conductive connection structure 400, and is connected to the conductive connection structure 400 and the test gate. Please refer to [link to relevant documentation]. Figures 6 to 9 .

[0100] Specifically, in step S100, a semiconductor base substrate is provided, and then the semiconductor base substrate is doped to form a well region. A shallow trench isolation structure (STI) is formed in the semiconductor base substrate. The shallow trench isolation structure (STI) isolates the well region into multiple active regions 110, thereby forming a semiconductor substrate.

[0101] Subsequently, a gate dielectric layer 220 can be formed on the semiconductor substrate, and then a patterned test gate 210 can be formed on the gate dielectric layer 220 to form multiple test transistor structures 200. The active layers 110 on both sides of the gate dielectric layer 220 form the source 111 and drain 112 of the test transistor structure 200 through processes such as ion implantation. The active layer 110 between the source 111 and the drain 112 constitutes the conductive channel region of the test transistor structure 200.

[0102] In step S300, the materials of the test hole structure 400 and the conductive connection structure 300 can be the same or different, and they can be formed simultaneously or separately, without any restrictions.

[0103] In this embodiment, the resistance test structure is formed based on the test transistor structure 200, making the test environment of the test hole structure 400 closer to its actual working environment. Therefore, when testing the contact hole resistance using the resistance test structure formed by the method of this application embodiment, other factors that may affect the contact hole resistance can be simulated, thereby making the measured contact hole resistance (resistance of the test hole structure 400) closer to its resistance value in the actual working environment, thus improving the test accuracy.

[0104] In one embodiment, see Figure 10The substrate also includes a dielectric layer 500. The dielectric layer 500 covers the test transistor structure 200. Specifically, the dielectric layer 500 can be formed on both the test transistor structure 200 and the surface of the semiconductor substrate.

[0105] It should be understood here that the dielectric layer 500 is not necessarily a single film layer; it can include one or more layers. When the dielectric layer 500 includes multiple film layers, the materials and formation locations of each film layer are not necessarily the same.

[0106] At this point, before step S300, the following also applies:

[0107] In step S200, a test contact hole 500a is formed within the dielectric layer 500. The test contact hole 500a is used to form the test hole structure 400. Please refer to [link / reference]. Figure 12 .

[0108] Specifically, please refer to Figure 11 First, a mask material layer 601 can be formed on the dielectric layer 500. Then, a patterned photoresist layer 700 can be formed on the mask material layer 601. Based on the patterned photoresist layer 700, the mask material layer 601 can be patterned to form a mask layer. Based on this mask layer, the dielectric layer 500 can be etched to form a test contact hole 500a. Please refer to [link to relevant documentation]. Figure 12 .

[0109] In one embodiment, the test contact hole 500a extends into the test gate 210, which allows the test hole structure 400 formed within the test contact hole 500a to have a larger contact area with the test gate 210, thereby enabling a good electrical connection between the two. Of course, in other embodiments, the test contact hole 500a may not extend into the test gate 210, and this is not a limitation.

[0110] In one embodiment, step S300 includes:

[0111] S311, deposition is performed within the test contact hole 500a and on the surface of the dielectric layer 500 to form the test hole structure 400 and the conductive connection structure 300. Please refer to [link / reference]. Figure 13 .

[0112] As an example, a metal material layer can be deposited inside the test contact hole 500a and on the surface of the dielectric layer 500. The metal material layer is then planarized to form a conductive metal structure. The portion of this conductive metal structure within the test contact hole 500a constitutes the test hole structure 400, and the remaining portion constitutes the conductive connection structure 300. In this embodiment, both the test hole structure 400 and the conductive connection structure 300 are components of the conductive metal structure, and good electrical signal transmission can occur between them.

[0113] In one embodiment, step S300 includes:

[0114] Step S321: Form a test hole structure 400 within the test contact hole 500a;

[0115] Step S322: A conductive connection structure 300 is formed on the surface of the test hole structure 400 and the surface of the dielectric layer 500.

[0116] The test hole structure 400 and the conductive connection structure 300 are formed in different process steps, which allows for more flexible settings in terms of materials and preparation methods.

[0117] In one embodiment, the substrate also includes a functional transistor structure (not shown).

[0118] A functional transistor structure is the transistor structure of the normal circuit portion of a device. In this embodiment, the test transistor structure 200 is formed on a substrate used to fabricate the functional transistor structure. Each layer of the structure can be formed using the same process as the corresponding functional film layer structure of the functional transistor structure, thereby making the test environment closer to the real working environment and reducing measurement errors.

[0119] In one embodiment, while forming a test contact hole 500a within the dielectric layer 500, a functional contact hole (not shown) is also formed within the dielectric layer 200. The functional contact hole is a contact hole used to expose the gate of a functional transistor structure. Furthermore, while forming a test hole structure 400 within the test contact hole 500a, a contact hole structure (not shown) is also formed within the functional contact hole. The contact hole structure allows external signals to be transmitted to the transistor gate.

[0120] In this embodiment, the test hole structure 400 and the contact hole structure are formed using the same process. This prevents the test contact hole 500a and the functional contact hole from having different dimensions due to the manufacturing process, and also prevents calculation errors in the contact hole resistance (resistance of the test hole structure 400) caused by such differences. Furthermore, in this embodiment, the contact hole structure and the contact hole structure 400 are formed simultaneously, making the contact hole resistance value obtained by testing and calculating the resistance of the test hole structure 400 more closely approximate the actual resistance value of the contact hole structure formed within the functional contact hole.

[0121] In one embodiment, a method for fabricating a resistance test structure is provided, comprising:

[0122] Step S100: Provide a substrate, which includes a semiconductor substrate, a test transistor structure 200 and a dielectric layer 500. The semiconductor substrate includes a plurality of active regions 110. The test transistor structure 200 is formed based on the active regions 110 and includes a test gate 210 and a gate dielectric layer 220. The test gate 210 of each test transistor structure 200 includes n square unit resistors.

[0123] In step S200, a test contact hole 500a is formed in the dielectric layer 500. The test contact hole 500a may be located only in the dielectric layer 500 or may extend into part of the test gate 210.

[0124] In step S300, a test hole structure 400 is formed in the test contact hole 500a, and a plurality of conductive connection structures 300 are formed on the surface of the test hole structure 400 and the surface of the dielectric layer 500. The conductive connection structures 300 and the test hole structure 400 can be formed in the same layer or in different layers.

[0125] Multiple conductive connection structures 300 connect the various test transistor structures 200 in series to form a series test circuit. The conductive connection structures 300 also electrically connect the test ports on both sides of the series test circuit. The test ports are used to apply test voltage to the series test circuit.

[0126] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0127] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0128] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A resistance testing structure, characterized in that, include: Semiconductor substrate, including the active region; A test transistor structure is formed based on the active region and includes a test gate; A conductive connection structure is electrically connected to each of the aforementioned test gates and test ports; A test hole structure is located between the test transistor structure and the conductive connection structure, and is connected to the conductive connection structure and the test gate; the resistance test structure includes multiple test transistor structures, the test gates of each test transistor structure are spaced apart and connected in series through a conductive interconnect structure to form a test circuit; each test gate of each test transistor structure includes n square unit resistors, where n is a positive integer, and two test hole structures are formed on each test gate of each test transistor structure. The expression for the resistance of the test hole structure is: R = [U / I - (N / 2)*n*Rs] / N, where U is the voltage applied across the test circuit, I is the current in the test circuit, N is the number of test hole structures, and Rs is the resistance value of the block unit resistor.

2. The resistance testing structure according to claim 1, characterized in that, The resistance test structure further includes a dielectric layer covering each of the test transistor structures, a test contact hole is formed in the dielectric layer, the test hole structure is located in the test contact hole, and the conductive connection structure connects the test hole structure and the dielectric layer.

3. The resistance testing structure according to claim 1, characterized in that, The test gates of all the test transistor structures described have the same size.

4. The resistance testing structure according to claim 2, characterized in that, Multiple test transistor structures are arranged in an array.

5. The resistance testing structure according to claim 1, characterized in that, The test gate comprises a polysilicon layer.

6. The resistance testing structure according to claim 1, characterized in that, The conductive connection structure is formed in the same layer as the test hole structure.

7. A method for fabricating a resistance testing structure, characterized in that, include: A substrate is provided, the substrate including a semiconductor substrate and a test transistor structure, the semiconductor substrate including an active region, the test transistor structure being formed based on the active region and including a test gate; A test hole structure and a conductive connection structure are formed. The conductive connection structure is electrically connected to each of the test gates and test ports. The test hole structure is located between the test transistor structure and the conductive connection structure, and is connected to the conductive connection structure and the test gates. The resistance test structure includes multiple test transistor structures. The test gates of each test transistor structure are spaced apart and connected in series through a conductive interconnect structure to form a test circuit. Each test gate of each test transistor structure includes n square unit resistors, where n is a positive integer. Two test hole structures are formed on each test gate of each test transistor structure. The expression for the resistance of the test hole structure is: R = [U / I - (N / 2)*n*Rs] / N, where U is the voltage applied across the test circuit, I is the current in the test circuit, N is the number of test hole structures, and Rs is the resistance value of the block unit resistor.

8. The method for fabricating the resistance testing structure according to claim 7, characterized in that, The substrate further includes a dielectric layer that covers the test transistor structure. Before forming the test hole structure and the conductive connection structure, the method further includes: A test contact hole is formed within the dielectric layer, and the test contact hole is used to form a test hole structure.

9. The method for fabricating the resistance testing structure according to claim 8, characterized in that, The test contact hole extends into the test gate.

10. The method for fabricating the resistance testing structure according to claim 8, characterized in that, The formation of the test hole structure and the conductive connection structure includes: Deposition is performed within the test contact hole and on the surface of the dielectric layer to form the test hole structure and the conductive connection structure.

11. The method for fabricating the resistance testing structure according to claim 8, characterized in that, The formation of the test hole structure and the conductive connection structure includes: The test hole structure is formed within the test contact hole; The conductive connection structure is formed on the surface of the test hole structure and the surface of the dielectric layer.

12. The method for fabricating the resistance testing structure according to claim 8, characterized in that, The substrate also includes a functional transistor structure.

13. The method for fabricating the resistance testing structure according to claim 12, characterized in that, While forming the test contact hole in the dielectric layer, a functional contact hole is also formed in the dielectric layer; While forming the test hole structure within the test contact hole, a contact hole structure is also formed within the functional contact hole.

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