Leadless power amplifier package with top-side terminals and its manufacturing method

Abstract

This disclosure relates to a leadless power amplifier package including a top-side terminal and a method of manufacturing the same. Embodiments disclose a leadless power amplifier (PA) package and a method for manufacturing a leadless PA package having a top-side terminal. In one embodiment, the method includes providing a conductive pillar support and a base flange. At least a first radio frequency (RF) power die is attached to a die mounting surface of the base flange and electrically interconnected with the pillar support. Pillar contacts are also provided, wherein the pillar contacts are electrically coupled to the pillar support and extend from the pillar support in the package height direction. The first RF power die is enclosed in a package body that at least partially defines a package top-side surface opposite a lower surface of the base flange. A top-side input / output terminal is formed, accessible from the package top-side surface, and electrically interconnected with the first RF power die via the pillar contacts and the pillar support.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to microelectronics, and more specifically, to leadless power amplifier (PA) packages and methods for manufacturing leadless PA packages with top-side terminations. Background Technology

[0002] A power amplifier (PA) package contains at least one semiconductor die carrying a transistor integrated circuit for radio frequency (RF) signal or power amplification purposes, referred to herein as an "RF power die". For example, in the case of a Doherty PA package, at least one carrier RF power die and at least one peaked RF power die are contained within the PA package body. The carrier and peaked RF power dies may be mounted to a conductive substrate such as a metal base flange, which provides electrical contact with the respective back side of the die and potentially also acts as a heat sink to help dissipate excess heat generated during operation of the RF power die. In some cases, the PA package may include a cap or cover enclosing a cavity; the term "cavity" according to industry conventions refers to a sealed cavity containing gas. In other cases, the PA package may be manufactured without such a cavity, instead containing a gapless package body in which the packaged RF power die, any other packaged microelectronic components (e.g., surface mount devices), and bonding wires or other interconnect features are embedded. This latter type of PA package is often referred to as "encapsulation," "overmolding," or "plastic" packaging, with "overmolding" being the primary term used herein. As noted above, the RF power die or multiple RF power dies contained within a PA package may be prone to generating excessive heat during operation, specifically in the case of carrier RF power dies operating at higher frequencies (e.g., close to or above 3 GHz) and dies manufactured using power-intensive technologies (e.g., layered gallium nitride die structures). If not adequately dissipated, this excess heat can accumulate within the PA package and limit the performance of the RF power dies. Summary of the Invention

[0003] According to a first aspect of the present invention, a method for manufacturing a leadless power amplifier (PA) package is provided, the method comprising:

[0004] A conductive post support and a base flange spaced apart from the conductive post support are provided, the base flange having a die mounting surface and a lower flange surface opposite to the die mounting surface in the package height direction;

[0005] At least one first radio frequency (RF) power die is attached to the die mounting surface of the base flange;

[0006] The first RF power die and the conductive pillar support are electrically interconnected;

[0007] Before or after electrically interconnecting the first RF power die and the conductive pillar support, pillar contacts are provided, which are electrically coupled to the conductive pillar support and extend from the conductive pillar support in the package height direction.

[0008] The first RF power die is enclosed in a package, the package defining, at least in a large portion, a top surface of the package positioned opposite the lower flange surface; and

[0009] A top-side input / output (I / O) terminal is formed, which is accessible from the top surface of the package and electrically interconnected with the first RF power die via the pillar contacts and the conductive pillar support.

[0010] In one or more embodiments, the method further includes generating the package to enclose at least a portion of the first RF power die and the pillar contact, while exposing the outer end surface of the pillar contact from the top side surface of the package to form at least a portion of the top side I / O terminal.

[0011] In one or more embodiments, generating the package includes:

[0012] The conductive pillar support, the base flange, the first RF power die, and the pillar contacts are encapsulated in a molded package with a thickness sufficient to cover the pillar contacts; and

[0013] After encapsulating the conductive pillar support, the base flange, the first RF power die, and the pillar contact, the overmolded package is thinned to expose the outer end surface of the pillar contact at the top side surface of the package.

[0014] In one or more embodiments, the method further includes:

[0015] The conductive post support and the base flange are provided as part of a lead frame, the lead frame further including a sacrificial lead frame portion connecting the conductive post support and the base flange; and

[0016] After enclosing the first RF power die in the package, the lead frame is detached to remove the sacrificial lead frame portion and electrically isolate the base flange from the conductive post support.

[0017] In one or more embodiments, the lead frame is provided as part of a lead frame array, the lead frame array further comprising a plurality of additional interconnecting lead frames;

[0018] The method further includes plating the end surface of the post contact using an electroplating process, during which a potential is applied to the post contact through the lead frame array before the lead frame array is separated.

[0019] In one or more embodiments, the method further includes giving the package a bottom surface, the lower flange surface being exposed through the bottom surface to create a bottom thermal interface substantially opposite to the top I / O terminal in the package height direction.

[0020] In one or more embodiments, the first RF power die includes a peaked RF power die; and

[0021] The method further includes:

[0022] The leadless PA package is produced to have a Dougherty amplifier architecture including a peaking signal amplification path and a carrier signal amplification path;

[0023] At the first die mounting position through which the peaked signal amplification path extends, the peaked RF power die is attached to the base flange; and

[0024] Additionally, the carrier RF power die is attached to the base flange at the second die mounting position through which the carrier signal amplification path extends.

[0025] In one or more embodiments, the method further includes connecting a central isolation wall to the base flange such that the central isolation wall extends between the first die mounting location and the second die mounting location.

[0026] In one or more embodiments, the method further includes:

[0027] Electrically coupling the central isolation wall to the base flange; and

[0028] A ground terminal is provided that is accessible from the top side surface of the package, and the base flange is electrically coupled to the ground terminal through the central isolation wall.

[0029] In one or more embodiments, the central isolation wall is elongated along the length of the package; and

[0030] The method further includes providing lateral isolation wings that extend from the central isolation wall along an axis substantially perpendicular to the package length direction and the package height direction.

[0031] In one or more embodiments, the method further includes positioning the lateral isolation wing to extend over the peaked RF power die or the carrier RF power die, while being spaced apart from the peaked RF power die or the carrier RF power die by an isolation gap measured in the package height direction.

[0032] In one or more embodiments, the central partition wall includes a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion;

[0033] The method further includes producing the leadless PA package such that: (i) a first end portion of the central isolation wall extends between a first pair of post contacts, (ii) a second end portion of the central isolation wall extends between a second pair of post contacts, and (iii) a middle portion of the central isolation wall extends between the peaked RF power die and the carrier RF power die.

[0034] In one or more embodiments, the first end portion and the second end portion of the central isolation wall terminate adjacent to the first sidewall and the second sidewall of the package, respectively; and

[0035] The method further includes selecting the base flange to include a flange connecting strip that extends substantially parallel to the central isolation wall and parallel to the first and second sidewalls of the package.

[0036] According to a second aspect of the present invention, a method for manufacturing a leadless power amplifier (PA) package is provided, the method comprising:

[0037] Provides a base flange with a die mounting surface;

[0038] At the first die mounting position, a peaked radio frequency (RF) power die is attached to the base flange, and at the second die mounting position, a carrier RF power die is attached to the base flange.

[0039] The central isolation wall is connected to the die mounting surface of the base flange such that the central isolation wall is electrically coupled to the base flange and extends between the first die mounting position and the second die mounting position;

[0040] The peaked RF power die and the carrier RF power die are enclosed in a package, the package having a top surface that extends substantially parallel to the die mounting surface and opposite the base flange; and

[0041] A top-side input / output (I / O) interface is formed that is accessible from the top-side surface of the package. The top-side I / O interface includes a top-side ground terminal electrically coupled to the peaked RF power die and the carrier RF power die through the central isolation wall and the base flange.

[0042] In one or more embodiments, the method further includes:

[0043] Provides post contacts electrically coupled to the peaked RF power die and the carrier RF power die; and

[0044] The pillar contact, the base flange, the peaked RF power die, the carrier RF power die, and the central isolation wall are encapsulated in an overmolded package, the overmolded package having a thickness sufficient to cover the upper surface of the pillar contact and the central isolation wall;

[0045] The process includes removing material from the overmolded package to expose the upper surfaces of the pillar contacts and the central isolation wall through the top side surface of the package.

[0046] In one or more embodiments, the method further includes:

[0047] Provide lateral isolation wings extending from the central isolation wall; and

[0048] The lateral isolation wing is positioned to extend on the peaked RF power die or the carrier RF power die.

[0049] According to a third aspect of the present invention, a leadless power amplifier (PA) package is provided, comprising:

[0050] The base flange has a die mounting surface and a lower flange surface positioned relative to the die mounting surface in the package height direction;

[0051] A conductive post support, which is spaced apart from the base flange;

[0052] A first radio frequency (RF) power die is attached to the die mounting surface of the base flange and electrically interconnected with the conductive post support.

[0053] A post contact, electrically coupled to the conductive post support and extending from the conductive post support in the package height direction;

[0054] A package housing that encloses the first RF power die and has a top package surface opposite the lower flange surface, the top package surface extending substantially parallel to the die mounting surface; and

[0055] The top-side input / output (I / O) terminal is accessible from the top surface of the package and electrically interconnected with the first RF power die via the pillar contacts and the conductive pillar support.

[0056] In one or more embodiments, the package includes an overmolded package having an outer main surface that at least partially defines the top side surface of the package; and

[0057] The top-side I / O terminal includes the end surface of the pillar contact that is exposed along the outer main surface of the overmolded package and substantially coplanar with the outer main surface.

[0058] In one or more embodiments, the first RF power die includes a peaked RF power die; and

[0059] The leadless PA package further includes:

[0060] A central isolation wall, which is mounted to the die mounting surface and electrically coupled to the base flange, wherein the first RF power die is positioned adjacent to a first side of the central isolation wall; and

[0061] The carrier RF power die is positioned adjacent to the second opposite side of the central isolation wall.

[0062] In one or more embodiments, the post contact includes:

[0063] The first pair of post contacts are positioned adjacent to the first sidewall of the package;

[0064] The second pair of post contacts is positioned adjacent to the second sidewall of the package body opposite the first sidewall; and

[0065] The central isolation wall includes:

[0066] The first end portion extends between the first pair of post contacts;

[0067] The second end portion extends between the second pair of post contacts; and

[0068] The middle portion, located between the first end portion and the second end portion, has the peaked RF power die and the carrier RF power die located on opposite sides of the middle portion of the central isolation wall.

[0069] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0070] At least one example of the invention will be described below with reference to the accompanying drawings, in which like reference numerals denote like elements, and:

[0071] Figure 1 A multipath amplifier circuit (here referring to a bidirectional Dougherty amplifier circuit) according to an example embodiment of the present disclosure is schematically shown, a portion of which may be implemented using a leadless power amplifier (PA) package;

[0072] Figure 2 This is an isometric view of a leadless PA package including a top-side input / output (I / O) interface, an overlay molded package (shown in dotted lines), and a top-side terminal isolation structure, as shown in an exemplary embodiment of this disclosure.

[0073] Figure 3 and 4 They are Figure 2 The example top and bottom side views of a leadless PA package are shown, in which the overmolded package body is hidden and not visible.

[0074] Figure 5 and 6 yes Figures 2 to 4 The example leadless PA package shown is a relative side view, in which the overmolded package body is shown in outline;

[0075] Figure 7 and 8 yes Figures 2 to 6 The example leadless PA package shown is a relative side view (relative to) Figure 5 and 6 The side view is rotated 90 degrees around the package centerline, in which the encapsulated molded package is hidden and not visible;

[0076] Figures 9 to 12 Show Figures 2 to 8 Example leadless PA packages are shown at various manufacturing stages and produced according to example manufacturing processes;

[0077] Figure 13 As shown in the example embodiment Figures 2 to 8 Example of a leadless PA package that can be mounted in the reverse direction within a larger electronic system or component; and

[0078] Figure 14 This is an isometric view of a leadless PA package including a top-side I / O interface, an overlay molded package (shown in dotted lines), and a top-side terminal isolation structure, as shown in another exemplary embodiment of this disclosure.

[0079] For the sake of simplicity and clarity, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the following detailed description. It should also be understood that, unless otherwise stated, features or elements appearing in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the drawings may be enlarged relative to other elements or regions to improve understanding of embodiments of the invention. Detailed Implementation

[0080] Embodiments of this disclosure are illustrated in the accompanying drawings, which have been briefly described above. Various modifications to the exemplary embodiments will be contemplated by those skilled in the art without departing from the scope of the invention as set forth in the appended claims. The terms "integrated circuit die" or "IC die" encompass integrated passive devices, metal-oxide-semiconductor capacitor devices, and other such circuit elements formed on a die containing discrete semiconductor material; as well as semiconductor-containing dies containing more complex active integrated circuits such as transistor amplifier circuits of the type described below.

[0081] Overview

[0082] The following describes a power amplifier (PA) package and methods for manufacturing a leadless PA package that includes a top-side input / output (I / O) interface and other unique features such as a bottom-side thermal interface. For a given embodiment of a leadless PA package, the top-side I / O interface may include an end that is substantially coplanar with or may be slightly recessed or convex relative to the top-side surface of the package. As presented herein, the term "package top-side surface" refers to the outer main surface of the PA package positioned relative to the base flange or similar die support substrate contained within the PA package. If truncated along a package centerline, the PA package also includes a package bottom-side surface positioned relative to the package top-side surface, the package centerline being an axis extending orthogonally to the die mounting surface of the base flange (corresponding to the "package height direction" described below). Such directional terms are used in a relative sense, where terms such as "upper," "top-side," "lower," and "bottom-side" are defined according to their respective proximity to the package base flange (or similar die support substrate). It should be noted that a given leadless PA package can function in any direction in three-dimensional space. In this latter aspect, when mounted on a component-level substrate such as a motherboard or other printed circuit board (PCB) included in a larger microelectronic system or component, embodiments of the leadless PA package can be mounted in the reverse direction. Furthermore, embodiments of the leadless PA package are conveniently manufactured as flat leadless packages, i.e., leadless packages with a substantially planar top side surface, where the ends or contact pads of the top side I / O interface are substantially coplanar or flush with the top side surface. Again, it should be noted that the ends or contact pads may be slightly recessed or convex relative to the top side surface, for example, due to plating of the exposed contact surfaces after planarization or back-grinding steps. Examples of such flat leadless packages include dual flat leadless (DFN) packages or quad flat leadless (QFN) packages. These embodiments of the leadless PA package can have various leadless form factors when the PA package includes a top side I / O interface and a bottom side thermal interface that may be used to extract excess heat from the PA package, as discussed further below.

[0083] Embodiments of leadless PA packages are advantageously manufactured to include a Dougherty PA architecture, and are described primarily below accordingly. Embodiments of leadless PA packages can be manufactured to have other PA architectures, provided that the PA package contains a radio frequency (RF) power die carrying at least one transistor for power or signal amplification purposes. Furthermore, in embodiments, in addition to a transistor integrated circuit (IC) or multiple transistor ICs serving as amplifier sections or multiple amplifier sections of the PA package, the leadless PA package may also contain additional circuitry. Such additional circuitry can be implemented using discrete microelectronic components such as surface mount devices (SMDs) additionally contained within the leadless PA package and / or possibly using a small PCB (or similar electrical routing substrate) additionally embedded in the PA package. However, more commonly, such additional circuitry (when included in a given instance of a PA package) is formed on a discrete IC die, which is further contained in a leadless PA package and mounted to a support surface or "die mount surface" of the base flange; but in some cases, such additional circuitry may also be formed on a common die having a single-state or multi-stage amplifier circuitry. Thus, in various embodiments, additional IC dies may be included in a given instance of a leadless PA package and carry or emulate IC features that provide any combination of input and / or output impedance matching, transistor biasing, harmonic termination, and other such functions. Therefore, in general, embodiments of leadless PA packages can be described as containing one or more IC dies, wherein at least one IC die (and typically at least two IC dies) takes the form of an RF power die. In the case of the Dougherty PA architecture, specifically, the packaged IC dies will typically include at least one peaking RF power die and at least one carrier RF power die positioned in a parallel amplification path, the parallel amplification path being in the form of peaking and carrier signal amplification paths extending in parallel within the leadless PA package.

[0084] To support the formation of top-side I / O interfaces, a given PA package may include certain basic structures or base elements, upon which other components of the PA package are assembled during PA package manufacturing. Such basic structures may include, for example, base flanges and conductive pillar supports. The conductive pillar supports are spaced apart from the base flange in one or more directions viewed from a die mount plane coplanar with the die mount surface of the base flange. For manufacturing efficiency, the base flange and conductive pillar supports may initially be provided as leadframes with sacrificial leadframe portions (e.g., including tie bars, spars, or similar connecting sections) that physically interconnect the base flange and conductive pillar supports during most of the manufacturing process. Subsequently, after forming the PA package body, the sacrificial portions of the leadframe are removed during individual assembly to electrically isolate the base flange and conductive pillar supports (collectively referred to as the "base structure"). Furthermore, such leadframes can be included in a larger leadframe array containing a relatively large number of interconnecting leadframes and processed globally to produce several leadless PA packages in parallel. While it is possible in embodiments to fabricate instances of leadless PA packages as cavity packages, the leadless PA packages will typically be produced as overmolded or encapsulated packages containing an overmolded package body. In this latter case, after performing certain processing steps (described below), the leadframe array can be encapsulated in an overmolded board, and the overmolded board and the leadframe array (collectively referred to as the “overmolded leadframe array”) subsequently undergo parallel single-drilling processes. Single-drilling of the overmolded leadframe array produces multiple PA packages, each PA package containing an overmolded package body formed by single-drilling of the overmolded board and single-drilling of leadframes embedded in the overmolded package body (e.g., base flanges and post supports).

[0085] During the example PA package manufacturing process, the base structure (base flange and conductive pillar support) is initially placed on the upper surface of a carrier, stage, or similar temporary support surface. As noted above, the base structure is conveniently provided, rather than primarily, in the form of a leadframe. One or more IC dies, including at least one RF power die, are then attached to the die mounting surface of the base flange. Where appropriate, the IC die and pillar support are electrically interconnected by wire bonding or using another interconnection method. In an embodiment, the pillar contacts are physically attached and electrically coupled to the pillar supports, wherein the attachment of the pillar supports occurs at any suitable junction point prior to the encapsulation or overmolding of the PA package. In an embodiment, the pillar contacts may take the form of a metal piece, for example, having a strip or columnar shape factor; as presented herein, the term "metal" refers to a material consisting primarily of one or more metals by weight percentage. As a specific example, in an embodiment, the pillar contacts may be in the form of copper (Cu) or other metal blocks, bars, or similar forms; the term "copper" refers to a metallic material consisting primarily of Cu by weight percentage. The pillar contacts can be connected to the pillar support using a conductive bonding material, such as a conductive die attachment material, solder, or sintered bonding material, examples of which are described below. In one method, a conductive bonding material (e.g., a paste containing metal particles) is printed or otherwise applied to a selected portion of the pillar support or a target mounting location on the pillar support. The pillar contacts are then positioned in the desired location using a pick-and-place tool and cured to complete the electromechanical bonding process. In another embodiment, the pillar contacts can take different forms suitable for providing vertical interconnection with the top-side I / O terminal; for example, the pillar contacts can be provided as conductive features or conductors formed in and passing through a surrounding dielectric body. For example, in this latter case, one or more pillar contacts can be provided using a layout substrate (e.g., a PCB) sheet with metal vias, embossing, or similar conductive features to provide the desired interconnection with the top-side I / O terminal.

[0086] Regardless of the specific manner in which the pillar contacts are provided during the manufacturing process, the pillar contacts are sized and positioned to extend from the pillar support in the package height direction and toward the top side surface of the package. After positioning the pillar contacts, the top side surface of the package is defined by forming a package body, which is the material body, structure, or assembly enclosing the IC die and other electroactive components contained in the PA package. As noted above, embodiments of leadless PA packages are readily manufactured as overmolded or encapsulated packages, including an overmolded package body in which the IC die, pillar support, pillar contacts, and base flange are embedded. In embodiments in which several PA packages are manufactured in parallel, an overmolding process can be performed to produce a relatively large overmolded plate having an excess thickness or overlay covering the upper end of the pillar contacts; the upper end being the pillar contact end furthest from the base flange in the package height direction. Then, a suitable material removal process, such as back-grinding, can be used to thin the overlay molding plate to expose the ends or surfaces of the pillar supports and at least partially define the top-side package surface of the molded package. With the top-side package surface exposed in this way, the upper surface of the pillar support forms the top-side I / O terminals included in the top-side I / O interface of the package. In some embodiments, electroplating can then be performed to deposit a plating finish on the top-side I / O terminals, which may include the exposed surfaces of the pillar contacts and, in some cases, the exposed surfaces of the “top-side terminal isolation structure” discussed further below. When the leadless PA package is produced in parallel with multiple additional PA packages, the electroplating process can be performed by applying a potential to the pillar support and the top-side terminal isolation structure through the lead frame array itself. In this way, in at least some embodiments of this disclosure, the desired plating or multilayer plating system can be easily deposited onto the terminals of the top-side I / O interface without additional processing steps such as solder ball deposition. Next, a single split is performed to divide the leadframe array and molding board into multiple discrete leadless PA packages, each of which includes a top-side I / O interface.

[0087] Embodiments of leadless PA packages are fabricated to include a top-side termination isolation structure, i.e., a conductive structure, that provides shielding to reduce unwanted electromagnetic (EM) coupling during PA package operation, and that structure is electrically coupled to a terminal (e.g., ground) included in the top-side I / O interface. When provided, the top-side termination isolation structure may include at least one central partition or isolation wall extending between separate signal amplification paths within a given leadless PA package. The central isolation wall itself may be at least partially constructed of a conductive (e.g., metallic) material and is electrically coupled to ground during leadless PA package operation; as presented herein, the term "ground" refers to an electrical ground (or similar reference voltage) applied to the terminal of the top-side I / O interface during package operation. In one possible approach, the central isolation wall may include an upper end surface opposite the base flange, which is exposed along the top side surface of the package in a manner similar to that described above for the bonding post contacts. This exposure is achieved, for example, by back-grinding or otherwise thinning (e.g., as included in a larger overmolded package) of the overmolded package. The central isolation wall can be electrically coupled to the base flange by attaching it, for example, using a conductive (e.g., sintered) bonding material. The base flange can then be electrically coupled to a ground terminal included in the packaged RF power die; for example, in the case of a Dougherty amplifier architecture, the peaked and carrier RF power dies can be electrically coupled to the base flange using a conductive bonding material. Therefore, in such embodiments, an electrical connection is provided to the ground terminal (e.g., a bonding pad) of the carrier and peaked RF power die, the electrical connection passing through the base flange, through the central isolation wall and reaching the ground terminal included in the top-side I / O interface, the ground terminal being at least partially defined by the upper surface of the central isolation wall accessible from the top-side surface of the leadless PA package.

[0088] As noted above, in embodiments of leadless PA packages with a Dougherty amplifier architecture or layout, the peaking and carrier RF power dies can be positioned on opposite sides of the central isolation wall. Similarly, when any additional packaged circuitry elements or segments included in the peaking and carrier signal amplification paths are contained within the PA package, such additional circuitry elements can also be positioned on opposite sides of the central isolation structure. For example, any number of impedance matching networks can be implemented using discrete IC dies, which can be deployed on opposite sides of the central isolation wall to reduce EM coupling between amplifier signal paths, thereby enhancing the RF performance characteristics of the PA package. Alternatively or concurrently, the central isolation wall can be sized to span, if not substantially all, of the PA package in a given direction, such as, for example, where the central isolation wall is an elongated longitudinal direction. Therefore, embodiments of the central isolation wall may include: a first end portion terminating at or adjacent to a first sidewall of the package and positioned between a first pair of post contacts (e.g., two input post contacts spaced apart along a first edge of the PA package); a middle portion extending between IC dies located on different signal amplification paths and dividing the IC dies (e.g., separating a peaked RF power die and a carrier RF power die in a Dougherty layout); and a second opposing end portion terminating at or adjacent to a second opposing sidewall of the package and positioned between a second pair of post contacts (e.g., two output post contacts spaced apart along a second edge of the PA package). Additionally, a base flange may be formed to include an extension or "flange connecting strip," which, as seen when viewed downwards on the PA package in the package height direction, is substantially parallel to and extends below the central isolation wall. Furthermore, the flange connecting strip may extend to opposing outer edges or sidewalls of the PA package to allow interconnection of base flanges in leadframe form or leadframe arrays, as previously described.

[0089] Additional electrical isolation can be provided by forming a top-side termination isolation structure, which further includes one or more extensions, fins, or transverse walls extending from the ground isolation wall in a lateral direction—that is, along an axis substantially parallel to the die mount surface of the base flange and substantially perpendicular to the central isolation wall along its elongated axis. For example, as seen when viewed downwards on the die mount surface of the base flange, the top-side termination isolation structure may include one or more lateral isolation wings extending from the central isolation wall and entering separate (e.g., carrier and peaking) signal amplification paths. Such lateral isolation wings may be suspended or protruding above the die mount surface of the base flange at a vertical isolation gap, which may be filled with encapsulant or overmolding material in embodiments in which the PA package is manufactured with an overmolded package. Furthermore, in some cases, lateral isolation wings may extend over one or more RF power dies (e.g., carrier and peaked RF power dies) contained within the PA package and have a lower edge positioned in a non-contact relationship very close to the adjacent surface of the RF power die (again, the term "lower" is defined relative to proximity to the base flange). Due to this positioning, enhanced isolation can be achieved between the input or side of the RF power die and the output or side, specifically because each lateral isolation wing may be at least partially composed of a conductive material electrically coupled to the ground terminal of the PA package through a central isolation wall. In embodiments, the lateral isolation wings and the central isolation wall may be provided as a single piece or an integral structure; in other embodiments, this may not be the case. When utilizing wire bonding to interconnect the RF power dies to achieve the enhanced isolation benefits, the lateral isolation wings may additionally have a height sufficient to exceed the peak bond height. In embodiments, for example when the PA package additionally contains one or more discrete IC dies carrying input-side and / or output-side impedance matching networks, additional lateral isolation wings may be provided to extend over other IC dies that may be included in the PA package and provide additional die-specific I / O bond isolation.

[0090] In the above approach, cost-effective and improved reliable manufacturing processes can be used to fabricate PA packages with a compact leadless form factor and enhanced isolation. As another benefit, embodiments of the PA package can provide enhanced thermal performance by including a unique bottom-side thermal interface. As presented herein, the term "bottom-side thermal interface" refers to an externally accessible interface exposed along the bottom surface of a leadless PA package, through which excess heat can be rapidly extracted from the body of the leadless PA package, and more specifically, from locations adjacent to one or more RF power dies (and possibly other heat-generating components) within the PA package. The bottom-side thermal interface can be, for example, the lower main surface of a metal base flange or other substrate (e.g., a small PCB with imprints or a coreless substrate) exposed at the bottom side of the PA package and substantially coplanar with said bottom side. When the PA package is mounted within a larger electronic component or system, the bottom-side thermal interface can be exposed (uncovered) to allow convective heat transfer to the surrounding environment. However, more usefully, when the PA package is mounted within a larger electronic component, the bottom thermal interface can be thermally coupled to a component-level heatsink to further facilitate the outflow of excess heat from the PA package and dissipate it into the surrounding environment. Such a component-level heatsink can be, for example, a fin array, a metal chassis, or another thermally conductive structure adapted to absorb excess heat extracted from the PA package and transfer or release it to the surrounding environment via convection. Additionally, an electrical connection is formed between the top I / O interface of the PA package and a component-level substrate such as a motherboard, which is mounted to the motherboard in the opposite direction when the PA package is mounted within a larger electronic component or system. Therefore, in a general sense, heat can be extracted from the PA package via conduction in a first general direction (through the bottom thermal interface), while electrical signals are exchanged with the PA package via the top I / O interface in a second opposing direction.

[0091] Considering the enhanced thermal performance and isolation capabilities provided by embodiments of this disclosure, the currently disclosed leadless PA package is well-suited for applications that benefit from increased reliability, minimized system cost, reduced radio size, and greater heat dissipation, such as massive MIMO systems. The PA package is also well-suited for use in conjunction with high power density die technologies that are typically prone to generating excessive heat (specifically, in the case of the Dougherty PA architecture used to fabricate carrier RF power dies). Examples of such high-performance dies include layered base die structures, such as layered gallium nitride (GaN) structures and layered gallium arsenide (GaAs) structures; and IC dies fabricated using certain high-resistivity substrates, such as high-resistivity bulk silicon (Si) substrates, silicon-on-insulator (SOI) substrates, and diamond-based and glass-based substrates. The following will be combined with… Figures 1 to 8The first example leadless PA package with a top-side I / O interface and other unique features (e.g., a top-side termination isolation structure) is described, while example methods for manufacturing such PA packages in combination with multiple similar or identical PA packages are further incorporated below. Figures 9 to 12 Discussion. The following text combines... Figure 13 The discussion can Figures 2 to 8 The leadless PA package shown is mounted in reverse within a larger electronic component or system. Finally, the following section combines... Figure 14 A second example embodiment of a leadless PA package with a top-side I / O interface and a top-side terminal isolation structure is described.

[0092] General discussion of leadless power amplifier packages including top-side terminals

[0093] Figure 1 This is a schematic diagram of the Doherty PA circuit 20 according to an exemplary embodiment of this disclosure. Figure 1 The PA package 22, generally outlined in the diagram, provides one or more portions of the Doughnut PA circuit 20. A leadless PA package 22 can be produced to include leadless top-side I / O interfaces 24, 26, 28, 30, 32, wherein each terminal or contact included in the top-side I / O interfaces 24, 26, 28, 30, 32 is exposed at the top-side package surface of the PA package body 34 of the PA package 22, said top-side package surface being, for example, the outer main surface of the PA package body 34, which may (but not necessarily) have a generally planar or “flat” topology extending generally in the XY plane of coordinate diagram 36. In the present example, specifically, the leadless PA package 22 is implemented as a DFN package having a first set of input terminals 24, 30, a second set of output terminals 26, 32, and at least one ground terminal 28. In other embodiments, the leadless PA package 22 may be fabricated with other top-side I / O interface layouts and various other form factors may be employed depending on, for example, the number and type of microelectronic components (primarily IC dies) contained within the PA package 34, the package component layout and interconnect scheme used, and other design factors. Further description of exemplary implementations of the PA package 22 is set forth below. However, the Dougherty PA circuit 20 is first described in more detail to provide an illustrative, non-limiting context in which embodiments of the PA package 22 can be better understood.

[0094] In the illustrated example, the Dougherty PA circuit 20 includes an input node 38, an output node 40, and a power divider 42 (or power splitter) between nodes 38 and 40. The Dougherty PA circuit 20 also includes a carrier (primary) signal amplification path and at least one peaking (secondary) signal amplification. The power divider 42 is configured to split the power of the input RF signal received at the input node 38 into a carrier portion and a peaking portion, respectively guided along the carrier signal amplification path and the peaking signal amplification path. The carrier and peaking signal amplification paths extend in parallel until they are subsequently reassembled at a power combiner 44 electrically coupled to the circuit output node 40. Figure 1 The Chinese text is marked as "AP" CS As indicated by the first arrow 48, a portion of the carrier signal amplification path extends through the leadless PA package 22. Similarly, as marked "AP PS As indicated by the second arrow 50, a portion of the peaking signal amplification path extends parallel to the carrier signal amplification path (arrow 48) through the PA package 22. During operation of a larger component or system in which the Dougherty PA circuit 20 is housed, the electrical load 46 is coupled directly or via any number of additional circuit elements (e.g., impedance transformers, not shown) to the circuit output node 40. The Dougherty PA circuit 20 is well-suited for incorporation into a larger PA system (e.g., a cellular base station or other wireless communication system), where the load 46 receives amplified RF signals from the Dougherty PA circuit 20 for subsequent airborne radiation via an antenna array.

[0095] The leadless PA package 22 contains a carrier amplifier 52 positioned in a carrier signal amplification path 48 and a peaking amplifier 54 positioned in a peaking signal amplification path 50. Amplifiers 52 and 54 each include at least one power transistor IC for amplifying the RF signal conducted through amplifiers 52 and 54. Each power transistor IC may be fabricated on semiconductor dies 56 and 57 and may have a single-stage or multi-stage configuration. In embodiments, all amplifier stages (or the final amplifier stage) of any one or both of amplifiers 52 and 54 may be implemented using any of the following transistor technologies: silicon-based field-effect transistors (e.g., laterally diffused metal-oxide-semiconductor FETs or LDMOS FETs) or group III-V FETs (e.g., gallium nitride (GaN) FETs, gallium arsenide (GaAs) FETs, gallium phosphide (GaP) FETs, indium phosphide (InP) FETs, or indium antimonide (InSb) FETs, or another type of group III-V transistor). When, for example, the Dougherty PA circuit 20 has a symmetrical configuration, the carrier transistor IC and the peaking transistor IC may be the same size. Alternatively, the carrier transistor IC and the peaking transistor IC may vary in size in various asymmetric Dougherty configurations; it should be understood that the term "size," as used in this context, refers to the effective perimeter or total effective gate width of the power transistor IC. In an asymmetric Dougherty configuration, specifically, the peaking transistor IC may be a multiple of the carrier transistor IC. For example, the peaking transistor IC may be twice the size of the carrier transistor IC, such that the current-carrying capacity of the peaking transistor IC is approximately twice that of the carrier transistor IC. Peaking to carrier amplifier IC size ratios other than 2:1 may also be utilized. For ease of explanation and to reflect the fact that FETs are primarily used to generate PA devices, the foregoing paragraphs and this document as a whole focus primarily on implementations of PA devices (e.g., Dougherty) utilizing FETs. However, in alternative embodiments of this disclosure, other transistor types, including bipolar transistors, may be used. Thus, in general, embodiments of this disclosure are not limited to use in conjunction with any particular transistor type or die technology.

[0096] During circuit operation, the carrier amplifier 52 of the Dougherty PA circuit 20 can be biased to operate in Class AB mode, while the peaking amplifier 54 is biased to operate in Class C mode. At low power levels (e.g., when the power of the input signal applied to input node 38 is less than the turn-on threshold level of the peaking amplifier 54), the Dougherty PA circuit 20 operates in low-power or backoff mode. In low-power (backoff) mode, the carrier amplifier 52 can be the only amplifier supplying current to the load 46. However, when the power of the input signal exceeds the threshold level of the peaking amplifier 54, the Dougherty PA circuit 20 switches to full-power or high-power mode, where both the carrier amplifier 52 and the peaking amplifier 54 simultaneously supply current to the load 46. In this case, the peaking amplifier 54 provides active load modulation at the power combiner 44, thereby allowing a sustained, substantially linear increase in the current output of the carrier amplifier 52. Additionally, since the Dougherty PA circuit 20 operates in full-power mode, during which amplifiers 52 and 54 simultaneously supply current to load 46, the power divider 42 accordingly distributes the input signal power between the signal amplification paths. When the Dougherty PA circuit 20 has a symmetrical Dougherty PA configuration, the power divider 42 can distribute power in a substantially equal manner, such that approximately half of the input signal power is provided to each signal amplification path (arrows 48, 50). In other cases, such as when the Dougherty PA circuit 20 has an asymmetrical Dougherty PA configuration, the power divider 42 can be configured to distribute power unequally between the signal amplification paths (arrows 48, 50). Essentially, the power divider 42 then divides the input RF signal supplied at input node 38, wherein the divided signal portion is then amplified separately along the carrier or "primary" signal amplification path (arrow 48) and the peaked or "secondary" signal amplification path (arrow 50).

[0097] In the example shown, the Dougherty PA circuit 20 also includes two input impedance matching circuits or networks 58, 60 and two output impedance matching circuits or networks 62, 64. Where appropriate, matching networks 58, 60, 62, 64 can be used to increase the circuit impedance incrementally toward the load impedance or source impedance. In some embodiments, matching networks 58, 60, 62, 64 may each be implemented wholly or partially within the PA package 22. For example, as Figure 1 The instructions in the text and in conjunction with the following text Figures 2 to 14In the corresponding example described, input matching networks 58 and 60 may be included within PA package 22; for example, input impedance matching network 58 may be implemented on a discrete IC die included in PA package 22 and located on the first side (“carrier side”) of the central isolation wall 66 (described below), while input impedance matching network 60 may similarly be implemented on a discrete IC die additionally included in PA package 22 and located on the second opposite side (“peaking side”) of the central isolation wall 66. In contrast, in such embodiments, output impedance matching networks 62 and 64 may be implemented on a printed circuit board (PCB) or another component-level substrate on which PA package 22 is mounted, wherein networks 62 and 64 are implemented using any combination of circuit elements formed in the IC die, surface mount device (SMD), or the component-level PCB itself. In other cases, all matching networks, no matching network, or different subsets of matching networks in matching networks 58, 60, 62, and 64 may be integrated into PA package 22. Therefore, there is generally a high degree of design flexibility in implementing PA package 22 and Dougherty PA circuit 20. Furthermore, in more complex embodiments, any one or both of the power amplifiers 52 and 54 may be implemented with multiple parallel amplification paths (rather than having a single amplification path). For example, in an example asymmetric Dougherty configuration, carrier amplifier 52 may be implemented with two (or a greater number) parallel amplification paths, while peaking amplifier 54 may be implemented with three (or some other number) parallel amplification paths. Additionally, in the case of an N-channel Dougherty amplifier (N>2), PA package 22 may contain multiple peaking amplifiers with different configurations or levels.

[0098] exist Figure 1In a relatively simple example, the Dougherty PA circuit 20 has a standard load network configuration. Therefore, the input-side circuitry is configured such that, at, for example, the center operating frequency of the Dougherty PA circuit 20, the input signal supplied to the peaking amplifier 54 is delayed by 90 degrees relative to the input signal supplied to the carrier amplifier 52. To ensure that the carrier input RF signal and the peaking input RF signal arrive at amplifiers 52 and 54 with a phase shift of approximately 90 degrees, a first phase delay element 68 can be incorporated into the Dougherty PA circuit 20 to provide a phase delay of approximately 90 degrees to the peaking input signal. For example, the phase delay element 68 may comprise a quarter-wavelength transmission line, or another suitable type of delay element with an electrical length of approximately 90 degrees. To compensate for the resulting 90-degree phase delay difference at the inputs of amplifiers 52 and 54 between the carrier amplification path and the peaking amplification path (arrows 48, 50), and thereby ensure that the amplified signals arrive in phase at the power combiner 44, the output-side circuitry is similarly configured to apply a phase delay of approximately 90 degrees to the signal between the output of the carrier amplifier 52 and the power combiner 44. This can be achieved by providing an additional phase delay element 70. While the Dougherty PA circuit 20 has a standard load network configuration in the illustrated embodiment, other load network configurations may be possible in other embodiments. For example, in an alternative embodiment, the Dougherty PA circuit 20 may be modified to have an alternative (or "opposite") load network configuration. In this case, the input-side circuitry may be configured such that, at the center operating frequency of the Dougherty PA circuit 20, the input signal supplied to the carrier amplifier 52 is delayed by 90 degrees relative to the input signal supplied to the peaking amplifier 54. Accordingly, the output-side circuitry may be configured to apply a phase delay of approximately 90 degrees to the signal between the output of the peaking amplifier 52 and the power combiner 44.

[0099] The leadless PA package 22 is manufactured to include top-side I / O interfaces 24, 26, 28, 30, and 32. Furthermore, as by... Figure 1 As indicated by Figure 72 shown in the lower right corner, the top-side I / O interfaces 24, 26, 28, 30, and 32 may include the following "terminals" or ends: (i) input terminals 24 and 30; (ii) output terminals 26 and 32; and (iii) at least one center ground terminal 28. The ends of the top-side I / O interfaces 24, 26, 28, 30, and 32 are accessible from the top surface of the leadless PA package 22, thereby facilitating the mounting of the PA package 22 in larger electronic systems or components using various surface mount methods, as described below. Figure 13Further discussion. As discussed in detail below, ends 24, 26, 30, and 32 may be formed by the exposed end surfaces of a plurality of elongated pillar contacts 74 extending from the conductive pillar support 76 in the package height direction (corresponding to the Z-axis of coordinate diagram 36). The pillar contacts 74 and the pillar support 76 are made of conductive material; and in some embodiments, some or all of the pillar contacts 74 may be integrally formed as a single piece or a single unit (e.g., metal) with their associated conductive pillar support 76. However, more commonly, the pillar contacts 74 are implemented using elongated metal blocks, rods, or similar conductive structures mounted to the pillar support 76 using conductive bonding materials and, in some cases, sintered bonding materials. Thus, a conductive path is created from the upper end surface of the pillar support 76 defining the top-side ends 24, 26, 30, and 32 to the associated pillar support 76. The pillar support 76 is then electrically coupled to the appropriate end (e.g., bonding pad) of the IC die contained in the leadless PA package 22. Similarly, electrical interconnects are formed between the input matching networks 58, 60 and the RF power die 56, either through wire bonding or by utilizing another interconnect technology, such as 3D printing technology that uses conductive ink to form conformal traces. The following section combines... Figures 2 to 8 Additional descriptions are provided for the column contact 74 and the column support 76.

[0100] Continue to refer to Figure 1 The leadless PA package 22 also includes top-side termination isolation structures 66, 84. While a wide range of forms are possible, in the example shown, the top-side termination isolation structures 66, 84 include the aforementioned central isolation wall 66 and several lateral isolation wings 84. Furthermore, in Figure 1 In the schematic diagram, the dimensions and positioning of the central isolation wall 66 and the lateral isolation wings 84 are drawn in a general conceptual sense. The following will combine... Figures 2 to 8A more realistic example of the internal isolation structures 66, 84 is presented. This feature of the PA package 22 with respect to the first central isolation wall 66 may take the form of a conductive (e.g., metallic) fin-like body or component extending in the package height direction (again, corresponding to the Z-axis of coordinate diagram 36) from or near the top side surface of the PA package 22 toward the die attachment surface of the aforementioned base flange 78 further contained within the PA package 22. In embodiments, the central isolation wall 66 may be physically attached and electrically coupled to the base flange 78 at the wall-flange interface by, for example, bonding using a sintered bonding material or another conductive bonding material. As indicated by the crosshair pattern identified in Figure 72, the upper surface or ridge of the central isolation wall 66 (i.e., the surface of the central isolation wall 66 furthest from the die mounting surface of the base flange 78) may be exposed along the top side surface of the PA package 22 to define a top-side ground terminal, possibly together with similar exposure of the upper surface or ridge of the lateral isolation wing 84. As discussed further below, these exposed surfaces may be plated or left bare; it should be noted that the surfaces of the central isolation wall 66, the lateral isolation wings 84 (if exposed), and the pillar contacts 74 are considered to be exposed at or along the top surface of the package when plated or otherwise coated with one or more layers of conductive material (and therefore accessible from the top surface of the package).

[0101] With the above structural arrangement, the central isolation wall 66 provides a relatively large electrical path between the ground terminals of the top-side I / O interfaces 24, 26, 28, 30, 32 and the base flange 78 in the lower portion of the embeddable package 34. Furthermore, considering the relatively expensive surface area of ​​the top-side terminal isolation structures 66, 84, as measured in the XY plane of coordinate diagram 36, a relatively large surface area is used for bonding and conductivity when the PA package 22 is mounted within a larger electronic system or assembly. The RF power die 56 may also include a ground terminal or bonding pad, which is electrically coupled to the base flange 78, for example, by attaching the RF power die 56 to the die mounting surface of the base flange 78 using a conductive bonding material such as a sintered metal (e.g., a silver (Ag-containing) bonding layer). Therefore, a robust electrical grounding path is formed, extending from the top-side ground terminal 28 of the PA package 22 (again defined by the plated or unplated surface exposed on the upper part of the top-side terminal isolation structures 66, 84) through the body of the central isolation wall 66, through the base flange 78, and to the corresponding ground terminals of the RF power die 56 and the transistor IC circuitry (peaking and carrier amplifiers) integrated in the RF power die 56. Furthermore, as in Figure 1As can be seen, the carrier RF power die 56 carrying the carrier transistor IC 52 and the peaking RF power die 56 carrying the peaking amplifier IC 54 are positioned on opposite sides of the central isolation wall 66. As a grounded conductive structure, the central isolation wall 66 provides EM shielding between the RF power dies 56 to reduce or eliminate unwanted EM coupling between the carrier transistor IC 52 and the peaking amplifier IC 54. Furthermore, as... Figure 1 As indicated, the central isolation wall 66 may extend from a position adjacent to the first package sidewall 80 to a position adjacent to the second opposing package sidewall 82 of the PA package 22. Thus, the central isolation wall 66 may span substantially the entire length of the signal amplification paths 48, 50; and span, if not substantially the entire length, of the PA package 22, as measured along the X-axis of coordinate diagram 36.

[0102] Therefore, the central isolation wall 66 can be described as having: a first end portion extending between the first pair of pillar contacts (corresponding to the top side ends 24, 30); a second end portion extending between the second pair of pillar contacts (corresponding to the top side ends 26, 32); and an intermediate portion located between the first end portion and the second end portion, wherein the RF power die 56 carrying the carrier amplifier 52 and the RF power die 56 carrying the peaking amplifier 54 are located on opposite sides of the intermediate portion of the central isolation wall. Thus, the central isolation wall 66 provides full or complete EM shielding along the package length direction (corresponding to the X-axis of coordinate diagram 36). Furthermore, in an embodiment, in the package height direction (corresponding to the Z-axis of coordinate diagram 36), the central isolation wall 66 may extend away from the die mounting surface of the base flange 78 and sufficiently extend to the top side surface of the PA package 22. Therefore, in such embodiments, the central isolation wall 66 further provides EM isolation between the top ends 24, 30 (and corresponding post contacts 74) positioned adjacent to the package sidewall 80, which are separated by a first intermediate end portion of the wall 66 when viewed in the package width direction (corresponding to the Y-axis of coordinate diagram 36). Similarly, the central isolation wall 66 further provides EM isolation between the top ends 26, 32 (and corresponding post contacts 74), which are separated by a second end portion of the wall 66 when viewed in the package width direction. Thus, between the carrier signal amplification path (arrow 48) and the peaking signal amplification path (arrow 50), the central isolation wall 66 provides EM shielding or isolation along all or substantially all portions of these paths.

[0103] As indicated above, embodiments of the PA package 22 may be manufactured to include one or more isolation fins, transverse walls, or wings 84 extending from the central isolation wall 66 in a lateral direction (corresponding to the "package width direction" and parallel to the Y-axis of coordinate diagram 36). When provided, the lateral isolation wings 84 may be suspended above the die mounting surface of the base flange 78 at a predetermined vertical spacing or isolation gap. Although Figure 1 Not shown, but for clarity, the IC dies carrying input matching networks 58, 60 and / or the RF power dies carrying amplifier ICs 52, 54 may be positioned under the lateral isolation wings 84 such that each isolation wing 84 extends with a close but non-contact proximity to the middle portion or center segment of each die. Meanwhile, as measured in the package height direction (corresponding to the Y-axis of coordinate diagram 36), the isolation wings 84 may have a height sufficient to extend to an upper terminal point adjacent to and possibly substantially coplanar with the upper end surface of the central isolation wall 66. Furthermore, in embodiments where the various electrical interconnections between IC dies are formed by wire bonding, the upper end surface of the lateral isolation wings 84 (again, the surface of the isolation wing 84 furthest from the base flange 78 when viewed in the package height direction) may be located closer to the top side surface of the package (and, in fact, substantially coplanar with said top side surface) compared to the bonding wires obtained at peak bonding wire height. Considering this positioning, and further considering the electrical coupling (and possibly integral formation) of the lateral isolation wings 84 to the ground center isolation wall 66, each isolation wing 84 can provide additional electrical isolation or shielding between the input and output sides (bonding pads) of the dies carrying circuits 52, 54, 58, 60 and between the bond wires electrically coupled to each end. Despite these advantages, in alternative embodiments, the lateral isolation wings 84 and possibly the center isolation wall 66 can be omitted from the PA package 22.

[0104] Now refer to Figures 2 to 8 The leadless PA package 22 is shown from a series of perspectives. Figure 1 An example embodiment of the leadless PA package 86 is referred to below as "leadless PA package 86". In this particular example, the leadless PA package 86 is manufactured as an overmolded package or encapsulated package including an overmolded package body 88 having a top surface 90 and a bottom surface 92 opposite each other in the package height direction (corresponding to the Z-axis of coordinate diagram 94). Figure 4 A molded encapsulated package 88 is formed above and around various internal structures or components of the leadless PA package 22, said internal structures or components including a base flange 96 and a plurality of pillar supports 97 to 100 (generally corresponding to...). Figure 1 The base flange 78 and column support 76 are shown. Figures 2 to 8The molded package 88 is at least partially depicted with dotted lines or hidden from view to more clearly show the interior of the leadless PA package 22; however, the lower dielectric body portion 102, in which the base flange 96 and pillar supports 97 to 100 are embedded, is also shown. (See below for further details.) Figures 9 to 12 More fully, the lower dielectric body portion 102 can be integrally formed with the remainder of the overmolded package 88 as a single overmolded body. In an alternative embodiment, the lower dielectric body portion 102 can be formed via an initial overmolding process, while the remainder of the overmolded package 88 is subsequently formed using a second overmolding process. As another possibility, the lower dielectric body portion 102 may not be overmolded and may instead be made of ceramic, PCB resin, or another dielectric material; in this case, the lower dielectric body 102, the base flange 96, and the pillar supports 97 to 100 can initially be produced as a prefabricated structure; for example, in this case, the prefabricated substrate may be purchased from a supplier or otherwise obtained as a single unit or in the form of an interconnect board.

[0105] The base flange 96 includes an upper surface 104 (referred to herein as "die mounting surface 104") and an opposing lower flange surface 106. A plurality of IC dies 108 to 111 are attached to different locations distributed on the die mounting surface 104 of the base flange 96. In at least some embodiments of the leadless PA package 86, the die mounting surface 104 may extend substantially parallel to the top side surface 90 of the package. The leadless PA package 86 shown has a Dougherty amplifier architecture and generally corresponds to the above-described combination. Figure 1 In the example of the leadless PA package 22 described, the PA package 86 contains four IC dies 108 to 111: (i) the first IC die 108 (referred to herein as "MN") carrying the carrier-side input matching network. CS (ii) A second IC die 109 (referred to herein as "MN") carrying the peaking-side input matching network. PS (iii) a third IC die 110 carrying a carrier amplifier IC (referred to herein as "carrier RF power die 110"); and (iv) a fourth IC die 111 carrying a peaking amplifier IC (referred herein as "peaking RF power die 111"). CS Die 108 and carrier RF power die 110 are positioned in the carrier signal amplification path, which extends through the leadless PA package 86 and is... Figure 3 The first arrow 112 shown in the upper part indicates this. Conversely, MN PS Die 109 and peaked RF power die 111 are positioned in the carrier signal amplification path, which also extends through PA package 86 and is... Figure 3 The second arrow 112 shown in the lower part indicates this.

[0106] Several pillar contacts 116 to 119 and a central isolation wall 120 are further embedded in an overmolded package 88. As discussed below, the upper surfaces of the pillar contacts 116 to 119 and the central isolation wall 120 may be exposed along the top surface 90 of the package to define top-side I / O interfaces 121, 122, 123, 124, and 125. In the example shown, specifically, the upper surface of pillar contact 116 defines a top-side carrier input 121, the upper surface of pillar contact 117 defines a top-side carrier output 122, the upper surface of pillar contact 118 defines a top-side peaked input 123, the upper surface of pillar contact 119 defines a top-side peaked output 124, and the upper surface of the central isolation wall 120 defines a top-side ground 125. Specifically, the top-side ground terminal 125 may be further defined by several transverse wall structures extending from the central isolation wall 120 or by the exposed upper surface or ridge of the "lateral isolation wings" 126 to 129; however, this may not be the case in alternative embodiments where the lateral isolation wings 126 to 129 terminate in the height direction before breaking through the top-side surface 90 of the package (or when the lateral isolation wings 126 to 129 are omitted entirely from the leadless PA package 86). In embodiments, the post contacts 116 to 119 defining the top-side terminals 121, 122, 123, 124, 125 and the upper surface of the central isolation wall 120 may be plated or otherwise coated with at least one layer of conductive material. In other embodiments, the post contacts 116 to 119 defining the top-side terminals 121, 122, 123, 124, 125 and the upper surface of the central isolation wall 120 may remain bare or unplated. In any case, the upper surface of the pillar contacts 116 to 119 defining the top sides 121, 122, 123, 124, 125 and the central isolation wall 120 is considered exposed when accessible from the top side surface 90 of the package for electrical connection to a corresponding electrical interface provided on the motherboard or other component-level substrate, as described below. Figure 13 To elaborate more fully.

[0107] Post contacts 116 to 119 are each attached to post supports 97 to 100 and extend upward from post supports 97 to 100 in the package height direction. Post contacts 116 to 119 may each be elongated in the package height direction and have sufficient height to extend from post supports 97 to 100 to the top side surface 90 of the package. In an embodiment, the height of post contacts 116 to 119 (in...) Figure 5 and 6 The height (as indicated by the first arrow 140) may exceed and possibly be at least twice the height or thickness of the base flange 96, as measured in the package height direction and as indicated by... Figure 5 and 6As indicated by the second arrow 142 in the diagram. In the example shown, the height of the center isolation wall 120 (when provided) may also exceed the height or thickness of the base flange 96 and may be substantially equivalent to the corresponding heights of the pillar contacts 116 to 119. The center isolation wall 120 extends further along its length and may extend, if not the entire length of the leadless PA package 86, but most of its length, as measured in the package length direction (corresponding to the X-axis of coordinate diagram 94). Thus, the center isolation wall 120 may extend from a first position adjacent to the first sidewall of the overmolded package 88 across the widened portion of the base flange 96 between the pillar contacts 116, 117, between the pillar contacts 118, 119, and into the second opposing sidewall of the overmolded package 88. In other words, the center isolation wall 120 includes a first end portion positioned between a pair of pillar contacts 116, 117, and positioned at MN CS die 108 and MN CS The middle portion between the dies 109 and between the carrier RF power die 110 and the peaked RF power die 111, and the second end portion located between a pair of post contacts 118, 119.

[0108] The central isolation wall 120 is bonded to the die mounting surface 104 of the base flange 96; and in an embodiment, the central isolation wall 120 may be electrically coupled to the base flange 96 using a conductive bonding material such as a sintered bonding material. Figure 4 As most clearly shown, a base flange 96 is formed to include a body, with two extensions or “flange connecting strips” 130 extending from the body in opposite directions. The flange connecting strips 130 are located beneath the central isolation wall 120 (as seen when viewed downwards on the die mounting surface 104 of the base flange 96), extend substantially parallel to the central isolation wall 120, and extend sufficiently to (and thus break through) the opposing package sidewalls adjacent to the post contacts 116 to 119. When present, the flange connecting strips 130 provide at least two benefits. First, the flange connecting strips 130 provide an increased surface area for engagement with the central isolation wall 120 (e.g., metallurgically) along its entire or substantially entire length to provide a high-strength, low-resistance contact at this interface. Second, the flange die strips 130 facilitate providing the base flange 96 as a lead frame, which also includes post supports 97 to 100. The following is combined with… Figure 9 Discuss examples of this type of leader frame.

[0109] Different groups of bonding wires 132 to 138 are used for conductive pillar supports 96 to 100 and IC dies 108 to 111. For example, and first referring to the carrier signal amplification side of the leadless PA package 86, the first group of bonding wires 132 electrically couples the pillar support 94 to MN. CS Input pad of die 108; second set of bonding wires 133 will connect MNCS The input and output pads of die 108 are electrically coupled to the input pad of carrier RF power die 110; and a third set of bonding wires 134 electrically couples the output pad of carrier RF power die 110 to pillar support 94. Similarly, referring to the peaking signal amplification side of leadless PA package 86, a fourth set of bonding wires 135 electrically couples pillar support 96 to MN. PS Input pad of die 109; fourth set of bonding wires 136 will connect MN PS The input and output pads of die 109 are electrically coupled to the input pad of peaked RF power die 111; and the sixth bonding wire 137 electrically couples the output pad of peaked RF power die 111 to the pillar support 100. In this way, the conductive carrier signal amplification path ( Figure 3 Arrow 112 is formed to extend from the top end 121, through the post contact 116, through the post support 97, and finally to the carrier RF power die 110; and extends from the carrier RF power die 110, through the post support 98, through the post contact 117, and to the top end 122. Similarly, the conductive peaking signal amplification path ( Figure 3 Arrow 114 is formed to extend from top end 123, through post contact 118, through post support 99 and finally to peaked RF power die 111; and from peaked RF power die 111, through post support 100, through post contact 119 and to top end 124. Given the positioning and dimensional specification of the central isolation wall 120 in the package length (X-axis) and package height (Z-axis) directions, the central isolation wall 120 provides in-package EM shielding across substantially the entire signal amplification path to optimize RF performance. The central isolation wall 120 is thermally imparted to the bonding wires 132 to 138 exceeding the peak bonding wire height truncated along the entire carrier and peaked signal amplification paths. Therefore, isolation is provided between the carrier and peaked sections of the Dougherty PA package 86 via the central isolation wall 120, while simultaneously grounding the top-side termination of the RF power dies 110, 111.

[0110] As indicated above, embodiments of the leadless PA package 22 may be manufactured including one or more lateral isolation wings 126 to 129 extending from the central isolation wall 120 in the lateral direction (corresponding to the "package width direction" and parallel to the Y-axis of coordinate diagram 94). When provided, the lateral isolation wings 126 to 129 may be suspended above the die mounting surface of the base flange 78 at predetermined vertical intervals or isolation gaps, such as... Figures 5 to 8 The most clearly shown is the lateral isolation wings 126 to 129, positioned on the die mounting surface 104 of the base flange 96 and extending over the IC dies 108 to 111, while being suspended in a non-contact relationship above them. Figure 7 and 8As most clearly shown, the lateral isolation wings 126 to 129 can each extend between the input and output pads of a given IC die 108 to 111 to provide EM isolation between specific bond lines 132 to 138 connected to the input and output pads of the IC die. Sufficient spacing is provided to accommodate the arched path following the bond lines 132 to 138, but there is no contact between the bond lines 132 to 138 and the lateral isolation wings 126 to 129. It should also be noted that the depicted structure is embedded in the overmolded package 88 (in... Figure 7 and 8 (Hidden and invisible). Regarding MN PS The bonding wire 136 electrically couples die 109 to peaked RF power die 111. Figure 7 Specifically, one or more bonding wires 136 may extend upward from the die 109, 110 in a direction opposite to the base flange 96 and enter the space between the lateral isolation wings 128, 129. Similarly, MN... CS Die 108 is electrically coupled to one or more bonding wires 136 of the carrier RF power die 110. Figure 8 The lateral isolation wings 128 and 129 extend upwards from the dies 108 and 110 into the space between the lateral isolation wings 126 and 127. The lateral isolation wings 128 and 129 thus provide additional electrical isolation or EM shielding between the input and output sides of the IC dies 108 to 111 and the associated bond wires 132 to 138 to further enhance the RF performance of the PA package 22. Furthermore, in at least some embodiments of the PA package 86, the bond wires 132, 134, 135, and 137 can be easily sized as appropriate to compensate for the inductance added by providing the post contacts 116 to 119.

[0111] Embodiments of a leadless PA package 22 may also be produced to include a bottom-side thermal interface 144. Figure 4 The bottom-side thermal interface 144 is formed by exposing the lower flange surface 106 through the package bottom-side surface 92; for example, in an embodiment, the lower flange surface 106 may be substantially coplanar with the package bottom-side surface 92, or may extend beyond the package bottom-side surface 92 by some amount. In contrast, and as... Figure 5 and 6 As indicated by arrow 153, the pillar supports 97 to 100 have a reduced thickness (e.g., a half-etched feature) to ensure that the pillar supports 97 to 100 do not extend sufficiently into the bottom surface 92 of the package to prevent electrical bridging when the conductive component-level heat sink is positioned to contact the bottom surface 92 of the package and the lower flange surface 106, and in this case, as described below. Figure 7 and 8The image is further indicated by heat extraction arrow 146, thus forming a direct, dimensionally robust heat extraction path extending from IC dies 109 to 111 through the thermally conductive bonding layer of die mounting surface 104 for attaching IC dies 109 to 111 to base flange 96 and extending to lower flange surface 106. When such a component-level heat sink is present within a larger electronic component in which the PA package 18 is ultimately mounted, an efficient, direct (non-tortuous), and volumetrically robust heat conduction path is used to transfer excess heat from IC dies 109 to 111, and specifically from RF power dies 110, 111, to the component-level heat sink outside the leadless PA package 86. In a general sense, the electrical and thermal paths of the leadless PA package 22 are thus separated, traveling in opposite directions through the PA package 22 so that the PA package 22 can be mounted between the component-level substrate for electrical connection and the component-level heat sink for heat dissipation. Specifically, when RF power dies 110 and 111 (and most relevantly, carrier RF power die 110) are manufactured using power-dense die technologies such as GaN layered die structures, this provides an efficient thermal management solution to further optimize RF power die performance. The following section combines... Figure 13 Provide additional details on this aspect. However, firstly, combine... Figures 9 to 12 Examples of manufacturing processes suitable for producing leadless PA packages 22 and several similar PA packages are discussed.

[0112] Example method for manufacturing a leadless PA package with top-side terminals

[0113] Figures 9 to 12 Showing the various manufacturing stages Figures 2 to 8 The example shown is a leadless PA package 86. First, refer to... Figure 3 The leadless PA package 86 is shown as being in an intermediate manufacturing stage and is therefore identified by the reference numeral "86`". The basic symbol (`) is added to the reference numeral when indicating structural components in an unfinished or partially manufactured state. Additionally, in Figure 9 A leadless PA package 86 is fabricated using a leadframe-based manufacturing method, wherein a limited area of ​​a leadframe array 148 is shown. The leadframe array 148 is processed to produce a plurality of additional leadless PA packages 150 in parallel with the leadless PA package 86. The process steps described below in conjunction with the leadless PA package 86 are performed globally across the leadframe array 148, and therefore should be understood to apply equally to the additional leadless PA packages 150 and other unshown leadless PA packages produced in parallel with the leadless PA package 86. For this reason, Figures 10 to 12The focus is on the portions of the leadframe array 148 that are processed to specifically produce the leadless PA package 86 (i.e., leadframes 96 to 100, 152), but the processing of leadframes 96 to 100, 152 (and, when produced, the larger overlay molding) is not shown on a larger scale.

[0114] In the illustrated example embodiment, IC dies 108 to 111 are attached to a base flange 96 included in lead frames 96 to 100, 152, and bonding wires 132 to 137 are formed prior to the attachment of post contacts 116 to 119 and top-side terminal isolation structures 120, 126 to 129. Thus, IC dies 108 to 111 are placed in their desired positions on the die mounting surface 104 of the base flange 96 and bonded to said desired positions using a suitable bonding material. In embodiments where it is desired to electrically couple one or more of IC dies 108 to 111 to the base flange 96 (e.g., as in the case of carrier RF power die 110 and peaked RF power die 111), a conductive bonding material is used. In one embodiment, one or more sintered bonding layers may be used, and the one or more sintered bonding layers may be formed by depositing a sintered precursor material and subsequently curing the sintered precursor material to form a sintered bonding layer that attaches one or more of the IC dies 108 to 111 to the base flange 96. In embodiments, such sintered bonding layers are also advantageously used to attach post contacts 116 to 119 and top-side terminal isolation structures 120, 126 to 129 to the base flange 96. In other embodiments, various conductive materials may be used to provide mechanical and electrical connections to the base flange 96 at the desired locations, including solder and conductive die attachment materials, such as metal-filled (e.g., Ag-filled) epoxy resins. The IC dies 108 to 111 may initially be provided on tapes and reels, or using another medium, and placed at the desired locations using pick-and-place tools. The selected bonding material can be applied to the appropriate location on the base flange 96 before die placement and can be thermo-cured or UV-cured after die placement. After attaching IC dies 108 to 111, ball bonding and other wire bonding techniques are performed to produce bond wires 132 to 137.

[0115] Next reference Figure 10The post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 are positioned onto the post supports 97 to 100 and the base flange 96, respectively. In the illustrated embodiment, the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 are placed as discrete units; however, in other embodiments, the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 may be positioned as an array. Similarly, a conductive bonding material is used to form desired mechanical and electrical contacts between the post contacts 116 to 119 positioned on the post supports 97 to 100 and the base flange 96 and the top-side terminal isolation structures 120, 126 to 129. As noted above, various conductive bonding materials can be used, including solder, metal-filled (e.g., Ag-filled) epoxy resins, and conductive die attachment materials. In other embodiments, the column contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 can be connected to the column supports 97 to 100 and the base flange 96 using a sintered bonding layer; said sintered bonding layer is a bonding layer formed from sintered metal particles and consisting primarily of one or more metal components by weight. When formed from such sintered materials, the bonding layer may consist primarily of Cu, Ag, gold (Au), or mixtures thereof by weight. Additionally, in such cases, the sintered bonding layer may or may not contain organic materials, such as epoxy resin added for reinforcement purposes. In some embodiments, the sintering precursor material is applied using wet or dry (e.g., film) application techniques. For example, in one method, the sintering precursor material can be deposited onto selected areas of the column supports 97 to 100 and the base flange 96 by screen printing or stencil printing or by using a fine-needle application technique. In other embodiments, before the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 are placed onto the post supports 97 to 100 and the base flange 96, a sintering precursor material (e.g., by spraying or impregnation) may be applied to the appropriate surfaces of the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129. Subsequently, curing may be performed by low-temperature heating (with or without pressure) to transform the sintering precursor material into a sintered bonding layer, thereby forming a metallurgical bond at various interfaces between the post contacts 116 to 119, the top-side terminal isolation structures 120, 126 to 129, the post supports 97 to 100, and the base flange 96.

[0116] After the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 are attached, the aforementioned components included in the partially manufactured leadless PA package 86' (and more generally, the lead frame array 148) are overmolded. Overmolding may involve applying a suitable encapsulating material (e.g., a thermosetting polymer) in a heated, flowable state. An overmolded plate (including...) is formed. Figure 11The overmolded package 88 shown has an excessive thickness or overlay having fully encapsulated post contacts 116 to 119 and top-side terminal isolation structures 120, 126 to 129. Thereafter, the overmolded package 88 (and more broadly, the overmolded plate) is thinned by removing material from the top-side surface 90 of the package. For this purpose, a back-grinding process can be used, where the term back-grinding encompasses various grinding and polishing processes suitable for removing material from the overmolded package 88 (and generally, the overmolded plate) in a controlled manner. The top-side package surface 90 is back-grinded to expose the respective upper surfaces of the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129, thereby creating a top-side I / O interface including top-side I / O terminals 121 to 125. Figure 12 (As shown in the diagram). If necessary, the newly exposed top-side I / O terminals 121 to 125 can be electroplated to form a suitable plating finish on the top-side I / O terminals 121 to 125, and possibly on other exposed metal areas of the partially manufactured PA package. In embodiments, such plating layers may be made of tin (Sn), nickel-palladium-gold (NiPdAu), or another metallic material. It is worth noting that if the leadframe array 148 remains electrically coupled to the post contacts 116 to 119 and the top-side terminal isolation structures 120, 126 to 129 at the current junction point during manufacturing, such electroplating can be performed by applying a potential to the leadframe array 148 itself. Finally, the overlay molding plate and the leadframe array 148 are individually separated (e.g., by sawing) to produce a plurality of leadless PA packages including leadless PA packages 86. The individual separation removes the sacrificial portion 152 (in) from the leadframe array 148. Figure 9 (Identified in the middle) Electrically isolated post contacts 116 to 119 and top-side terminal isolation structures 120, 126 to 129. In another embodiment, the sacrificial portion 152 may be reduced in one or more dimensions, a groove may be formed on the bottom side of the sacrificial portion 152, or a similar volume reduction modification may be made to the sacrificial portion 152 to minimize the volume of metal through which the saw blade passes during a single segment of the lead frames 96 to 100, 152.

[0117] Therefore, an example method for manufacturing a leadless PA package 86 in parallel with multiple similar PA packages has been described above. Other embodiments of the manufacturing process may differ in various ways. For example, in alternative manufacturing methods, bonding materials such as a paste containing metal particles (e.g., Ag) may initially be printed or otherwise applied across the lead frame array 148 in a desired pattern; IC dies 109 to 111, post contacts 116 to 119, and top-side terminal isolation structures 120, 126 to 129 may then be positioned across the lead frame array 148 and positioned at appropriate mounting locations on post supports 97 to 100 and base flange 96; and a global curing step may be performed to simultaneously bond IC dies 109 to 111, post contacts 116 to 119, and top-side terminal isolation structures 120, 126 to 129 to post supports 97 to 100 and base flange 96. Further processing steps, such as plasma cleaning, may then be performed, followed by interconnection (e.g., wire bonding), overmolding, and separation, as previously described. In other embodiments, similar processing steps may be followed, with post contacts 116 to 119 and / or top-side terminal isolation structures 120, 126 to 129 provided in the form of an interconnect array, which is separated into electrically isolated portions by the leadframe array 148 and the separation of the overmolding plate. Alternatively, in other embodiments, post contacts 116 to 119 and / or top-side terminal isolation structures 120, 126 to 129 may be integrally formed with the leadframe array 148 to improve manufacturing through the aforementioned post contact and isolation structure attachment steps (but with the potential trade-off of higher costs when manufacturing or purchasing the leadframe array itself). Finally, in another embodiment, the leadless PA package 86 may be produced as a cavity package rather than an overmolded or encapsulated package. For example, in this latter case, embodiments of the leadless PA package can be manufactured as a covered cavity package, wherein an opening is provided in the cover or enclosure of the PA package to allow access to the upper ends of the pillar contacts included in the top-side I / O interface. This approach can be more practical when the PA package is large in size.

[0118] Although described above primarily as conductive (e.g., metallic) blocks or similar structures, the pillar contacts 116 to 119 can take any form suitable for providing a conductive path from pillar supports 98 to 100 to the corresponding top-side terminals 121 to 124. For example, in other embodiments, pillar supports 98 to 100 can be provided in the form of electrically laid substrate sheets or strips, such as substrate (e.g., single-layer or multi-layer PCB) portions or sheets, with conductive features along... Figures 2 to 4The Z-axis of the coordinate diagram 94 shown (generally parallel to the package height direction or centerline of the PA package 86) extends through the portion or sheet. For example, the sheet of ceramic, PCB, or other base dielectric substrate may be fabricated to contain via clusters or fields, metal imprints, or similar conductive features, thereby allowing electrical connections to be made vertically through the substrate sheet. Additionally, in such embodiments, ground vias or similar electrical grounding features may be formed in the disposed substrate sheet to achieve additional EMI shielding at target locations within the leadless PA package 86, for example, between pillar contacts 116 to 119 that conduct gate and drain signals to the FET circuitry carried by the RF power dies 110, 111. Such electrical grounding features may take the form of ground vias, metal imprints, or other conductive features that may coaxially surround the signal-carrying vias or imprints, or conversely, may extend vertically along selected edges or sidewalls of the substrate sheet serving as pillar contacts 116 to 119 (e.g., pillar sidewalls facing inward toward the package interior). Furthermore, in such embodiments, a single sheet or segment of the substrate can be used to provide multiple pillar contacts when the dimensions are appropriate. For example, see reference... Figure 2 and 3 On the left side of the PA package 86, in the illustrated example, the left end of the central isolation wall 120 may be shortened (or the central isolation wall 120 may be omitted) so that a single substrate piece having a generally rectangular planar shape can span the area occupied by the pillar contacts 116, 118, wherein an imprint or via cluster is formed at an appropriate location in the substrate piece to serve as the pillar contacts 116, 118. A similar approach can also be used to replace the pillar contacts 117, 119 at this location within the package with a PCB, ceramic, or other substrate piece or strip. Typically, the pillar contacts 116 to 119 can then be provided in various forms to achieve the desired electrical connection between the pillar supports 98 to 100 and the top-side terminals 121 to 124, including one or more electrically laid substrate pieces, as conductive (e.g., metal) blocks, or combinations thereof.

[0119] The statements in the preceding paragraph also apply to the top-side termination isolation structures 120, 126 to 129 additionally included in the leadless PA package 86. In this latter aspect, the top-side termination isolation structures 120, 126 to 129 may be provided as a monolithic or integral conductive (e.g., Cu or other metal) element, as a plurality of conductive elements assembled in some manner, or as an electrical layout substrate (e.g., a single-layer or multi-layer PCB, ceramic substrate, or other dielectric substrate) having through-holes, imprints, or other conductive features that vertically connect the top-side ground terminal 125 to the base flange 96 and / or provide the aforementioned shielding function. Furthermore, in various embodiments, a single, relatively large T-shaped or I-shaped substrate sheet (e.g., a PCB or other layout substrate sheet cut to a desired planar geometry) may span an area encompassing any combination of the central isolation wall 120 and the pillar contacts 116 to 119, wherein conductive features (e.g., through-holes, imprints, etc.) are formed in appropriate locations within the substrate sheet to serve as or effectively form the central isolation wall 120 and the pillar contacts 116 to 119. In this manner, the larger electrical layout substrate piece can be incorporated into the leadless PA package 86 to provide desired vertical interconnects between pillar supports 97 to 100 and top-side terminals 121 to 124, and desired vertical interconnects between base flange 96 and top-side terminal 125. In other words, in embodiments, conductive ground, gate, drain, and shielding paths can be formed through a single PCB (or other substrate) piece, which may have an I-shaped geometry, wherein (i) a first gate, ground, and second gate conductive path extends through one end portion of the PCB; (ii) a first drain, ground, and second drain extend through a second opposite end portion of the PCB; and (iii) a ground-to-ground path extends from the first end portion to the second end portion. Various combinations of such structural approaches are also possible in other embodiments of the leadless PA package 86.

[0120] Example mounting of leadless PA packages in electronic systems or components

[0121] Figure 13 As shown in the example embodiment Figures 2 to 8The leadless PA package 86 can be mounted within a larger electronic system or component 154. The electronic component 154 includes a component-level substrate 156, such as a motherboard, to which the PA package 86 is mounted in the reverse direction, such that the top-side surface 131 of the package faces the component-level substrate 156. The top-side I / O interface of the PA package 86 is electrically coupled to corresponding interconnect features (e.g., bonding pads and traces) on the upper surface of the component-level substrate 156 using any suitable interconnect technology, such as solder connections to an LGA 158 (note solder body 160). In other embodiments, the PA package 86 can be mounted to the component-level substrate 156 and electrically interconnected with it using a patterned solder layer, a lead grid array (PGA), or a ball grid array (BGA). Furthermore, for clarity, Figure 13 Only a limited portion of the component-level substrate 156 is shown. Various other components may be distributed across the unshown portions of the component-level substrate 156 to form a desired circuit structure.

[0122] In one embodiment, the component-level heat sink 162 can be directly mounted to the bottom surface 92 of the PA package 86 and bonded to the bottom thermal interface 144 using, for example, a thermally conductive bonding layer 164. Figure 4 The thermally conductive bonding layer 164 may be made of any thermally conductive bonding material, such as a sintered bonding layer or another bonding material (whether conductive or dielectric) with relatively low heat resistance. In other embodiments, the component-level heat sink 162 may be thermally coupled to the bottom thermal interface 144 in a less direct manner. For example, in other cases, the component-level heat sink 162 may be spatially separated from the PA package 86, and heat pipes, such as metal bodies or elongated heat pipes, may be thermally coupled between the heat sink 162 and the bottom thermal interface 144. Regardless of the specific location of the component-level heat sink 162 relative to the PA package 86, the component-level heat sink 162 may be any thermally conductive structure or device adapted to absorb excess heat extracted from the PA package 86 through the bottom thermal interface 144. For example, in embodiments, the component-level heat sink 162 may be a metal chassis, a finned structure (e.g., a pin-fin array), or another thermally conductive body outside the PA package 86. The component-level heat sink 162 can be cooled convectively by releasing heat to the surrounding environment; and, in some embodiments, a fan can direct airflow toward the component-level heat sink 162 to promote convective heat transfer to the impinging airflow. In embodiments, a liquid coolant may also be used for active cooling of the component-level heat sink 162. Thus, in general, the component-level heat sink 162 may take different forms and configurations depending on the characteristics of the electronic component 154. The PA package 86 may also be mounted within a larger electronic system or component, and if such an arrangement enables sufficient heat dissipation from the PA package 86 in some applications, the bottom thermal interface 144 remains exposed (and therefore not directly thermally coupled to the heat sink).

[0123] Additional examples of leadless PA packages with top-side terminals

[0124] Figure 14 This is an isometric view of a leadless PA package 166 as shown in another exemplary embodiment of this disclosure. In many respects, the leadless PA package 166 is similar to the one described above. Figures 2 to 8 The described leadless PA package 86. For example, the leadless PA package 166 includes top-side I / O interfaces 168 to 174 that at least partially define the top-side surface 178 of the package, and an overmolded package body 176 (shown in dotted lines). Base flanges 180, like a plurality of pillar supports 182, are embedded in the overmolded package body 176. Contact pillars 184 are also connected to the pillar supports 182 and extend therefrom to the top-side surface 178 of the package to define ends 168 to 171 included in the top-side I / O interfaces 168 to 174. A plurality of IC dies 181 are bonded to the base flange 180 and interconnected with each other and, where appropriate, interconnected with the pillar supports 182 via bonding wires 185. Thus, parallel signal amplification paths, such as parallel peaking and carrier signal amplification paths, are formed by the leadless PA package 166. Specifically, a first (e.g., carrier) signal amplification is provided, extending from top end 170 to top end 171, passing through the corresponding post contact 184, post support 182, bonding wire 185, and IC die 181. Similarly, a second (e.g., peaking) signal amplification is formed to extend from top end 168 to top end 169, passing through the corresponding post contact 184, post support 182, bonding wire 185, and IC die 181. Furthermore, although in Figure 14 While the flange 180 is hidden and not visible, its bottom surface can be exposed through the bottom side surface of the leadless PA package 166, and may be substantially coplanar with said bottom side surface to form a bond-like structure. Figure 4 The bottom-side thermal interface described is used to dissipate excess heat generated by the IC die 181 during use of the leadless PA package 166.

[0125] The leadless PA package 166 also includes a central isolation wall 186 that extends over and substantially across a base flange 180, which includes a flange connecting strip 188. Figure 14In this example, the leadless PA package 166 also includes two additional peripheral isolation walls 190, 192 positioned adjacent to the opposing sidewalls of the overlay molded package 176 and extending substantially parallel to the central isolation wall 186. The peripheral isolation walls 190, 192 extend laterally to or along with the signal amplification path extending from the top end 168 to 171, such that at least a majority of each signal amplification path lies between one of the peripheral isolation walls 190, 192 and the central isolation wall 186 to provide additional EM shielding in the lateral direction. Additionally, the peripheral isolation walls 190, 192 may further extend from the base flange 180 to the top surface 178 of the package to form additional top peripheral ground terminals 173, 174 in conjunction with the central top ground terminal 172 defined by the exposed upper surface of the central isolation wall 186. In total, the top-side ground terminals 172 to 174 can provide a bulk-robust electrical connection to the ground base flange 180 by bonding to one or more corresponding pads, solder pads or similar features provided on the component-level substrate. Figure 14 The dashed outline 194 illustrates an example plus-shaped geometry of such pads or solder joints to which the top-side ground terminals 172 to 174 can be electrically mounted when the leadless PA package 166 is mounted within a larger electronic system or component. While the lateral isolation wings are lacking in the illustrated example, other embodiments may produce a leadless PA package 166 to include similar features as described above. Figures 2 to 8 The lateral isolation wings described herein. When provided, such isolation wings may extend between bridging isolation walls 186, 190, 192 to form a single grid-like structure. In other embodiments, any or all of isolation walls 186, 190, 192 may be omitted from the leadless PA package 166.

[0126] Summarize

[0127] Leadless PA packages with top-side terminations and methods for manufacturing such leadless PA packages have been provided. Embodiments of the leadless package can be manufactured to include pillar contacts and pillar supports, which facilitates the formation of top-side I / O interfaces using reliable and cost-effective manufacturing processes such as leadframe-based processing, global overlay molding, and improved plating techniques. Additionally, embodiments of the leadless PA package may include a bottom-side thermal interface to separate the primary heat dissipation path from the electrical signal path of the PA package to improve thermal performance, while also facilitating mounting in larger electronic components or systems. A unique top-side termination isolation structure, including an electrically active (e.g., grounded) central isolation wall, can be further deployed within the PA package to enhance EM shielding and RF performance advantages. In some embodiments, smaller fin-like lateral walls or "isolation wings" may be additionally provided to extend over target areas of the packaged RF power die (and possibly other IC dies) for additional input-to-output shielding. The result is a leadless PA package (e.g., DFN or QFN package) with optimal RF and thermal performance characteristics, while allowing for production using improved manufacturing processes.

[0128] In an embodiment, a method for manufacturing a leadless PA package, such as a QFN or DFN package, includes the following steps or processes: providing conductive pillar supports and base flanges spaced apart from the conductive pillar supports, for example, by obtaining pillar supports and base flanges (e.g., by independent manufacturing or purchase from a supplier) and by placing the pillar supports and base flanges on a machined surface, such as a lead frame. The base flange has a die mounting surface and a lower flange surface, the lower flange surface being positioned relative to the die mounting surface in a package height direction (parallel to an axis orthogonal to the die mounting surface). One or more IC dies are attached to the die mounting surface of the base flange, wherein at least one of the IC dies includes an RF power die; for example, when producing the leadless PA package to include a Dougherty amplifier layout, carrier and peaked RF power dies are attached to the base flange using, for example, a conductive bonding material. The IC die or multiple IC dies (at least one first RF power die) and the conductive pillar supports are interconnected by wire bonding or using another suitable interconnect technology. Before or after electrically interconnecting the IC die and the conductive pillar support, pillar contacts are provided (e.g., placed as discrete bodies such as metal blocks), which are electrically coupled to the conductive pillar support and extend from the pillar support in the package height direction. The IC die or multiple IC dies are overmolded or otherwise enclosed in a package body that at least partially defines a top-side surface of the package opposite the lower flange surface. A top-side I / O terminal is formed that is accessible from the top-side surface of the package and electrically interconnected with the IC die via the pillar contacts and the conductive pillar support. In various embodiments in which the leadless PA package is manufactured to include an overmolded package body, the top-side I / O terminal may be formed by exposing the upper surface of the pillar contacts (and possibly the central isolation wall) using a back-grinding process.

[0129] In another embodiment, a method for manufacturing a leadless PA package includes the following steps or processes: providing a base flange having a die mounting surface; attaching a peaked radio frequency (RF) power die to the base flange at a first die mounting location and attaching a carrier RF power die to the base flange at a second die mounting location; and connecting a central isolation wall to the die mounting surface of the base flange such that the central isolation wall is electrically coupled to the base flange and extends between the first and second die mounting locations. The peaked RF power die and the carrier RF power die are enclosed in a package having a top-side surface positioned relative to the base flange and extending substantially parallel to the die mounting surface. A top-side I / O interface is created that is accessible from the top-side surface of the package. The top-side I / O interface includes a top-side ground terminal electrically coupled to the peaked RF power die and the carrier RF power die via the central isolation wall and the base flange. In at least some embodiments, the method further includes the steps or processes of: (i) providing pillar contacts electrically coupled to a peaked RF power die and electrically coupled to a carrier RF power die; and (ii) encapsulating the pillar contacts, base flange, peaked RF power die, carrier RF power die, and central isolation wall in an overmolded package having a thickness sufficient to cover the upper end surfaces of the pillar contacts and the central isolation wall. In such embodiments, the forming step or process may include removing material from the overmolded package to expose the upper end surfaces of the pillar contacts and the central isolation wall through the top side surface of the package.

[0130] A leadless PA package is also disclosed; and in one embodiment, the leadless PA package includes a base flange having a die mounting surface and a lower flange surface positioned opposite the die mounting surface in the package height direction. A conductive post support is spaced apart from the base flange, and one or more IC dies (including at least one RF power die or comprising at least one RF power die) are attached to the die mounting surface of the base flange and electrically interconnected with the conductive post support. Post contacts are electrically coupled to the conductive post support and extend from the conductive post support in the package height direction, and the package body encloses the IC die or multiple IC dies (e.g., at least one RF power die) and has a package top side surface opposite the lower flange surface. In at least some cases, the package top side surface may extend substantially parallel to the die mounting surface. Top-side I / O terminals are accessible from the package top side surface and electrically interconnected with the IC die or multiple IC dies via post contacts and the conductive post support. Furthermore, in some implementations, the package body takes the form of an overmolded package having an outer main surface that at least partially defines the top side surface of the package, while the top I / O terminal takes the form of a pillar contact end surface (plated or unplated) that exposes along the outer main surface of the overmolded package and is substantially coplanar with the outer main surface. In other embodiments, the pillar contacts include a first pair of pillar contacts positioned adjacent to a first sidewall of the package and a second pair of pillar contacts positioned adjacent to a second sidewall of the package opposite to the first sidewall. In contrast, the central isolation wall includes: (i) a first end portion extending between the first pair of pillar contacts, (ii) a second end portion extending between the second pair of pillar contacts; and (iii) an intermediate portion positioned between the first end portion and the second end portion, wherein the peaked RF power die and the carrier RF power die are located on opposite sides of the intermediate portion of the central isolation wall.

[0131] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the invention in any way. In fact, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing exemplary embodiments of the invention, and it should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the invention as set forth in the appended claims. Numerical identifiers, such as “first,” “second,” “third,” etc., have been used above according to the order in which certain elements are introduced in the foregoing detailed description. Such numerical identifiers may also be used in the subsequent claims to indicate the order of introduction in the claims. Therefore, such numerical identifiers may differ between the detailed description and the subsequent claims to reflect differences in the order of introduction of elements.

Claims

1. A method for manufacturing a leadless power amplifier (PA) package, characterized in that, The method includes: A conductive post support and a base flange spaced apart from the conductive post support are provided, the base flange having a die mounting surface and a lower flange surface opposite to the die mounting surface in the package height direction; At least one first RF power die is attached to the die mounting surface of the base flange; The first RF power die and the conductive pillar support are electrically interconnected; Before or after electrically interconnecting the first RF power die and the conductive pillar support, pillar contacts are provided, which are electrically coupled to the conductive pillar support and extend from the conductive pillar support in the package height direction. The first RF power die is enclosed in a package, the package defining, at least in a large portion, a package top side surface positioned opposite the lower flange surface; A top-side I / O terminal is formed, which is accessible from the top surface of the package and electrically interconnected with the first RF power die via the pillar contacts and the conductive pillar support. The conductive post support and the base flange are provided as part of a lead frame, the lead frame further including a sacrificial lead frame portion connecting the conductive post support and the base flange; and After enclosing the first RF power die within the package, the lead frame is detached to remove the sacrificial lead frame portion and electrically isolate the base flange from the conductive post support. The lead frame is provided as a portion of a lead frame array, the lead frame array further including a plurality of additional interconnecting lead frames, and The method further includes plating the end surface of the post contact using an electroplating process, during which a potential is applied to the post contact through the lead frame array before the lead frame array is separated.

2. The method according to claim 1, characterized in that, It also includes creating the package to enclose at least a portion of the first RF power die and the pillar contact, while exposing the outer end surface of the pillar contact from the top side surface of the package to form at least a portion of the top side I / O terminal.

3. The method according to claim 2, characterized in that, The production of the package includes: The conductive pillar support, the base flange, the first RF power die, and the pillar contacts are encapsulated in a molded package with a thickness sufficient to cover the pillar contacts; and After encapsulating the conductive pillar support, the base flange, the first RF power die, and the pillar contact, the overmolded package is thinned to expose the outer end surface of the pillar contact at the top side surface of the package.

4. The method according to claim 1, characterized in that, It also includes giving the package a bottom surface, through which the lower flange surface is exposed to create a bottom thermal interface substantially opposite to the top I / O terminal in the package height direction.

5. The method according to claim 1, characterized in that, The first RF power die includes a peaked RF power die; and The method further includes: The leadless power amplifier package is produced to have a Dougherty amplifier architecture including a peaked signal amplification path and a carrier signal amplification path; At the first die mounting position through which the peaked signal amplification path extends, the peaked RF power die is attached to the base flange; and Additionally, the carrier RF power die is attached to the base flange at the second die mounting position through which the carrier signal amplification path extends.

6. The method according to claim 5, characterized in that, It also includes connecting a central isolation wall to the base flange such that the central isolation wall extends between the first die mounting position and the second die mounting position.

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