Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device can include a substrate, an active pattern located in an upper portion of the substrate and extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction crossing the first direction, a first gate spacer covering a side surface of the gate electrode, a first suppression layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer can include a high-k dielectric layer and a gate oxide layer. The gate oxide layer can be between the high-k dielectric layer and the active pattern. The high-k dielectric layer can be locally disposed between the gate oxide layer and the gate electrode.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2020-0128176, filed on October 5, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and / or a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a field-effect transistor and / or a method of manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices are considered essential components in the electronics industry due to their small size, versatility, and / or low cost. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements. With the development of the electronics industry, the demand for semiconductor devices with improved characteristics is increasing. For example, there is a growing need for semiconductor devices with high reliability, high performance, and / or versatility. To meet these demands, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device with improved electrical and reliability characteristics.

[0005] An embodiment of the inventive concept provides a semiconductor device with low power consumption properties.

[0006] According to embodiments of the inventive concept, a semiconductor device may include: a substrate; an active pattern located in an upper portion of the substrate and extending in a first direction; a gate electrode intersecting the active pattern and extending in a second direction intersecting the first direction; a first gate spacer covering a side surface of the gate electrode; a first suppression layer located between the gate electrode and the first gate spacer; and a gate insulating layer located between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be located between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be partially disposed between the gate oxide layer and the gate electrode.

[0007] According to embodiments of the inventive concept, a semiconductor device may include: a substrate; an active pattern located in an upper portion of the substrate and extending in a first direction; a gate electrode intersecting the active pattern and extending in a second direction intersecting the first direction; a first gate spacer covering a side surface of the gate electrode; a first suppression layer located between the gate electrode and the first gate spacer; and a gate insulating layer located between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be located between the high-k dielectric layer and the active pattern. The high-k dielectric layer may extend along the top surface of the gate oxide layer and the side surface of the first suppression layer. The thickness of the high-k dielectric layer on the top surface of the gate oxide layer may be greater than the thickness of the high-k dielectric layer on the side surface of the first suppression layer.

[0008] According to embodiments of the inventive concept, a semiconductor device may include: a substrate; an active pattern located in an upper portion of the substrate and extending in a first direction, the active pattern including a plurality of channel layers stacked on top of each other; a gate electrode intersecting the active pattern and surrounding the plurality of channel layers, the gate electrode extending in a second direction intersecting the first direction; a gate spacer covering a side surface of the gate electrode; a suppression layer located between the gate electrode and the gate spacer; a pair of source / drain patterns located on either side of the gate electrode; a gate insulating layer located between the gate electrode and each of the plurality of channel layers; an interlayer insulating layer covering the gate electrode and the gate spacer; an active contact penetrating the interlayer insulating layer and correspondingly connected to the pair of source / drain patterns; and a gate contact penetrating at least a portion of the interlayer insulating layer and connected to the gate electrode. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be located between the high-k dielectric layer and each of the plurality of channel layers. The high-k dielectric layer may be partially disposed between the gate oxide layer and the gate electrode. Attached Figure Description

[0009] The exemplary embodiments will become clearer from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0010] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 2A and Figure 2B They are respectively along Figure 1 The cross-sectional views taken along lines I-I' and II-II' are used to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0012] Figures 3A to 3F Each of these represents a portion of a semiconductor device according to an embodiment of the inventive concept (e.g., Figure 2A An enlarged sectional view of part A in the diagram.

[0013] Figure 4 It is along Figure 1 The cross-sectional view taken along line II-II' is used to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0014] Figure 5A and Figure 5B They are respectively along Figure 1 The cross-sectional views taken along lines I-I' and II-II' are used to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0016] Figure 6B , Figure 7B , Figure 8 , Figure 9 , Figure 10B , Figure 11 , Figure 12 , Figure 13B , Figure 14A , Figure 15B , Figure 16A and Figure 17A Each along Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A A sectional view taken from the corresponding line I-I', used to illustrate a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0017] Figure 6C , Figure 7C , Figure 14B , Figure 15C , Figure 16B and Figure 17B Each along Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A A sectional view taken from the corresponding line II-II' is used to illustrate a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0018] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in certain exemplary embodiments and are intended to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range or nature of the values ​​covered by the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0019] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Furthermore, when the words “approximately” and “substantially” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather that the boundaries of the shape are within the disclosed range. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0020] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0021] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 2A and Figure 2B They are respectively along Figure 1 The cross-sectional views taken along lines I-I' and II-II' are used to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0022] Reference Figure 1 , Figure 2A and Figure 2B A substrate 100 may be provided, comprising a first unit region PR and a second unit region NR. The substrate 100 may include a semiconductor substrate or a compound semiconductor substrate, wherein the semiconductor substrate is formed of or includes one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In an embodiment, the substrate 100 may be a silicon substrate. The top surface of the substrate 100 may be parallel to a first direction D1 and a second direction D2, and may be perpendicular to a third direction D3. The first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0023] A second trench TR2 may be formed in the upper part of the substrate 100 to define a first cell region PR and a second cell region NR. The second trench TR2 may be positioned between the first cell region PR and the second cell region NR. The first cell region PR and the second cell region NR may be spaced apart from each other in a second direction D2, and the second trench TR2 is positioned between the first cell region PR and the second cell region NR.

[0024] The first unit region PR and the second unit region NR can be regions in which standard units constituting logic circuits are disposed. As an example, the first unit region PR can be a region in which a PMOS field-effect transistor is disposed, and the second unit region NR can be a region in which an NMOS field-effect transistor is disposed.

[0025] The first active pattern AP1 and the second active pattern AP2 can be defined by a first trench TR1 formed in the upper part of the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be respectively disposed on the first cell region PR and the second cell region NR. The first trench TR1 can be shallower than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 can be portions of the substrate 100 protruding in the third direction D3. The widths of the first active pattern AP1 and the second active pattern AP2 in the first direction D1 and the second direction D2 can decrease as they are measured along the third direction D3.

[0026] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of or comprise silicon oxide. The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude above the device isolation layer ST (e.g., see...). Figure 2B The device isolation layer ST may not cover the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover a portion of the side surface of each of the first active pattern AP1 and the second active pattern AP2.

[0027] Each of the first active pattern AP1 and the second active pattern AP2 may include a plurality of stacked channel layers CH. The channel layers CH may be disposed on the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The channel layers CH may be spaced apart from each other on a third direction D3. The channel layers CH may be formed or comprise at least one of, for example, silicon (Si), germanium (Ge), and silicon-germanium (SiGe). As an example, the channel layers CH may be formed or comprise silicon (Si).

[0028] A pair of first source / drain patterns SD1 can be disposed on the upper part of the first active pattern AP1. As an example, the first source / drain patterns SD1 can be an impurity region of a first conductivity type (e.g., p-type). The channel layer CH can be disposed between the pair of first source / drain patterns SD1.

[0029] A pair of second source / drain patterns SD2 can be disposed on the upper part of the second active pattern AP2. As an example, the second source / drain patterns SD2 can be an impurity region of a second conductivity type (e.g., n-type). The channel layer CH can be disposed between the pair of second source / drain patterns SD2.

[0030] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. For example, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be substantially at the same level as the highest surface of the highest channel layer CH in the channel layer CH. However, the inventive concept is not limited to this example, and in embodiments, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at a level higher than the highest surface of the highest channel layer CH in the channel layer CH.

[0031] The first source / drain pattern SD1 may be formed of or comprise a semiconductor material (e.g., SiGe) whose lattice constant is greater than that of the semiconductor material of the substrate 100. The first source / drain pattern SD1 may apply compressive stress to the channel layer CH. The second source / drain pattern SD2 may be formed of or comprise the same semiconductor material (e.g., Si) as the substrate 100.

[0032] The gate electrode GE can be configured to intersect with the first active pattern AP1 and the second active pattern AP2 and extend in the second direction D2. A portion of the gate electrode GE can be stacked with the channel layer CH in the third direction D3.

[0033] Reference Figure 2AThe gate electrode GE may include a first portion GE1 and a second portion GE2. The first portion GE1 is disposed on the top surface of each of the first active pattern AP1 and the second active pattern AP2, and the second portion GE2 is disposed in each of the regions between the first source / drain pattern SD1 and the second source / drain pattern SD2. The first portion GE1 of the gate electrode GE may be located at a level higher than the top surfaces of each of the first active pattern AP1 and the second active pattern AP2, and the top surfaces of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. The second portion GE2 of the gate electrode GE may extend in a second direction D2 between the channel layers CH, parallel to the bottom surface of the first portion GE1 of the gate electrode GE.

[0034] Reference Figure 2B The gate electrode GE can be disposed on the top surface, bottom surface, and side surface of each of the channel layers CH. For example, each transistor in the first cell region PR and the second cell region NR can be a three-dimensional field-effect transistor in which the gate electrode GE is configured to surround the channel layer CH in three dimensions.

[0035] The first gate spacer GS1 and the second gate spacer GS2 can be configured to cover the side surface of the gate electrode GE. (Refer to...) Figure 2A The first gate spacer GS1 can cover the side surface of the first portion GE1 of the gate electrode GE, and the second gate spacer GS2 can cover the side surface of the second portion GE2 of the gate electrode GE.

[0036] The first gate spacer GS1 and the second gate spacer GS2 may extend in the second direction D2 or along the gate electrode GE. The top surface of the first gate spacer GS1 may be located at a level higher than the top surface of the first portion GE1 of the gate electrode GE. The first gate spacer GS1 and the second gate spacer GS2 may be formed of, for example, at least one of SiCN, SiCON, and SiN, or include, for example, at least one of SiCN, SiCON, and SiN. In embodiments, the first gate spacer GS1 and the second gate spacer GS2 may be a multilayer structure comprising at least two different materials selected from SiCN, SiCON, and SiN.

[0037] A first suppression layer INH1 may be disposed between the first gate spacer GS1 and the first portion GE1 of the gate electrode GE. The first suppression layer INH1 may be in direct contact with the first portion GE1 of the gate electrode GE. The first gate spacer GS1 and the first portion GE1 of the gate electrode GE may be spaced apart from each other, and the first suppression layer INH1 is positioned between the first gate spacer GS1 and the first portion GE1 of the gate electrode GE. The first suppression layer INH1 may cover the side surface of the first gate spacer GS1 adjacent to the first portion GE1 of the gate electrode GE.

[0038] The second suppression layer INH2 can be disposed between the second gate spacer GS2 and the second portion GE2 of the gate electrode GE. The second suppression layer INH2 can be in direct contact with the second portion GE2 of the gate electrode GE. The second gate spacer GS2 and the second portion GE2 of the gate electrode GE can be spaced apart from each other, and the second suppression layer INH2 is disposed between the second gate spacer GS2 and the second portion GE2 of the gate electrode GE. The second suppression layer INH2 can cover the side surface of the second gate spacer GS2 adjacent to the second portion GE2 of the gate electrode GE, and can also cover the top and bottom surfaces of the second gate spacer GS2 adjacent to the channel layer CH.

[0039] The first suppression layer INH1 and the second suppression layer INH2 can prevent or suppress the deposition of the high-k dielectric layer HK, which will be described below, on the side surface of the gate electrode GE. The high-k dielectric layer HK may not be deposited on the surface where the first suppression layer INH1 or the second suppression layer INH2 is disposed, and even when the high-k dielectric layer HK is deposited on the surface where the first suppression layer INH1 or the second suppression layer INH2 is disposed, the high-k dielectric layer HK can be deposited to have a thickness thinner than the thickness on the surface where the first suppression layer INH1 or the second suppression layer INH2 is not disposed. The first suppression layer INH1 and the second suppression layer INH2 may be formed of or comprise the same material. As an example, in the case where the high-k dielectric layer HK comprises hafnium oxide (HfO2), the first suppression layer INH1 and the second suppression layer INH2 may comprise acetylacetone (CH3COCH2COCH3), but the inventive concept is not limited to this example. For example, the material properties of the first suppression layer INH1 and the second suppression layer INH2 may be changed depending on the material properties of the high-k dielectric layer HK.

[0040] A gate cap pattern GP can be disposed on the gate electrode GE. For example, a first suppression layer INH1 can be disposed between the gate cap pattern GP and the first gate spacer GS1, and the gate cap pattern GP can contact the first suppression layer INH1. The gate cap pattern GP can extend along the gate electrode GE and in a second direction D2. The gate cap pattern GP can be formed of or include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. For example, the gate cap pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0041] A gate insulating layer GI can be disposed between the gate electrode GE and the channel layer CH. More specifically, the gate insulating layer GI, comprising a gate oxide layer IL and a high-k dielectric layer HK, can be disposed between a first portion GE1 of the gate electrode GE and the highest channel layer CH in the channel layer CH, and between a second portion GE2 of the gate electrode GE and the channel layer CH. The gate insulating layer GI can extend along the bottom surface of the first portion GE1 of the gate electrode GE and the top and bottom surfaces of the second portion GE2. The gate insulating layer GI can cover the top surface of the device isolation layer ST disposed below the gate electrode GE.

[0042] When in Figure 2A When viewed in a cross-sectional view, the gate oxide layer IL and the high-k dielectric layer HK of the gate insulating layer GI can be stacked with a portion of each channel layer CH in the first direction D1, and can be not stacked with the first suppression layer INH1 and the second suppression layer INH2, as well as the first gate spacer GS1 and the second gate spacer GS2 in the first direction D1. Figure 2B When viewed in a cross-sectional view, the gate oxide layer IL and the high-k dielectric layer HK of the gate insulating layer GI can be configured to surround the top, bottom, and side surfaces of each channel layer CH. The gate oxide layer IL can be disposed between the high-k dielectric layer HK and the channel layer CH.

[0043] The gate oxide layer IL may be formed of, for example, silicon oxide and silicon oxynitride, or may include, for example, at least one of silicon oxide and silicon oxynitride. In an embodiment, the gate oxide layer IL may be formed of or include silicon oxide. The high-k dielectric layer HK may be formed of or include at least one of a high-k dielectric material with a dielectric constant higher than that of silicon oxide and silicon oxynitride. The high-k dielectric layer HK can be formed or include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0044] Reference Figures 3A to 3F A more detailed description is provided of the gate insulating layer GI, which includes the gate oxide layer IL and the high-k dielectric layer HK, as well as other adjacent components.

[0045] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to each channel layer CH. The first metal pattern may include work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, it is possible to achieve a transistor with a desired threshold voltage.

[0046] The first metal pattern may be formed of or comprise a metal nitride. For example, the first metal pattern may comprise at least one metallic material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). In embodiments, the first metal pattern may further comprise carbon (C). The first metal pattern may comprise a plurality of stacked active power metal layers.

[0047] The second metal pattern may include a metal material whose resistance is lower than that of the first metal pattern. For example, the second metal pattern may include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0048] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the first gate spacer GS1 and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer insulating layer 110 may have a top surface substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the first gate spacer GS1. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the top surface of the gate cap pattern GP and the top surface of the first gate spacer GS1. For example, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may be formed of silicon oxide or include silicon oxide.

[0049] The active contact AC can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively disposed on both sides of the gate electrode GE. When viewed in a plan view, each active contact AC can be a strip pattern extending in the second direction D2.

[0050] Each active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the side and bottom surfaces of the conductive pattern FM. In an embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN), or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0051] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed in a self-aligned manner using a gate cap pattern GP and a first gate spacer GS1. For example, the active contact AC can cover at least a portion of the side surface of the first gate spacer GS1. Unlike the structure shown, the active contact AC can cover a portion of the top surface of the gate cap pattern GP.

[0052] A silicide pattern SC can be disposed between each of the active contacts AC and each of the first source / drain pattern SD1 and the second source / drain pattern SD2. Each active contact AC can be electrically connected to a corresponding one of the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. The silicide pattern SC can be formed of or include at least one of metal silicide materials. For example, the silicide pattern SC can be formed of or include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0053] The gate contact GC, electrically connected to the gate electrode GE, can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP. For example, the gate contact GC can be disposed on the device isolation layer ST between the first cell region PR and the second cell region NR. When viewed in a plan view, the gate contact GC can be a strip pattern extending in the first direction D1. Similar to the active contact AC, the gate contact GC can include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM.

[0054] A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A first interconnect M1, a first via V1, and a second via V2 may be disposed within the third interlayer insulating layer 130. The first via V1 and the second via V2 may be disposed below the first interconnect M1. The first interconnect M1 may extend in a first direction D1. The first interconnect M1 may be arranged in either the first direction D1 or the second direction D2. The first via V1 may be disposed between one of the first interconnect M1 and one of the active contacts AC to electrically connect them to each other. The second via V2 may be disposed between one of the first interconnect M1 and one of the gate contacts GC to electrically connect them to each other.

[0055] The first interconnect M1 and either the first via V1 or the second via V2 can be connected to form a single conductive structure. For example, the first interconnect M1 and either the first via V1 or the second via V2 can be formed using the same process. The first interconnect M1 and either the first via V1 or the second via V2 can constitute a single conductive structure formed using a dual damascene process. Although not shown, additional metal layers (e.g., M2, M3, M4, etc.) can also be stacked on the third interlayer insulating layer 130.

[0056] Figures 3A to 3F Each of these represents a portion of a semiconductor device according to an embodiment of the inventive concept (e.g., Figure 2A An enlarged sectional view of Part A (see section A). Refer to... Figures 3A to 3F A more detailed description of the structure of the semiconductor device.

[0057] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3A Each channel layer CH may include a first portion CHa and a second portion CHb. The first portion CHa is stacked on a third direction D3 with a first gate spacer GS1, a second gate spacer GS2, a first suppression layer INH1, and a second suppression layer INH2. The second portion CHb is disposed between the first portions CHa, extends in a first direction D1, and is stacked on a third direction D3 with a gate electrode GE. The first portions CHa may be spaced apart from each other in the first direction D1, and the second portions CHb are disposed between the first portions CHa. The second portions CHb may be disposed between the first portions CHa and may have a uniform thickness in the third direction D3.

[0058] Each first portion CHa may have a first thickness T1 in the third direction D3, and the second portion CHb may have a second thickness T2 in the third direction D3. For example, the first thickness T1 may be defined as the maximum thickness of each first portion CHa in the third direction D3. The first thickness T1 may be greater than the second thickness T2.

[0059] Each first portion CHa may have an inner surface CHas adjacent to the second portion CHb. The inner surface CHas of each first portion CHa may be parallel to, for example, a third direction D3. A portion of the inner surface CHas of each first portion CHa may contact the second portion CHb, and another portion may contact the gate insulating layer GI but not the second portion CHb.

[0060] The second portion CHb may have a top surface CHbt adjacent to the gate electrode GE. The top surface CHbt of the second portion CHb may be parallel to, for example, a first direction D1 and a second direction D2, and may be perpendicular to the inner surface CHa of each first portion CHa. The top surface CHbt of the second portion CHb may be covered with a gate oxide layer IL.

[0061] A gate insulating layer GI, comprising a gate oxide layer IL and a high-k dielectric layer HK, can be disposed in the space surrounded by the opposing inner surfaces CHa of the first portion CHa and the top surface CHbt of the second portion CHb. Specifically, the gate oxide layer IL and the high-k dielectric layer HK can be stacked with the first portion CHa in a first direction D1 and can be disposed between the gate electrode GE and the second portion CHb. The gate oxide layer IL can cover portions of the top surface CHbt of the second portion CHb and the inner surface CHa of the first portion CHa, and the high-k dielectric layer HK can cover portions of the top surface ILt of the gate oxide layer IL and the inner surface CHa of the first portion CHa that are not covered by the gate oxide layer IL.

[0062] The top surface HKt of the high-k dielectric layer HK can contact the top or bottom surface of the gate electrode GE. The high-k dielectric layer HK may not be disposed on the side surfaces INH1s of the first suppression layer INH1 and the side surfaces INH2s of the second suppression layer INH2. In other words, the high-k dielectric layer HK may not contact the first suppression layer INH1 and the second suppression layer INH2. The thickness of the high-k dielectric layer HK in the third direction D3 can have a substantially constant value between the first portion CHa. The top surface HKt of the high-k dielectric layer HK can be parallel to the first direction D1 and the second direction D2. For example, the top surface HKt of the high-k dielectric layer HK can be substantially coplanar with the top or bottom surface of the gate electrode GE. For example, the top surface HKt of the high-k dielectric layer HK can be located at a level lower than or equal to the top surface of the first portion CHa and the bottom surface of the first gate spacer GS1.

[0063] Since the high-k dielectric layer HK is not disposed on the side surfaces INH1s of the first suppression layer INH1 and INH2s of the second suppression layer INH2, the capacitance between the gate electrode GE and the first source / drain pattern SD1 can be reduced. This enables the realization of a low-power semiconductor device.

[0064] Since the high-k dielectric layer HK is configured to have a constant thickness on the top or bottom surface of the gate electrode GE, it is possible to reduce the internal leakage current in the semiconductor device, thereby improving the reliability of the semiconductor device.

[0065] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3B The high-k dielectric layer HK can be disposed on the top surface ILt of the gate oxide layer IL, the side surface INH1s of the first suppression layer INH1, and the side surface INH2s of the second suppression layer INH2. For the sake of brevity, the previously described elements can be identified by the same reference numerals without repeating their description.

[0066] The high-k dielectric layer HK may extend in a first direction D1 to cover the top surface ILt of the gate oxide layer IL, and may extend in a third direction D3 to cover each of the side surfaces INH1s of the first suppression layer INH1 and the side surfaces INH2s of the second suppression layer INH2. The high-k dielectric layer HK may be configured to surround the gate electrode GE. Unlike what is shown in the figures, the high-k dielectric layer HK may be configured to cover a portion of each of the side surfaces INH1s of the first suppression layer INH1 and the side surfaces INH2s of the second suppression layer INH2.

[0067] A portion of the high-k dielectric layer HK disposed on the top surface ILT of the gate oxide layer IL can have a third thickness T3 in the third direction D3. Another portion of the high-k dielectric layer HK disposed on the side surfaces INH1s of the first suppression layer INH1 and INH2s of the second suppression layer INH2 can have a fourth thickness T4 in the first direction D1. The third thickness T3 can be larger than the fourth thickness T4. This structure, where the third thickness T3 is larger than the fourth thickness T4, can be due to the difference in material properties between the high-k dielectric layer HK and the first and second suppression layers INH1 and INH2.

[0068] Since the high-k dielectric layer HK is thinner on the side surfaces INH1s of the first suppression layer INH1 and INH2s of the second suppression layer INH2 than on the top surface ILt of the gate oxide layer IL, it is possible to reduce the parasitic capacitance between the gate electrode GE and the first source / drain pattern SD1. This enables the realization of a low-power semiconductor device.

[0069] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3C The gate oxide layer IL can be configured to cover the first portion CHa and the second portion CHb of each channel layer CH. For the sake of brevity, the previously described elements can be identified by the same reference numerals without repeating their descriptions.

[0070] The gate oxide layer IL can conformally cover the inner surface CHas of the first portion CHa and the top surface CHbt of the second portion CHb. The thickness of the gate oxide layer IL can be substantially constant on the inner surface CHas of the first portion CHa and the top surface CHbt of the second portion CHb. The highest surface ILt of the gate oxide layer IL can be substantially coplanar with the top surface of the first portion CHa, the top surface HKt of the high-k dielectric layer HK, and the top or bottom surface of the gate electrode GE.

[0071] The high-k dielectric layer HK can be surrounded by the gate oxide layer IL and the gate electrode GE. The high-k dielectric layer HK can be spaced apart from the channel layer CH, and the gate oxide layer IL is placed between the high-k dielectric layer HK and the channel layer CH.

[0072] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3D The gate oxide layer IL can be configured to cover a first portion CHa and a second portion CHb of each channel layer CH, and a high-k dielectric layer HK can be disposed on the gate oxide layer IL to extend along the top surface of the gate oxide layer IL. For the sake of brevity, the previously described elements can be identified by the same reference numerals without repeating their description.

[0073] The gate oxide layer IL can cover the inner surface CHa of the first portion CHa and the top surface CHbt of the second portion CHb. The thickness of the gate oxide layer IL can be substantially constant on the inner surface CHa of the first portion CHa and the top surface CHbt of the second portion CHb. The thickness of the gate oxide layer IL can be greater than... Figures 3A to 3C In this embodiment, the gate oxide layer IL has a small thickness. The high-k dielectric layer HK can be surrounded by the gate oxide layer IL and the gate electrode GE. The high-k dielectric layer HK can be spaced apart from the channel layer CH, and the gate oxide layer IL is located between the high-k dielectric layer HK and the channel layer CH.

[0074] The thickness of the high-k dielectric layer HK on the third-direction D3 may not be constant. Specifically, the top surface HKt of the high-k dielectric layer HK may have a first surface HKt1 and a second surface HKt2. The first surface HKt1 of the top surface HKt of the high-k dielectric layer HK may be located at a lower level than the second surface HKt2 of the top surface HKt of the high-k dielectric layer HK. The first surface HKt1 may be located at a lower level than the highest surface ILt of the gate oxide layer IL, and the second surface HKt2 may be substantially coplanar with the highest surface ILt of the gate oxide layer IL. The first surface HKt1 may be closer to the second portion CHb of each channel layer CH than the second surface HKt2.

[0075] The gate electrode GE may protrude toward the second portion CHb of each channel layer CH in a direction parallel to or antiparallel to the third direction D3. At least a portion of the gate electrode GE may be surrounded by a high-k dielectric layer HK. The portion of the gate electrode GE surrounded by the high-k dielectric layer HK may be stacked with the first portion CHa of each channel layer CH in the first direction D1.

[0076] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3E The inner surface CHa of each first portion of the channel layer CH can have a specific tilt angle relative to the third direction D3. For the sake of brevity, the previously described elements can be identified by the same reference numerals without repeating their description.

[0077] The inner surface Chas of each first portion CHa may not be perpendicular to the top surface CHbt of the second portion CHb. As an example, the inner surface Chas of each first portion CHa may form an acute angle with the top surface CHbt of the second portion CHb. For example, at least a portion of the gate oxide layer IL may be stacked on the third direction D3 with the first suppression layer INH1 and the second suppression layer INH2, as well as the first gate spacer GS1 and the second gate spacer GS2.

[0078] However, the inventive concept is not limited to this example. In embodiments, the inner surface CHa of each first portion CHa may form an obtuse angle with the top surface CHbt of the second portion CHb.

[0079] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3F The inner surface CHa of the first portion of each channel layer CH can have a curved profile. For the sake of brevity, the previously described elements can be identified by the same reference numerals without repeating their descriptions.

[0080] The inner surface Chas of each first portion CHa may not be perpendicular to the top surface CHbt of the second portion CHb. For example, the inner surface Chas of each first portion CHa may be connected to the top surface CHbt of the second portion CHb, while having a continuously varying tilt angle. Therefore, a portion of the bottom surface of the gate oxide layer IL that contacts each channel layer CH and a portion of the bottom surface of the high-k dielectric layer HK that contacts the gate oxide layer IL may also have a curved profile.

[0081] Figure 4 It is along Figure 1 A cross-sectional view taken along line II-II', used to illustrate a semiconductor device according to an embodiment of the inventive concept. Below is a description of... Figure 4 In the description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0082] Reference Figure 1 , Figure 2A and Figure 4 The channel layers CH can extend in the upper portion of each of the first active pattern AP1 and the second active pattern AP2 in a first direction D1. The channel layers CH can be spaced apart from each other in a third direction D3. (Refer to previous reference) Figure 1 , Figure 2A and Figure 2B The described channel layer CH is different, when in Figure 4 When viewed in a cross-sectional view, each channel layer CH can have a circular cross-section. For example, the channel layer CH can be a cylindrical pattern extending in a first direction D1. The cross-sectional diameter CHr of each channel layer CH can be substantially equal to the upper width of each of the first active pattern AP1 and the second active pattern AP2. However, the inventive concept is not limited to this example, and in embodiments, the cross-section of each channel layer CH can have various shapes (e.g., elliptical, truncated circular, and polygonal (e.g., rectangular) shapes).

[0083] The cross-sectional diameter CHR of each channel layer CH can be determined by using it as a reference in the manufacturing process. Figure 16A and Figure 16B The trimming process described is reduced. However, the inventive concept is not limited to this example; in embodiments, the cross-section of each channel layer CH may have a circular shape, with its upper and / or lower portions partially cut by the trimming process described below.

[0084] The gate electrode GE can be configured to surround each channel layer CH. A gate insulating layer GI, comprising a gate oxide layer IL and a high-k dielectric layer HK, can be disposed between the gate electrode GE and each channel layer CH. The gate insulating layer GI can also be configured to surround each channel layer CH. For example, each transistor on the first cell region PR and the second cell region NR can be a three-dimensional field-effect transistor with its gate electrode GE configured to three-dimensionally surround the channel layer CH.

[0085] Figure 5A and Figure 5B They are respectively along Figure 1 The cross-sectional views taken along lines I-I' and II-II' are used to illustrate a semiconductor device according to an embodiment of the inventive concept. Below are further details... Figure 5A and Figure 5B In the description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0086] Reference Figure 1 , Figure 5A and Figure 5B , compared with previous references Figure 1 , Figure 2A and Figure 2B The first active pattern AP1 and the second active pattern AP2 described are different in that they may not include channel layers CH stacked and spaced apart from each other on a third-direction D3. The first active pattern AP1 and the second active pattern AP2 may each include an upper portion shaped like a single fin protruding above the device isolation layer ST. The fin protruding above the device isolation layer ST may be disposed between the first source / drain pattern SD1 or the second source / drain pattern SD2, and may be defined as the channel layer CH. In other words, each of the transistors in the first cell region PR and the second cell region NR may be a fin field-effect transistor.

[0087] A suppression layer INH can be disposed between the gate electrode GE and the gate spacer GS. A gate insulating layer GI, including a gate oxide layer IL and a high-k dielectric layer HK, can be disposed between the gate electrode GE and the channel layer CH. As an example, the high-k dielectric layer HK can be partially disposed on the gate oxide layer IL and may not be disposed on the side surface of the gate electrode GE that contacts the suppression layer INH. As another example, see reference... Figure 3B As described, the high-k dielectric layer HK can extend along the side surface INHs of the suppression layer INH and can be disposed in the space between the side surface of the suppression layer INH and the gate electrode GE, but such a portion can be thinner than another portion of the high-k dielectric layer HK disposed on the gate oxide layer IL.

[0088] Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A This is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the inventive concept. Figure 6B , Figure 7B , Figure 8 , Figure 9 , Figure 10B , Figure 11 , Figure 12 , Figure 13B , Figure 14A , Figure 15B , Figure 16A and Figure 17A Each along Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A A sectional view taken from the corresponding line I-I', used to illustrate a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Figure 6C , Figure 7C , Figure 14B , Figure 15C , Figure 16B and Figure 17B Each along Figure 6A , Figure 7A , Figure 10A , Figure 13A and Figure 15A The cross-sectional view taken from line II-II' illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing the semiconductor device will be described in more detail below with reference to the accompanying drawings.

[0089] Reference Figure 6A , Figure 6B and Figure 6C A substrate 100 may be provided. In embodiments, the substrate 100 may be configured as a plate extending in a first direction D1 and a second direction D2, and may be formed of or comprise a semiconductor material. A first semiconductor layer and a second semiconductor layer may be alternately stacked on the substrate 100. Each of the first and second semiconductor layers may be formed of or comprise at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In embodiments, the materials of the first and second semiconductor layers may be different from each other. For example, the first semiconductor layer may be formed of or comprise silicon (Si), and the second semiconductor layer may be formed of or comprise silicon-germanium (SiGe).

[0090] A first patterning process can be performed on substrate 100 to form a first trench TR1 defining a first active pattern AP1 and a second active pattern AP2. During the first patterning process, a first semiconductor layer and a second semiconductor layer can be patterned to form a first semiconductor pattern SP1 and a second semiconductor pattern SP2, respectively. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be alternately stacked on each of the first active pattern AP1 and the second active pattern AP2.

[0091] A second patterning process can be performed on the substrate 100 to form a second trench TR2 defining a first cell region PR and a second cell region NR. The second trench TR2 can be formed to be deeper than the first trench TR1. A first active pattern AP1 and a second active pattern AP2 can be formed on the first cell region PR and the second cell region NR, respectively.

[0092] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of or include at least one of the insulating materials (e.g., silicon oxide). The device isolation layer ST can be recessed to expose the upper portions of the first active pattern AP1 and the second active pattern AP2. In an embodiment, the upper portions of the first active pattern AP1 and the second active pattern AP2 can protrude over the device isolation layer ST in a third direction D3.

[0093] A buffer layer BF can be formed to cover the upper portions of the first active pattern AP1 and the second active pattern AP2 that protrude above the device isolation layer ST. The buffer layer BF can extend to cover at least a portion of the top surface of the device isolation layer ST. The buffer layer BF can be formed of, for example, silicon oxide or include, for example, silicon oxide.

[0094] Reference Figure 7A , Figure 7B and Figure 7C A sacrificial pattern PP can be formed to intersect with the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can be a linear or strip pattern extending in the second direction D2.

[0095] Specifically, the step of forming the sacrificial pattern PP may include: forming a sacrificial layer on a substrate 100; forming a hard mask pattern MP on the sacrificial layer; and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer and the buffer layer BF. The sacrificial layer may be formed of, for example, polysilicon or may include, for example, polysilicon. The hard mask pattern MP may be formed of, for example, silicon nitride or may include, for example, silicon nitride.

[0096] Reference Figure 8A first suppression layer INH1 can be formed to cover the top surface of the highest first semiconductor pattern SP1, the buffer layer BF, the side surfaces of each of the sacrificial pattern PP and the hard mask pattern MP, and the top surface of the hard mask pattern MP.

[0097] Reference Figure 9 An etch-back process can be performed to remove the first suppression layer INH1 from the top surface of the highest first semiconductor pattern SP1 and the top surface of the hard mask pattern MP. Therefore, the first suppression layer INH1 can be locally retained on the side surfaces of each of the buffer layer BF, the sacrificial pattern PP, and the hard mask pattern MP.

[0098] A first gate spacer GS1 can be formed to cover the top surface of the highest first semiconductor pattern SP1 exposed to the outside by an etch-back process and the top surface of the hard mask pattern MP exposed to the outside by an etch-back process. The first gate spacer GS1 can extend on the third direction D3 to cover the first suppression layer INH1.

[0099] Reference Figure 10A and Figure 10B The first gate spacer GS1 can be removed from the top surface of the hard mask pattern MP by an etching process. Unlike the structure shown, a portion of the hard mask pattern MP can also be removed during the etching process of the first gate spacer GS1. Therefore, the first gate spacer GS1 can be partially left on the side surface of the first suppression layer INH1.

[0100] Subsequently, each of the first active pattern AP1 and the second active pattern AP2 can be partially recessed to form a first recessed region RC1. The first recessed region RC1 can be formed on both sides of the sacrificial pattern PP. The step of forming the first recessed region RC1 may include etching the upper portion of each of the first active pattern AP1 and the second active pattern AP2 using a hard mask pattern MP and a first gate spacer GS1 as an etching mask. For example, each first recessed region RC1 may be stacked with the first gate spacer GS1 on the third direction D3. However, the inventive concept is not limited to this example; in embodiments, each first recessed region RC1 may be locally formed in a region located between adjacent sacrificial patterns in the sacrificial pattern PP but not stacked with the first gate spacer GS1 on the third direction D3.

[0101] Although not shown, at least a portion of the device isolation layer ST between the first cell region PR and the second cell region NR may be recessed during etching of the upper portion of each of the first active pattern AP1 and the second active pattern AP2.

[0102] Reference Figure 11 Each second semiconductor pattern SP2 can be partially recessed in the first direction D1 to form a second recessed region RC2. During the step of forming the second recessed region RC2, the first semiconductor pattern SP1 exposed through the first recessed region RC1 may not be recessed. For example, the second recessed region RC2 can be formed by an etching process that has high etch selectivity (e.g., a faster etch rate) for the second semiconductor pattern SP2 relative to the first semiconductor pattern SP1.

[0103] Subsequently, a second suppression layer INH2 can be formed to cover the top surfaces of the first active pattern AP1 and the second active pattern AP2, as well as the side surfaces of the first semiconductor pattern SP1 exposed through the first recessed region RC1 and the second semiconductor pattern SP2 exposed through the second recessed region RC2. The second suppression layer INH2 can extend to cover the side and top surfaces of the first gate spacer GS1 and the top surface of the hard mask pattern MP.

[0104] Reference Figure 12 A second gate spacer GS2 can be formed to fill each second recessed region RC2. The step of forming the second gate spacer GS2 may include: forming a second gate spacer layer to fill at least a portion of the second recessed region RC2 and the first recessed region RC1; and then performing an etch-back process to remove the second gate spacer layer from the first recessed region RC1.

[0105] The portion of the second suppression layer INH2 formed outside the second recessed region RC2 can be removed during the etch-back process of the second gate spacer layer. Specifically, the second suppression layer INH2 can be removed from the top surface of the first active pattern AP1 and the second active pattern AP2, the side surface of the first semiconductor pattern SP1, the side and top surfaces of the first gate spacer GS1, and the top surface of the hard mask pattern MP, and the second suppression layer INH2 can be partially left in the second recessed region RC2.

[0106] Reference Figure 13A and Figure 13BA first source / drain pattern SD1 can be formed to fill the first recessed region RC1 in the upper part of the first active pattern AP1, and a second source / drain pattern SD2 can be formed to fill the first recessed region RC1 in the upper part of the second active pattern AP2. The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed on both sides of the sacrificial pattern PP. The top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 is shown as substantially coplanar with the top surface of the highest first semiconductor pattern SP1 in the first semiconductor pattern SP1, but the inventive concept is not limited to this example. For example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed to have a top surface located at a level higher than the top surface of the highest first semiconductor pattern SP1 in the first semiconductor pattern SP1.

[0107] A first source / drain pattern SD1 and a second source / drain pattern SD2 can be formed using a selective epitaxial growth process, in which the inner surface of the first recessed region RC1 serves as a seed layer. Selective epitaxial growth processes can include, for example, chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0108] As an example, impurities can be implanted in situ into the first source / drain pattern SD1 and the second source / drain pattern SD2 during a selective epitaxial growth process for forming the first source / drain pattern SD1 and the second source / drain pattern SD2. As another example, impurities can be implanted into the first source / drain pattern SD1 and the second source / drain pattern SD2 after their formation. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0109] Reference Figure 14A and Figure 14B A first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, and the hard mask pattern MP (e.g., see...). Figure 13B ) and the first gate spacer GS1.

[0110] Next, the first interlayer insulating layer 110 can be planarized to expose the top surface of the sacrificial pattern PP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. In an embodiment, the hard mask pattern MP can be completely removed during the planarization process (e.g., see...). Figure 13BAfter the planarization process, the first interlayer insulating layer 110 may have a top surface that is substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the first gate spacer GS1.

[0111] Reference Figure 15A , Figure 15B and Figure 15C The sacrificial pattern PP can be selectively removed (e.g., see...). Figure 14A and Figure 14B As a result of removing the sacrificial pattern PP, a first empty space ET1 can be formed to expose the first active pattern AP1 and the second active pattern AP2.

[0112] Subsequently, the second semiconductor pattern SP2 can be selectively removed to form a second empty space ET2. Specifically, the second semiconductor pattern SP2 can be exposed through the first empty space ET1. The second semiconductor pattern SP2 can be selectively removed using an etching process that has high etch selectivity (e.g., a faster etch rate) relative to the first semiconductor pattern SP1, and in this case, the first semiconductor pattern SP1 may not be removed. As a result of removing the second semiconductor pattern SP2, a second empty space ET2 can be formed between the first semiconductor patterns SP1. Each second empty space ET2 can be defined as a space located between first semiconductor patterns SP1 that are adjacent to each other on a third direction D3.

[0113] Reference Figure 16A and Figure 16B A trimming process can be performed to partially etch each first semiconductor pattern SP1 exposed through the first empty space ET1 and the second empty space ET2. In each first semiconductor pattern SP1, the etched portion may be a portion on the third direction D3 that is not stacked with the first gate spacer GS1 and the second gate spacer GS2, as well as the first suppression layer INH1 and the second suppression layer INH2.

[0114] The thickness of each first semiconductor pattern SP1 on the third-direction D3 can be smaller after the trimming process than before the trimming process, for example... Figure 16A and 16B SP1b in the middle can be compared to Figure 15B and 15C SP1a is small.

[0115] Reference Figure 17A and Figure 17B A gate insulating layer GI can be formed in the first empty space ET1 and the second empty space ET2. Specifically, a gate oxide layer IL can be formed in the first empty space ET1 and the second empty space ET2, and a high-k dielectric layer HK can be formed to cover the gate oxide layer IL.

[0116] When in Figure 17A When viewed in a cross-sectional view, the gate oxide layer IL can be formed to cover the top and bottom surfaces of the first semiconductor pattern SP1 exposed through the first empty space ET1 and the second empty space ET2. When in Figure 17B When viewed in a cross-sectional view, the gate oxide layer IL can be formed around a first semiconductor pattern SP1 exposed through a first empty space ET1 and a second empty space ET2.

[0117] The high-k dielectric layer HK covering the gate oxide layer IL can be formed to have a uniform thickness using a selective atomic layer deposition (selective ALD) process. The selective ALD process can be performed such that the high-k dielectric layer HK is not formed on the side surfaces INH1s of the first suppression layer INH1 and the side surfaces INH2s of the second suppression layers INH2.

[0118] As a reference Figure 16A and Figure 16B As a result of the described trimming process, the high-k dielectric layer HK can be formed to be partially superimposed on the first semiconductor pattern SP1 in the first direction D1, but not superimposed on the first gate spacer GS1 and the second gate spacer GS2, as well as the first suppression layer INH1 and the second suppression layer INH2.

[0119] Return to reference Figure 1 , Figure 2A and Figure 2B A gate electrode GE can be formed to fill at least a portion of the first empty space ET1 and the second empty space ET2. A gate cap pattern GP can be formed on the gate electrode GE to completely fill the first empty space ET1. A second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. An active contact AC can be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0120] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer may be formed in the third interlayer insulating layer 130, and in an embodiment, the first metal layer may include a first interconnect M1, a first via V1, and a second via V2.

[0121] According to embodiments of the inventive concept, a semiconductor device may include a high-k dielectric layer partially disposed on the top and / or bottom surfaces of a gate electrode, and in this case, it may be possible to reduce parasitic capacitance in the device, thereby achieving a low-power device.

[0122] Additionally, according to embodiments of the inventive concept, the semiconductor device may include a high-k dielectric layer, which is configured to have a relatively large thickness on the top and / or bottom surfaces of the gate electrode and a relatively small thickness on the side surfaces of the gate electrode. Even in this case, it is possible to reduce parasitic capacitance in the device, thereby achieving a low-power device.

[0123] While some exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Base; An active pattern is located in the upper part of the substrate and extends in the first direction; The gate electrode intersects the active pattern and extends in a second direction that intersects the first direction; The first gate spacer covers the side surface of the gate electrode; The first suppression layer is located between the gate electrode and the first gate spacer; as well as A gate insulating layer is located between the gate electrode and the active pattern. The gate insulating layer comprises a high-k dielectric layer and a gate oxide layer, with the gate oxide layer located between the high-k dielectric layer and the active pattern. The high-k dielectric layer and the gate oxide layer are not stacked with the first suppression layer and the first gate spacer in the first direction, and A high-k dielectric layer is locally disposed between the gate oxide layer and the gate electrode, and does not contact the first suppression layer.

2. The semiconductor device according to claim 1, wherein, Active patterns include multiple channel layers. The multiple channel layers are stacked on top of each other. The gate electrode surrounds the plurality of channel layers. Each of the plurality of channel layers includes a first portion and a second portion located between the first portions. Each first portion is vertically stacked with the first gate spacer. The second part extends in the first direction and is vertically stacked with the gate electrode, and The thickness of each first part is greater than the thickness of the second part.

3. The semiconductor device according to claim 2, wherein, The gate oxide layer and the high-k dielectric layer are located in the space surrounded by the inner surface of the first part and the top surface of the second part.

4. The semiconductor device according to claim 3, wherein, A high-k dielectric layer covers the top surface of the gate oxide layer and contacts the inner surface of the first portion.

5. The semiconductor device according to claim 3, wherein, The gate oxide layer conformally covers the inner surface of the first portion and the top surface of the second portion, and The high-k dielectric layer is spaced apart from the plurality of channel layers and the gate oxide layer is located between the high-k dielectric layer and the plurality of channel layers.

6. The semiconductor device according to claim 5, wherein, The top surface of the high-k dielectric layer has a first surface and a second surface. The first surface of the high-k dielectric layer is positioned at a lower level than the highest surface of the gate oxide layer. The second surface is positioned at a level higher than the first surface of the high-k dielectric layer and is coplanar with the highest surface of the gate oxide layer. The gate electrode protrudes toward the second portion of each of the plurality of channel layers.

7. The semiconductor device according to claim 3, wherein, Each inner surface of the first part forms an acute angle with respect to the top surface of the second part.

8. The semiconductor device according to claim 3, wherein, Each inner surface of the first part connects to the top surface of the second part, while having a continuously varying tilt angle.

9. The semiconductor device according to claim 2, further comprising: A pair of source / drain patterns are disposed on both sides of the gate electrode; The second gate spacer is vertically stacked with the first gate spacer and the first portion of the plurality of channel layers, and the second gate spacer is in contact with one of the source / drain patterns of the pair of source / drain patterns; as well as The second suppression layer is located between the gate electrode and the second gate spacer. The second suppression layer is in direct contact with the gate electrode.

10. The semiconductor device according to claim 9, wherein, The second suppression layer surrounds the second gate spacer and contacts one of the source / drain patterns of the pair of source / drain patterns.

11. The semiconductor device according to claim 1, wherein, The top surface of the high-k dielectric layer is located at a level that is lower than or equal to the bottom surface of the first gate spacer.

12. A semiconductor device, the semiconductor device comprising: Base; An active pattern, located in the upper part of the substrate and extending in a first direction, comprises multiple channel layers stacked on top of each other; A gate electrode that intersects the active pattern and surrounds the plurality of channel layers, the gate electrode extending in a second direction that intersects the first direction; Gate spacers cover the side surface of the gate electrode; A suppression layer is located between the gate electrode and the gate spacer; A pair of source / drain patterns are located on both sides of the gate electrode; A gate insulating layer is located between the gate electrode and each of the plurality of channel layers; An interlayer insulating layer covers the gate electrode and the gate spacer; Active contacts penetrate the interlayer insulation layer and are correspondingly connected to the pair of source / drain patterns; as well as A gate contact, penetrating at least a portion of the interlayer insulating layer and connected to the gate electrode, wherein... The gate insulating layer includes a high-k dielectric layer and a gate oxide layer. The gate oxide layer is located between the high-k dielectric layer and each of the plurality of channel layers. The high-k dielectric layer and the gate oxide layer are not stacked with the first suppression layer and the first gate spacer in the first direction, and A high-k dielectric layer is locally disposed between the gate oxide layer and the gate electrode, and does not contact the first suppression layer.

13. The semiconductor device according to claim 12, wherein, Each of the plurality of channel layers has a column shape that intersects with the gate electrode and extends in a first direction, and The cross-section of each of the plurality of channel layers is circular, elliptical, or rectangular.

14. The semiconductor device according to claim 12, wherein, Each of the plurality of channel layers includes a first portion and a second portion located between the first portions. Each first portion is vertically stacked with the gate spacer. The second part extends in the first direction and is vertically stacked with the gate electrode, and The thickness of each first part is greater than the thickness of the second part.

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