集成组合件及形成集成组合件的方法
By forming alternating conductive structures and semiconductor pillars on the substrate structure and combining this with improved etching processes in grain boundary regions, the problem of low integration density in memory architecture has been solved, achieving efficient memory integration and performance improvement.
CN114388506BActive Publication Date: 2026-07-17MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2021-09-28
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing memory architectures, the integration of transistors and memory cells suffers from low efficiency and low integration density.
Method used
By combining conductive structures on a substrate with pillars of semiconductor material, alternating steps and recessed regions are formed, and the etching process is improved by utilizing grain boundary regions to form semiconductor pillars with vertical sidewalls, which are then coupled to memory elements.
Benefits of technology
It improves memory integration and efficiency, enhances etch alignment, and improves memory performance uniformity and threshold voltage characteristics.
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Figure CN114388506B_ABST
Abstract
本申请案涉及集成组合件及形成集成组合件的方法。一些实施例包含一种集成组合件，其包含基底结构。所述基底结构包含沿第一方向延伸的一系列导电结构。所述导电结构具有沿所述第一方向与凹入区交替的台阶。半导体材料的支柱在所述台阶上方。所述半导体材料包含选自周期表的第13族的至少一种元素结合选自周期表的第16族的至少一种元素。在一些应用中，所述半导体材料可为半导体氧化物。一些实施例包含形成集成组合件的方法。
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