Method for preparing three-dimensional memory and three-dimensional memory

Abstract

The embodiments of the present application provide a method for preparing a three-dimensional memory and a three-dimensional memory. The method for preparing a three-dimensional memory includes: forming a stacked structure including a plurality of steps on one side of a substrate, each step including alternatingly stacked gate sacrificial layers and insulating layers; forming a buffer layer covering the steps; forming a first dielectric layer covering the buffer layer; and forming a first mask layer covering the first dielectric layer and having a first opening corresponding to the sidewall of the step, and etching the first dielectric layer and the buffer layer covering the sidewall of the step through the first opening. The embodiments of the present application use the first mask layer to remove the buffer layer remaining on the sidewall of the step, which can reduce the probability of short circuits between different gate layers (i.e., word line bridging between different layers), thereby improving the yield of the three-dimensional memory.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor design and manufacturing, and more specifically, to a method for preparing a three-dimensional memory and a three-dimensional memory. Background Art

[0002] With the improvement of the integration level of three-dimensional memory and the increase of the number of stacked layers, the depth of the step structure in the stacked structure is getting deeper and deeper. In the process of forming the conductive contact structure of the word line, the problem of word line breakdown is prone to occur. In order to reduce this problem, at present, silicon nitride is often deposited on the surface of the step after the step is formed to increase the process window of the conductive contact structure.

[0003] However, after adding the process of depositing silicon nitride on the step surface, the yield of the three-dimensional memory is easily affected due to process deviation. Summary of the invention

[0004] The embodiments of the present application provide a method for preparing a three-dimensional memory and a three-dimensional memory that can at least partially solve the above-mentioned problems existing in some embodiments.

[0005] An embodiment of the present application provides a method for preparing a three-dimensional memory, comprising: forming a stacked structure including a plurality of steps on one side of a substrate, each step including alternatingly stacked gate sacrificial layers and insulating layers; forming a buffer layer covering the steps; forming a first dielectric layer covering the buffer layer; and forming a first mask layer covering the first dielectric layer and having a first opening corresponding to the sidewall of the step, and etching the first dielectric layer and the buffer layer covering the sidewall of the step through the first opening.

[0006] In some embodiments of the present application, before forming the first dielectric layer, the method also includes: forming a second mask layer covering the buffer layer; trimming the second mask layer covering the top surface of the step to form a second opening corresponding to the side wall of the step, and etching the buffer layer covering the side wall of the step through the second opening; and removing the second mask layer.

[0007] In some embodiments of the present application, the second mask layer includes a hard mask layer.

[0008] In some embodiments of the present application, the first mask layer further has a third opening corresponding to a scribe line region of the stacked structure.

[0009] In some embodiments of the present application, the first mask layer includes a soft mask layer.

[0010] In some embodiments of the present application, the material of the soft mask layer includes photoresist.

[0011] In some embodiments of the present application, the method further includes: filling a second dielectric layer in an opening formed by etching the first dielectric layer and the buffer layer covering the step sidewalls through the first opening to cover the step sidewalls.

[0012] In some embodiments of the present application, the method further includes: removing the first mask layer.

[0013] In some embodiments of the present application, before forming the buffer layer covering the steps, the method further includes: exposing at least a portion of the gate sacrificial layer of each step.

[0014] In some embodiments of the present application, the method further includes: planarizing the surface of the first dielectric layer.

[0015] In some embodiments of the present application, the method further includes: replacing the gate sacrificial layer with a gate layer; and replacing the buffer layer remaining after etching through the first opening with a conductor layer, wherein the gate layer and the conductor layer are made of the same material.

[0016] In some embodiments of the present application, the method further includes: forming a plurality of conductive contact structures penetrating the first dielectric layer and connecting the conductor layer.

[0017] Another aspect of the embodiments of the present application provides a three-dimensional memory, which is formed by the method for preparing a three-dimensional memory mentioned in the above embodiments.

[0018] According to the method for preparing a three-dimensional memory and the three-dimensional memory provided by the embodiments of the present application, after forming the first dielectric layer, a first mask layer covering the first dielectric layer and having a first opening corresponding to the step sidewall is formed, and the buffer layer on the step sidewall is etched through the first mask layer having the first opening, so that the buffer layer covering the step sidewall can be removed more cleanly, thereby reducing the short circuit of different gate layers (i.e., word lines) caused by the residual buffer layer covering the step sidewall, thereby reducing the storage failure of the three-dimensional memory due to the short circuit of the gate layer, thereby improving the yield of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0020] Figure 1 is a schematic diagram of the structure of a three-dimensional memory in some embodiments;

[0021] Figure 2a is a top view of a scanning electron microscope schematic diagram of a region where a step with a deeper depth is located in a three-dimensional memory in some embodiments;

[0022] Figure 2b yes Figure 2a A cross-sectional SEM diagram of the three-dimensional memory shown;

[0023] Figure 2c yes Figure 2b A cross-sectional SEM diagram of a three-dimensional memory after a gate sacrificial layer is replaced with a gate layer;

[0024] Figure 3 is a schematic flow chart of a method for preparing a three-dimensional memory according to one embodiment of the present application;

[0025] Figure 4 is a schematic structural diagram of a three-dimensional memory after forming a stacked structure with multiple steps according to an embodiment of the present application;

[0026] Figure 5 is a schematic structural diagram of a three-dimensional memory device that exposes at least a portion of a gate sacrificial layer of each step according to an embodiment of the present application;

[0027] Figure 6 is a schematic structural diagram of a three-dimensional memory after a buffer layer is formed according to an embodiment of the present application;

[0028] Figure 7 is a schematic structural diagram of a three-dimensional memory after etching the buffer layer covering the step sidewall through the second opening according to an embodiment of the present application;

[0029] Figure 8 is a schematic structural diagram of a three-dimensional memory after forming a first dielectric layer covering a buffer layer according to an embodiment of the present application;

[0030] Fig. 9 is a schematic structural diagram of a three-dimensional memory after forming a first mask layer having a first opening according to an embodiment of the present application;

[0031] Fig.10 is a schematic structural diagram of a three-dimensional memory after etching the first dielectric layer and the buffer layer covering the step sidewalls through the first opening according to an embodiment of the present application;

[0032] Fig.11 is a schematic diagram of the positions of a step, a first mask layer and a first opening of a three-dimensional memory according to an embodiment of the present application;

[0033] Fig.12 is a schematic structural diagram of a three-dimensional memory after a second dielectric layer is filled in an opening formed by etching to cover the sidewall of a step according to an embodiment of the present application;

[0034] Fig.13is a schematic structural diagram of a three-dimensional memory after removing the first mask layer according to an embodiment of the present application;

[0035] Fig.14 is a schematic structural diagram of a three-dimensional memory after a gate sacrificial layer is replaced with a gate layer according to an embodiment of the present application;

[0036] Fig.15 is a schematic structural diagram of a three-dimensional memory after a conductive contact structure is formed according to an embodiment of the present application;

[0037] Fig.16 is a block diagram of a three-dimensional memory according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first dielectric layer discussed in this application may also be referred to as the second dielectric layer, the first opening may also be referred to as the second opening, and vice versa.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] The terms used herein are for the purpose of describing specific exemplary embodiments and are not intended to be limiting. When used in this specification, the terms "comprise", "comprising", "including" and / or "comprising" indicate the presence of features, integral bodies, elements, parts and / or combinations thereof, but do not exclude the presence of one or more other features, integral bodies, elements, parts and / or combinations thereof.

[0042] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0044] With the improvement of the integration level of three-dimensional memory and the increase of stacking layers, the depth of the step structure in the stacking structure is getting deeper and deeper. In the process of forming the conductive contact structure of the word line (also called the gate layer), the problem of word line breakdown is prone to occur. In order to reduce this problem, Figure 1 As shown, after forming the step 101 of the three-dimensional memory, a buffer layer is often deposited on the surface of the step 101, so that the silicon nitride on the surface of the step can be replaced with a conductive material to form a conductor layer 102, so as to increase the process window of the conductive contact structure 103 of the word line. The material of the buffer layer can be, for example, silicon nitride. Generally, the process of forming the conductor layer 102 may include: forming a buffer layer covering the step 101; forming a mask layer covering the buffer layer; trimming the mask layer to form an opening corresponding to the side wall of the step 101; etching the buffer layer on the side wall of the step 101 through the opening of the mask layer. Among them, the process of forming the mask layer may include: deposition of a carbon-based polymer material (C dep), and deposition of a carbon-based polymer material for curing (Cure C dep). Cure C dep is a plasma vertical deposition. The inventors found that if the step is relatively inclined, Cure C will be deposited on the top surface of the step 101, each stacked layer 104 in the step 101 (see Figure 2b ) on the exposed top surface and side walls of each stacked layer 104. During the process of trimming the mask layer, it is difficult to completely remove the portion of Cure C deposited on the top surface and side walls of the stacked layer 104, resulting in the buffer layer deposited on the top surface and side walls of the stacked layer 104 being protected and unable to be etched cleanly, which in turn leads to the problem of word line short circuit after the buffer layer is replaced by the conductor layer 102.

[0045] For example, Figure 2a is a top view of a scanning electron microscope schematic diagram of a region where a step 101 with a relatively deep depth of the three-dimensional memory is located. Figure 2b yes Figure 2a The cross-sectional SEM diagram of the three-dimensional memory is shown. Figure 2c yes Figure 2b The schematic cross-sectional SEM diagram of the gate sacrificial layer 1041 in the three-dimensional memory is shown in FIG. Figure 2a to Figure 2cAs shown in area A, the step 101 is formed by etching a plurality of stacked layers 104 (including a gate sacrificial layer 1041 and an insulating layer 1042). Due to the large number of etched stacked layers 104, the silicon nitride on the side wall of the step 101 is more easily retained during the mask layer trimming process, resulting in the silicon nitride being replaced by a conductive material, which short-circuits the gate layer formed by replacing the gate sacrificial layer 1041 with a conductive material.

[0046] Figure 3 FIG. 1 is a flow chart of a method 1000 for preparing a three-dimensional memory according to an embodiment of the present application. Figure 3 As shown, a method 1000 of manufacturing a three-dimensional memory according to an embodiment of the present application includes:

[0047] S11, forming a stacked structure including a plurality of steps on one side of the substrate, each step including alternately stacked gate sacrificial layers and insulating layers.

[0048] S12, forming a buffer layer covering the step.

[0049] S13, forming a first dielectric layer covering the buffer layer.

[0050] S14, forming a first mask layer covering the first dielectric layer and having a first opening corresponding to the step sidewall, and etching the first dielectric layer and the buffer layer covering the step sidewall through the first opening.

[0051] According to the method for preparing a three-dimensional memory provided by at least one embodiment of the present application, after forming a first dielectric layer, a first mask layer covering the first dielectric layer and having a first opening corresponding to a step sidewall is formed, the first opening can expose a portion of the first dielectric layer corresponding to the step sidewall, and then the step sidewall can be etched, so that the buffer layer covering the step sidewall can be removed more cleanly, reducing the short circuit of different gate layers (i.e., word lines) caused by the residual buffer layer covering the step sidewall, and then reducing the storage failure of the three-dimensional memory due to the short circuit of the gate layer, thereby improving the yield of the three-dimensional memory.

[0052] The following will be combined Figures 4 to 15 The specific process of each step of the above-mentioned preparation method 1000 is described in detail.

[0053] Step S11

[0054] Figure 4 It is a schematic structural diagram of a three-dimensional memory after forming a stacked structure 200 with a plurality of steps 300 according to an embodiment of the present application. Figure 5 3 is a schematic structural diagram of a three-dimensional memory device that exposes at least a portion of the gate sacrificial layer 220 of each step 300 according to an embodiment of the present application.

[0055] like Figure 4 As shown, in one embodiment of the present application, on the substrate 100, a stacked structure 200 may be formed on one side of the substrate by one or more thin film deposition processes. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0056] In some embodiments of the present application, the substrate 100 may be made of any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or III-V compounds such as gallium arsenide. Alternatively, the substrate 100 may be made of single crystal silicon material.

[0057] Alternatively, the substrate 100 may be a composite substrate for supporting a device structure thereon. The substrate 100 may be formed by sequentially depositing a plurality of layers made of different materials by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0058] In some embodiments of the present application, Figure 4 As shown, the stacked structure 200 may include, for example, a plurality of pairs of insulating layers 210 and gate sacrificial layers 220 alternately stacked with each other. For example, the stacked structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate sacrificial layers 220. In some embodiments, the insulating layer 210 includes a first dielectric material, and the gate sacrificial layer 220 includes a second dielectric material different from the first dielectric material. Exemplary materials for forming the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as the insulating layer 210 to isolate the gate sacrificial layer 220, and a silicon nitride layer may be used as the gate sacrificial layer 220.

[0059] The laminate structure 200 may have a core region (not shown) and a step region (e.g. Figure 4 As shown), the core region is used to form an array memory cell string, which is a plurality of interconnected memory cells formed in a direction perpendicular to the substrate 100; the step region is used to form a conductive contact structure 800 on the gate sacrificial layer 220 (see Fig.15 ) to draw current from it.

[0060] It should be noted that, in order to explain the present application concisely and clearly, this document only takes the stacked structure 200 including a single sub-stack as an example to illustrate the process. It should be understood by those skilled in the art that the stacked structure 200 may also include multiple sub-stacks, that is, the stacked structure 200 may be formed by a single sub-stack or by stacking multiple sub-stacks in sequence. It should also be noted that, for the sake of clarity, in the various drawings of the present application, only the portion of the stacked structure 200 in the step region is shown.

[0061] See again Figure 4 In one embodiment of the present application, a step 300 is formed in the step region of the stacked structure 200. As an example, a plurality of steps 300 may be formed in the step region by performing repeated etching-trimming processes on the stacked structure 200 using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and may be removed after the step 300 is formed. Figure 4 , the top surface of each step 300 formed may be, for example, an insulating layer 210. That is, each step 300 includes at least one stacked layer, and each stacked layer includes, from top to bottom, an insulating layer 210 and a gate sacrificial layer 220. It should be understood that each stacked layer may also include, from top to bottom, a gate sacrificial layer 220 and an insulating layer 210, and the present application does not limit this.

[0062] In one embodiment of the present application, see Figure 4 The step 300 includes a plurality of stacked layers, and the ends of the stacked layers in the same step 300 form a stepped structure in a direction perpendicular to the substrate 100. For example, the farther the distance between the stacked layer and the substrate 100 is, the smaller the size of the stacked layer is, so that the ends of the stacked layers of the step 300 are staggered.

[0063] In one embodiment of the present application, the step 300 may be formed at one side edge or multiple side edges of the stacked structure 200 , or may be formed at the center of the stacked structure 200 .

[0064] It should be noted that, in order to explain the present application concisely and clearly, the drawings herein only show the case where each step 300 includes 5 stacking layers. It should also be noted that the number of stacking layers of each step can be adjusted as needed, and the number of stacking layers included in different steps can be different.

[0065] In one embodiment of the present application, the method 1000 for preparing a three-dimensional memory may further include, for example: exposing at least a portion of the gate sacrificial layer 220 of each step 300. As an alternative, see Figure 5 , in the formation Figure 4After the steps 300 are formed, the portion of the insulating layer 210 exposed on the top surface of each step 300 can be removed by wet etching or dry etching to expose at least a portion of the gate sacrificial layer 220 underneath, so that the surface of the step 300 is the gate sacrificial layer 220.

[0066] Step S12

[0067] Figure 6 It is a schematic structural diagram of a three-dimensional memory after forming a buffer layer 400 according to an embodiment of the present application. Figure 7 It is a schematic structural diagram of a three-dimensional memory after etching the buffer layer 400 covering the sidewall of the step 300 through the second opening according to an embodiment of the present application.

[0068] like Figure 6 As shown, in an exemplary embodiment of the present application, a buffer layer 400 may be formed on the top surface and sidewalls of each step 300. The buffer layer 400 may cover the exposed portion of the gate sacrificial layer 220 on the top surface of each step 300 and may cover the sidewalls of each step 300.

[0069] As an example, the buffer layer 400 may be formed on the top surface and sidewall of each step 300 by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD) or any combination thereof. For example, the buffer layer 400 may be formed by an atomic layer deposition process.

[0070] As an example, TS SIN can be selected as the material for forming the buffer layer 400. For example, when wet etching is performed using phosphoric acid or the like as an etchant, the TS SIN material has an etching rate about two to three times that of normal SIN, and the gate sacrificial layer 220 is usually made of normal SIN, so that in the subsequent etching process of the gate sacrificial layer 220 and the buffer layer 400, the buffer layer 400 can be etched more cleanly.

[0071] In some embodiments of the present application, see Figure 7, the method 1000 for preparing a three-dimensional memory may also include, for example: forming a second mask layer (not shown) covering the buffer layer 400; trimming the second mask layer covering the top surface of the step 300 to form a second opening (not shown) corresponding to the side wall of the step 300; etching the buffer layer 400 covering the side wall of the step 300 through the second opening; and removing the second mask layer. Exemplarily, the step 300 includes a plurality of stacked layers, and the ends of each stacked layer of the step 300 are staggered, resulting in the second mask layer being deposited on the exposed top surface and side wall of each stacked layer, so that in the process of trimming the second mask layer, the second mask layer corresponding to the top surface and side wall of other stacked layers except the stacked layer at the top of the step 300 may not be completely removed, resulting in the inability to completely remove the buffer layer 400 covering the top surface and side wall of other stacked layers.

[0072] For example, for the conductor layer 410 to be formed (see Fig.14 ), the buffer layer 400 on the sidewall of the step 300 is etched to form a spacing groove 310, so that the buffer layer 400 on the top surface of the step 300 is separated from the gate sacrificial layer 220 on other planes, so that the buffer layer 400 is subsequently replaced by the conductor layer 410 (see Fig.14 ) and the gate sacrificial layer 220 is subsequently replaced by the gate layer 230 (see Fig.14 ) can prevent the conductor layer 410 (see Fig.14 ) and other plane gate layers 230 (see Fig.14 ) contact, which can effectively avoid different gate layers 230 (see Fig.14 ) between the short circuit (ie, the word line bridge between different layers). In addition, the buffer layer 400 is replaced by the conductor layer 410 (see Fig.14 ) can also prevent the gate layer 230 from being broken through when the contact hole is subsequently formed (see Fig.14 ).

[0073] As an example, the second mask layer may be, for example, a hard mask layer, and the material of the hard mask layer may be, for example, a carbon-based polymer material.

[0074] It should be understood that the second mask layer may be formed of other materials without departing from the teaching of the present application, and the present application does not limit this.

[0075] As an example, the second mask layer may be trimmed by photolithography technology to form the second opening.

[0076] It should be understood that, without departing from the teaching of the present application, the second mask layer may be trimmed in other ways to form the second opening, and the present application does not limit this.

[0077] Step S13

[0078] Figure 8 4 is a schematic structural diagram of a three-dimensional memory after forming a first dielectric layer 500 covering the buffer layer 400 according to an embodiment of the present application.

[0079] like Figure 8 As shown, a first dielectric layer 500 is formed on the step 300. As an example, the first dielectric layer 500 may be formed by depositing an oxide, and the oxide may be selected from, for example, a silicon oxide-based material.

[0080] In one embodiment of the present application, the first dielectric layer 500 may be formed by filling TEOS-based silicon oxide. The first dielectric layer 500 may be a multi-layer structure, and a first sub-film layer with good step coverage is first formed, such as silicon oxide (SiO) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD), etc.; and then a second sub-film layer with high filling efficiency is formed, and the second sub-film layer may be, for example, TEOS-based silicon oxide (TESO-based SiO). The density of the first sub-film layer is higher than that of the second sub-film layer, so that the first sub-film layer has good step coverage, and the second sub-film layer has high filling efficiency.

[0081] As an example, the surface of the first dielectric layer 500 may be planarized by further using processes such as chemical mechanical polishing, so that the first dielectric layer 500 provides a substantially flat upper surface for the step region of the stacked structure 200 .

[0082] Step S14

[0083] Fig. 9 It is a schematic structural diagram of a three-dimensional memory after forming a first mask layer 600 having a first opening 610 according to an embodiment of the present application. Fig.10 It is a schematic structural diagram of a three-dimensional memory after etching the first dielectric layer 500 and the buffer layer 400 covering the sidewall of the step 300 through the first opening 610 according to an embodiment of the present application.

[0084] See also Fig. 9 In one embodiment of the present application, the first mask layer 600 includes a soft mask layer.

[0085] Exemplarily, the material of the soft mask layer includes photoresist (PR), and the first mask layer 600 can be formed by PR development technology. For example, the process of forming the first mask layer 600 covering the first dielectric layer 500 and having the first opening 610 corresponding to the side wall of the step 300 can include: after the first dielectric layer 500 is planarized, cleaned and dried, photoresist can be coated on the surface of the first dielectric layer 500 to form the first mask layer 600; the first mask layer 600 is exposed through a photolithography mask having a pattern corresponding to the first opening 610, and then a development process is performed to form the first opening 610 corresponding to the side wall of the step 300 in the first mask layer 600.

[0086] Exemplarily, the step 300 includes a plurality of stacked layers. Considering that the sidewall of the step 300 is more likely to have a Cure C dep than the sidewall of the step 300 formed by etching a small amount (such as a pair) of alternately stacked gate sacrificial layers 220 and insulating layers 210, which leads to the situation that the buffer layer 400 on the sidewall of the step 300 is not removed cleanly during the process of removing the buffer layer 400 on the sidewall of the step 300 through the second mask layer, the embodiment of the present application forms a first opening 610 in the step 300 region through the PR development technology after applying the photoresist. The first opening 610 can expose the first dielectric layer covering the sidewall of the step 300. Through the first opening 610, the buffer layer 400 covering the sidewall of the step 300 can be removed cleanly.

[0087] See also Fig.10 In one embodiment of the present application, the first dielectric layer 500 and the buffer layer 400 covering the sidewall of the step 300 are etched through the first opening 610 to form an opening 620 .

[0088] In one embodiment of the present application, the first mask layer 600 further has a third opening (not shown) corresponding to a scribe line region (not shown) of the stacked structure 200 .

[0089] For example, the photolithography mask used in the process of forming the first mask layer 600 by the PR development technology may be, for example, a bottom silicon nitride removal photolithography mask (BNRM mask). The photolithography mask has a pattern of a third opening for forming a cutting road area for opening the three-dimensional memory. On this basis, a pattern of the first opening 610 is formed on the photolithography mask so that the first mask layer 600 having the first opening 610 corresponding to the side wall of the step 300 is formed later, which can reduce the process cost.

[0090] In one embodiment of the present application, the first opening 610 is formed at a step region with a relatively deep depth. For example, a schematic diagram of the positions of the step 300, the first mask layer 600 and the first opening 610 of the three-dimensional memory is shown in FIG. Fig.11 As shown, the dotted line frame area is the coverage area of ​​the first mask layer 600. Fig.11 The first mask layer 600 has a first opening 610 corresponding to the sidewall of the step 300 with a deeper depth, and the first opening 610 may not be formed at the step 300 with a shallower depth.

[0091] It should be understood that, without departing from the teaching of the present application, the step region where the first opening 610 needs to be formed can be selected based on the etching of the buffer layer 400 on the sidewall of the step 300 based on the second opening, and the present application does not impose any limitation on this.

[0092] Fig.12 is a schematic structural diagram of a three-dimensional memory after a second dielectric layer 700 is filled in an opening 620 formed by etching to cover a side wall of a step 300 according to an embodiment of the present application; Fig.13 It is a schematic structural diagram of a three-dimensional memory after removing the first mask layer 600 according to an embodiment of the present application.

[0093] In one embodiment of the present application, see Fig.12 The method for preparing a three-dimensional memory may also include, for example: filling a second dielectric layer 700 through the first opening 610 in the opening 620 formed by etching the first dielectric layer 500 and the buffer layer 400 covering the sidewall of the step 300 to cover the sidewall of the step 300 .

[0094] By way of example, the second dielectric layer 700 may be formed by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

[0095] In one embodiment of the present application, see Fig.13 The method 1000 for manufacturing a three-dimensional memory may further include, for example: removing the first mask layer 600. Exemplarily, the first mask layer 600 may be removed by dry etching or wet etching.

[0096] In one embodiment of the present application, the method 1000 for manufacturing a three-dimensional memory may further include, for example: polishing a side of the stacked structure 200 away from the substrate 100 to provide a planarized surface.

[0097] Fig.14 It is a schematic structural diagram of a three-dimensional memory after the gate sacrificial layer 220 is replaced by a gate layer 230 according to an embodiment of the present application.

[0098] In one embodiment of the present application, see Fig.14 The method for preparing a three-dimensional memory may also include, for example: replacing the gate sacrificial layer 220 with a gate layer 230; and replacing the buffer layer 400 remaining after etching through the first opening with a conductor layer 410, wherein the gate layer 230 and the conductor layer 410 may be made of the same material.

[0099] As an example, the method for preparing a three-dimensional memory may further include, for example, forming a gate gap (not shown). The steps of replacing the gate sacrificial layer 220 with the gate layer 230 and replacing the buffer layer 400 remaining after etching through the first opening with the conductor layer 410 may, for example, include: removing the buffer layer 400 through the gate gap (see Fig.13 ) to form a space, and remove the gate sacrificial layer 220 through the gate gap to form a sacrificial gap (not shown); deposit a first conductive material through the gate gap, the first conductive material fills the sacrificial gap to form a gate layer 230, and fills the space formed after removing the buffer layer 400 to form a conductor layer 410.

[0100] Alternatively, the gate layer 230 may be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0101] Alternatively, the conductor layer 410 may be formed in the space formed after the buffer layer 400 is removed by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0102] Fig.15 It is a schematic structural diagram of a three-dimensional memory after a conductive contact structure 800 is formed according to an embodiment of the present application.

[0103] In one embodiment of the present application, see Fig.15 The method for preparing a three-dimensional memory may further include, for example: forming a plurality of conductive contact structures 800 penetrating the first dielectric layer 500 and connecting the conductor layer 410 .

[0104] As an example, forming the conductive contact structure 800 may include, for example: forming a contact hole (not shown) in the step region that penetrates the first dielectric layer 500 and extends to the conductor layer 410, and filling the contact hole with a second conductive material to form the conductive contact structure 800. The contact hole may extend only to the top surface of the conductor layer 410.

[0105] As an example, the first dielectric layer 500 can be removed by a wet etching process and extended to the conductor layer 410 and at least a portion of the gate layer 230 farthest from the substrate 100. Since the conductor layer 410 is located above the gate layer 230, the probability of the gate layer 230 being broken down can be reduced. Then, the removed space is filled with a conductive material such as tungsten alloy to form a conductive contact structure 800. It should be noted that the selection of the above-mentioned layers of materials and the specific processes of their formation and removal are only for the purpose of more clearly and concisely explaining the present application, rather than limiting the present application.

[0106] As an example, the second conductive material may, for example, include a conductive material such as iron nitride, dove alloy, or the like.

[0107] As an example, the conductor layer 410 and the gate layer 230 may be made of metal tungsten material, and the first dielectric layer 500 and the insulating layer 210 may be made of SiO 2 material.

[0108] According to an embodiment of the present application, even if over-etching occurs during the process of etching to form the contact hole, the conductive contact structure 800 subsequently formed in the contact hole extends to the conductor layer 410 to effectively avoid bridging of the gate layer 230 between different layers.

[0109] In one embodiment of the present application, the method for preparing a three-dimensional memory may further include, for example: forming a dummy channel structure (not shown) penetrating the step region and extending to the substrate 100. The dummy channel structure may be, for example, disposed in the step region.

[0110] As an example, a virtual channel hole (not shown) penetrating the dielectric layer and extending to the substrate 100 may be formed in the step region by photolithography and etching processes, and then an insulating material may be filled in the virtual channel hole to form a virtual channel structure, such as by depositing silicon nitride-based material by ALD.

[0111] As an example, the dummy channel hole may also be formed together with the contact hole, and then filled with the insulating material and the conductive material respectively.

[0112] On the other hand, the present application provides a three-dimensional memory, which can be prepared by the method for preparing a three-dimensional memory mentioned in the above embodiment.

[0113] Fig.16 is a schematic block diagram of a three-dimensional memory mentioned according to some embodiments of the present application.

[0114] like Fig.16 As shown, the three-dimensional memory 3000 may include, for example: a first semiconductor structure 3100 and a second semiconductor structure 3200. The structure of the first semiconductor structure 3100 may be, for example Fig.15As shown, the second semiconductor structure 3200 includes a stacked structure 200 , a conductor layer 410 , a first dielectric layer 500 , a second dielectric layer 700 and a conductive contact structure 800 . The second semiconductor structure 3200 includes a peripheral circuit electrically connected to the first semiconductor structure 3100 .

[0115] In one embodiment of the present application, on the substrate 100, a stacked structure 200 may be formed on one side of the substrate by one or more thin film deposition processes. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0116] In some embodiments of the present application, the substrate 100 may be made of any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or III-V compounds such as gallium arsenide. Alternatively, the substrate 100 may be made of single crystal silicon material.

[0117] Alternatively, the substrate 100 may be a composite substrate for supporting a device structure thereon. The substrate 100 may be formed by sequentially depositing a plurality of layers made of different materials by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0118] See also Fig.15 , the stacked structure 200 may be disposed on one side of the substrate 100, and may, for example, include a plurality of pairs of insulating layers 210 and gate layers 230 alternately stacked with each other. For example, the stacked structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate layers 230. In some embodiments, the insulating layer 210 includes a first dielectric material, and the gate layer 230 includes a conductive material. Exemplary materials for forming the insulating layer 210 and the gate layer 230 may include silicon oxide and metal tungsten, respectively. A silicon oxide layer may be used as the insulating layer 210 to isolate the gate layer 220, and a metal tungsten layer may be used as the gate layer 230.

[0119] The laminate structure 200 may have a core region (not shown) and a step region (e.g. Fig.15 As shown), wherein the core region is used to form array memory cell strings, which are multiple interconnected memory cells formed in a direction perpendicular to the substrate 100; the step region is used to form a conductive contact structure 800 on the gate layer 230 to draw current therefrom.

[0120] It should be noted that, in order to explain the present application concisely and clearly, this document only takes the stacked structure 200 including a single sub-stack as an example to illustrate the process. It should be understood by those skilled in the art that the stacked structure 200 may also include multiple sub-stacks, that is, the stacked structure 200 may be formed by a single sub-stack or by stacking multiple sub-stacks in sequence. It should also be noted that, for the sake of clarity, in the various drawings of the present application, only the portion of the stacked structure 200 in the step region is shown.

[0121] In various embodiments of the present application, the step 300 may be formed at one side edge or multiple side edges of the stacked structure 200, or may be formed at the center of the stacked structure 200. As an example, the step region at the center may also include a first connection region, a second connection region, and a third connection region that are sequentially arranged, and the step 300 is formed only in the second connection region, and the first connection region and the third connection region located on both sides of the second connection region do not form the step 300.

[0122] It should be noted that, in order to explain the present application concisely and clearly, the drawings herein only show the case where each step 300 includes multiple stacked layers. It should also be noted that the number of stacked layers of each step can be adjusted as needed.

[0123] The conductor layer 410 may be disposed on a side of the gate layer 230 away from the substrate 100 . The conductive contact structure 800 may extend to the conductor layer 410 , or penetrate the conductor layer 410 and extend to the gate layer 230 .

[0124] The three-dimensional memory may also include, for example, a first dielectric layer 500 and a second dielectric layer 520 covering the conductor layer 410 and the side of the step 300. The insulating layer 210, the first dielectric layer 500 and the second dielectric layer 700 may all be, for example, insulating materials. The materials of the gate layer 230 and the conductor layer 410 may both include, for example, tungsten metal.

[0125] In one embodiment of the present application, the three-dimensional memory may further include a dummy channel structure (not shown). The dummy channel structure may be formed in the step region, penetrate the step region and extend to the substrate 100 .

[0126] As an example, a virtual channel hole (not shown) penetrating the dielectric layer and extending to the substrate 100 may be formed in the step region by photolithography and etching processes, and then an insulating material may be filled in the virtual channel hole to form a virtual channel structure, such as by depositing silicon nitride-based material by ALD.

[0127] As an example, the dummy channel hole may also be formed together with the contact hole, and then filled with the insulating material and the conductive material respectively.

[0128] For example, see Fig.16, the peripheral circuit may, for example, include an address decoder 3201, a page buffer 3202, a control logic circuit 3203, an I / O circuit 3204, and a voltage generator 3205.

[0129] The first semiconductor structure 3100 may be connected to the address decoder 3201 through, for example, word lines WL, and connected to the page buffer 3202 through, for example, bit lines BL.

[0130] The address decoder 3201 may control the word line WL in response to the control logic circuit 3203. In other words, the address decoder 3201 may receive and decode the address ADDR from the control logic circuit 3203, and select one of the plurality of memory blocks in the memory cell array formed in the first semiconductor structure 3100 according to the decoded address ADDR.

[0131] The page buffer 3202 may be used as a write driver or a sense amplifier according to the operation mode. For example, in a programming operation, the page buffer 3202 may provide a bit line voltage corresponding to the data DATA to be programmed to the bit line BL. The data DATA may be multi-bit data to be programmed. In a read operation, the page buffer 3202 may sense the data stored in the selected memory cell through the bit line BL and output the sensed data DATA to the I / O circuit 3204. The page buffer 3202 may include a plurality of page buffers respectively connected to the bit lines BL.

[0132] The control logic circuit 3203 may control the address decoder 3201, the page buffer 3202, and the voltage generator 3205 in response to a command CMD (e.g., a program command and a read command) and an address ADDR from the I / O circuit 3204. In addition, the control logic circuit 3203 may control the three-dimensional memory 3000 to perform a programming operation through a multi-step method. The multi-step method may perform a programming operation multiple times to configure a desired programming state, and may include a pre / main programming method, a reprogramming method, a shadow programming method, etc.

[0133] The voltage generator 3205 may generate a voltage required to be provided to the word line WL under the control of the control logic circuit 3203 .

[0134] Those skilled in the art should understand that the operations performed by the address decoder 3201, the page buffer 3202, the control logic circuit 3203, and the voltage generator 3205 described in the present application can be performed by a processing circuit. The processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0135] According to at least one embodiment of the present application, in the preparation process of the three-dimensional memory, after forming the first dielectric layer, a first mask layer covering the first dielectric layer and having a first opening corresponding to the step sidewall is formed, so that in the process of forming the first mask layer having the first opening, the region on the top surface of the first dielectric layer corresponding to the step sidewall is less likely to have mask deposition, so that the buffer layer covering the step sidewall can be removed more cleanly, reducing the short circuit of different gate layers (i.e., word lines) caused by the residual buffer layer covering the step sidewall, thereby reducing the storage failure of the three-dimensional memory due to the short circuit of the gate layer, thereby improving the yield of the three-dimensional memory.

[0136] The contents and structures involved in the method for preparing a three-dimensional memory described above may be fully or partially applicable to the three-dimensional memory described here, and therefore, the contents related or similar thereto will not be described in detail here.

[0137] Although an exemplary method and structure of manufacturing a three-dimensional memory are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the three-dimensional memory. In addition, the illustrated layers and materials are merely exemplary.

[0138] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: include: Forming a stacked structure including a plurality of steps on one side of the substrate, each of the steps including alternately stacked gate sacrificial layers and insulating layers; forming a buffer layer covering the step; forming a first dielectric layer covering the buffer layer; as well as A first mask layer covering the first dielectric layer and having a first opening corresponding to the step sidewall is formed, and the first dielectric layer covering the step sidewall and the buffer layer are etched through the first opening.

2. The method according to claim 1, wherein: Before forming the first dielectric layer, the method further includes: forming a second mask layer covering the buffer layer; trimming the second mask layer covering the top surface of the step to form a second opening corresponding to the side wall of the step, and etching the buffer layer covering the side wall of the step through the second opening; and The second mask layer is removed.

3. The method according to claim 2, wherein: The second mask layer includes a hard mask layer.

4. The method according to claim 1, wherein: The first mask layer also has a third opening corresponding to a scribe line region of the stacked structure.

5. The method according to claim 1, wherein: The first mask layer includes a soft mask layer.

6. The method according to claim 5, wherein: The material of the soft mask layer includes photoresist.

7. The method according to claim 1, wherein: The method further comprises: The second dielectric layer is filled in the opening formed by etching the first dielectric layer and the buffer layer covering the step sidewall through the first opening to cover the step sidewall.

8. The method according to claim 1, wherein: The method further comprises: The first mask layer is removed.

9. The method according to claim 1, wherein: Before forming a buffer layer covering the step, the method further comprises: At least a portion of the gate sacrificial layer of each of the steps is exposed.

10. The method according to claim 1, wherein: The method further comprises: The surface of the first dielectric layer is planarized.

11. The method according to claim 1, wherein: The method further comprises: replacing the gate sacrificial layer with a gate layer; and The buffer layer remaining after etching through the first opening is replaced with a conductor layer, wherein the gate layer and the conductor layer are made of the same material.

12. The method according to claim 11, wherein: The method further comprises: A plurality of conductive contact structures are formed that penetrate the first dielectric layer and connect the conductor layer.

13. A three-dimensional memory, characterized in that: The three-dimensional memory is formed by the preparation method according to any one of claims 1-12.

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