Three-dimensional memory and methods of making the same

Abstract

A three-dimensional memory and a method of fabricating the same are disclosed. The method includes providing a stack structure including a plurality of stepped terraces on a substrate; forming a buffer layer covering a top surface and sidewalls of each stepped terrace; removing the buffer layer covering the sidewalls of each stepped terrace and forming a dielectric layer over the stepped terraces; and removing a portion of the buffer layer and a gate sacrificial layer thereunder of a top surface of each stepped terrace to form a space, and filling a conductive material in the space to form a floating contact structure on the top surface of each stepped terrace.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to three-dimensional memory and methods for fabricating the same. Background Technology

[0002] Generally, a three-dimensional memory comprises a stacked structure formed by alternating gate layers and interlayer insulating layers. External circuitry is electrically connected to the gate through contact portions located in the stepped regions of the stacked structure. In the actual fabrication process of a three-dimensional memory, to achieve electrical connection between the contact portions and the gate layers in the stacked structure, contact holes are etched in the dielectric layer covering the stacked structure to expose the top surfaces of each gate layer in the stepped regions. Then, conductive material is filled into the contact holes to form the contact portions.

[0003] However, with the increasing integration and stacking of 3D memory, the stepped structure makes it difficult to control the depth of the contact holes, which can easily cause gate layer breakdown during the contact hole formation process. In this case, filling the contact holes with conductive material to form the contacts can lead to short circuits between different gate layers (i.e., word line bridging between different layers), thereby causing memory failure.

[0004] Therefore, there is a need for a three-dimensional memory and its fabrication method to effectively improve the word line bridging problem, thereby improving the electrical performance or yield of the three-dimensional memory.

[0005] It should be understood that this background section is intended to provide some useful background for understanding the technology and does not necessarily belong to the prior art prior to the filing date of this application. Summary of the Invention

[0006] To address or partially address the aforementioned problems in the prior art, one aspect of this application provides a method for fabricating a three-dimensional memory. The method may include: forming a stacked structure comprising multiple stepped steps on a substrate, each stepped step comprising a gate sacrificial layer and an interlayer insulating layer, at least a portion of the upper surface of the gate sacrificial layer being exposed; forming a buffer layer covering the top surface and sidewalls of each stepped step; removing the buffer layer covering the sidewalls of each stepped step and forming a dielectric layer above the stepped step; and removing the buffer layer on the top surface of each stepped step and a portion of the gate sacrificial layer below it to form a space, and filling the space with a conductive material to form a floating contact structure on the top surface of each stepped step.

[0007] In one embodiment of this application, a material with an etching rate greater than that of the gate sacrificial layer is selected when forming the buffer layer.

[0008] In one embodiment of this application, the material of the buffer layer can be TS SIN, and the material of the gate sacrificial layer can be SIN.

[0009] In one embodiment of this application, phosphoric acid can be used as an etchant to remove the buffer layer on the top surface of each step and a portion of the gate sacrificial layer below it using a wet etching process.

[0010] In one embodiment of this application, the dielectric layer may fill the space formed by the removal of the buffer layer with sidewalls removed.

[0011] In one embodiment of this application, forming a stacked structure including multiple stepped steps on a substrate may include: alternately stacking a gate sacrificial layer and an interlayer insulating layer over the substrate to form a stacked structure; forming the gate sacrificial layer and the interlayer insulating layer into a stepped form with multiple stepped steps, the top surface of each stepped step exposing at least a portion of the corresponding interlayer insulating layer; and removing the exposed portion of the interlayer insulating layer to expose at least a portion of the gate sacrificial layer below.

[0012] In one embodiment of this application, removing the exposed portion of the interlayer insulation layer may include: removing the exposed portion using a dry etching process.

[0013] In one embodiment of this application, the method may further include: forming a contact hole that penetrates the dielectric layer and is connected to the floating contact structure, and filling the contact hole with conductive material to form a contact portion.

[0014] In one embodiment of this application, the method may further include: forming a contact hole that penetrates the dielectric layer and the floating contact structure, and filling the contact hole with conductive material to form a contact portion.

[0015] In one embodiment of this application, the method may further include: forming a virtual channel via that penetrates the dielectric layer and the buffer layer and the portion of the gate sacrificial layer below it that has not been removed and extends to the substrate, and filling the virtual channel via with insulating material to form a virtual channel structure.

[0016] Another aspect of this application provides a three-dimensional memory, which may include: a semiconductor layer; a stacked structure disposed on the semiconductor layer, the stacked structure including alternatingly stacked gate layers and interlayer insulating layers forming a plurality of stepped steps, wherein the gate layers include gate conductive portions and gate sacrificial portions; and a floating contact structure located on the top gate layer of the stepped steps away from the semiconductor layer, and in contact with both the gate conductive portions and the gate sacrificial portions included in the top gate layer.

[0017] In one embodiment of this application, the three-dimensional memory further includes a buffer layer portion, which is located between adjacent floating contact structures in the same layer in a direction perpendicular to the gate gap.

[0018] In one embodiment of this application, the buffer layer portion is characterized in that its length in the direction perpendicular to the gate gap is shorter than that of the gate sacrificial portion located below it.

[0019] In one embodiment of this application, the material of the buffer layer portion is TS SIN, and the material of the gate sacrificial portion is SIN.

[0020] In one embodiment of this application, the material of the buffer layer portion is TS SIN, and the material of the gate sacrificial portion is SIN.

[0021] In one embodiment of this application, the three-dimensional memory further includes a dielectric layer. The dielectric layer is located above the stepped steps and floating contact structures, wherein the floating contact structures located on the top surfaces of adjacent stepped steps are separated by the dielectric layer.

[0022] In one embodiment of this application, the three-dimensional memory further includes a contact portion. The contact portion penetrates the dielectric layer and is electrically connected to a floating contact structure.

[0023] In one embodiment of this application, the three-dimensional memory further includes a virtual channel structure. The virtual channel structure penetrates the dielectric layer, the buffer layer portion, and the gate sacrificial portion and extends to the semiconductor layer.

[0024] In one embodiment of this application, the floating contact structure, which is further away from the semiconductor layer, has a greater thickness in the direction perpendicular to the semiconductor layer.

[0025] Another aspect of this application provides a memory system, which may include: a controller; and any of the above-mentioned memory, wherein the controller is coupled to the memory and is used to control the memory to store data.

[0026] This application utilizes a buffer layer to form a floating contact structure, and then uses the floating contact structure to achieve electrical connection between the gate and the contact portion. Compared with the prior art, the solution of this application improves the process controllability of the step region and effectively avoids word line bridging between different gate layers caused during the contact hole formation process. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein: Figure 1 This is a perspective view of a partial structure of a memory according to one embodiment of this application; Figure 2 This is a top view of a partial memory structure according to one embodiment of this application; Figure 3A and Figure 3B This is a cross-sectional schematic diagram of a partial structure of a memory according to one embodiment of this application; Figure 4 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application; Figure 5 This is a partial cross-sectional schematic diagram of the memory structure after the substrate and the stacked structure are provided according to one embodiment of this application; Figure 6 This is a partial cross-sectional schematic diagram of the memory structure after a stepped step is formed in the stepped area according to one embodiment of this application; Figure 7 This is a partial cross-sectional schematic diagram of the memory structure after removing the exposed portion of the interlayer insulation layer according to one embodiment of this application; Figure 8 This is a partial cross-sectional schematic diagram of the memory structure after forming a buffer layer covering the top surface and sidewalls of each step according to one embodiment of this application; Figure 9 This is a partial cross-sectional schematic diagram of the memory structure after removing the buffer layer formed on the sidewall of the stepped step according to one embodiment of this application; Figure 10A and Figure 10B This is a partial cross-sectional schematic diagram of a memory structure after a dielectric layer is formed above a stepped step, according to one embodiment of this application; Figure 11Aa , Figure 11Ab and Figure 11B This is a partial cross-sectional schematic diagram of the memory structure after the floating contact structure is formed, according to one embodiment of this application; Figure 12A and Figure 12B This is a partial cross-sectional schematic diagram of the memory structure after the contact portion has been formed according to one embodiment of this application; and Figure 13 This is a schematic diagram of a memory system according to one embodiment of this application. Detailed Implementation

[0028] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. Furthermore, the order in which the processing steps are described in this application does not necessarily indicate the order in which these processes occur in actual operation, unless otherwise expressly defined or inferred from the context.

[0030] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0031] Additionally, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Therefore, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Therefore, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0032] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0033] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added to the top surface of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0034] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Further, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the non-homogeneous continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers.

[0035] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings") on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0036] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0038] The present application will now be described in detail with reference to the accompanying drawings and embodiments. To better illustrate the process steps, the following will first refer to... Figures 1 to 3B A brief description of the local structure of the memory is provided.

[0039] This application also provides a three-dimensional memory. The memory structure disclosed in this application will be described in detail below with reference to the accompanying drawings. Figure 1This is a perspective view of a partial structure of a memory according to one embodiment of this application; Figure 2 This is a top view of a partial memory structure according to one embodiment of this application; Figure 3A This is a cross-sectional schematic diagram of a partial structure of a memory according to one embodiment of this application; and Figure 3B This is a Y-section schematic diagram of a partial structure of a memory according to one embodiment of this application.

[0040] like Figure 1 and Figure 2 As shown, a three-dimensional memory may include a semiconductor layer 110, a stacked structure 200 disposed on the semiconductor layer 110, and a plurality of stepped steps 300. Figure 2 As shown, the three-dimensional memory may include a core region 201 (not fully shown) and a stepped region 202. In the stepped region 202, a plurality of stepped steps 300 are arranged linearly along the X-axis and spaced apart. Contact portions 610 are correspondingly provided on each stepped step 300 for forming electrical connections with the gate layer on the stepped step 300. Furthermore, a virtual channel structure 810 may be provided in the stepped region 202 to provide physical support for the stepped region during gate replacement to prevent its collapse. The three-dimensional memory may also include a gate gap 700 for processing such as gate replacement within the stacked structure 200.

[0041] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, a three-dimensional memory may include a stacked structure 200, a floating contact structure 410, and a buffer layer portion 400' disposed on a semiconductor layer 110. The stacked structure 200 may include alternatingly stacked gate layers 230 and interlayer insulating layers 210 forming a plurality of stepped steps 300. The gate layer 230 may include a gate sacrificial portion 230-1 and a gate conductive portion 230-2. For example, the gate sacrificial portion 230-1 may be a portion of the gate sacrificial layer that is retained during gate replacement, and the gate conductive portion 230-2 may be a gate portion obtained through gate replacement. The floating contact structure 410 is located on the top gate layer away from the semiconductor layer in the stepped steps and is in contact with both the gate conductive portion 230-2 and the gate sacrificial portion 230-1 included in the top gate layer.

[0042] In one embodiment of this application, such as Figure 3A and Figure 3BAs shown, the three-dimensional memory may further include a buffer layer portion 400'. In a direction perpendicular to the gate gap, the buffer layer portion 400' is located between adjacent floating contact structures 410 on the same layer. For example, the buffer layer portion 400' may be fabricated by filling the space formed by removing the buffer layer 400 with a conductive material. The buffer layer portion 400' may be a portion retained when the buffer layer 400 is removed, to space apart adjacent floating contact structures 410 on the same layer.

[0043] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, in the direction perpendicular to the gate gap, the length of the buffer layer portion 400' is shorter than that of the gate sacrificial portion 230-1 located below it. This arrangement ensures that the gate sacrificial portion 230-1 remains insulated directly below the floating contact structure 410, so that even if etching occurs during the formation of the contact hole, it will not be electrically connected to the adjacent gate layer below.

[0044] As an example, the buffer layer 400 located on the top surface of the stepped platform can be TS SIN, and the gate sacrificial layer 220 can be SIN. In this case, when the TS SIN layer 400 and the underlying SIN layer 220 are partially removed by a wet etching process, the difference in etching rate ratio between TS SIN and SIN using phosphoric acid (i.e., the etching rate of TS SIN is greater than that of SIN) can be utilized to make the portion of the buffer layer removed larger than the portion of the gate sacrificial layer removed, thereby the length of the remaining buffer layer portion 400' is shorter than that of the gate sacrificial portion 230-1 located below it.

[0045] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, the floating contact structure 410 extends below the previous step. However, the floating contact structure 410 in the figure is merely exemplary; in other embodiments, the floating contact structure may extend only to the sidewall of the previous step.

[0046] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, the thickness d of the floating contact structure in the direction perpendicular to the semiconductor layer is presented as approximately the same. However, the floating contact structure 410 in the figure is merely exemplary; in other embodiments, the thickness d of the floating contact structure located on the top surface of each step may differ from each other or be partially different. For example, since steps farther from the substrate are more prone to over-etching in the actual process of forming contact holes, the thickness d of the floating contact structure farther from the semiconductor layer can be set higher to better ensure the process window of the contacts on each step.

[0047] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, the shapes of each side of the floating contact structure 410 are square. However, the floating contact structure 410 in the figure is merely exemplary, and in other embodiments, at least one side of the floating contact structure may also be arc-shaped.

[0048] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, the contact surface between the floating contact structure and the gate layer is planar. However, the floating contact structure 410 in the figure is merely exemplary; in other embodiments, the contact surface between the floating contact structure and the gate layer can also be concave or convex.

[0049] In one embodiment of this application, such as Figure 3A and Figure 3B As shown, the three-dimensional memory may further include a dielectric layer 500, which is located above the stepped steps 300 and the floating contact structures 410, wherein the floating contact structures 410 located on the top surfaces of adjacent stepped steps 300 are spaced apart by the dielectric layer 500. As an example, the dielectric layer 500 may also be planarized using processes such as chemical mechanical polishing, so that the dielectric layer 500 can provide a flat upper surface for the stepped areas of the stacked structure 200.

[0050] In one embodiment of this application, such as Figures 2 to 3B As shown, the three-dimensional memory may also include a contact portion 610. The contact portion 610 may penetrate the dielectric layer 500 and connect to the floating contact structure 410. In addition, the contact portion 610 may also penetrate the dielectric layer 500 and the floating contact structure 410 and extend to the gate sacrificial portion 230-1 of the underlying interlayer insulating layer or gate layer.

[0051] In one embodiment of this application, such as Figures 2 to 3B As shown, the three-dimensional memory may also include a virtual channel structure 810. The virtual channel structure 810 extends through the dielectric layer 500, the buffer layer portion 400', and the gate sacrificial portion 230-1 of the gate layer and extends to the semiconductor layer 110. As an example, the virtual channel structure 810 may also include an insulating filler layer filling its interior, such as an insulating material made of silicon oxide, silicon nitride, or silicon oxynitride.

[0052] This application also provides a method 1000 for fabricating a three-dimensional memory. Figure 4 A flowchart of preparation method 1000 is shown.

[0053] like Figure 4 As shown, the method 1000 for fabricating a three-dimensional memory may include the following steps: S1: A stacked structure including multiple stepped steps is formed on a substrate, each stepped step including a gate sacrificial layer and an interlayer insulating layer, at least a portion of the upper surface of the gate sacrificial layer being exposed (see [reference]). Figures 5 to 7 ); S2: Form a buffer layer covering the top surface and sidewalls of each step (see...) Figure 8 ); S3: Remove the buffer layer on the sidewalls of each step (see...) Figure 9 ); S4: A medium layer is formed above the stepped steps to provide a flat upper surface for the stepped areas of the laminated structure (see [link]). Figure 10A , 10B );as well as S5: Remove at least a portion of the buffer layer covering the top surface of each step and the gate sacrificial layer below it, and fill with conductive material to form a floating contact structure on the top surface of each step (see...). Figure 11B ).

[0054] In existing technologies, contact formation is typically achieved using an IMP (In-Metal Lithography) process. Specifically, after forming a stepped structure, the gate sacrificial layer on the top surface of the stepped structure is modified, and then the contact is formed using the etching ratio of the modified material to the conventional material. However, the consistency of the IMP process is difficult to control, and it can easily damage the interlayer insulating layer below the gate sacrificial layer or even the next gate sacrificial layer, leading to short circuits between different gate layers and causing memory failure.

[0055] As described above, the solution of this application involves forming a buffer layer with an etching rate approximately two to three times higher on the gate sacrificial layer at the top surface of the stepped step after the step is formed. Then, the buffer layer and a portion of the gate sacrificial layer below it are removed, and the space left by the removed buffer layer is filled with conductive material to form a floating contact structure. This floating contact structure enables electrical connection between the gate and the contact portion. Compared to the existing IMP solution that directly modifies the gate sacrificial layer to act as an etching buffer layer, the solution of this application improves the process controllability of each stepped structure by forming a new etching buffer layer on the gate sacrificial layer, and effectively avoids damage to the underlying layers.

[0056] The following will combine Figures 5 to 12B The specific processes for each step in the above preparation method 1000 are described in detail.

[0057] like Figures 5 to 7 As shown, in one embodiment of this application, the step of forming a multilayer structure including multiple stepped steps on the substrate (step S1) may include the following sub-steps: S1-1: Set up a substrate, and alternately stack a gate sacrificial layer and an interlayer insulating layer on the substrate to form a stacked structure, the stacked structure including a stepped region (see...). Figure 5 ); S1-2: The gate sacrificial layer and interlayer insulating layer in the stepped region are formed into a stepped form with multiple steps, and the top surface of each step exposes at least a portion of the corresponding interlayer insulating layer (see [reference]). Figure 6 ); S1-3: Remove a portion of the interlayer insulating layer exposed on the top surface of each step to expose at least a portion of the underlying gate sacrificial layer (see [link]). Figure 7 ); Figure 5 This is a partial cross-sectional schematic diagram of a substrate and a stacked structure provided according to one embodiment of this application.

[0058] like Figure 5 As shown, a substrate 100 is first set and a semiconductor layer 110 is set on the substrate 100. Then, an interlayer insulating layer 210 and a gate sacrificial layer 220 are alternately stacked on the semiconductor layer 110 to form a stacked structure 200 (step S1-1). The stacked structure 200 may include a core region 201 (with memory cells arranged) and a step region 202 (with word line connection structure arranged).

[0059] It should be noted that the substrate 100 is typically removed after the memory fabrication process is completed to allow for bonding with peripheral circuit chips or other devices. The fabrication processes for the peripheral circuit chips and the bonding between the two devices (e.g., bonding processes) can employ existing conventional processes, tailored to specific needs, and will not be elaborated upon here.

[0060] In various embodiments of this application, the substrate 100 may be, for example, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. The substrate 100 may also be a stacked structure, such as Si / SiGe; or other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0061] In various embodiments of this application, the formation of the stacked structure 200 on the semiconductor layer 110 can be achieved through one or more deposition processes. These deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the interlayer insulating layer 210 and the gate sacrificial layer 220 are not limited to... Figure 4The quantities and thicknesses shown are such that, without departing from the concept of this application, those skilled in the art can provide any number and thickness of interlayer insulating layer 210 and gate sacrificial layer 220 as needed. Furthermore, the materials of interlayer insulating layer 210 and gate sacrificial layer 220 can be selected from suitable materials known in the art. For example, interlayer insulating layer 210 can be an oxide layer (such as silicon oxide), and gate sacrificial layer 220 can be a nitride layer (such as silicon nitride).

[0062] In various embodiments of this application, the laminated structure 200 may have a core region (not shown) and a stepped region (e.g., a step area located at the center of the laminated structure) Figure 5 As shown in the diagram, it can also be referred to as the central step region. The core region is used to form array memory cell strings, which are multiple interconnected memory cells formed in a direction perpendicular to the substrate 100; the step region is used to form contacts on the gate sacrificial layer 220 to draw current from them.

[0063] It should be noted that, for the sake of brevity and clarity, this document only uses a stacked structure 200 including a single sub-stack as an example to illustrate the process. Those skilled in the art should understand that the stacked structure 200 may also include multiple sub-stacks; that is, the stacked structure 200 may be formed by a single sub-stack or by multiple sub-stacks stacked sequentially. It should also be noted that, for clarity, only the portion of the stacked structure 200 located in the stepped area is shown in the accompanying drawings of this application.

[0064] Figure 6 This is a partial cross-sectional schematic diagram of the memory structure after a stepped step is formed in the stepped area according to one embodiment of this application.

[0065] like Figure 6 As shown, in one embodiment of this application, a plurality of stepped steps 300 are formed in the stepped region (steps S1-2). As an example, the plurality of stepped steps 300 can first be formed in the stepped region by performing a repeated etch-trimming process on the stacked structure 200 using a patterned mask (not shown). The patterned mask may include a photoresist or a carbon-based polymer material and can be removed after the stepped steps are formed. Reference Figure 6 The top surface of each step 300 exposed at least a portion of the interlayer insulating layer 210 located in the corresponding layer. That is, each step 300 includes at least one level, and each level includes, from top to bottom, an interlayer insulating layer 210 and a gate sacrificial layer 220.

[0066] In various embodiments of this application, the stepped steps can be formed at the center of the stacked structure. As an example, the stepped area at the center may also include a first connecting area, a second connecting area, and a third connecting area arranged sequentially, with the stepped steps formed only in the second connecting area, and no stepped steps formed in the first connecting area and the third connecting area located on both sides of the second connecting area.

[0067] In various embodiments of this application, the height of the steps can gradually increase or decrease along the direction away from the core area of ​​the stacked structure, or it can be arranged symmetrically with respect to the center.

[0068] In various embodiments of this application, each step of the step region may expose a portion of the top surface of the corresponding interlayer insulating layer, or a portion of the top surface of the corresponding gate sacrificial layer.

[0069] In various embodiments of this application, the step area can be a single-step step structure or a partitioned step structure, and the partitioned step structure can have different partitions (e.g., 3 partitions, 4 partitions or more partitions, etc.).

[0070] It should be noted that, for the sake of brevity and clarity, the accompanying figures only show the case where each step comprises one level. It should also be noted that the number of steps can be adjusted as needed, depending on the number of gate sacrificial layers in the stack-up structure and the number of levels contained in each step.

[0071] Figure 7 This is a partial cross-sectional schematic diagram of the memory structure after the exposed portion of the interlayer insulation layer has been removed according to one embodiment of this application.

[0072] like Figure 7 As shown, in one embodiment of this application, when forming as Figure 6 Following the stepped structure shown, at least a portion of the interlayer insulating layer 210 exposed at the top surface of the step can be removed, for example, by wet etching or dry etching, to expose at least a portion of the underlying gate sacrificial layer 220 (steps S1-3). This allows the formation of multiple stepped structures 300-1 in the step region, each step 300-1 comprising at least one level, and each level comprising, from top to bottom, the gate sacrificial layer 220 and the interlayer insulating layer 210. It is understood that the hierarchical structure of the stepped structures 300-1 formed in this step is different from that formed in step S1-2.

[0073] Figure 8 This is a partial cross-sectional schematic diagram of the memory structure after forming a buffer layer covering the top surface and sidewalls of each step according to one embodiment of this application.

[0074] like Figure 8 As shown, in one embodiment of this application, a buffer layer 400 is formed on the top surface and sidewall of each step 300-1 (step S2). The buffer layer 400 covers the portion of the gate sacrificial layer 220 exposed on the top surface of each step; and covers the sidewall of each step, i.e., the common sidewall of the gate sacrificial layer 220 and the interlayer insulating layer 210 exposed on each sidewall.

[0075] As an example, a buffer layer 400 can be formed on the top surface and sidewalls of each step 300-1 by one or more deposition processes, including but not limited to atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the buffer layer 400 can be formed by an atomic layer deposition process.

[0076] As an example, the buffer layer 400 can be formed using a material with an etching ratio greater than 1 compared to the gate sacrificial layer material. For instance, the material forming the buffer layer 400 can be TS SIN, in which case, when wet etching is performed using phosphoric acid or the like as an etchant, TS SIN has an etching rate approximately two to three times that of normal SIN. This characteristic of TS SIN material is beneficial for the subsequent formation of floating contact structures.

[0077] Figure 9 This is a partial cross-sectional schematic diagram of the memory structure after removing the buffer layer formed on the sidewall of the stepped step according to one embodiment of this application.

[0078] like Figure 9 As shown, in one embodiment of this application, the buffer layer 400 formed on the sidewall of the stepped step is removed (step S3), so that the buffer layers 400 on the top surfaces of adjacent steps are spaced apart from each other. Therefore, when the buffer layer 400 is subsequently replaced with a floating contact structure, this spacing can effectively prevent the word lines of adjacent gate layers from bridging each other and causing a short circuit.

[0079] As an example, methods for removing the buffer layer formed on the sidewalls of a stepped platform may include, but are not limited to, etching. For example, dry etching such as deep ion reactive etching (RIDE) may be used, as well as wet etching (such as using phosphoric acid as an etchant).

[0080] See you again Figure 9 Each step 300-2 includes at least one level, and each level includes, from top to bottom, a buffer layer 400, a gate sacrificial layer 220, and an interlayer insulating layer 210. It can be seen that, compared to a conventional step, it also includes a buffer layer 400.

[0081] Figure 10A and Figure 10BThis is a partial cross-sectional schematic diagram of a memory structure after a dielectric layer is formed above a stepped platform according to one embodiment of this application. Figure 10A It is a partial cross-sectional view along the X-axis, while Figure 10B It is a partial cross-sectional view along the Y-axis.

[0082] like Figure 10A and Figure 10B As shown, a medium layer 500 is formed above the step (step S4). It can be seen that the medium layer 500 not only fills the space above the step, but also fills the space formed by removing the buffer layer 400 on the side wall of the step 300.

[0083] As an example, the dielectric layer 500 can be formed by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. In one embodiment of this application, the dielectric layer 500 may be formed by filling silicon oxide based on TEOS. The dielectric layer 500 can be a multilayer structure, first forming a first sub-film layer with good step coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then forming a second sub-film layer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). The density of the first sub-film layer is higher than that of the second sub-film layer, thus the first sub-film layer has good step coverage, while the second sub-film layer has high filling efficiency.

[0084] As an example, the dielectric layer 500 can be further planarized using processes such as chemical mechanical polishing, so that the dielectric layer 500 provides a substantially flat upper surface for the stepped area of ​​the laminated structure 200.

[0085] Figure 11Aa , Figure 11Ab and Figure 11B This is a partial cross-sectional schematic diagram of the memory structure after forming the floating contact structure according to one embodiment of this application. To fully illustrate the floating contact structure, several partial cross-sectional views are shown here, in which... Figure 11Aa , Figure 11Ab These are partial cross-sectional views taken at different positions along the X-axis. Figure 11Aa It is a partial cross-sectional view along the X direction at the middle position of the stepped area, and Figure 11Ab It is a partial cross-sectional view along the X direction at a location near the core area in the stepped region; and Figure 11B It is a partial cross-sectional view along the Y-axis.

[0086] like Figure 11Aa , Figure 11Ab and Figure 11BAs shown, in one embodiment of this application, the buffer layer 400 located on the top surface of the stepped step and a portion of the gate sacrificial layer in the stepped step below it can be removed by the gate gap 700, for example by an etching process (e.g., wet etching), and then the removed space is filled with conductive material, thereby forming a floating contact structure 410 and a gate layer 230 on the top surface of each stepped step (step S5).

[0087] It should be noted that the buffer layer 400 and the gate sacrificial layer 220 below it were not completely removed. The formed gate layer 230 includes the gate sacrificial portion 230-1 (e.g., Figure 11Aa and Figure 11B (as shown) and gate conductive portion 230-2 (as shown) Figure 11Ab and Figure 11B As shown), the gate sacrificial portion 230-1 is the portion of the gate sacrificial layer retained during gate replacement, and the gate conductive portion 230-2 is the gate portion obtained through gate replacement. (See reference...) Figure 11B When the buffer layer 400 is removed, a portion of it is also retained, which may be referred to as the buffer layer portion 400', to separate adjacent floating contact structures 410 located on the same layer.

[0088] In one embodiment of this application, the buffer layer may be selected from a material with an etching ratio greater than 1 compared to the gate sacrificial layer material. For example... Figure 11B As shown, after the above etching process, in the direction perpendicular to the gate gap, the length of the retained buffer layer portion 400' is shorter than that of the retained gate sacrificial layer portion (i.e., the gate sacrificial portion 230-1 of the gate layer). Therefore, even if over-etching occurs during the formation of the contact hole and extends to the underlying gate layer or interlayer insulating layer, the contact portion will not contact the gate line of another gate layer due to the presence of the gate sacrificial layer portion, thereby avoiding word line bridging between different layers.

[0089] As an example, the buffer layer 400 located on the top surface of the stepped step can be made of TS SIN material, and the gate sacrificial layer 220 can be made of conventional SIN material. In this case, phosphoric acid can be used as the etchant, and the TS SIN layer and a portion of the underlying SIN layer located on the top surface of the stepped step can be removed by a wet etching process. At this time, since the etching rate of TS SIN is about two to three times that of conventional SIN, the rate at which the TS SIN layer is etched away is much faster than that of the underlying SIN layer. Then, the space formed by removing the TS SIN layer and the underlying SIN layer is filled with a conductive material such as titanium nitride or tungsten alloy to form the floating contact structure 410 and the gate layer 230.

[0090] However, conventional IMP methods modify the SIN layer in the stepped structure and then utilize the higher etching rate of the modified material (e.g., about twice that of the normal material) to form the contact structure. However, this process is difficult to control and consistency is hard to guarantee, easily causing damage to the interlayer insulating layer below the gate sacrificial layer and even the next gate sacrificial layer, leading to short circuits between different gate layers. In this application, the floating contact structure 410 is only located on the top surface of the stepped structure, and a portion of the insulating gate sacrificial layer is still retained in the gate layer 230 below it; that is, the gate layer 230 also includes a gate sacrificial portion 230-1. Therefore, even if etching occurs during the subsequent formation of contact holes for leading out the gate layers of the corresponding stepped steps, the contact portion will not contact the gate lines of another gate layer, thus avoiding word line bridging between different layers. In other words, the method of this application also facilitates the subsequent contact formation process.

[0091] It should be noted that the selection of the above-mentioned materials and the specific processes for their formation and removal are only for the purpose of more clearly and concisely illustrating this application, and not for limiting this application.

[0092] Figure 12A and Figure 12B This is a partial cross-sectional schematic diagram of the memory structure after the contact portion has been formed according to one embodiment of this application. Figure 12A It is a partial cross-sectional view along the X-axis, while Figure 12B It is a partial cross-sectional view along the Y-axis.

[0093] like Figure 12A and Figure 12B As shown, in one embodiment of this application, the method for fabricating a three-dimensional memory further includes: forming a contact hole 600 in the step region that penetrates the dielectric layer 500 and connects to the floating contact structure 410, and filling the contact hole 600 with conductive material to form a contact portion 610. (Reference) Figure 12A The contact hole 600 may extend only to the top surface of the floating contact structure 410, or it may be over-etched to the interlayer insulating layer below, or even to the gate sacrificial portion 230-1 of the gate layer below (i.e., the portion of the gate sacrificial layer retained during gate replacement). According to an exemplary embodiment of this application, even if etching occurs during the etching process to form the contact hole 600, causing the contact portion 610 subsequently formed in the contact hole 600 to extend into the floating contact structure 410 or even through the floating contact structure 410 to the interlayer insulating layer below, word line bridging between different layers can be effectively avoided.

[0094] As an example, multiple contact holes 600 can be formed in the step region first using photolithography and etching processes. Then, conductive materials such as titanium nitride or tungsten alloy are filled into the contact holes 600 to form contact portions 610. It can be seen that the contact portions 610 form an electrical connection with the floating contact structure 410 of the corresponding layer, and the floating contact structure 410 forms an electrical connection with the gate, thereby leading out the gate current.

[0095] Refer again Figure 12B In one embodiment of this application, the method for fabricating a three-dimensional memory may further include forming a virtual channel hole 800 that penetrates the dielectric layer 500, the buffer layer portion 400', and the gate sacrificial portion 230-1 in the step region and extends to the substrate, and filling the virtual channel hole 800 with insulating material to form a virtual channel structure 810.

[0096] As an example, a virtual channel hole 800 extending through the dielectric layer and into the substrate 100 can be formed in the step region by photolithography and etching processes; then, an insulating material is filled into the virtual channel hole 800 to form a virtual channel structure 810, for example, by depositing a silicon nitride-based material by ALD.

[0097] This application also provides a memory system 2000. Figure 13 This is a schematic diagram of a memory system 2000 according to one embodiment of this application.

[0098] like Figure 13 As shown, in one embodiment of this application, the memory system 2000 may include a memory 2100 and a controller 2200. The memory 2100 may be the same as the memory described in any of the embodiments above, and will not be described again in this application. The memory system 2000 may be a two-dimensional memory system or a three-dimensional memory system; the following description uses a three-dimensional memory system as an example.

[0099] The three-dimensional memory system 2000 may include a three-dimensional memory 2100, a controller 2200, and a host 2300. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 2200 controls the three-dimensional memory 2100 via channel CH, and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200 in response to requests from the host 2300. The three-dimensional memory 2100 receives commands CMD and addresses ADDR from the controller 2200 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on the region selected by the address.

[0100] In some embodiments, the three-dimensional memory system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. This application provides peripheral circuits, memory, and memory systems, which, due to the semiconductor structure provided in this application, have the same beneficial effects as the semiconductor structure described herein, and will not be elaborated upon here.

[0101] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0102] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a three-dimensional memory, the method comprising: A stacked structure comprising multiple stepped steps is provided on a substrate, each stepped step comprising a gate sacrificial layer and an interlayer insulating layer, wherein at least a portion of the upper surface of the gate sacrificial layer is exposed; A buffer layer is formed covering the top surface and sidewalls of each of the aforementioned steps; Remove the buffer layer covering the sidewalls of each of the steps and form a medium layer above the steps; as well as A portion of the buffer layer on the top surface of each step and a portion of the gate sacrificial layer below the buffer layer are removed to form a space, and the space is filled with conductive material to form a floating contact structure on the top surface of the remaining gate sacrificial layer of each step. The remaining buffer layer forms a buffer layer portion, which is located between adjacent floating contact structures in the same layer to separate adjacent floating contact structures in the same layer.

2. The method according to claim 1, characterized in that, When forming the buffer layer, a material with an etching rate greater than that of the gate sacrificial layer is selected.

3. The method according to claim 2, characterized in that, When phosphoric acid is used as an etchant for wet etching, the etching rate of the buffer layer is greater than that of the gate sacrificial layer.

4. The method according to claim 3, characterized in that, Using phosphoric acid as an etchant, a wet etching process is employed to remove the buffer layer on the top surface of each step and a portion of the gate sacrificial layer below it.

5. The method according to claim 1, characterized in that, The medium layer fills the space formed by removing the buffer layer from the sidewall.

6. The method according to claim 1, characterized in that, The stacked structure comprising multiple stepped steps on the substrate includes: A gate sacrificial layer and an interlayer insulating layer are alternately stacked over the substrate to form a stacked structure; The gate sacrificial layer and the interlayer insulating layer are formed in a stepped configuration with multiple steps, wherein the top surface of each step exposes at least a portion of the corresponding interlayer insulating layer; and Remove the exposed portion of the interlayer insulating layer to expose at least a portion of the underlying gate sacrificial layer.

7. The method according to claim 6, characterized in that, Removing the exposed portion of the interlayer insulation layer includes using a dry etching process to remove the exposed portion.

8. The method according to claim 1, characterized in that, Also includes: A contact hole is formed that penetrates the dielectric layer and connects to the floating contact structure, and a contact portion is formed by filling the contact hole with conductive material.

9. The method according to claim 1, characterized in that, Also includes: A virtual channel hole is formed that penetrates the dielectric layer and the buffer layer and the portion of the gate sacrificial layer below it that has not been removed, and extends to the substrate. An insulating material is then filled into the virtual channel hole to form a virtual channel structure.

10. A three-dimensional memory, comprising: Semiconductor layer; A stacked structure is disposed on the semiconductor layer, the stacked structure including alternating stacked gate layers and interlayer insulating layers forming multiple stepped steps, wherein the gate layers include gate conductive portions and gate sacrificial portions; as well as A floating contact structure is located on the top gate layer of the stepped step, away from the semiconductor layer, and is in contact with both the gate conductive portion and the gate sacrificial portion included in the top gate layer. The buffer layer portion, located between adjacent floating contact structures on the same layer and on the side of the gate sacrificial portion facing away from the semiconductor layer, is used to separate adjacent floating contact structures on the same layer.

11. The three-dimensional memory according to claim 10, characterized in that, The length of the buffer layer portion in the direction perpendicular to the gate gap is shorter than the gate sacrifice portion located below it.

12. The three-dimensional memory according to claim 10, characterized in that, The three-dimensional memory also includes: A medium layer is located above the stepped steps and the floating contact structure, wherein the floating contact structure located on the top surface of adjacent stepped steps is separated by the medium layer.

13. The three-dimensional memory according to claim 12, characterized in that, The three-dimensional memory also includes: The contact portion penetrates the dielectric layer and is electrically connected to the floating contact structure.

14. The three-dimensional memory according to claim 12, characterized in that, The three-dimensional memory also includes: The virtual channel structure extends through the dielectric layer, the buffer layer portion, and the gate sacrificial portion and into the semiconductor layer.

15. The three-dimensional memory according to claim 10, characterized in that, The floating contact structure, which is further away from the semiconductor layer, has a greater thickness in the direction perpendicular to the semiconductor layer.

16. A memory system, characterized in that, The memory system includes: Controller; and The three-dimensional memory according to any one of claims 10 to 15, The controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

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