Semiconductor device and method of manufacturing the semiconductor device

Abstract

The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. According to the present technology, a method for manufacturing a semiconductor device can include the steps of forming a gap fill target structure on a semiconductor substrate, the gap fill target structure including a horizontal recess and a vertical slit, the horizontal recess being parallel to the semiconductor substrate and having a first surface, the vertical slit extending from the horizontal recess and having a second surface perpendicular to the semiconductor substrate; removing a native oxide from the first surface to form a pre-clean first surface; forming a first semiconductor material in situ on the pre-clean first surface; and forming a second semiconductor material on the first semiconductor material.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] Manufacturing electronic devices, such as semiconductor devices, requires gap filling for three-dimensional or high aspect ratio structures. High aspect ratio gap filling is performed, for example, in the manufacture of vertical semiconductor devices. Summary of the Invention

[0003] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a gap-filling target structure on a semiconductor substrate, the gap-filling target structure including a horizontal recess and a vertical slit, the horizontal recess being parallel to the semiconductor substrate and having a first surface, the vertical slit extending from the horizontal recess and having a second surface perpendicular to the semiconductor substrate; removing native oxide from the first surface to form a pre-cleaned first surface; forming a first semiconductor material in-situ on the pre-cleaned first surface; and forming a second semiconductor material on the first semiconductor material.

[0004] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a lower-level stack on a semiconductor substrate, the lower-level stack including a source sacrificial layer and a source layer; forming an alternating stack on the lower-level stack, the alternating stack including an insulating layer and a sacrificial layer; forming a vertical channel structure including a channel layer penetrating the alternating stack and the lower-level stack; forming a slit that exposes the source sacrificial layer and penetrates the alternating stack; forming a sealing layer on the sidewalls of the slit; forming a horizontal recess extending from the slit by removing the source sacrificial layer; exposing a portion of the channel layer from the horizontal recess; a pre-cleaning process that exposes the exposed surface of the channel layer to a halogen gas; and selectively growing a polysilicon layer in situ on the exposed surface of the channel layer after the pre-cleaning process.

[0005] According to embodiments of the present disclosure, a semiconductor device may include: an alternating stack including an insulating layer and a gate electrode alternately stacked on a semiconductor substrate; a source channel contact layer between the semiconductor substrate and the alternating stack; a vertical channel layer penetrating the alternating stack and the source channel contact layer; and a memory layer between the vertical channel layer and the alternating stack, wherein the source channel contact layer includes an epitaxial polysilicon layer contacting the vertical channel layer and an amorphous silicon layer on the epitaxial polysilicon layer. Attached Figure Description

[0006] Figure 1 and Figure 2This is a diagram illustrating a vertical semiconductor device according to an embodiment.

[0007] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a diagram illustrating an example method for manufacturing a vertical semiconductor device according to an embodiment.

[0008] Figure 18 , Figure 19 , Figure 20 and Figure 21 This is a diagram illustrating a method for manufacturing a vertical semiconductor device according to an embodiment.

[0009] Figure 22A This is a diagram illustrating a method for manufacturing a vertical semiconductor device according to a comparative example.

[0010] Figure 22B This is a diagram showing the results of secondary ion mass spectrometry (SIMS) analysis based on a comparative example.

[0011] Figure 23 This is a diagram showing the results of the SIMS analysis according to the implementation method. Detailed Implementation

[0012] Embodiments of this disclosure are described below with reference to schematic cross-sectional views, plan views, or block diagrams. The drawings may be altered or modified depending on manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure are not limited to the specific types shown and illustrated herein, but may cover changes or modifications resulting from manufacturing processes. For example, the regions or areas shown in the figures are schematic and their shapes are provided merely as examples and not to limit the category or scope of this disclosure.

[0013] Embodiments of this disclosure may provide a vertical semiconductor device with better reliability and a method for manufacturing the vertical semiconductor device.

[0014] According to this technology, high and uniform current can be ensured by removing the natural oxides on the surface of the channel layer through a cleaning process using halogen gas.

[0015] According to this technology, since the polysilicon layer is selectively grown as the source channel contact layer, phosphorus accumulation at the interface between the channel layer and the source channel contact layer can be prevented.

[0016] Figure 1 and Figure 2 This is a diagram illustrating a vertical semiconductor device according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken by line A-A'.

[0017] Reference Figure 1 and Figure 2 The vertical semiconductor device 100 may include a semiconductor substrate 101, a lower-level stack 110 formed on the semiconductor substrate 101, and alternating stacks 120 on the lower-level stack 110. The lower-level stack 110 may include source layers 111 and 112 and a source channel contact layer 110S.

[0018] The alternating laminate 120 may include insulating layers 121 and gate electrodes 122 formed alternately with each other. The lowest insulating layer among the insulating layers 121 may be thicker than the other insulating layers. The insulating layer 121 may include silicon oxide, and the gate electrode 122 may include a metal base material. The gate electrode 122 may include a laminate of tungsten or titanium nitride and tungsten.

[0019] The vertical semiconductor device 100 may further include a vertical channel structure 130 penetrating the alternating stack 120. The vertical channel structure 130 may include a memory layer 131, a channel layer 132, and a core insulating layer 133. The core insulating layer 133 may fill the internal space of the channel layer 132, and the memory layer 131 may surround the outer wall of the channel layer 132. The lower portion of the vertical channel structure 130 may penetrate the lower-level stack 110 and contact the semiconductor substrate 101. The upper portion of the vertical channel structure 130 may penetrate the alternating stack 120.

[0020] The vertical semiconductor device 100 may further include a slit 119 penetrating the alternating layers 120. The slit 119 may be spaced apart from the vertical channel structure 130. An encapsulation layer 117 may be formed on the sidewalls of the slit 119. The slit 119 may be shaped as a trench. The encapsulation layer 117 may cover a first end of the gate electrode 122. The encapsulation layer 117 may include silicon oxide, silicon nitride, carbon-containing silicon oxide, or a combination thereof.

[0021] The following describes the lower-level stack 110.

[0022] The lower-level stack 110 may include source layers 111 and 112 and a source channel contact layer 110S between source layers 111 and 112. Source layers 111 and 112 may include a lower source layer 111 and an upper source layer 112. The lower-level stack 110 may also include a horizontal recess 118. The horizontal recess 118 may be defined between the lower source layer 111 and the upper source layer 112. The source channel contact layer 110S may be formed between the lower source layer 111 and the upper source layer 112. The source channel contact layer 110S may fill the horizontal recess 118. The lower source layer 111 and the upper source layer 112 may include the same material, such as a semiconductor material (e.g., polysilicon). The source channel contact layer 110S may include a semiconductor material (e.g., silicon).

[0023] The source channel contact layer 110S may include a first silicon layer 113 and a second silicon layer 114. The first silicon layer 113 may cover the surface of the horizontal recess 118. The first silicon layer 113 may directly contact the channel layer 132 of the vertical channel structure 130. A portion of the first silicon layer 113 may extend to cover the bottom of the slit 119, thereby contacting the sealing layer 117. The second silicon layer 114 may fill the horizontal recess 118 on the first silicon layer 113 and extend to fill the slit 119.

[0024] The first silicon layer 113 and the second silicon layer 114 can be silicon layers with different crystalline phases. The first silicon layer 113 can be a crystalline silicon layer, and the second silicon layer 114 can be an amorphous silicon layer. The first silicon layer 113 can be an epitaxial polycrystalline silicon layer, and the second silicon layer 114 can be an amorphous silicon layer. The first silicon layer 113 can be an epitaxial polycrystalline silicon layer, and the second silicon layer 114 can be a deposited amorphous silicon layer. The epitaxial polycrystalline silicon layer can be formed by epitaxial growth, and the deposited amorphous silicon layer can be formed by deposition. The first silicon layer 113 and the second silicon layer 114 may include dopants. The dopants may include phosphorus. The first silicon layer 113 may include a phosphorus-doped epitaxial polycrystalline silicon layer, and the second silicon layer 114 may include a phosphorus-doped amorphous silicon layer.

[0025] The source channel contact layer 110S may further include an interface layer 115 between the first silicon layer 113 and the second silicon layer 114. The interface layer 115 may include silicon oxide. The interface layer 115 may include an oxide of the first silicon layer 113. The interface layer 115 may be thinner than the first silicon layer 113 and the second silicon layer 114. The interface layer 115 can be used to improve the surface roughness of the first silicon layer 113, thereby preventing seams or voids in the second silicon layer 114. For electrical contact between the first silicon layer 113 and the second silicon layer 114, the interface layer 115 may be extremely thin.

[0026] As described above, the contact surface between the channel layer 132 and the first silicon layer 113 may include an oxide-free surface, and the contact surface between the first silicon layer 113 and the second silicon layer 114 may include an oxide surface. The oxide surface may include an interface layer 115. An oxide-free surface refers to a surface free of oxides, the surface of the channel layer 132 has a pre-cleaned surface, and the first silicon layer 113 may be selectively grown on the pre-cleaned surface.

[0027] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a diagram illustrating an example method for manufacturing a vertical semiconductor device according to an embodiment. Figures 3 to 17 It is along Figure 1 A cross-sectional view taken by line A-A'.

[0028] like Figure 3 As shown, a stacked structure including a lower source layer 12, an upper source layer 16, pad layers 13 and 15, and a source sacrificial layer 14 can be formed on a semiconductor substrate 11. The source sacrificial layer 14 can be formed between the lower source layer 12 and the upper source layer 16, and the pad layers 13 and 15 can be formed between the source sacrificial layer 14 and the lower source layer 12 / upper source layer 16. The lower source layer 12, the source sacrificial layer 14, and the upper source layer 16 may comprise the same material, and the pad layers 13 and 15 may comprise materials different from those of the lower source layer 12, the source sacrificial layer 14, and the upper source layer 16. The lower source layer 12, the source sacrificial layer 14, and the upper source layer 16 may have etch selectivity for the pad layers 13 and 15. The lower source layer 12, the source sacrificial layer 14, and the upper source layer 16 may comprise semiconductor materials, and the pad layers 13 and 15 may comprise insulating materials. The lower source layer 12, the source sacrificial layer 14, and the upper source layer 16 may comprise polysilicon, and the pad layers 13 and 15 may comprise silicon oxide. The pad layers 13 and 15 may be thinner than the lower source layer 12, the source sacrificial layer 14, and the upper source layer 16.

[0029] Next, an upper-level stack comprising an insulating layer 17 and a sacrificial layer 18 may be formed on the upper source layer 16. The upper-level stack may include insulating layers 17 and sacrificial layers 18 stacked alternately on top of each other. Insulating layers 17 and sacrificial layers 18 may be stacked alternately several times. Insulating layers 17 and sacrificial layers 18 may comprise different materials. Insulating layer 17 may have etch selectivity for sacrificial layer 18. Insulating layer 17 may comprise silicon oxide, and sacrificial layer 18 may comprise silicon nitride. Insulating layers 17 and sacrificial layers 18 may have the same thickness. Insulating layers 17 and sacrificial layers 18 may be thicker than pad layers 13 and 15, and thinner than the lower source layer 12 and the upper source layer 16. Among the insulating layers 17, the lowest insulating layer 17 may be thicker than the other insulating layers 17.

[0030] The insulating layer 17 and the sacrificial layer 18 can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0031] Reference Figure 4 A vertical opening 19 can be formed. To form the vertical opening 19, an insulating layer 17, a sacrificial layer 18, an upper source layer 16, pad layers 13 and 15, a source sacrificial layer 14, and a lower source layer 12 can be etched.

[0032] The vertical opening 19 may be formed perpendicular to the surface of the semiconductor substrate 11. The vertical opening 19 may be shaped to penetrate the insulating layer 17 and the sacrificial layer 18 and extend to penetrate the upper source layer 16, pad layers 13 and 15, the source sacrificial layer 14, and the lower source layer 12. Although not shown, in a plan view, a plurality of vertical openings 19 may be formed, and the plurality of vertical openings 19 may have a hole array structure. When forming the vertical opening 19, the surface of the semiconductor substrate 101 may be recessed. According to embodiments, the vertical opening 19 may be referred to as a "vertical recess," a "vertical hole," or a "channel hole."

[0033] Reference Figure 5 A vertical channel structure 20 can be formed in the vertical opening 19. The vertical channel structure 20 can fill the vertical opening 19. The vertical channel structure 20 can be represented as a "column structure".

[0034] The vertical channel structure 20 may include a memory layer 21, a channel layer 22, and a core insulating layer 23. The memory layer 21 may have a stacked structure including a barrier layer, a charge trapping layer, and a tunnel insulating layer. The barrier layer and tunnel insulating layer may include oxides, and the charge trapping layer may include nitrides. The memory layer 21 may have an oxide-nitride-oxide (ONO) structure. The channel layer 22 may include an undoped polysilicon layer free of impurities. The channel layer 22 may have a cylindrical shape including an inner space. The memory layer 21 may surround the outer wall of the channel layer 22. The inner space of the channel layer 22 may be completely filled by the core insulating layer 23. The core insulating layer 23 may include silicon oxide or silicon nitride.

[0035] Reference Figure 6 A slit 24 can be formed. The slit 24 can be formed by etching the insulating layer 17 and the sacrificial layer 18, and the slit 24 can extend downwards to a portion of the upper source layer 16. The bottom surface of the slit 24 may not penetrate the upper source layer 16. The slit 24 may also be referred to as a trench. From a top view, the slit 24 can be shaped as a line extending in any direction. The slit 24 can be formed perpendicular to the surface of the semiconductor substrate 11. The slit 24 may be referred to as a vertical slit.

[0036] Reference Figure 7 The gate electrode 25 can replace the sacrificial layer 18 via the slit 24. For example, after the sacrificial layer 18 is removed, the gate electrode 25 can be used to fill the space created by removing the sacrificial layer 18. The gate electrode 25 may include tungsten, titanium nitride, or a combination thereof.

[0037] Reference Figure 8 A sealing layer 26 may be formed on the sidewalls of the slit 24. The sealing layer 26 may include at least one sealing material. The sealing layer 26 may include oxides, nitrides, or combinations thereof. For example, the sealing layer 26 may include a nitride-oxide-nitride (i.e., a non-non structure) laminate. Subsequently, the sealing layer 26 may be etched to remain as spacers in the two sidewalls of the slit 24.

[0038] Next, the sealing layer 26 can be used as a barrier to etch the upper source layer 16, the pad layer 15, and the source sacrificial layer 14. The pad layer 13 and the lower source layer 12 can be left unetched.

[0039] Reference Figure 9 The source sacrificial layer 14 can be selectively removed via slit 24. Therefore, a horizontal recess 27 can be formed. The horizontal recess 27 can extend from slit 24. Since the horizontal recess 27 removes the source sacrificial layer 14 through an etch process, the horizontal recess 27 can be formed between pad layers 13 and 15. The horizontal recess 27 can be parallel to the surface of the semiconductor substrate 11. When the source sacrificial layer 14 is removed, pad layers 13 and 15 may remain unremoved due to etching selectivity. The horizontal recess 27 can be formed between the lower source layer 12 and the upper source layer 16. When the source sacrificial layer 14 is removed, the lower source layer 12 and the upper source layer 16 may not be removed. Wet etching can be applied to remove the source sacrificial layer 14. Since the source sacrificial layer 14 comprises a polysilicon layer, the wet etching can include chemicals used to etch the polysilicon layer.

[0040] The horizontal recess 27 exposes the lower sidewall of the vertical channel structure 20. The outer wall of the vertical channel structure 20 may be part of the memory layer 21. In a top view, the horizontal recess 27 may be shaped to surround the lower sidewall of the vertical channel structure 20.

[0041] Reference Figure 10 The padding layers 13 and 15 can be removed. Therefore, the volume of the horizontal recess 27 can be increased. An enlarged horizontal recess 28 can be formed. Hereinafter, this is referred to as horizontal recess 28.

[0042] After the padding layers 13 and 15 are removed, a portion of the memory layer 21 of the vertical channel structure 20 can be removed.

[0043] Through the aforementioned series of processes, the horizontal recess 28 exposes the lower outer wall of the channel layer 22. A portion of the memory layer 21 can be cut by the horizontal recess 28. Therefore, an undercut 28E can be formed between the channel layer 22 and the lower source layer 12 / upper source layer 16.

[0044] The horizontal recess 28 may be parallel to the semiconductor substrate 11 and have a first surface. The slit 24 may extend from the horizontal recess 28 and have a second surface perpendicular to the semiconductor substrate 11. In other words, a gap-filling target structure including the horizontal recess 28 with the first surface and the slit 24 with the second surface may be formed on the semiconductor substrate 11. The first surface may be provided by the channel layer 22, the lower source layer 12, and the upper source layer 16, and the second surface may be provided by the sealing layer 26. The first surface may be the surface of a silicon layer, and the second surface may be the surface of an insulating material.

[0045] Subsequently, through Figures 11 to 17 The series of processes shown can utilize the gaps in semiconductor material to fill the horizontal recess 28 and slit 24.

[0046] Reference Figure 11 Pre-processing process 29 can be performed. Pre-processing process 29 can be performed before the semiconductor substrate 11 is loaded into the furnace chamber to form the source contact layer.

[0047] Pretreatment process 29 may include a process for thinning or removing native oxides remaining on the exposed surfaces of the channel layer 22. Fluorine-based chemicals may be used to perform pretreatment process 29. After removing or thinning the native oxides as thinly as possible, it needs to be subsequently loaded into the furnace chamber. The time from pretreatment process 29 to loading the substrate into the furnace chamber can be within two hours. Fluorine-based chemicals may include NF3 or HF.

[0048] Reference Figure 12 The pretreated (29) semiconductor substrate 11 is loaded into the furnace chamber to deposit the source contact layer.

[0049] Next, a pre-cleaning process 30 can be performed in the furnace chamber using in-situ etching gas. The pre-cleaning process 30 can remove native oxides that inevitably form on the surface of the channel layer 22 during substrate movement and loading. The etching gas used in the pre-cleaning process 30 may include halogen gases such as Cl or HBr. Removal of native oxides using etching gas can be performed as follows: the etching gas penetrates through the tiny gaps present in the native oxides and etches the channel layer 22, then the native oxides are stripped away. Therefore, if the time spent from the pretreatment process 29 to loading the substrate into the furnace chamber is increased, the tiny gaps in the native oxides may disappear, significantly reducing the efficiency of in-situ etching. Native oxides present on the exposed surfaces of the upper source layer 16 and the lower source layer 12 can also be removed by the pre-cleaning process 30. The channel layer 22 may include an oxide-free pre-cleaned surface. The exposed surfaces of the upper source layer 16 and the lower source layer 12 may also include oxide-free pre-cleaned surfaces.

[0050] Reference Figure 13 Source contact layers 31 and 32 can be formed. Source contact layers 31 and 32 can be deposited in situ in the furnace chamber after the pre-cleaning process 30. Source contact layers 31 and 32 can be formed by depositing a first semiconductor material. The first semiconductor material may include a polycrystalline silicon layer 31. During the formation of source contact layers 31 and 32, the polycrystalline silicon layer 31 can be selectively epitaxially grown on a first surface (i.e., the exposed surfaces of the upper source layer 16, channel layer 22, and lower source layer 12). A sacrificial amorphous silicon layer 32 is grown on an amorphous material such as silicon oxide or silicon nitride (i.e., the second surface). The polycrystalline silicon layer 31 may be an epitaxially grown polycrystalline silicon layer.

[0051] Therefore, the deposition process of the polysilicon layer 31 can selectively epitaxially grow the polysilicon layer 31 on the exposed surface of the pre-cleaned trench layer 22, while simultaneously selectively forming a sacrificial amorphous silicon layer 32 on the surface of the sealing layer 26. The terms "simultaneously" and "at the same time" as used herein refer to events occurring over overlapping time intervals. For example, if the first event occurs within a first time interval and the second event occurs simultaneously within a second time interval, then the first and second intervals at least partially overlap, such that there exists a time when both the first and second events occur.

[0052] The deposition process of the polycrystalline silicon layer 31 and the sacrificial amorphous silicon layer 32 can adjust the mixing ratio of the chlorinated silicon source material and the chlorine-free silicon source material, thereby adjusting the deposition ratio of the polycrystalline silicon layer 31 to the sacrificial amorphous silicon layer 32. The chlorinated silicon source material may include dichlorosilane (SiH2Cl2, DCS), and the chlorine-free silicon source material may include silane (SiH4). The deposition process of the polycrystalline silicon layer 31 and the sacrificial amorphous silicon layer 32 can be performed, wherein the proportion of the chlorine-free silicon source material is greater than the proportion of the chlorinated silicon source material.

[0053] The mixing ratio and pressure of dichlorosilane (DCS) and silane (SiH4) can increase the growth rate of the polycrystalline silicon layer 31 to a level equal to the growth rate of the sacrificial amorphous silicon layer 32. For example, the process temperature can be from 450°C to 490°C, the mixing ratio of silane to dichlorosilane can be from 7:1 to 9:1, and the pressure can be set to less than 1 Torr.

[0054] If the proportion of dichlorosilane (DCS) is increased, the formation rate of polycrystalline silicon layer 31 is higher than that of sacrificial amorphous silicon layer 32, but the uniformity within the wafer may deteriorate.

[0055] If the proportion of silane (SiH4) increases, the uniformity in the wafer improves, but the formation rate of the amorphous silicon layer 32 increases at the expense of the slit 24, and the interior of the slit 24 can be blocked. If the slit 24 is blocked, it becomes difficult to form a polycrystalline silicon layer.

[0056] The pressure needs to be less than 1 Torr to ensure uniform deposition in the wafer.

[0057] For example, when the ratio of silane (SiH4) to dichlorosilane (DCS) is 3:1, the deposition ratio of polycrystalline silicon layer 31 to sacrificial amorphous silicon layer 32 can be about 1.5:1. In this case, the uniformity is about 5% to 9% (0.5 Torr to 4.5 Torr).

[0058] When the ratio of silane (SiH4) to dichlorosilane (DCS) is 8:1, the deposition ratio of polycrystalline silicon layer 31 to sacrificial amorphous silicon layer 32 can be about 1.1:1, and the uniformity is about 2% to 4% (0.5 Torr to 4.5 Torr).

[0059] The deposition ratio of polycrystalline silicon layer 31 to sacrificial amorphous silicon layer 32 can be maintained under pressure changes ranging from 0.5 Torr to 4.5 Torr, depending on the gas ratio.

[0060] The principle of adjusting the deposition ratio of polycrystalline silicon layer 31 to sacrificial amorphous silicon layer 32 based on the ratio of silane (SiH4) to dichlorosilane (DCS) is as follows. The Cl2 gas generated by dichlorosilane (DCS) can suppress the formation of the sacrificial amorphous silicon layer 32 (or etch it simultaneously with deposition). As the amount of Cl2 gas increases, the deposition rate of the sacrificial amorphous silicon layer 32 decreases, but it may not be able to suppress the deposition of the polycrystalline silicon layer 31. Therefore, the thickness difference between the polycrystalline silicon layer 31 and the sacrificial amorphous silicon layer 32 can be adjusted according to the ratio of dichlorosilane (DCS).

[0061] Furthermore, the thickness distribution deteriorates as the proportion of dichlorosilane (DCS) increases. Therefore, the ratio of silane (SiH4) to dichlorosilane (DCS) can be set to 8:1 to improve the thickness distribution. Additionally, the deposition ratio of polycrystalline silicon layer 31 to sacrificial amorphous silicon layer 32 can be optimized by setting the ratio of silane (SiH4) to dichlorosilane (DCS) to 8:1.

[0062] As described above, a polycrystalline silicon layer 31 is deposited on the surface of the horizontal recess 28 using a mixed gas of silane (SiH4) and dichlorosilane (DCS), and a sacrificial amorphous silicon layer 32 is deposited on the sealing layer 26 by optimizing the mixing ratio of silane (SiH4) and dichlorosilane (DCS).

[0063] Fractured silicon lattices may exist on the surfaces of the channel layer 22, lower source layer 12, and upper source layer 16, where the native oxides have been removed using a pre-cleaning process 30 with halogen gas. Therefore, due to the low growth energy in the crystallization direction, a polycrystalline silicon layer 31 is epitaxially grown on the surfaces of the channel layer 22, lower source layer 12, and upper source layer 16.

[0064] The polycrystalline silicon layer 31 may be thinner than the sacrificial amorphous silicon layer 32. The sacrificial amorphous silicon layer 32 may not completely fill the interior of the slit 24. The polycrystalline silicon layer 31 and the sacrificial amorphous silicon layer 32 may have the same thickness.

[0065] In another embodiment, the deposition process of the polycrystalline silicon layer 31 and the sacrificial amorphous silicon layer 32 can be performed using only silane (SiH4).

[0066] Reference Figure 14 The sacrificial amorphous silicon layer 32 can be selectively removed. HBr gas can be used to remove the sacrificial amorphous silicon layer 32. The sacrificial amorphous silicon layer 32 can be completely removed from the slit 24. During the etching process using HBr gas, the etching rate of the sacrificial amorphous silicon layer 32 can be approximately 10 times faster or more than the etching rate of the polycrystalline silicon layer 31.

[0067] For example, when the sacrificial amorphous silicon layer 32 is grown to approximately 400 Å and the polycrystalline silicon layer 31 is grown to approximately 250 Å, the polycrystalline silicon layer 31 can be etched to 400 Å simultaneously using HBr gas to etch the sacrificial amorphous silicon layer 32 to 400 Å. As a result, after the sacrificial amorphous silicon layer 32 is completely removed, a polycrystalline silicon layer 31 with a thickness of 210 Å can be left.

[0068] Therefore, after the sacrificial amorphous silicon layer 32 is completely removed, the polycrystalline silicon layer 31 can be retained. The polycrystalline silicon layer 31 can be retained in the horizontal recess 28.

[0069] Reference Figure 15An interface layer 33 can be formed. The interface layer 33 can be formed by oxidizing the surface of the polysilicon layer 31. The interface layer 33 may include silicon oxide. The interface layer 33 may be thinner than the polysilicon layer 31. The interface layer 33 can improve the surface roughness of the polysilicon layer 31.

[0070] Reference Figure 16 A second semiconductor material can be formed on the interface layer 33 to fill the slit 24. The second semiconductor material may include an amorphous silicon layer 34. The amorphous silicon layer 34 can be formed by deposition. The amorphous silicon layer 34 is formed after the interface layer 33 is formed. Therefore, seams or voids can be prevented during the deposition of the amorphous silicon layer 34. The interface layer 33 may be extremely thin for electrical contact between the polycrystalline silicon layer 31 and the amorphous silicon layer 34. The polycrystalline silicon layer 31 and the amorphous silicon layer 34 may include dopants. The dopants may include phosphorus. The polycrystalline silicon layer 31 may include a phosphorus-doped epitaxial polycrystalline silicon layer, and the amorphous silicon layer 34 may include a phosphorus-doped amorphous silicon layer.

[0071] Through the aforementioned series of processes, the horizontal recess 28 can be void-free and filled by a polysilicon layer 31, an interface layer 33, and an amorphous silicon layer 34. The slit 24 can be filled by the amorphous silicon layer 34. A portion of the polysilicon layer 31 can extend to cover the bottom of the slit 24, thereby contacting the bottom surface of the sealing layer 26. The amorphous silicon layer 34 can fill the horizontal recess 28 and extend to fill the slit 24. The contact surface between the polysilicon layer 31 and the amorphous silicon layer 34 may include an interface layer 33, and the interface layer 33 may include an oxide layer.

[0072] Reference Figure 17 After the amorphous silicon layer 34 is recessed to a predetermined depth, it can be filled with a metal-based material 35. The metal-based material 35 may include tungsten, titanium nitride, or a combination thereof.

[0073] Figure 18 , Figure 19 , Figure 20 and Figure 21 This is a diagram illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. Figures 18 to 21 In, the same labels are used to represent the same as Figures 3 to 17 The components listed are identical. Duplicate components will not be described in detail.

[0074] First, it can be done through, for example Figures 3 to 12 The process shown is used to form the horizontal depression 28. Then, a pretreatment process 29 and a pre-cleaning process 30 can be performed.

[0075] Next, as Figure 18As shown, a source contact layer can be formed. The source contact layer can be deposited in situ in the furnace chamber after the pre-cleaning process 30. The source contact layer may include a polysilicon layer 31'. When forming the source contact layer, the polysilicon layer 31' can be epitaxially grown on the exposed surfaces of the lower source layer 12, the channel layer 22, and the upper source layer 16. However, a sacrificial amorphous silicon layer 32' is grown on an amorphous material such as silicon oxide or silicon nitride. The polysilicon layer 31' may completely fill the horizontal recess 28. The sacrificial amorphous silicon layer 32' may not be formed in the horizontal recess 28. The sacrificial amorphous silicon layer 32' may be selectively formed on the sealing layer 26.

[0076] Therefore, if the horizontal recess 28 is completely filled by the polysilicon layer 31', the process is simplified.

[0077] The above combination Figure 13 The description provided can be applied to the deposition process of polycrystalline silicon layer 31' and sacrificial amorphous silicon layer 32'. For example, a mixture of chlorinated silicon source material and chlorine-free silicon source material can be used to perform the deposition process of polycrystalline silicon layer 31' and sacrificial amorphous silicon layer 32'. The chlorinated silicon source material may include dichlorosilane (SiH2Cl2, DCS), and the chlorine-free silicon source material may include silane (SiH4). The deposition process of polycrystalline silicon layer 31' and sacrificial amorphous silicon layer 32' can be performed, wherein the proportion of chlorine-free silicon source material is greater than the proportion of chlorinated silicon source material.

[0078] The mixing ratio and pressure of dichlorosilane (DCS) and silane (SiH4) can increase the growth rate of the polycrystalline silicon layer 31' to a level equal to that of the sacrificial amorphous silicon layer 32'. For example, the process temperature can be from 450°C to 490°C, the mixing ratio of silane to dichlorosilane can be from 7:1 to 9:1, and the pressure can be set to less than 1 Torr.

[0079] As described above, a polycrystalline silicon layer 31' is deposited on the surface of the horizontal recess 28 using a mixed gas of silane (SiH4) and dichlorosilane (DCS), and a sacrificial amorphous silicon layer 32' is deposited on the sealing layer 26 by optimizing the mixing ratio of silane (SiH4) and dichlorosilane (DCS).

[0080] In another embodiment, the deposition process of the polycrystalline silicon layer 31' and the sacrificial amorphous silicon layer 32' can be performed using only silane (SiH4).

[0081] Reference Figure 19 The sacrificial amorphous silicon layer 32' can be selectively removed. HBr gas can be used to remove the sacrificial amorphous silicon layer 32'.

[0082] After the sacrificial amorphous silicon layer 32' is removed, the polycrystalline silicon layer 31' can remain in the horizontal recess 28. The polycrystalline silicon layer 31' can fill the horizontal recess 28.

[0083] Reference Figure 20 An amorphous silicon layer 34' can be formed on the polycrystalline silicon layer 31' to fill the slit 24. The amorphous silicon layer 34' can be formed by deposition. The polycrystalline silicon layer 31' and the amorphous silicon layer 34' may include dopants. The dopants may include phosphorus. The polycrystalline silicon layer 31' may include a phosphorus-doped epitaxial polycrystalline silicon layer, and the amorphous silicon layer 34' may include a phosphorus-doped amorphous silicon layer.

[0084] An air gap AG may be formed between the polycrystalline silicon layer 31' and the amorphous silicon layer 34'. Alternatively, the air gap AG may be filled by the amorphous silicon layer 34'.

[0085] Reference Figure 21 After the amorphous silicon layer 34' is recessed to a predetermined depth, it can be filled with a metal-based material 35. The metal-based material 35 may include tungsten, titanium nitride, or a combination thereof.

[0086] According to the above embodiment, since the native oxide is removed by using a pre-cleaning process 30 with halogen gas, the phosphorus (Ph) diffusing from the polysilicon layers 31 and 31' can be easily controlled. Therefore, NAND operations can be performed smoothly, especially erase operations using gate-induced drain leakage (GIDL) current.

[0087] Furthermore, since the native oxides are removed by using a pre-cleaning process 30 with halogen gas, the current inhibitors between the channel layer 22 and the polysilicon layers 31 and 31' can be released, thus ensuring high and uniform current.

[0088] Furthermore, due to the selective formation of polycrystalline silicon layers 31 and 31' and sacrificial amorphous silicon layers 32 and 32', a relatively high etching rate can be ensured compared to other portions of the polycrystalline silicon layers 31 and 31' during subsequent etching processes. Therefore, etch margin can be easily ensured in subsequent etching processes.

[0089] Because etching margins are easily ensured, the incidence of defective etching of polysilicon layers 31 and 31' due to the etching process can be reduced. For example, using a combination of polysilicon layer 31 and sacrificial amorphous silicon layer 32 can further reduce defects.

[0090] Figure 22A This is a diagram illustrating a method for manufacturing a vertical semiconductor device according to a comparative example. In the comparative example, details are omitted. Figure 12 Cleaning process 30.

[0091] Reference Figure 22A A polycrystalline silicon layer can be deposited as the source contact layer. However, since the native oxide NO is on the surface of the channel layer 22, the amorphous silicon layer 34'' can be deposited earlier than the polycrystalline silicon layer. The amorphous silicon layer 34'' can fill the horizontal recess 28.

[0092] Figure 22B The results of secondary ion mass spectrometry (SIMS) analysis based on the comparative example are shown. Phosphorus (P) accumulation may occur at the interface surface between channel layer 22 and amorphous silicon layer 34'' due to native oxide NO.

[0093] Figure 23 The results of SIMS analysis according to the embodiment are shown. No phosphorus deposition occurs on the interface surface between the channel layer 22 and the polysilicon layers 31 and 31'.

[0094] In another embodiment, the selective polysilicon layer deposition process can be applied to both the drain contact layer and the source channel contact layer.

[0095] In another embodiment, the selective polysilicon layer deposition process is a low-temperature process (450°C to 490°C) compared to the conventional epitaxial process, and is applied in low-temperature epitaxial processes.

[0096] As another implementation, since the selective polysilicon deposition process can adjust the ratio of polysilicon to amorphous silicon layers, it is also suitable for hard mask processes requiring differences in light transmittance between amorphous and polysilicon layers. By utilizing the property that the transmittance of the polysilicon layer is higher than that of the amorphous silicon layer, a hard mask can be formed so that regions can be distinguished by localized amorphous and crystalline formation. For example, in order to form Figure 4 The vertical opening 19 can utilize a hard mask layer, in which case the hard mask layer can be used. Figure 13 The hard mask layer is formed using a selective polycrystalline silicon deposition process. In other words, the hard mask layer may include a stack of polycrystalline silicon layers and amorphous silicon layers, and the stack of polycrystalline silicon layers and amorphous silicon layers may be deposited using a mixed gas of silane and dichlorosilane.

[0097] Although the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

[0098] Cross-references to related applications

[0099] This application claims priority to Korean Patent Application No. 10-2020-0135081, filed on October 19, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A method for manufacturing a vertical semiconductor device, the method comprising the following steps: A gap-filling target structure is formed on a semiconductor substrate. The gap-filling target structure includes a horizontal recess and a vertical slit. The horizontal recess is parallel to the semiconductor substrate and has a first surface. The vertical slit extends from the horizontal recess and has a second surface perpendicular to the semiconductor substrate. Remove native oxides from the first surface to form a pre-cleaned first surface; A first semiconductor material is formed in situ on the pre-cleaned first surface; as well as A second semiconductor material is formed on the first semiconductor material. The step of forming the first semiconductor material includes the following steps: A deposition process is performed to selectively form a sacrificial amorphous silicon layer on the second surface, while simultaneously selectively growing a polycrystalline silicon layer on the pre-cleaned first surface; and The sacrificial amorphous silicon layer is selectively removed.

2. The method according to claim 1, wherein, The first surface includes the surface of a silicon layer, and the second surface includes the surface of an insulating material.

3. The method according to claim 1, wherein, The deposition process is performed using a mixture of chlorinated silicon source materials and chlorine-free silicon source materials.

4. The method according to claim 3, wherein, The chlorinated silicon source material includes dichlorosilane, and the chlorine-free silicon source material includes methylsilane.

5. The method according to claim 3, wherein, The deposition process is performed in which the proportion of the chlorine-free silicon source material is greater than the proportion of the chlorine-containing silicon source material.

6. The method according to claim 3, wherein, The deposition process adjusts the deposition ratio of the polycrystalline silicon layer to the sacrificial amorphous silicon layer to 1.1:1 to 1.3:

1.

7. The method according to claim 5, wherein, The deposition process is performed in which the mixing ratio of the chlorinated silicon source material to the chlorine-free silicon source material is adjusted to 7:1 to 9:

1.

8. The method according to claim 1, wherein, The step of removing the natural oxide from the first surface is performed using fluorine-based chemicals.

9. The method according to claim 1, wherein, The first semiconductor material includes polycrystalline silicon, and the second semiconductor material includes amorphous silicon.

10. The method according to claim 1, wherein, The first semiconductor material and the second semiconductor material fill the horizontal recess, and wherein the second semiconductor material extends to fill the vertical slit.

11. The method according to claim 1, wherein, The first semiconductor material fills the horizontal recess, and the second semiconductor material fills the vertical slit.

12. The method according to claim 1, wherein, The steps for forming the gap-filling target structure include the following steps: A stacked structure is formed on the semiconductor substrate, the stacked structure including a source sacrificial layer, a source layer, and a plurality of insulating layers and a plurality of sacrificial layers alternately formed on the source layer; Forming a vertical channel layer that penetrates the stacked structure; Etch the stacked structure to form the vertical slit; A sealing layer is formed on the sidewall of the vertical slit to provide the second surface of the vertical slit; Selectively remove the source sacrificial layer to form the horizontal recess; and A portion of the vertical channel layer is exposed from the horizontal recess to provide the first surface of the horizontal recess.

13. The method according to claim 12, wherein, The first surface of the horizontal recess also includes the exposed surface of the source layer.

14. The method according to claim 12, wherein, The vertical channel layer and the source layer comprise polycrystalline silicon.

15. The method according to claim 1, wherein, The deposition process is performed using only silane (SiH4).

16. A method for manufacturing a vertical semiconductor device, the method comprising the steps of: A lower-level stack is formed on a semiconductor substrate, the lower-level stack including a source sacrificial layer and a source layer; An alternating laminate is formed on the lower-level laminate, the alternating laminate comprising an insulating layer and a sacrificial layer; A vertical channel structure is formed, comprising a channel layer that penetrates the alternating stack and the lower-level stack; A slit is formed that exposes the source sacrificial layer and penetrates the alternating layers; A sealing layer is formed on the sidewall of the slit; A horizontal recess extending from the slit is formed by removing the source sacrificial layer; A portion of the channel layer is exposed from the horizontal recess; A pre-cleaning process that exposes the exposed surfaces of the channel layer to halogen gases; as well as Following the pre-cleaning process, a polycrystalline silicon layer is selectively grown in situ on the exposed surface of the trench layer. The step of growing the polycrystalline silicon layer includes the following steps: A deposition process is performed to selectively form a sacrificial amorphous silicon layer on the surface of the sealing layer, while simultaneously selectively epitaxially growing the polycrystalline silicon layer on the pre-cleaned exposed surface of the channel layer; and The sacrificial amorphous silicon layer is selectively removed.

17. The method of claim 16, further comprising the step of: Prior to the pre-cleaning process, the surface of the trench layer is exposed to a pretreatment process to remove native oxides from the exposed surfaces.

18. The method according to claim 16, wherein, The polycrystalline silicon layer is selectively epitaxially grown on the exposed surface of the channel layer.

19. The method of claim 16, wherein, The polysilicon layer comprises a polysilicon layer selectively epitaxially grown on the exposed surface of the channel layer.

20. The method of claim 16, wherein, The deposition process is performed using a mixture of chlorinated silicon source materials and chlorine-free silicon source materials.

21. The method according to claim 20, wherein, The chlorinated silicon source material includes dichlorosilane, and the chlorine-free silicon source material includes methylsilane.

22. The method according to claim 20, wherein, The deposition process is performed in which the proportion of the chlorine-free silicon source material is greater than the proportion of the chlorine-containing silicon source material.

23. The method according to claim 22, wherein, The deposition process adjusts the deposition ratio of the polycrystalline silicon layer to the sacrificial amorphous silicon layer to 1.1:1 to 1.3:

1.

24. The method according to claim 22, wherein, The deposition process is performed in which the mixing ratio of the chlorinated silicon source material to the chlorine-free silicon source material is adjusted to 7:1 to 9:1.

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