Electronic devices with recessed conductive structures and related methods and systems

Abstract

This application relates to electronic devices and related methods and systems having recessed conductive structures. The electronic device includes: a stacked structure comprising vertically alternating insulating and conductive structures arranged in layers; a post extending vertically through the stacked structure; and a barrier material covering the stacked structure. The electronic device includes a first insulating material extending through the barrier material and into an upper layer portion of the stacked structure, and a second insulating material laterally adjacent to the first insulating material and laterally adjacent to at least some of the conductive structures in the upper layer portion of the stacked structure. At least a portion of the second insulating material is vertically aligned with the barrier material.

Description

[0001] Priority application

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 064,092, filed on October 6, 2020, entitled “Electronic Devices with Receded Conductive Structures and Related Methods and Systems”. Technical Field

[0003] The embodiments disclosed herein relate to electronic devices and the manufacture of electronic devices. More specifically, embodiments of this disclosure relate to electronic devices having recessed conductive structures and insulating extensions adjacent to the recessed conductive structures, as well as related methods and systems. Background Technology

[0004] Memory devices provide data storage for electronic systems. Flash memory devices are one type of memory device and have many uses in modern computers and other electrical devices. Conventional flash memory devices comprise memory arrays with a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In NAND architecture-type flash memory, the memory cells arranged in columns are coupled in series, and the first memory cell in the column is coupled to a data line (e.g., a bit line). In three-dimensional NAND (3D NAND) memory devices (a type of vertical memory device), not only are the memory cells arranged in a horizontal array of rows and columns, but the layers of the horizontal array are also stacked on top of each other (e.g., vertically stacked), thus providing a three-dimensional array of memory cells. The layers contain alternating conductive and insulating (e.g., dielectric) materials. The conductive material acts as the control gate for, for example, the access lines (e.g., word lines) of the memory cells.

[0005] As memory density increases, 3D NAND memory devices may include one or more stacks (e.g., stacked structures) comprising alternating layers of conductive and dielectric materials. Vertical structures (e.g., memory posts containing channel regions) extend along vertical strings of memory cells. Each vertical memory string may include at least one selection device coupled in series to a series combination of vertically stacked memory cells. The drain end of the string is adjacent to one of the top and bottom of the vertical structure (e.g., memory post), while the source end of the string is adjacent to the other of the top and bottom of the post. The drain end is operatively connected to a bit line, while the source end is operatively connected to a source. A string driver drives access line (e.g., word line) voltages to write to or read from the memory cells in the vertical string. 3D NAND memory devices also include additional conductive materials configured to provide electrical connections between word lines and other conductive structures of the device, such that memory cells of the memory posts can be selected for write, read, and erase operations.

[0006] To form memory pillars, the layers of the stack are patterned to form pillar openings, cell films and filler materials are formed within these openings, and contact plugs are formed on top of the cell films and filler materials, thereby creating memory pillars extending through one or more stacks. The cell films comprise channel material and cell material. As the number of conductive structure layers increases, the processing conditions for forming contacts aligned with the various components of a 3D NAND memory device become increasingly difficult. Additionally, other techniques for increasing memory density have reduced the spacing between adjacent vertical memory strings. However, reducing the spacing between adjacent vertical memory strings can increase the difficulty of forming individual electrical connections to the vertical memory strings without shorting them. Summary of the Invention

[0007] The embodiments described herein include electronic devices and related methods and systems having recessed conductive structures. According to one embodiment described herein, an electronic device includes: a stacked structure comprising vertically alternating insulating and conductive structures arranged in layers; a post extending vertically through the stacked structure; a barrier material covering the stacked structure; a first insulating material extending through the barrier material and into an upper layer portion of the stacked structure; and a second insulating material laterally adjacent to the first insulating material and laterally adjacent to at least some of the conductive structures in the upper layer portion of the stacked structure, at least a portion of the second insulating material being vertically aligned with the barrier material.

[0008] According to an additional embodiment described herein, an electronic device includes: a guide post disposed in a sub-block of a stacked structure; and a layer comprising conductive structures separated by an insulating structure within the stacked structure, wherein at least some of the conductive structures in the upper layer portion of the stacked structure are laterally adjacent to the periphery of a single sub-block of the stacked structure, wherein the outer diameter of a portion of the additional insulating material at the height of the uppermost conductive structure in the upper layer portion of the stacked structure is greater than the outer diameter of another portion of the additional insulating material at the height of the lowermost conductive structure in the upper layer portion of the stacked structure.

[0009] Furthermore, according to additional embodiments described herein, a method of forming a memory device includes: forming a stacked structure comprising vertically alternating insulating and conductive structures arranged in layers; forming a barrier material vertically covering the stacked structure and extending horizontally across the stacked structure; forming at least one opening penetrating the barrier material and entering an upper layer portion of the stacked structure; recessing a sacrificial portion of the conductive structure in the upper layer portion adjacent to the at least one opening, the recessed area of ​​the conductive structure being directly vertically aligned with the barrier material; and forming an insulating material in the recessed area of ​​the conductive structure and the at least one opening.

[0010] According to other embodiments described herein, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device including: a stacked structure comprising alternating layers of insulating and conductive structures; a central insulating material between sub-blocks of the stacked structure; and an insulating extension extending laterally from the central insulating material, the insulating extension laterally adjacent to the conductive structure of an upper selection gate of the stacked structure. Attached Figure Description

[0011] Figure 1A This is a cross-sectional view of an electronic device comprising guide posts arranged in sub-blocks of a stacked structure according to an embodiment of the present disclosure;

[0012] Figure 1B It was intercepted along line AA. Figure 1A A top view of an electronic device;

[0013] Figures 1C to 1F These are cross-sectional views at various stages of forming an electronic device according to embodiments of the present disclosure;

[0014] Figure 1G is in a state of being with Figure 1FCross-sectional view of a conventional electronic device in a similar processing stage;

[0015] Figure 2 This is a partial sectional perspective view of an electronic device according to an embodiment of the present disclosure;

[0016] Figure 3 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0017] Figure 4 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0018] An electronic device (e.g., apparatus, microelectronic device, semiconductor device, memory device) is disclosed, comprising posts disposed in sub-blocks of a stacked structure, wherein an upper conductive structure serving as an upper select gate (e.g., drain-side select gate (SGD)) of the electronic device is recessed (e.g., laterally recessed) relative to a vertically adjacent insulating structure of the stacked structure. A barrier material is formed on the stacked structure. An insulating material is formed in openings (e.g., gaps) of the stacked structure and is configured as a continuous material extending between adjacent posts in a central region of the stacked structure. The insulating material serves to electrically isolate one sub-block of the stacked structure (e.g., a memory sub-block) from another (e.g., adjacent) sub-block of the stacked structure of the electronic device. Insulating extensions (e.g., additional insulating material regions) are formed in the recessed regions of the upper conductive structure. Compared to conventional electronic devices, where a portion of the contact structure (e.g., contact point, post contact) extends below the barrier material, the electronic devices according to embodiments of this disclosure reduce the occurrence of bridging (e.g., electrical connections) between two or more portions of the conductive structure by forming an insulating extension that is vertically adjacent to the insulating material and laterally adjacent to the upper conductive structure. Unlike conventional electronic devices where SGD isolation is provided solely by an insulating material with openings and without an insulating extension, the insulating extension can help reduce the etching profile requirements for upper select gate (e.g., SGD) isolation provided by the insulating material.

[0019] The following description provides specific details, such as material types and processing conditions, to provide a sufficient description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without employing these specific details. In fact, embodiments of the apparatus and methods can be practiced in conjunction with conventional semiconductor manufacturing techniques used in the industry.

[0020] The manufacturing processes described herein do not form a complete process flow for processing electronic devices (e.g., microelectronic devices, semiconductor devices, memory devices) or their structures (e.g., systems). The remainder of the process flow is known to those skilled in the art. Therefore, this document only describes the methods and structures necessary for understanding embodiments of the electronic devices and methods of this disclosure.

[0021] Unless otherwise specified, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, thick-layer coating (e.g., spraying), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by a person skilled in the art. Unless the context otherwise indicates, the removal of the material can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion polishing, polishing planarization (e.g., chemical mechanical planarization), or other known methods.

[0022] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, electronic device, or electronic system. Variations in the shapes depicted in the drawings should be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include shape deviations, for example, due to manufacturing processes. For example, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims of the invention. The drawings are not necessarily drawn to scale. Additionally, common elements between the drawings may retain the same numerical designation.

[0023] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” are intended to include the plural forms as well.

[0024] As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0025] As used herein, the terms “about” or “approximately” for numerical values ​​of a particular parameter include, as understood by one of ordinary skill in the art, a value and the degree of variation of the value within acceptable tolerances for the particular parameter. For example, “about” or “approximately” for a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0026] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” may be used herein for ease of description to describe the relationship of one element or feature to another as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figures is reversed, then an element described as “below,” “under,” “below,” or “on the bottom” of another element or feature will be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0027] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure. The height of a corresponding material or feature (e.g., the structure) can be defined as a dimension in the vertical plane.

[0028] As used herein, the term “width” refers to and includes a dimension along a horizontal plane (e.g., at a certain height, if identified), defining the maximum distance a particular material or structure can travel along such a plane. For example, the “width” of a structure that is at least partially hollow is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer diameter of a hollow cylindrical structure.

[0029] As used herein, the term “configured as” refers to the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device that facilitate the operation of one or more of the structure and device in a predetermined manner.

[0030] As used herein, features described as “adjacent” to each other (e.g., area, material, structure, device) refer to and include one or more of the disclosed identified features located closest to each other (e.g., closest to each other). Additional features (e.g., additional area, additional material, additional structure, additional device) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Therefore, features described as “vertically adjacent” to each other refer to and include one or more of the disclosed identified features located closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other refer to and include one or more of the disclosed identified features located closest to each other (e.g., horizontally closest to each other).

[0031] As used in this article, the term “split” refers to the distance between identical points in two adjacent (i.e., adjacent) features.

[0032] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of the other element, directly adjacent to (e.g., directly laterally adjacent to, directly vertically adjacent to) the other element, directly below the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of the other element, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to) the other element, indirectly below the other element, or nearby, and that other elements are present between them. In contrast, when an element is referred to as "directly on" or "directly adjacent to" another element, no intermediate elements are present.

[0033] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct resistive connection or by indirect connection (e.g., via another structure).

[0034] As used herein, the term "selectively removable" refers to and includes a material exhibiting a greater removal rate relative to another material exposed to the same treatment conditions (e.g., exposure to radiation (e.g., heat)). A material selectively removable relative to another material can be substantially completely removed without removing any of the other material.

[0035] As used herein, the term "selectively etchable" means and includes a material exhibiting a greater etching rate relative to another material exposed to a given etching chemical and / or processing condition in response to exposure to the same etching chemical and / or processing conditions. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater. Those skilled in the art can select the etching chemicals and etching conditions used for selectively etching the desired material.

[0036] As used herein, the term "opening" refers to a volume that extends through at least one structure or at least one material, leaving a gap within said at least one structure or at least one material, or a volume that extends between structures or materials, leaving a gap between said structures or materials. Unless otherwise described, an "opening" does not necessarily contain no material. That is, an "opening" does not have to be a void. An "opening" formed in or between a structure or material may include structures or materials other than those in which the opening is formed. Furthermore, a structure or material "exposed" within an opening is not necessarily in contact with the atmosphere or a non-solid environment. A structure or material "exposed" within an opening may be adjacent to or in contact with other structures or materials disposed within the opening.

[0037] As used herein, the term “sacrifice” in relation to the use of a material or structure means and includes a material, structure, or part of a material or structure that is formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0038] As used herein, the term "electronic device" includes, but is not limited to, memory devices, and semiconductor devices that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices. Furthermore, electronic devices may incorporate memory and other functionalities, such as a so-called "system-on-a-chip" (SoC) that includes a processor and memory, or an electronic device that includes logic and memory. Electronic devices comprise alternating layers of conductive and dielectric materials.

[0039] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based alloys, Fe-based alloys, etc.). Alloys based on Ni, alloys based on Fe and Ni, alloys based on Co and Ni, alloys based on Fe and Co, alloys based on Co, Ni, and Fe, alloys based on Al, alloys based on Cu, alloys based on magnesium (Mg), alloys based on Ti, steel, low-carbon steel, stainless steel), materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" refers to and includes structures formed of and containing conductive materials.

[0040] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium dioxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y And at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y Additionally, "insulating structure" refers to and includes structures formed of insulating materials and structures containing insulating materials.

[0041] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition conforms to variance (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0042] As used herein, the term "substrate" refers to and includes a material (e.g., a base material) or structure on which additional material is formed. A substrate can be an electronic substrate, a semiconductor substrate, a base semiconductor layer on a support structure, an electrode, an electronic substrate on which one or more materials, layers, structures, or regions are formed, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. The material on an electronic or semiconductor substrate may include, but is not limited to, semiconductive, insulating, and conductive materials. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. Substrates may be doped or undoped.

[0043] exist Figure 1A and 1B The diagram shows an electronic device 100, which includes post 105 in a stacked structure 110 adjacent to a substrate structure 115 (e.g., a substrate) (e.g., vertically adjacent to and on it), wherein Figure 1B This is a top view taken along line AA in Figure 1. The electronic device 100 also includes a layer 120, a conductive structure 125, an insulating structure 130, a source structure 135, a filler material 140, a post opening 145, a unit membrane 150, an upper insulating structure 155, a contact plug 160, and at least one opening 165 (e.g., at least one slit). The opening 165 can divide the stacked structure 110 of the electronic device 100 into separate sub-blocks, such as a first sub-block 166 and a second sub-block 168, but additional sub-blocks (e.g., four sub-blocks) are also contemplated. Figure 1A and 1B As shown, the first sub-block 166 and the second sub-block 168 may each include a plurality (e.g., several, more than one) of guide posts 105. Guide posts 105 may be formed in guide post openings 145 that extend at least partially vertically through layer 120. Guide posts 105 may be configured to be operatively coupled (e.g., electrically connected) to memory posts (e.g., channel posts) of the source structure 135. For example, guide post openings 145 in… Figure 1A The diagram shows a cell membrane 150 and a filler material 140. At least some of the posts 105 may be configured to be non-operably coupled (e.g., electrically connected) to so-called "dummy posts" of the source structure 135. For example, such dummy posts can provide mechanical integrity and support for memory posts within the stacked structure 110.

[0044] The electronic device 100 further includes a first insulating material 170 located within an opening 165, a barrier material 180 adjacent to (e.g., vertically adjacent to and on) the upper surfaces of the upper insulating structure 155 and the contact plug 160, a second insulating material 184 adjacent to (e.g., vertically adjacent to and on) the barrier material 180, and a third insulating material 186 adjacent to (e.g., vertically adjacent to and on) the second insulating material 184. A contact structure 195 (e.g., a contact point, a post contact) is located in an opening extending vertically through each of the third insulating material 186, the second insulating material 184, and the barrier material 180. In some embodiments, the contact structure 195 may be adjacent to (e.g., vertically adjacent to and on) the contact plug 160 and in direct electrical contact with it. In other embodiments, an additional contact structure (e.g., a contact through-hole) may be located between the contact structure 195 and the contact plug 160. In some such embodiments, additional portions of the barrier material 180 may be adjacent to (e.g., vertically adjacent to, or on) additional contact structures, wherein at least some of the conductive structures 125 are vertically located between the two portions of the barrier material 180. The barrier material 180 may be divided into two portions by an opening 182 corresponding to an opening 165 in the stacked structure 110. Therefore, the barrier material 180 in… Figure 1A The horizontal direction may be discontinuous, wherein the first insulating material 170 separates the portions of the barrier material 180.

[0045] The electronic device 100 further includes a fourth insulating material 188 located within a recessed region 190 adjacent to (e.g., laterally adjacent to) an opening 165 of a stacked structure 110, of a first insulating material 170. The fourth insulating material 188 is adjacent to (e.g., laterally adjacent to) at least some of the conductive structures 125 within the respective layers 120 of the stacked structure 110. The fourth insulating material 188 extends laterally outward away from the first insulating material 170 in the opening 165, thereby forming an insulating extension 192 within the recessed region 190. For example, the insulating extension 192 may be located at at least some of the conductive structures 125 within an upper layer portion 120A of an adjacent layer 120, while a lower layer portion 120B of a layer 120 below (e.g., vertically adjacent to) the lower surface of the opening 165 may not include (e.g., not have) the insulating extension 192 adjacent to the conductive structures 125. The insulating extension 192 alternates vertically with the ends of the insulating structures 130 within the upper layer portion 120A. Therefore, the width of the portion of the conductive structure 125 that is close to the first insulating material 170 and within the upper layer portion 120A (e.g., the portion of the conductive structure 125 that is laterally adjacent to the insulating extension 192) is shorter than (e.g., the width is relatively smaller than) the width of at least some portions of the conductive structure 125 in the lower layer portion 120B.

[0046] Each layer 120 of the stacked structure 110 of the electronic device 100 may each include at least one of the conductive structures 125 that are vertically adjacent to at least one of the insulating structures 130. The stacked structure 110 may include a desired number of layers 120. For example, the stacked structure 110 may include conductive structures 125 and insulating structures 130 of eight (8) or more, sixteen (16) or more, thirty-two (32) or more, sixty-four (64) or more, one hundred and twenty-eight (128) or more, or two hundred and fifty-six (256) or more of the layers 120.

[0047] The conductive structure 125 of the electronic device 100 may be formed of and contain at least one conductive material. In some embodiments, the conductive structure 125 is formed of tungsten (W). The conductive structure 125 may be operatively coupled to the conductive structure to couple to the contact plug 160 and the source structure 135. The conductive structure 125 may also provide electrical access to other conductive components of the electronic device 100, which may include, but are not limited to, data lines (e.g., bit lines, select lines), contacts, interconnects, routing structures, CMOS circuitry, or other conductive components vertically above or below the stacked structure 110. By way of example only, the conductive structure 125 may electrically connect the source structure 135 to other conductive components of the electronic device 100. For example, the conductive structure 125 of layer 120 may be configured as an access line (e.g., word line, gate) of the electronic device 100, which is formed by replacing a sacrificial material (e.g., a nitride material) through a so-called “replacement gate” process. The electronic device 100 may alternatively be formed via a so-called "gate-first" process, wherein a layer 120 having alternating conductive structures 125 and insulating structures 130 is formed prior to the formation of the post 105. For example, the layer 120 having alternating conductive structures 125 and insulating structures 130 is present in the electronic device 100 prior to the formation of the post 105, and the post 105, contact plug 160, opening 165, first insulating material 170, and fourth insulating material 188 of insulating extension 192 are subsequently formed after the gate-first process.

[0048] The insulating structure 130, including the upper insulating structure 155, may be formed of and contain at least one dielectric material. In some embodiments, the insulating structure 130 is formed of and contains SiO2. For example, the insulating structure 130 may be configured to electrically isolate the conductive structures 125 of the electronic device 100 from each other and from other conductive components of the electronic device 100 (e.g., additional components vertically above or below the stacked structure 110). The insulating structure 130 of layer 120 is positioned between the conductive structures 125 of layer 120.

[0049] At least one lower conductive structure 125 of the stacked structure 110 may serve as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the electronic device 100. In some embodiments, a single (e.g., only one) conductive structure 125 of the vertically bottommost layer 120 of the stacked structure 110 may serve as a lower select gate (e.g., an SGS) of the electronic device 100. In some embodiments, an upper conductive structure 125 of the stacked structure 110 may serve as an upper select gate (e.g., a drain-side select gate (SGD)) of the electronic device 100. In some embodiments, horizontally adjacent (e.g., in the Y direction) conductive structures 125 of the vertically topmost layer 120 of the stacked structure 110 may serve as upper select gates (e.g., SGDs) of the electronic device 100. In other embodiments, the stack structure 110 includes a lower portion and an upper portion. The lower portion includes a conductive structure 125 laterally adjacent to the guide post 105, and the upper portion includes a conductive structure 125 laterally adjacent to an additional contact structure located between the contact structure 195 and the contact plug 160, and is separated from the lower portion of the stack structure 110 by a barrier material 180. The conductive structure 125 within the upper portion may serve as an SGD (e.g., a de-integrated SGD).

[0050] In some embodiments, the upper layer portion 120A comprises approximately 0.1% to approximately 3% of the total number (e.g., total number) of the uppermost layer 120, such as the layers 120 of the stacked structure 110. For example, the upper layer portion 120A may comprise the uppermost two layers to the uppermost nine layers of layer 120. A specific amount (e.g., number) of layers 120 included in the upper layer portion 120A may be selected or otherwise customized to the amount that most readily makes electrical contact (e.g., bridging) with a portion of the contact structure 195 in the absence of the insulating extension 192. For example, the amount in the upper layer portion 120A of layer 120 may comprise the number of conductive structures 125 (e.g., word lines) that serve as the upper select gate of the electronic device 100. Furthermore, the depth (e.g., vertical range) of the opening 165 (e.g., SGD isolation) may be selected to correspond to the number of conductive structures 125 that serve as the upper select gate.

[0051] like Figure 1AAs shown, electronic device 100 includes a single stack. However, this disclosure is not limited thereto. For example, electronic device 100 may include more than one stack (e.g., two stacks), including a lower stack and an upper stack, wherein each stack includes alternating layers 120 of conductive structure 125 and insulating structure 130. In such embodiments, the lower stack and the upper stack are vertically adjacent to each other. In additional embodiments, electronic device 100 may include a greater number of stacks within a stack structure 110. In some such embodiments, the upper select gate of electronic device 100 may be located vertically above the stack structure 110 overlying it (e.g., within an additional stack structure (not shown) of a multi-stacked device). Although Figure 1A The stacked structure 110 of the electronic device 100 includes five layers 120 in the upper layer portion 120A and four layers 120 in the lower layer portion 120B, but each of the upper layer portion 120A and the lower layer portion 120B may contain more or fewer layers 120. Although in Figure 1A Not shown, but a complementary metal-oxide-semiconductor (CMOS) circuit system may exist beneath the substrate structure 115, as shown in the reference. Figure 2 To describe in more detail.

[0052] The guide post 105 extends from the upper surface of the contact plug 160 to the upper surface of the source structure 135 adjacent to the substrate structure 115. Optionally, the guide post 105 may extend at least partially into the source structure 135, or may extend through the source structure 135 and into the substrate structure 115. Although Figure 1A and 1B Eight contact plugs 160 and eight guide posts 105 are shown, but additional contact plugs 160 and guide posts 105 may be present depending on the required configuration of the electronic device 100.

[0053] Guide post 105 includes channel material and unit material on the sidewall of layer 120 (in Figure 1AThe diagram typically shows a cell film 150 and a filler material 140 between opposing portions of the cell film 150. The filler material 140 and the cell film 150 of the post 105 extend from the upper surface of the stacked structure 110 through the lower surface. The channel material may comprise polysilicon or other channel materials known in the art. In some embodiments, the channel material is polysilicon. The cell material may comprise one or more of dielectric materials, conductive materials, etc. The cell material may comprise one or more of oxide materials, storage materials, or tunnel dielectric materials, as known in the art. By way of example only, the cell material may comprise an oxide-nitride-oxide (ONO) structure having a tunnel dielectric material, a charge trapping material, and a charge blocking material between the channel material and the insulating structure 130 or between the channel material and the conductive structure 125. The charge trapping material may be located directly between the tunnel dielectric material and the charge blocking material. In some embodiments, the tunnel dielectric material is in direct contact with the channel material and the charge trapping material. The charge blocking material can directly contact the charge trapping material and the insulating structure 130 or the conductive structure 125, and can be positioned close to them.

[0054] The filler material 140 may be a dielectric material. In some embodiments, the filler material 140 is an oxide material. The filler material 140 may substantially completely fill the post opening 145 in which the post 105 is formed. The upper surface of the filler material 140 may be substantially coplanar with the upper surface of the unit film 150. The filler material 140 separates opposing portions of the unit film 150 in the post opening 145.

[0055] The guide post 105 also includes a contact plug 160 positioned over the filler material 140 and the unit film 150 of the guide post 105. The contact plug 160 is formed of a conductive material (e.g., containing a conductive material). In some embodiments, the contact plug 160 is formed of polysilicon.

[0056] The guide posts 105 and contact plugs 160 are formed at a distance (e.g., having the same spacing). The upper surface of the contact plug 160 may be substantially coplanar with the upper surface of the upper insulating structure 155 of the uppermost layer 120. The contact plug 160 may be operatively coupled (e.g., electrically connected) to the contact structure 195. The contact structure 195 may in turn be operatively coupled (e.g., electrically connected) to other conductive materials of the electronic device 100, such as additional contacts and / or conductive lines (not shown) above the stack structure 110. Each guide post 105 and its corresponding contact plug 160 is associated with a single (e.g., one) contact structure 195. For clarity and to facilitate understanding of the figures and associated description, Figure 1A There are no additional contact structures 195 around the opening 165.

[0057] Contact structure 195 may be formed of and comprise at least one conductive material. As a non-limiting example, contact structure 195 may be formed of and comprise n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or a metal. In some embodiments, contact structure 195 comprises n-doped polysilicon. In other embodiments, contact structure 195 comprises tungsten (W). The outer surface (e.g., sidewall) of contact structure 195 may exhibit a wedge-shaped profile, wherein the upper portion of each contact structure 195 has a critical dimension (e.g., width) larger than its lower portion, such as... Figure 1A As shown in the diagram. In other embodiments, the contact structure 195 has different profiles, such as a substantially orthogonal (e.g., substantially rectangular) profile, a disc-shaped profile, or any other three-dimensional recessed shape, such that at least a portion of the contact structure 195 (e.g., the lateral extent of the upper surface) extends beyond the sidewall of the guide post 105 in at least one lateral direction (e.g., the X direction). Figure 1A As shown, the contact structure 195 may be laterally offset (e.g., eccentrically positioned or staggered) to facilitate electrical connection with the contact plug 160 of the guide post 105.

[0058] Contact structure 195 is located in an opening extending vertically through each of the third insulating material 186, the second insulating material 184, and the barrier material 180. The second insulating material 184 and the third insulating material 186 may each be formed of and contain at least one dielectric material. In some embodiments, one or more of the second insulating material 184 and the third insulating material 186 are formed of and contain SiO2. The material composition of the third insulating material 186 may be substantially the same as or different from the material composition of the second insulating material 184, and the material composition of at least one of the second insulating material 184 and the third insulating material 186 may be substantially the same as or different from the material composition of the insulating structure 130 of the layer 120 of the stacked structure 110.

[0059] The upper insulating structure 155 and the second insulating material 184 of the stacked structure 110 are separated from each other by a barrier material 180. The barrier material 180 may be formed of and contain at least one dielectric material. For example, the barrier material 180 may include a nitride material (e.g., silicon nitride, oxide nitride), such as an etch-stopping material located on the upper surfaces of the upper insulating structure 155 and the contact plug 160. The barrier material 180 may be characterized as a so-called "nitride etch-stopping" material, the material comprising a material composition different from that of the insulating structure 130 of layer 120 containing the upper insulating structure 155, and different from the material composition of each of the second insulating material 184 and the third insulating material 186, such that the barrier material 180 can be selectively removed relative to the insulating structure 130, the second insulating material 184, and the third insulating material 186.

[0060] The first insulating material 170 and the fourth insulating material 188 may each be formed of and contain at least one dielectric material. In some embodiments, one or more of the first insulating material 170 and the fourth insulating material 188 are formed of and contain SiO2. In other embodiments, one or more of the first insulating material 170 and the fourth insulating material 188 are formed of and contain a low-k dielectric material. The material composition of the fourth insulating material 188 may be selected to promote substantially complete filling of the recessed region 190 adjacent to the opening 165, and the material composition of the first insulating material 170 may be selected to promote substantially complete filling of the opening 165. In some embodiments, one or more of the first insulating material 170 and the fourth insulating material 188 are high-quality silicon oxide materials. For example, the fourth insulating material 188 and / or the first insulating material 170 may be highly uniform and highly conformal silicon oxide (SiO2). x The material (e.g., a highly uniform and conformal SiO2 material). One or more of the first insulating material 170 and the fourth insulating material 188 can be highly uniform and conformal, as, for example, by ALD deposition. The material composition of the first insulating material 170 may be substantially the same as or different from the material composition of the fourth insulating material 188 and / or the insulating structure 130 of layer 120. In embodiments where the insulating structure 130, the first insulating material 170, and the fourth insulating material 188 (and therefore the insulating extension 192) are formed of and contain the same material, the insulating structure 130, the first insulating material 170, and the insulating extension 192 are not visually distinguishable in the electronic device 100. Furthermore, the material composition of each of the first insulating material 170 and the fourth insulating material 188 may differ from the material composition of the barrier material 180.

[0061] The lower portion of the first insulating material 170 in the opening 165 directly contacts the upper surface of one of the insulating structures 130 (e.g., the uppermost insulating structure 130 within the lower layer portion 120B of layer 120). The fourth insulating material 188 within the recess 190 directly contacts the first insulating material 170 in the opening 165 and directly contacts (e.g., directly adjacent to) the lateral side surface of the conductive material of the conductive structure 125 within the upper layer portion 120A of layer 120. The upper and lower surfaces of the fourth insulating material 188 directly contact the vertically adjacent portions of the insulating structure 130. Therefore, the first insulating material 170 and the fourth insulating material 188 divide the conductive structure 125 into two parts.

[0062] As in Figure 1B As most clearly shown, the guide posts 105 (underlying contact plugs 160) within adjacent sub-blocks (e.g., first sub-block 166, second sub-block 168) are separated by a first insulating material 170, which extends substantially continuously in the Y direction between adjacent guide posts 105. Therefore, the first insulating material 170 is configured as a substantially continuous (e.g., undivided) material extending between the first sub-blocks 166 and second sub-blocks 168 of the stacked structure 110. The first insulating material 170 and the fourth insulating material 188 (in...) Figure 1B (Not shown in the perspective view) is used to electrically isolate the first sub-block 166 from the second sub-block 168. Furthermore, because the insulating extension 192 is laterally adjacent to the first insulating material 170 in the upper layer portion 120A, the insulating extension 192 is used to further electrically isolate the conductive structures 125 from each other and from the contact structure 195, to significantly reduce (e.g., substantially prevent) physical and / or electrical connections between adjacent portions of the conductive structures 125.

[0063] like Figure 1A As shown, the electronic device 100 also includes a source structure 135 adjacent to (e.g., vertically adjacent to and on) a substrate structure 115. The source structure 135 may be formed of one or more of the conductive materials discussed earlier. In some embodiments, the source structure 135 is formed of doped polysilicon. In other embodiments, the source structure 135 is formed of tungsten silicide. The source structure 135 is operatively coupled to a memory post, but isolated from the dummy post of post 105. The channel material of the memory post of post 105 is in electrical contact with the source structure 135.

[0064] An electronic device 100 according to an embodiment of the present disclosure includes a plurality of memory cells. Each memory cell is defined by an intersection point between the conductive structure 125 of layer 120 and the channel material of the memory posts of post 105, and post 105 includes a string of memory cells. For example, the electronic device 100 may be a memory device comprising a plurality of memory planes, each memory plane comprising a memory block. Figure 1A and 1B As shown, the electronic device 100 includes eight guide posts 105. The guide posts 105 are arranged in a block (e.g., a memory block) that includes multiple sub-blocks 166, 168 (e.g., memory sub-blocks). However, there may be more or fewer guide posts 105 in a sub-block, and other configurations of the guide posts 105 may be expected in a sub-block. Figure 1A and 1B The electronic device 100 includes four posts in each of the first sub-block 166 and the second sub-block 168. An opening 165 containing a first insulating material 170 forms two sub-blocks spaced apart from each other, each sub-block containing four posts 105. By using the first insulating material 170 to separate the two sub-blocks from each other, each sub-block can be individually controlled. The first insulating material 170 and the fourth insulating material 188 provide electrical isolation between the conductive structures 125 and with respect to the contact structures 195. The electronic device 100 according to embodiments of the present disclosure may include, but is not limited to, 3D electronic devices, such as 3D NAND flash memory devices (e.g., multi-stack 3D NAND flash memory devices). However, the electronic device 100 according to embodiments of the present disclosure can be used in other memory devices having multiple stacks in which electrical isolation between adjacent sub-blocks is desired.

[0065] Therefore, an electronic device is disclosed, comprising: a stacked structure including vertically alternating insulating and conductive structures arranged in layers; guide posts extending vertically through the stacked structure; and a barrier material covering the stacked structure. The electronic device includes a first insulating material extending through the barrier material and into an upper layer portion of the stacked structure, and a second insulating material laterally adjacent to the first insulating material and laterally adjacent to at least some of the conductive structures in the upper layer portion of the stacked structure. At least a portion of the second insulating material is vertically aligned with the barrier material.

[0066] Therefore, another electronic device is disclosed, comprising: guide posts arranged in sub-blocks of a stacked structure; and a layer comprising conductive structures separated by an insulating structure within the stacked structure. At least some of the conductive structures in the upper layer portion of the stacked structure are laterally adjacent to the periphery of individual sub-blocks of the stacked structure, containing additional insulating material. The outer diameter of a portion of the additional insulating material at the height of the uppermost conductive structure in the upper layer portion of the stacked structure is larger than the outer diameter of another portion of the additional insulating material at the height of the lowermost conductive structure in the upper layer portion of the stacked structure.

[0067] Figures 1C to 1F Showing the formation Figure 1A and 1B Method of electronic device 100. (See reference) Figure 1C The diagram illustrates an electronic device 100 manufactured in part according to this disclosure. The alternating conductive structures 125 and insulating structures 130 of the stacked structure 110 can each be formed using conventional processes, which are not described in detail herein.

[0068] The guide post 105 can be formed in the stacked structure 110 using conventional processes (e.g., conventional deposition processes) and conventional processing equipment, which are not described in detail herein. For example, the guide post 105 can be formed in a guide post opening 145 extending vertically through a layer 120 of the stacked structure 110, with a unit film 150 and filler material 140 formed into the opening. A portion of the filler material 140 and unit film 150 is removed, such that the upper surfaces of the filler material 140 and unit film 150 in the guide post opening 145 are recessed. The conductive material of the contact plug 160 is formed adjacent to (e.g., on or above) the filler material 140 and unit film 150. Excess conductive material of the contact plug 160 can be removed using conventional techniques, such that the upper surface of the contact plug 160 is substantially coplanar with the upper insulating structure 155 of the stacked structure 110. At this processing stage, the contact plug 160 and unit film 150 are configured to be electrically connected to the source structure 135 adjacent to the substrate structure 115.

[0069] Barrier material 180 may be formed adjacent to (e.g., on or above) the exposed upper surfaces of the upper insulating structure 155 and the contact plug 160. In some embodiments, barrier material 180 may be in direct physical contact with each of the upper insulating structure 155 of the layer 120 of the stacked structure 110 and the contact plug 160 of the guide post 105. In other embodiments, barrier material 180 may be in direct physical contact with additional contact structures (not shown) and additional insulating structures 130 covering the upper insulating structure 155 and the contact plug 160. Barrier material 180 may be formed on or above portions of the exposed upper surfaces of the upper insulating structure 155 and the contact plug 160 using one or more conventional deposition processes (e.g., conventional CVD or PVD processes).

[0070] The second insulating material 184 may be formed adjacent to (e.g., on or above) the barrier material 180, and the third insulating material 186 may be formed adjacent to (e.g., on or above) the second insulating material 184. For example, the second insulating material 184 and the third insulating material 186 may be formed on or above the exposed portions of the barrier material 180 and the second insulating material 184 using one or more conventional deposition processes (e.g., conventional CVD or PVD processes). Each of the barrier material 180, the second insulating material 184, and the third insulating material 186 may be formed of and contain at least one dielectric material, including, but not limited to, oxides, nitrides, or oxynitrides. As a non-limiting example, the barrier material 180 may be a nitride material (e.g., silicon nitride or silicon oxynitride), and at least one (e.g., both) of the second insulating material 184 and the third insulating material 186 may be an oxide material (e.g., silicon oxide). In other words, the barrier material 180 can be formed of a different material with an etching selectivity different from that of each of the second insulating material 184 and the third insulating material 186. Furthermore, the third insulating material 186 can be formed of the same material as the second insulating material 184, or of a different material than the second insulating material 184.

[0071] like Figure 1CAs shown, an opening 165 is formed and extends through each of the third insulating material 186, the second insulating material 184, and the barrier material 180, and into the upper layer portion 120A of the layer 120 of the stacked structure 110. The opening 165 is formed to partially extend through the stacked structure 110 to the lower layer portion 120B, but not through it. The opening 165 may extend to the upper portion of the lower layer portion 120B. By way of example only, the opening 165 extends into the upper layer portion 120A to a depth of about one to about nine layers 120. In some embodiments, the opening 165 extends into about five layers 120 of the upper layer portion 120A. The opening 165 extends in a direction (Y direction) substantially parallel to the opening (e.g., a slit) (not shown) through which the gate replacement process is carried out. The opening 165 can be formed using conventional processes and conventional processing equipment, such as conventional photolithography and conventional material removal processes (e.g., etching processes, such as dry etching and / or wet etching), and conventional processing equipment is not described in detail herein. In some embodiments, portions of the third insulating material 186 and the second insulating material 184 can be removed by a first etching action for forming the opening 165, and the underlying portion of the barrier material 180 can be removed by a second etching action for forming an opening 182 corresponding to the opening 165.

[0072] The upper portion of the opening 165 has its sidewalls defined by the third insulating material 186, the second insulating material 184, and the remainder of the barrier material 180. The lower portion of the opening 165 has its sidewalls defined by the conductive structure 125 and the remainder of the insulating structure 130, including the upper insulating structure 155. Figure 1C As shown, the cross-section of opening 165 may be U-shaped or V-shaped, and its sidewalls are defined by the remaining portions of the third insulating material 186, the second insulating material 184, and the barrier material 180, as well as by the remaining portions of the conductive structure 125 and the insulating structure 130 of the layer 120 of the stacked structure 110. Opening 165 may divide the stacked structure 110 of the electronic device 100 into separate sub-blocks (e.g., first sub-block 166, second sub-block 168). For clarity and convenience, only a single (e.g., one) opening 165 is shown, but it should be understood that additional openings 165 may be included in other blocks of the stacked structure 110 of the electronic device 100 to separate additional sub-blocks from each other.

[0073] The sidewalls of at least the lower portion of the opening 165, defined by the conductive structure 125 and the insulating structure 130, may be inclined (e.g., gradually narrowing), wherein the lateral extent (e.g., width) of a portion of the opening 165 laterally adjacent to the barrier material 180 (e.g., at its opening 182) is greater than the lowermost portion of the opening 165 within the stacked structure 110. For clarity, as Figure 1CAs shown by the dashed lines, the upper boundary of region 194 (e.g., the so-called "shaded area") is defined by the main plane at the opening 182 of the barrier material 180, and the lower boundary coincides with the lowermost surface of the opening 165 and is defined by opposing lateral boundaries extending in a vertical direction (e.g., in the Z direction) substantially orthogonal to the main plane of the barrier material 180 into the underlying stacked structure 110. In other words, region 194 may exhibit a substantially orthogonal (e.g., substantially rectangular) outline, originating from the opening 182 of the barrier material 180, extending downward into the stacked structure 110, and terminating at the end of the opening 165 (e.g., the lowermost boundary of the upper layer portion 120A of layer 120).

[0074] A portion of the conductive structure 125 extending within region 194 of the upper layer portion 120A may herein be referred to as a sacrificial portion 175 of the conductive structure 125. In some embodiments, an additional portion of the conductive structure 125 adjacent to (e.g., immediately adjacent to) region 194 of the upper layer portion 120A may also be referred to as a sacrificial portion 175. In other words, portions of the conductive structure 125 within and adjacent to region 194 may be designated for removal during subsequent process operations. In some embodiments, the lateral extent of each sacrificial portion 175 may be substantially equal to that of the others. Because the sidewalls of the lower portion of the opening 165 defined by the conductive structure 125 and the insulating structure 130 may be inclined, the sacrificial portion 175 of the uppermost portion of the conductive structure 125 may extend to a greater lateral extent (e.g., beyond the contour of region 194) than the lateral extent of the sacrificial portion 175 within the lowermost portion of the conductive structure 125 within the upper layer portion 120A, as referenced Figure 1E To describe in more detail.

[0075] refer to Figure 1D The conductive structure 125 within the upper layer portion 120A of layer 120 can be recessed. Recessing the conductive structure 125 increases the width of the opening 165 in the upper layer portion 120A, thereby forming a recessed region 190 adjacent to the conductive structure 125 in the upper layer portion 120A. For example, the sacrificial portion 175 of the conductive structure within and near region 194... Figure 1CThe conductive structure 125 can be selectively removed relative to the insulating structure 130 to allow it to be recessed by a lateral distance. Because the sidewalls of the lower portion of the opening 165 defined by the conductive structure 125 and the insulating structure 130 are tilted, the recessed area 190 in the uppermost portion of the conductive structure 125 can extend to a greater lateral extent (e.g., beyond the contour of region 194) than the recessed area 190 in the lowermost portion of the conductive structure 125 within the upper layer portion 120A. In other words, each of the recessed areas 190 can extend substantially equally from the opening 165, such that the outer diameter of the uppermost portion of the recessed area 190 is greater than the outer diameter of the recessed area 190 in the lowermost portion of the conductive structure 125 within the upper layer portion 120A. Therefore, the insulating structure 130 and the conductive structure 125 widen with increasing depth from the top of the stacked structure 110. In other words, the width of the remaining portion of the insulating structure 130 and the conductive structure 125 adjacent to the laterally adjacent recessed region 190 decreases with increasing height relative to the substrate structure 115.

[0076] In some embodiments, the sacrificial portion 175 of the conductive structure 125 ( Figure 1C The conductive structure 125 is removed by exposing it to one or more etchants (e.g., wet etchants) via opening 165. The wet etchant may contain one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, or hydrogen peroxide. In some embodiments, the sacrificial portion 175 may be removed by a phosphoric acid / acetic acid / nitric acid (PAN) etching chemical reaction. However, this disclosure is not limited thereto, and the sacrificial portion 175 of the conductive structure 125 may be removed using other etchant and / or material removal processes (e.g., vapor phase removal processes, atomic layer removal processes). The recessed region 190 shortens a portion of the conductive structure 125 in the upper layer portion 120A such that the conductive structure 125 within the upper layer portion 120A and between the opening 165 and a post 105 immediately adjacent to the opening 165 is shorter (e.g., relatively smaller in width) than the conductive structure 125 in the lower layer portion 120B.

[0077] refer to Figure 1ENext, a fourth insulating material 188 can be formed (e.g., deposited) to fill (e.g., substantially fill) the recessed area 190, thereby forming an insulating extension 192 adjacent to the conductive structure 125 in the upper layer portion 120A of the adjacent layer 120, and a first insulating material 170 can be formed (e.g., deposited) to fill (e.g., substantially fill) the opening 165. The insulating extension 192 is directly vertically aligned with at least a portion of the adjacent insulating structure 130 in the upper layer portion 120A. In other words, the insulating extension 192 is vertically adjacent to the end of the insulating structure 130 in the upper layer portion 120A of the layer 120. Therefore, the width W1 of a portion of the conductive structure 125 in the upper layer portion 120A (e.g., a portion of the conductive structure 125 laterally adjacent to the insulating extension 192) is, for example, shorter than (e.g., relatively smaller than) the width W2 of at least some of the conductive structures 125 in the lower layer portion 120B. As a non-limiting example, the width W1 of the remaining portion of the upper conductive structure 125A between the opening 165 and the proximal guide post 105 can be in the range of about 5 nm to about 50 nm, and the width W2 of the lower conductive structure 125B between two adjacent guide posts 105 can be in the range of about 50 nm to about 200 nm. For example, the width W2 represents the combined width of the first insulating material 170 and the opposite portions of the recessed region 190 and the upper conductive structure 125A. In addition, the spacing between horizontally adjacent guide posts 105 can be in the range of about 50 nm to about 200 nm. The width W3 corresponds to the lateral distance by which the conductive structure 125 is recessed relative to the sidewall of the adjacent insulating structure in the insulating structure 130 facing the opening. As a non-limiting example, the recessed region 190 ( Figure 1D The width W3 of the insulating extension 192 and thus the width of the insulating extension 192 can be in the range of about 5 nm to about 50 nm. The outer diameter of the insulating extension 192 on a single layer of layer 120 is equal to twice the lateral distance of one of the insulating extensions 192 plus the width of the first insulating material 170 in the opening 165. Therefore, in embodiments where the insulating extension 192 extends to a lateral distance in the range of about 5 nm to about 50 nm, each of the insulating extensions 192 may have a width of, for example, about 10 nm to about 100 nm plus the width of the first insulating material 170 (in Figure 1E The outer diameter is shown in the range of width W4. As a non-limiting example, the width of the first insulating material 170 may be in the range of about 5 nm to about 150 nm. Since the adjacent structures (e.g., the first insulating material 170 in the post 105, the opening 165) gradually narrow, the “width” of a particular portion of the conductive structure 125 in either the upper layer portion 120A or the lower layer portion 120B of layer 120 may be its width along its uppermost surface, its width along its midline, or its width along its lowermost surface, or an average of the above.

[0078] For example, the transverse cross-sectional width (e.g., outer diameter) of the guide post 105 gradually narrows from its widest width at the top of the stacked structure 110 to its narrowest width near the base structure 115 throughout the height of the stacked structure 110. Because the sidewalls of the lower portion of the opening 165 defined by the conductive structure 125 and the insulating structure 130 are tiltable, the transverse cross-sectional width (e.g., outer diameter) of the first insulating material 170 in the opening 165 also gradually narrows from its widest width at the top of the stacked structure 110 to its narrowest width immediately above the lower layer portion 120B throughout a portion of the height of the stacked structure 110. Therefore, the transverse cross-sectional width (e.g., outer diameter) of the outer diameter of the insulating extension 192 having a width W4 also gradually narrows from its widest width at the top of the stacked structure 110 to its narrowest width immediately above the lower layer portion 120B throughout a portion of the height of the stacked structure. The width W4 of the outer diameter of the insulating extension 192 may be greater than or substantially equal to the width W5 of the opening 182 of the barrier material 180 near the top of the adjacent stacked structure 110, such that at least a portion of the fourth insulating material 188 of the insulating extension 192 is lower than at least a portion (e.g., an edge, a protrusion) of the barrier material 180 covering the stacked structure 110 (e.g., directly vertically aligned with it). In other words, the insulating extension 192 may extend to, and in some cases extend beyond, the periphery of the region 194 on the opposite side of the first insulating material 170. As a non-limiting example, the width W4 of the outer diameter of the insulating extension 192 may be in the range of about 10 nm to about 300 nm, and the width W5 of the opening 182 of the barrier material 180 may be in the range of about 10 nm to about 200 nm.

[0079] In some embodiments, at least some (e.g., each) of the conductive structures 125 in the upper layer portion 120A of layer 120 are laterally (e.g., horizontally) recessed relative to the vertically adjacent portions of the insulating structure 130. Furthermore, the conductive structures 125 in the upper layer portion 120A are laterally recessed relative to the barrier material 180 overlying the stacked structure 110. For example, a portion of the insulating extension 192 near the first insulating material 170 is vertically aligned with the opening 182 of the barrier material 180, and other portions of the insulating extension 192 away from the first insulating material 170 are vertically aligned with the barrier material 180 but not with its opening 182. Therefore, at least a portion of the insulating extension 192 extends vertically beneath the barrier material 180. Additionally, the insulating extension 192 is laterally adjacent to at least some of the conductive structures 125 (e.g., directly horizontally aligned with them). For example, the insulating extension 192 may be laterally adjacent to at least some of the upper selective gates (e.g., SGD) and the first insulating material 170 in the opening 165 (e.g., SGD isolation gap) (e.g., right in the middle of them).

[0080] Continue to refer to Figure 1E A fourth insulating material 188 may be formed in the recessed region 190, substantially completely filling the recessed region 190 to form an insulating extension 192, and a first insulating material 170 may be formed in the opening 165, substantially completely filling the opening 165. The fourth insulating material 188 and the first insulating material 170 may be formed in the recessed region 190 and the opening 165 respectively using conventional techniques (e.g., PVD process, CVD process, ALD process, spin coating process). In some embodiments, at least one (e.g., both) of the fourth insulating material 188 and the first insulating material 170 is a highly conformal ALD oxide, such as ALDSiO. x Excess first insulating material 170 can be removed using conventional techniques, such as chemimechanical planarization, such that the upper surface of the first insulating material 170 in the opening 165 is substantially coplanar with the upper surface of the third insulating material 186. In some embodiments, the cross-section of the opening 165 exhibits a U-shape or a V-shape, wherein the sidewalls are initially defined by the inclined surfaces of the conductive structure 125 and the insulating structure 130. However, the opening 165 may be defined by the substantially vertical sidewalls of the conductive structure 125 and the insulating structure 130 within the upper layer portion 120A, provided that the first insulating material 170 can be formed therein and no voids are formed in the fourth insulating material 188 and / or the first insulating material 170 (e.g., along the boundary therebetween).

[0081] In some embodiments, a fourth insulating material 188 is formed prior to the formation of a first insulating material 170. For example, the fourth insulating material 188 is conformally formed within a recess 190 to form an insulating extension 192 laterally adjacent to the remainder of the conductive structure 125. Subsequently, the first insulating material 170 may be formed in the opening 165. In other embodiments, the first insulating material 170 is formed during the formation of the fourth insulating material 188 in the insulating extension 192. For example, the first insulating material 170 and the fourth insulating material 188 may be formed substantially simultaneously to simplify the manufacturing process. In other words, the fourth insulating material 188 and the first insulating material 170 may be deposited to substantially fill the recess 190 and the opening 165 in a single deposition action. In some such embodiments, the interface between the fourth insulating material 188 and the first insulating material 170 may be invisible.

[0082] In an additional embodiment, more than two (e.g., three or more) deposition operations may be used during the formation of the fourth insulating material 188 and the first insulating material 170. For example, the fourth insulating material 188 may be formed first within the recessed region 190, and then the first insulating material 170 may be formed within the lower portion of the opening 165 laterally adjacent to the upper layer portion 120A. Subsequently, another portion of the first insulating material 170 may be formed in the upper portion of the opening 165 laterally adjacent to the third insulating material 186, the second insulating material 184, and the barrier material 180. However, this disclosure is not limited thereto, and additional deposition operations may be considered. For example, different portions of the fourth insulating material 188 and / or the first insulating material 170 (e.g., at different altitudes) may be formed by multiple deposition operations to form an insulating extension 192 laterally separated by the first insulating material 170.

[0083] refer to Figure 1F The contact structure 195 is formed in an additional opening (not shown) extending through each of the third insulating material 186, the second insulating material 184, and the barrier material 180. This additional opening can be formed using conventional techniques. For example, additional portions of the third insulating material 186 and the second insulating material 184 can be removed by a first etching action, and the underlying portion of the barrier material 180 can be removed by a second etching action to form the additional opening and expose the upper surface of the contact plug 160 of the guide post 105. However, this disclosure is not limited thereto, and the additional opening can be formed using a single material removal action. The contact structure 195 can be formed within the additional opening using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. The contact structure 195 can be formed between the contact plug 160 and other conductive elements formed on the contact structure 195. In some embodiments, the contact structure 195 is formed immediately adjacent to (e.g., directly on) the contact plug 160. In other embodiments, additional contact structures (not shown) may be formed between contact structure 195 and contact plug 160.

[0084] The contact structure 195 may be configured to be positioned above (e.g., directly vertically aligned with) the contact plug 160 of the guide post 105, such that at least a portion of the outer surfaces of the contact structure 195 and the contact plug 160 are substantially aligned with each other, such as Figure 1F As shown in the diagram. In other words, the outer surfaces of at least some of the contact structures 195 and contact plugs 160 may be substantially flush with each other along at least one side. As discussed above, the contact structure 195 may be laterally offset (e.g., eccentrically positioned or staggered) to facilitate electrical connection with the contact plugs 160.

[0085] However, even if the contact structures 195 are misaligned, bridging (e.g., shorting, electrical connection) between adjacent portions of the conductive structures 125 is unlikely to occur in the electronic device 100 according to embodiments of the present disclosure because of the presence of the insulating extension 192. During misalignment, one or more of the contact structures 195 may not be directly vertically aligned with the underlying contact plug 160 of the guide post 105. For example, as by Figure 1F As shown in the third contact structure 195 on the left, during the formation of the contact structure 195, the contact structure 195 may overlap with at least a portion of the first insulating material 170. Figure 1F The third contact structure 195 on the left side shows a contact structure 195 that is extremely misaligned with the unit membrane 150 and contact plug 160 of the underlying guide post 105. However, embodiments of this disclosure can also be used with electronic devices 100 that exhibit a contact structure 195 with a lower degree of misalignment. Figure 1F In the embodiments, the insulating extension 192 between the first insulating material 170 and the conductive structure 125 can significantly reduce (e.g., substantially prevent, substantially eliminate) the physical and / or electrical connection between the contact structure 195 and adjacent portions of the conductive structure 125 within a designated area (e.g., within and near region 194). By forming the insulating extension 192 between the first insulating material 170 and the conductive structure 125 in the upper layer portion 120A, the insulating extension 192 can separate (e.g., electrically isolate) the remaining portion 196 of the third contact structure 195 on the left side from at least some of the conductive structures 125 within the upper layer portion 120A, such as... Figure 1F As shown in the image.

[0086] For example, the presence of an insulating extension 192 (e.g., an additional area of ​​insulating material) laterally adjacent to the conductive structure 125 can significantly reduce (e.g., substantially prevent) bridging (e.g., electrical connection) between two or more portions of the conductive structure 125 when the remaining portion 196 of the contact structure 195 extends below the barrier material 180. In other words, when the contact structure 195 (e.g., a misaligned contact structure 195) overlaps with the first insulating material 170 in the opening 165 below the barrier material 180 (e.g., within the so-called “shaded area” of region 194), the insulating extension 192 can significantly reduce (e.g., substantially cut off) the electrical connection between adjacent portions of the conductive structure 125. Thus, the contact structure 195 can be formed above the corresponding contact plug 160 of the post 105, while no electrical connection is provided between adjacent portions of the conductive structure 125 via the remaining portion 196 of the contact structure 195. Therefore, the first insulating material 170 is surrounded by the barrier material 180, the second insulating material 184, and the third insulating material 186 above the stacked structure 110. The first insulating material 170 is surrounded by the insulating extension 192 within the layer 120 and the insulating structure 130 including the upper insulating structure 155. In other words, the first insulating material 170 directly contacts the fourth insulating material 188 of the insulating extension 192, but does not directly contact the conductive structure 125 within the upper layer portion 120A.

[0087] The first insulating material 170 is present in the central region of each block of the electronic device 100 and serves to electrically isolate one sub-block (e.g., a memory sub-block) of the electronic device 100 from another (e.g., an adjacent) sub-block of the electronic device 100. The presence of a fourth insulating material 188 laterally adjacent to the first insulating material 170 and laterally adjacent to the conductive structure 125 in the recessed region 190 alters the configuration of the stacked structure 110 of the electronic device 100 because the fourth insulating material 188 of the insulating extension 192 and the first insulating material 170 electrically isolate adjacent portions of the conductive structure 125 when the misaligned contact structure 195 overlaps with the first insulating material 170 in the opening 165. Therefore, adjacent portions of the conductive structure 125 are further physically and / or electrically isolated from each other by the insulating extension 192.

[0088] In contrast, a portion of the conductive structure 125 in a conventional electronic device is exposed below the opening 182 of the barrier material 180 (e.g., within region 194) during a corresponding stage of the manufacturing process, and may be susceptible to electrical contact (e.g., bridging) with the remaining portion 196 of the contact structure 195 during subsequent process operations. As shown in FIG1G, FIG1G is in the context of... Figure 1FA cross-sectional view of a conventional electronic device 10 at a similar manufacturing stage shows that there is no insulating extension 192 as described in the embodiments of this disclosure between the first insulating material 170 and the conductive structure 125 in the opening 165. Figure 1F The insulating structure of the conventional electronic device 10 is different. In contrast, the stacked structure 110 of the conventional electronic device 10 is divided into sub-blocks by a first insulating material 170, without forming the recessed area 190 of the conductive structure 125. Figure 1F ), and does not form an insulating extension 192 in such a recessed area ( Figure 1F ).

[0089] For example, compared to the insulating extension 192 between the first insulating material 170 and the conductive structure 125 in the upper layer portion 120A ( Figure 1F In conventional electronic devices, a contact (e.g., physical contact, electrical contact) may be formed between the remaining portion 196 of the contact structure 195 and the conductive structure 125, creating a contact point 198 therebetween. In conventional electronic devices, an SGD isolation opening (e.g., opening 165) may be formed after the formation of alternating layers of the insulating structure 130 and the conductive structure 125 (e.g., after a gate replacement process). Because the first insulating material 170 of a conventional electronic device is formed within opening 165 prior to the formation of the contact structure 195, at least a portion (e.g., the remaining portion 196) of the misaligned conductive material of the contact structure 195 may extend through opening 182 of the barrier material 180 and into or near the exposed portion of the conductive structure 125 within or near the contact area 194 during the formation of the contact structure 195. In other words, if the material composition of the underlying material (e.g., oxide material) within the stacked structure 110 is insufficient to provide a barrier for the formation of the remaining portion 196 of the contact structure 195 beneath the barrier material 180, then bridging may occur between the remaining portion 196 of the contact structure 195 and at least some of the conductive structures 125 in the upper layer portion 120A, resulting in unintended connections between adjacent conductive structures 125, which could short-circuit the subsequently formed electronic device during use and operation.

[0090] Therefore, exposure of conductive structures 125 in or near region 194 of conventional electronic device 10 may lead to bridging and / or increased contact resistance in conventional electronic device. Furthermore, the first insulating material 170 in conventional device may have increased width to provide sufficient isolation between adjacent contact plugs 160 and adjacent posts 105 in upper layer portion 120A, which may require increasing the area within the stacked structure of conventional electronic device (e.g., increased etch profile requirements for SGD isolation etching).

[0091] The method of this disclosure significantly reduces the occurrence of such unintended connections between adjacent conductive structures 125 due to the presence of insulating extensions 192 between the first insulating material 170 and the conductive structures 125 in the upper layer portion 120A. The formation of the insulating extensions 192 according to embodiments of this disclosure facilitates a reduction in the etch profile requirements for upper selected gate isolation provided by the first insulating material 170, and also facilitates a reduction in contact resistance within the upper layer portion 120A during use and operation. Furthermore, by laterally recessing the conductive structures 125 and forming the insulating extensions 192, the distance between the conductive structures 125 can be increased relative to the corresponding distance between conductive structures 125 in a conventional electronic device 10. The increased distance between the conductive structures 125 according to embodiments of this disclosure facilitates operation of the circuit system at significantly increased voltages while significantly reducing the risk of damage to the insulating material, without increasing the amount of area occupied by the first insulating material 170. Therefore, the formation of the insulating extension 192 can reduce the various processing complexities associated with the formation of conventional contact structures and associated insulating materials of electronic devices (e.g., the complexity associated with correctly sizing and aligning various contact openings and structures).

[0092] Therefore, a method for forming an electronic device is disclosed. The method includes: forming a stacked structure comprising vertically alternating insulating and conductive structures arranged in layers; forming a barrier material vertically covering the stacked structure and extending horizontally across the stacked structure; and forming at least one opening through the barrier material and into an upper layer portion of the stacked structure. The method includes recessing a sacrificial portion of the conductive structure in the upper layer portion adjacent to the at least one opening, and forming an insulating material in the recessed area of ​​the conductive structure and the at least one opening. The recessed area of ​​the conductive structure is substantially directly vertically aligned with the barrier material.

[0093] Figure 2 This is a partially sectional perspective view showing a portion of an electronic device 200 (e.g., a microelectronic device, a memory device such as a 3D NAND flash memory device) including an electronic device structure 201 (e.g., a microelectronic device structure). The electronic device 200 may be substantially similar to the previously referenced... Figures 1A to 1F The described electronic device 100. (e.g.) Figure 2 As shown, the electronic device structure 201 of the electronic device 200 may include a stepped structure 220, which defines a step structure 220 for connecting the access line 206 to the conductive structure 205 (e.g., corresponding to the conductive structure 125). Figure 1AThe contact area of ​​the electronic device structure 201 may include a vertical string 207 of memory cells 203 coupled in series with each other. The vertical string 207 may extend vertically (e.g., in the Z direction) orthogonal to conductive lines and conductive structures 205, such as data lines 202, source layers 204 (e.g., containing source structures 135). Figure 1A Access line 206, corresponding to the upper conductive structure 125A ( Figure 1E The first selection gate 208 (e.g., upper selection gate, drain selection gate (SGD)) corresponds to the lower conductive structure 125B. Figure 1E The selection line 209 and the second selection gate 210 (e.g., lower selection gate, source selection gate (SGS)). The selection gate 208 may be horizontally (e.g., in the Y direction) divided into a plurality of blocks 232 that are horizontally (e.g., in the Y direction) separated from each other by slots 230.

[0094] Vertical conductive contacts 211 can electrically couple components to each other, as shown. For example, select line 209 can be electrically coupled to first select gate 208, and access line 206 can be electrically coupled to conductive structure 205. Electronic device 200 may also include a control unit 212 positioned under a memory array, which may include at least one of a string driver circuitry, a gate, a circuitry for selecting gates, a circuitry for selecting conductive lines (e.g., data line 202, access line 206), a circuitry for amplifying signals, and a circuitry for sensing signals. For example, control unit 212 may be electrically coupled to data line 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, control unit 212 includes complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, control unit 212 may be characterized as having an "under-array CMOS" ("CuA") configuration.

[0095] The first select gate 208 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a first end (e.g., the upper end) of a corresponding first group of vertical strings 207 of memory cells 203. The second select gate 210 may be formed in a substantially flat configuration and may be coupled to a second opposite end (e.g., the lower end) of the vertical strings 207 of memory cells 203.

[0096] Data lines 202 (e.g., digital lines, bit lines) may extend horizontally in a second direction (e.g., in the Y direction), the second direction being at an angle (e.g., perpendicular to the first direction) relative to the first direction in which the first select gate 208 extends. Each data line 202 may be coupled at a first end (e.g., the upper end) of a vertical string 207 of a respective group to a respective group of vertical strings 207 extending in the second direction (e.g., the Y direction). Additional individual groups of vertical strings 207 extending in the first direction (e.g., the X direction) and coupled to each first select gate 208 may share a specific vertical string 207 with the individual group of vertical strings 207 coupled to a single data line 202. Thus, a single vertical string 207 of memory cells 203 at the intersection of a single first select gate 208 and a single data line 202 can be selected. Therefore, the first select gate 208 can be used to select memory cells 203 in the vertical string 207 of memory cells 203.

[0097] Conductive structures 205 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive structures 205 may be vertically stacked such that each conductive structure 205 is coupled to at least some of the vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stacked structure containing the conductive structures 205. The conductive structures 205 may be coupled to or may form the control gate of the memory cells 203.

[0098] The first selection gate 208 and the second selection gate 210 can be used to select a vertical string 207 of memory cells 203 inserted between the data line 202 and the source layer 204. Thus, a single memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the first selection gate 208, the second selection gate 210, and the conductive structure 205 appropriately coupled to a particular memory cell 203.

[0099] The stepped structure 220 can be configured to provide an electrical connection between the access line 206 and the conductive structure 205 via vertical conductive contacts 211. In other words, a single conductive structure 205 can be selected via an access line 206 electrically connected to a corresponding vertical conductive contact 211, which is electrically connected to the conductive structure 205.

[0100] Data line 202 can be connected via conductive contact structure 234 (e.g., in post 105). Figure 1A The contact structure 195 formed above is electrically coupled to the vertical string 207.

[0101] In embodiments of the electronic system disclosed herein, electronic devices (e.g., electronic devices 100, 200) and electronic device structures (e.g., electronic device structure 201) according to embodiments of the present disclosure may be used, which include an insulating extension 192 laterally adjacent to the conductive structure 125 in the upper layer portion 120A of the first insulating material 170 and layer 120. For example, Figure 3 This is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or Tablet computers, e-books, navigation devices, etc. Electronic system 303 includes at least one memory device 305. Memory device 305 may include, for example, electronic devices (e.g., previously referenced...). Figures 1A to 1F and Figure 2 Embodiments of the described electronic devices 100, 200 include an insulating extension 192 laterally adjacent to a first insulating material 170 and a conductive structure 125.

[0102] The electronic system 303 may further include at least one electronic signal processor device 307 (generally referred to as a "microprocessor"). The electronic signal processor device 307 may optionally include electronic devices or electronic device structures (e.g., previously referenced). Figures 1A to 1F and Figure 2 Embodiments of electronic devices 100, 200, or one or more of electronic device structures 201 described herein. Electronic system 303 may further include one or more input devices 309 for a user to input information into electronic system 303, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 309 and output device 311 may include a single touchscreen device that can simultaneously input information into electronic system 303 and output visual information to the user. Input device 309 and output device 311 may be electrically connected to one or more of memory device 305 and electronic signal processor device 307.

[0103] refer to Figure 4The present invention describes a processor-based system 400. The processor-based system 400 may include various electronic devices and electronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of electronic devices 100, 200, or electronic device structures 201). The processor-based system 400 may be any of various types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 400 may include one or more processors 402, such as microprocessors, for controlling system functions and request processing within the processor-based system 400. The processors 402 and other sub-components of the processor-based system 400 may include electronic devices and electronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of electronic devices 100, 200, or electronic device structures 201).

[0104] The processor-based system 400 may include a power source 404 operatively connected to the processor 402. For example, if the processor-based system 400 is a portable system, the power source 404 may include one or more of the following: a fuel cell, a power scavenging device, a permanent battery, a replaceable battery, and a rechargeable battery. The power source 404 may also include an AC adapter; thus, the processor-based system 400 can be plugged into, for example, a wall socket. The power source 404 may also include a DC adapter, allowing the processor-based system 400 to be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0105] Depending on the functions performed by the processor-based system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be coupled to the processor 402. The RF subsystem / baseband processor 410 may include antennas coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 412 may also be coupled to the processor 402. The communication port 412 can be used to couple to one or more peripheral devices 414, such as a modem, printer, computer, scanner or camera, or to a network, such as a local area network, remote area network, intranet or the Internet.

[0106] Processor 402 can control processor-based system 400 by implementing software programs stored in memory. The software programs may include, for example, operating systems, database software, drafting software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 402 to store various programs and facilitate their execution. For example, processor 402 may be coupled to system memory 416, which may include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), particle orbital memory, and other known memory types. System memory 416 may include volatile memory, non-volatile memory, or combinations thereof. System memory 416 is typically large enough to store dynamically loaded applications and data. In some embodiments, system memory 416 may include semiconductor devices, such as the electronic devices and electronic device structures described above (e.g., electronic devices 100, 200, or electronic device structure 201), or combinations thereof.

[0107] Processor 402 may also be coupled to non-volatile memory 418, which does not mean that system memory 416 must be volatile. Non-volatile memory 418 may include one or more of the following: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 416. The size of non-volatile memory 418 is typically chosen to be just large enough to store any required operating system, applications, and fixed data. In addition, non-volatile memory 418 may include mass storage, such as disk drive memory, such as a hybrid drive containing resistive memory or other types of non-volatile solid-state memory. Non-volatile memory 418 may include electronic devices, such as the electronic devices and microelectronic device structures described above (e.g., electronic devices 100, 200, or electronic device structure 201), or combinations thereof.

[0108] Therefore, a system is disclosed comprising an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device. The memory device is operatively coupled to the processor device and includes at least one microelectronic device comprising a stacked structure including alternating layers of insulating and conductive structures, a central insulating material between sub-blocks of the stacked structure, and an insulating extension laterally extending from the central insulating material. The insulating extension laterally adjacent to the conductive structure of an upper selected gate of the stacked structure.

[0109] Compared to conventional structures, conventional devices, and conventional systems, the electronic devices and systems of this disclosure advantageously facilitate one or more of the following: increased simplicity, greater package density, and increased component miniaturization. The methods of this disclosure facilitate the formation of devices (e.g., apparatus, microelectronic devices, memory devices) and systems (e.g., electronic systems) having one or more of the following: improved performance, reliability, and durability; lower cost; increased yield; increased component miniaturization; improved pattern quality; and greater package density compared to conventional devices (e.g., conventional apparatus, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems).

[0110] The embodiments of this disclosure may be further characterized in the manner described below, but not limited to the manner described below.

[0111] Example 1: An electronic device comprising: a stacked structure including vertically alternating insulating and conductive structures arranged in layers; a post extending vertically through the stacked structure; a barrier material covering the stacked structure; a first insulating material extending through the barrier material and into an upper layer portion of the stacked structure; and a second insulating material laterally adjacent to the first insulating material and laterally adjacent to at least some of the conductive structures in the upper layer portion of the stacked structure, wherein at least a portion of the second insulating material is vertically aligned with the barrier material.

[0112] Example 2: The electronic device according to Example 1 further includes a contact plug in the upper portion of the guide post and a contact structure covering the stacked structure, wherein the contact structure directly and physically contacts the contact plug through an opening in the barrier material.

[0113] Example 3: An electronic device according to Example 1 or Example 2, wherein the first insulating material comprises a substantially continuous material extending between adjacent sub-blocks of the stacked structure.

[0114] Example 4: An electronic device according to any one of Examples 1 to 3, wherein the conductive structure in the upper layer portion of the stacked structure is configured as a drain-side selected gate.

[0115] Example 5: An electronic device according to any one of Examples 1 to 4, wherein the width of the first insulating material gradually narrows from the widest width at the top of the stacked structure to the narrowest width at the bottom of the upper layer portion of the stacked structure.

[0116] Example 6: An electronic device according to any one of Examples 1 to 5, wherein the second insulating material is directly vertically aligned with at least a portion of an adjacent insulating structure in the upper layer portion of the stacked structure.

[0117] Example 7: An electronic device according to any one of Examples 1 to 6, wherein the conductive structure in the upper layer portion is recessed relative to the insulating structure.

[0118] Example 8: An electronic device according to any one of Examples 1 to 7, wherein the first insulating material and the second insulating material are in direct physical contact.

[0119] Example 9: An electronic device according to any one of Examples 1 to 8, wherein the lateral extent of the second insulating material is greater than the lateral extent of the central opening of the barrier material.

[0120] Example 10: An electronic device comprising: a post disposed in a sub-block of a stacked structure; and a layer comprising conductive structures separated by an insulating structure within the stacked structure, wherein at least some of the conductive structures in the upper layer portion of the stacked structure are laterally adjacent to the periphery of a single sub-block of the stacked structure, wherein a portion of the outer diameter of the additional insulating material at the height of the uppermost conductive structure in the upper layer portion of the stacked structure is larger than the outer diameter of another portion of the additional insulating material at the height of the lowermost conductive structure in the upper layer portion of the stacked structure.

[0121] Example 11: The electronic device according to Example 10, wherein the additional insulating material extends laterally to define an insulating extension, the insulating extension being vertically adjacent to the end of the insulating structure in the upper layer portion of the layer, the insulating extension electrically isolating the conductive structures from each other.

[0122] Example 12: The electronic device according to Example 11, wherein at least some of the conductive structures in the upper layer portion of the stacked structure are laterally recessed relative to the insulating structures in the layers of the stacked structure.

[0123] Example 13: An electronic device according to any one of Examples 10 to 12, further comprising a barrier material covering the stacked structure, wherein an additional insulating material extends away from the periphery of the individual sub-block, and wherein at least a portion of the additional insulating material is directly vertically aligned with the barrier material.

[0124] Example 14: The electronic device according to Example 13, wherein the additional insulating material comprises an oxide material and the barrier material comprises a nitride material.

[0125] Example 15: An electronic device according to any one of Examples 10 to 14, wherein a portion of the conductive structure in the upper layer of the stacked structure is relatively shorter in the horizontal direction than a portion of the conductive structure in the lower layer of the stacked structure.

[0126] Example 16: A method of forming an electronic device, comprising: forming a stacked structure including vertically alternating insulating and conductive structures arranged in layers; forming a barrier material vertically covering the stacked structure and extending horizontally across the stacked structure; forming at least one opening through the barrier material and into an upper layer portion of the stacked structure; recessing a sacrificial portion of the conductive structure in the upper layer portion adjacent to the at least one opening, the recessed area of ​​the conductive structure being directly vertically aligned with the barrier material; and forming an insulating material in the recessed area of ​​the conductive structure and the at least one opening.

[0127] Example 17: According to the method of Example 16, wherein recessing the sacrificial portion of the conductive structure includes recessing the conductive structure in the upper layer portion relative to the opening-facing sidewall of the adjacent insulating structure in the insulating structure.

[0128] Example 18: The method according to Example 16 or Example 17, wherein recessing the sacrificial portion of the conductive structure includes recessing the conductive structure in the upper layer portion, but not recessing the additional conductive structure in the lower layer portion of the stacked structure.

[0129] Example 19: The method according to any one of Examples 16 to 18, wherein forming the insulating material includes conformally forming the insulating material in the recessed region of the conductive structure and then forming the insulating material in the at least one opening.

[0130] Example 20: The method according to any of Examples 16 to 18, wherein forming the insulating material includes substantially completely filling the recessed area and the at least one opening using a single continuous ALD process or a single continuous CVD process.

[0131] Example 21: The method according to any of Examples 16 to 20, wherein forming the insulating material in the recessed area includes electrically isolating the conductive structures from each other in a region vertically subordinate to the barrier material and close to the at least one opening.

[0132] Example 22: A system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: a stacked structure including alternating layers of insulating and conductive structures; a central insulating material between sub-blocks of the stacked structure; and an insulating extension laterally extending from the central insulating material, the insulating extension laterally adjacent to the conductive structure of an upper selected gate of the stacked structure.

[0133] Example 23: The system according to Example 22 further includes a string of memory cells extending vertically through the stacked structure.

[0134] Example 24: The system according to Example 22 or Example 23, wherein the insulating extension directly contacts each of the central insulating material and the conductive material of the conductive structure.

[0135] Example 25: A system according to any one of Examples 22 to 24, wherein the memory device includes a 3D NAND flash memory device.

[0136] Although certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure, such as those claimed below, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. An electronic device comprising: A stacked structure comprising an insulating structure and a conductive structure arranged vertically alternately in an upper layer portion and a lower layer portion of the stacked structure, wherein the conductive structure in the upper layer portion is recessed relative to the insulating structure and defines a recessed area between the insulating structures in the upper layer portion. Guide posts, which extend vertically through the stacked structure; A barrier material is applied over the stacked structure; A first insulating material extends through the barrier material and into the upper layer portion of the stacked structure adjacent to the recessed area; as well as A second insulating material extends laterally outward from the first insulating material into the recessed area, and at least a portion of the second insulating material is vertically aligned with the barrier material.

2. The electronic device of claim 1, further comprising a contact plug in the upper portion of the guide post and a contact structure covering the stacked structure, wherein the contact structure directly physically contacts the contact plug through an opening in the barrier material.

3. The electronic device of claim 1, wherein the first insulating material comprises a substantially continuous material extending between adjacent sub-blocks of the stacked structure.

4. The electronic device according to any one of claims 1 to 3, wherein the conductive structure in the upper layer portion of the stacked structure is configured as a drain-side selected gate.

5. The electronic device according to any one of claims 1 to 3, wherein the width of the first insulating material gradually narrows from the widest width at the top of the stacked structure to the narrowest width at the bottom of the upper layer portion of the stacked structure.

6. The electronic device according to any one of claims 1 to 3, wherein the second insulating material is directly vertically aligned with at least a portion of an adjacent insulating structure in the upper layer portion of the stacked structure.

7. The electronic device according to any one of claims 1 to 3, wherein the first insulating material is in direct physical contact with the second insulating material.

8. The electronic device according to any one of claims 1 to 3, wherein the lateral extent of the second insulating material is greater than the lateral extent of the central opening of the barrier material.

9. An electronic device comprising: Guide pillars, which are arranged in the sub-blocks of the stacked structure; as well as A layer comprising conductive structures separated by insulating structures within the stacked structure, additional insulating material in the upper layer portion of the stacked structure being relatively shorter than the conductive structures in the lower layer portion of the stacked structure and laterally adjacent to the periphery of a single sub-block of the stacked structure, wherein a portion of the additional insulating material at the height of the uppermost conductive structure in the upper layer portion of the stacked structure has an outer diameter greater than the outer diameter of another portion of the additional insulating material at the height of the lowermost conductive structure in the upper layer portion of the stacked structure.

10. The electronic device of claim 9, wherein the additional insulating material extends laterally to define an insulating extension, the insulating extension being vertically adjacent to the end of the insulating structure in the upper layer portion of the layer, the insulating extension electrically isolating the conductive structures from each other.

11. The electronic device of claim 10, wherein at least some of the conductive structures in the upper layer portion of the stacked structure are laterally recessed relative to the insulating structures in the layers of the stacked structure.

12. The electronic device according to any one of claims 9 to 11, further comprising a barrier material overlying the stacked structure, the additional insulating material extending away from the periphery of the individual sub-block, wherein at least a portion of the additional insulating material is directly vertically aligned with the barrier material.

13. The electronic device of claim 12, wherein the additional insulating material comprises an oxide material and the barrier material comprises a nitride material.

14. A method of forming an electronic device, comprising: A stacked structure is formed, the stacked structure comprising vertically alternating insulating and conductive structures arranged in layers, the layers comprising an upper layer portion and a lower layer portion; A barrier material is formed, which is vertically overlaid on the stacked structure and extends horizontally across the stacked structure; At least one opening is formed, the at least one opening passing through the barrier material and entering the upper layer portion of the stacked structure; The sacrificial portion of the conductive structure in the upper layer portion adjacent to the at least one opening is recessed to form a recessed area that is directly vertically aligned with the barrier material; as well as An insulating material is formed in the recessed area and the at least one opening of the conductive structure.

15. The method of claim 14, wherein recessing the sacrificial portion of the conductive structure comprises recessing the conductive structure in the upper layer portion relative to the opening-facing sidewall of an adjacent insulating structure in the insulating structure.

16. The method of claim 14, wherein recessing the sacrificial portion of the conductive structure includes recessing the conductive structure in the upper layer portion but not recessing any additional conductive structure in the lower layer portion of the stacked structure.

17. The method according to any one of claims 14 to 16, wherein forming the insulating material comprises conformally forming the insulating material in the recessed region of the conductive structure and then forming the insulating material in the at least one opening.

18. The method according to any one of claims 14 to 16, wherein forming the insulating material comprises substantially completely filling the recessed area and the at least one opening using a single continuous ALD process or a single continuous CVD process.

19. The method according to any one of claims 14 to 16, wherein forming the insulating material in the recessed area includes electrically isolating the conductive structures from each other in a region vertically subordinate to the barrier material and adjacent to the at least one opening.

20. A system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: A stacked structure comprising alternating layers of conductive and insulating structures; A central insulating material that extends between the sub-blocks of the stacked structure, through the upper layer portion of the layer to the lower layer portion of the layer, and does not extend through the lower layer portion of the layer; and An insulating extension extending laterally from the central insulating material to a recessed region, the recessed region being laterally adjacent to the conductive structure of the upper select gate of the stacked structure.

21. The system of claim 20, further comprising a string of memory cells extending vertically through the stacked structure.

22. The system of claim 20 or claim 21, wherein the insulating extension directly contacts each of the central insulating material and the conductive material of the conductive structure.

23. The system of claim 20 or claim 21, wherein the memory device comprises a 3D NAND flash memory device.

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