A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a stack layer and a stop layer located on the stack layer, and the stop layer has a first surface away from the stack layer. The semiconductor device further comprises a channel structure penetrating through the stop layer and the stack layer, and a common source layer located on the first surface of the stop layer. The channel structure comprises a channel layer extending along a first direction and a storage layer surrounding the channel layer, and the channel layer has a channel layer external part extending out of the stop layer and not covered by the storage layer, and the common source layer is connected with the channel layer external part. The stop layer serves as an etching stop layer in a process of removing the storage layer of the channel structure, can well automatically control the etching process of the storage layer, can increase the distance from a bottom select gate in the stack layer to the etching stop layer, and further increase the anti-breakdown voltage of the bottom select gate. In addition, the stop layer does not need to be removed and is reserved in the semiconductor device, so that the process can be simplified and the cost can be reduced.

Description

Technical Field

[0001] This invention relates generally to electronic devices, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, and mobile communications, mobile devices, and cloud storage, the demand for memory capacity has exploded. Compared with other non-volatile memories, NAND memory has the characteristics of high integration, low power consumption, fast programming and erasing speed, high reliability, and low cost. NAND memory has gradually become the mainstream semiconductor memory. NAND Flash Memory, as the current mainstream non-volatile memory, has received widespread attention. NAND flash memory technology will remain one of the most important storage technologies for the next few decades.

[0003] Traditional 2D NAND flash memory has reached the limit of road map. Based on this, in order to seek new breakthroughs, 3D NAND, which develops in the vertical direction, has emerged. How to increase the storage capacity per unit area of ​​3D NAND Flash is a problem that needs to be solved. The current approach is to increase the number of effective storage layers and insulating layers in the vertical direction while keeping the thickness of each insulating layer and storage layer unchanged.

[0004] However, the process of connecting the channel layer and the common source electrode is difficult and hard to control. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method, which aims to better control the etching process of the storage layer of the semiconductor device.

[0006] In one aspect, the present invention provides a semiconductor device, comprising:

[0007] Stacked layers;

[0008] A stop layer located on the stacked layers, the stop layer having a first surface remote from the stacked layers;

[0009] A channel structure extending through the stop layer and the stacked layer in a first direction, the channel structure including a channel layer and a storage layer surrounding the channel layer, the channel layer having a channel layer outer portion extending out of the stop layer and not covered by the storage layer;

[0010] A common source electrode layer is located on the first surface of the stop layer, and the common source electrode layer is connected to the outer portion of the channel layer.

[0011] More preferably, the material of the stop layer is monocrystalline silicon.

[0012] More preferably, the channel layer has a channel layer sidewall extending along the first direction, a first end near the stop layer, and a second end away from the stop layer; the outer portion of the channel layer is the first end of the channel layer and the portion of the channel layer sidewall connected to the first end.

[0013] More preferably, the storage layer has a third end near the stop layer and a fourth end away from the stop layer, and the first surface of the stop layer is flush with the third end of the storage layer.

[0014] More preferably, the channel layer has a channel layer sidewall extending along the first direction, and the storage layer has a storage layer sidewall extending along the first direction.

[0015] The storage layer sidewall has an opening filled by the common source layer to expose the outer portion of the channel layer, the outer portion of the channel layer being a portion of the channel layer sidewall, and the side of the common source layer being connected to the outer portion of the channel layer.

[0016] More preferably, the semiconductor device further includes:

[0017] A gate wire slot structure that penetrates the stop layer and the stacked layer along the first direction;

[0018] An oxide layer located between the gate line slot structure and the stop layer.

[0019] More preferably, the semiconductor device further includes:

[0020] An insulating layer is located around the stacked layers, and the stop layer is also located between the insulating layer and the common source layer;

[0021] A through-contact that penetrates the stop layer and the insulating layer along the first direction.

[0022] More preferably, the semiconductor device further includes:

[0023] The peripheral circuit chip is bonded to the stacked layer and the insulating layer on the side away from the stop layer;

[0024] The peripheral circuit chip has a first bonding contact, and the through contact has a second bonding contact at the end away from the stop layer, wherein the first bonding contact is bonded to the second bonding contact.

[0025] More preferably, the semiconductor device further includes:

[0026] An interconnect layer covering the common source layer, wherein the through contact is connected to the interconnect layer via a conductive contact at one end near the stop layer.

[0027] More preferably, the stacked layer includes a memory region stacked layer and a stepped structure located around the memory region stacked layer, the stacked layer including an interlayer insulating layer and a gate layer alternately stacked along the first direction, the insulating layer covering the stepped structure and the stop layer; the semiconductor device further includes:

[0028] A word line contact extends through the insulating layer along the first direction, and the word line contact is connected to each of the gate layers.

[0029] On the other hand, the present invention provides a method for fabricating a semiconductor device, comprising:

[0030] Provide a first substrate;

[0031] A stop layer is formed on the first substrate;

[0032] A stacked structure is formed on the stop layer, the stop layer having a first surface remote from the stacked structure;

[0033] A channel structure is formed that extends through the stacked structure and the stop layer in a first direction, the channel structure including a channel layer extending in the first direction and a storage layer surrounding the channel layer;

[0034] Forming a channel layer outer portion that extends beyond the stop layer and is not covered by the storage layer;

[0035] A common source electrode layer is formed on the first surface of the stop layer, and the common source electrode layer is connected to the outer portion of the channel layer. More preferably, the material of the stop layer is monocrystalline silicon.

[0036] More preferably, the step of forming a stop layer on the first substrate includes:

[0037] A second substrate is formed, the second substrate comprising a substrate, an oxide layer on the substrate, and a single-crystal silicon layer on the oxide layer;

[0038] The single-crystal silicon layer of the second substrate is bonded to the first substrate;

[0039] The substrate and the oxide layer in the second substrate are removed to form the single-crystal silicon layer on the first substrate as the stop layer.

[0040] More preferably, the step of forming a stop layer on the first substrate includes:

[0041] An oxide layer, a polycrystalline silicon layer, and a conductive layer are sequentially formed on the first substrate;

[0042] The conductive layer is heated to induce the polycrystalline silicon layer to transform into a monocrystalline silicon layer as the stop layer.

[0043] More preferably, the step of forming the outer portion of the channel layer extending beyond the stop layer and not covered by the storage layer includes:

[0044] A sacrificial layer is formed between the first substrate and the stop layer, and the channel structure also extends through a portion of the sacrificial layer;

[0045] After the channel structure is formed, the sacrificial layer is removed to expose a portion of the storage layer of the channel structure;

[0046] Remove the exposed storage layer to form the outer portion of the channel layer.

[0047] More preferably, the channel layer extends into the sacrificial layer along the first direction, and the storage layer has a fifth end near the stop layer, a fourth end away from the stop layer, and a storage layer sidewall located between the fifth end and the fourth end; prior to the step of removing the sacrificial layer, the preparation method further includes:

[0048] Remove the first substrate;

[0049] After the sacrificial layer is removed, the storage layer exposes the fifth end of the storage layer and a portion of the storage layer sidewall connected to the fifth end.

[0050] More preferably, the channel layer has a channel layer sidewall extending along the first direction, a first end near the stop layer, and a second end away from the stop layer; the step of removing the exposed storage layer includes:

[0051] The exposed memory layer is etched, and the etching stops at the first surface of the stop layer, so that the first surface is flush with the third end of the memory layer;

[0052] Wherein, after removing the exposed storage layer, the outer portion of the channel layer is the first end of the channel layer and the portion of the channel layer sidewall connected to the first end.

[0053] More preferably, the preparation method further includes:

[0054] Forming peripheral circuit chips;

[0055] The peripheral circuit chip is bonded to the side of the stacked structure away from the stop layer.

[0056] More preferably, the channel layer extends into the first substrate along the first direction, the channel layer has channel layer sidewalls extending along the first direction, and the memory layer has memory layer sidewalls extending along the first direction; wherein,

[0057] Removing the sacrificial layer exposes part of the storage layer sidewall;

[0058] After removing the exposed storage layer sidewalls, the outer interface of the channel layer is exposed. The outer interface of the channel layer is a portion of the channel layer sidewalls, and the side of the common source layer is connected to the outer interface of the channel layer.

[0059] More preferably, the method for fabricating the semiconductor device further includes:

[0060] A gate wire slot structure is formed that penetrates the stop layer and the stacked structure along the first direction;

[0061] An oxide layer is formed between the gate gap structure and the stop layer.

[0062] More preferably, the method for fabricating the semiconductor device further includes:

[0063] An insulating layer is formed on the stop layer, located around the periphery of the stacked structure;

[0064] A through-contact is formed that penetrates the insulating layer and the stop layer along the first direction.

[0065] More preferably, the method for fabricating the semiconductor device further includes:

[0066] An interconnect layer is formed covering the common source layer. The interconnect layer is connected to the common source layer and the through contact via conductive contacts. The through contact is connected to the interconnect layer via the conductive contacts at one end near the stop layer.

[0067] More preferably, the stacked structure includes a memory region stacked structure and a stepped structure located around the memory region stacked structure. The stacked structure includes an interlayer insulating layer and a gate layer alternately stacked along the first direction. The insulating layer covers the stepped structure and the stop layer. The fabrication method further includes:

[0068] A word line contact is formed that penetrates the insulating layer along the first direction, and the word line contact is connected to each of the gate layers;

[0069] A virtual channel structure is formed that penetrates the insulating layer, the stepped structure, and the stop layer along the first direction.

[0070] The beneficial effects of this invention are: it provides a semiconductor device and a method for fabricating the same, including a stacked layer and a stop layer located on the stacked layer, the stacked layer including a memory region stacked layer, and the stop layer having a first surface remote from the stacked layer. The semiconductor device further includes a channel structure extending through the stop layer and the memory region stacked layer along a first direction, and a common source layer located on the first surface of the stop layer. The channel structure includes a channel layer extending along the first direction and a memory layer surrounding the channel layer, the channel layer having an outer portion extending out of the stop layer and not covered by the memory layer, and the common source layer being connected to the outer portion of the channel layer. In the fabrication process of this semiconductor device, the stop layer serves as an etch stop layer in the memory layer removal process of the channel structure, enabling better automatic control of the memory layer etching process and increasing the distance from the bottom select gate to the etch stop layer in the stacked layer, thereby increasing the breakdown voltage of the bottom select gate. Furthermore, the stop layer remains in the final structure of the semiconductor device and does not need to be removed, simplifying the process and reducing costs. Attached Figure Description

[0071] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0072] Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the first embodiment of the present invention;

[0073] Figure 2 This is a schematic diagram of the structure of the semiconductor device provided in the second embodiment of the present invention;

[0074] Figure 3 This is a schematic flowchart of the semiconductor device fabrication method provided in the first embodiment of the present invention;

[0075] Figures 4a-4n This is a schematic diagram of the fabrication process of the semiconductor device provided in the first embodiment of the invention;

[0076] Figure 5a This is a top view of the stacked layer structure in the semiconductor device provided in the first embodiment of the present invention;

[0077] Figure 5b This is a top view of the stacked layer structure in the semiconductor device provided in the third embodiment of the present invention;

[0078] Figure 6 This is a schematic flowchart of the semiconductor device fabrication method provided in the second embodiment of the present invention;

[0079] Figures 7a-7d This is a schematic diagram of the fabrication process of the semiconductor device provided in the second embodiment of the invention. Detailed Implementation

[0080] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0081] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0082] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0083] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0084] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0085] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the cross-section of a semiconductor device in various directions, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0086] Please see Figure 1 , Figure 1 This is a schematic diagram of the semiconductor device provided in the first embodiment of the present invention. It is understood that the gate slot structure 111 (or gate slot) and the step structure 12 will not appear in the same cross-section; therefore, arcs are used in the figures to distinguish cross-sections in different directions. For example, the cross-section of the step structure 12 is along the XZ direction, while the gate slot structure 111 is along the YZ direction. Subsequent figures are similar.

[0087] The semiconductor device 100 can be a three-dimensional memory, such as a 3D NAND flash memory. From the placement orientation of the illustrated semiconductor device 100, the device includes a stacked layer 10 (including a memory region stacked layer 11 and a stepped structure 12 surrounding the memory region stacked layer 11), an insulating layer 20 surrounding the stacked layer 10, a stop layer 30 (having a first surface 301 away from the stacked layer 10) on the stacked layer 10 and the insulating layer 20, a channel structure 40 penetrating the stop layer 30 and the memory region stacked layer 11 along a first direction (Z), and a common source layer 50 located on the first surface 301 of the stop layer 30. The first direction is perpendicular to the stop layer 30. The stop layer 30 can be made of monocrystalline silicon, and the common source layer 50 can be made of polycrystalline silicon with N-type doped ions.

[0088] The stacked layer 10 includes an interlayer insulating layer 101 and a gate layer 102 alternately stacked along the first direction. The material of the interlayer insulating layer 101 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The gate layer 102 may include a dielectric layer 1021 and a conductive layer. The conductive layer may include a first conductive layer 1022 and a second conductive layer 1023 formed sequentially, with the first conductive layer 1022 located between the dielectric layer 1021 and the second conductive layer 1023. The dielectric layer 1021 serves to isolate the conductive layer from the channel structure 40. The dielectric layer 1021 has an upper surface and a lower surface that contact two adjacent interlayer insulating layers 101, and a side surface that contacts the channel structure 40. The conductive layer is surrounded by the upper surface, the lower surface, and the side surface of the dielectric layer 1021. The material of the dielectric layer 1021 may include a high-k dielectric layer (such as aluminum oxide), the material of the first conductive layer 1022 may include titanium nitride, and the material of the second conductive layer 1023 may include tungsten. The primary function of the first conductive layer 1022 is to mitigate the diffusion of the second conductive layer 1023 into the dielectric layer 1021 and to improve the adhesion of the second conductive layer 1023. The first conductive layer 1022 also improves the diffusion of fluorine in the second conductive layer 1023.

[0089] The number of layers in the stack 10 determines the number of storage cells it contains in the first direction. For example, the number of layers in the stack 10 can be 32, 64, 96, 128, etc., and the more layers in the stack 10, the higher the integration of the corresponding three-dimensional memory.

[0090] The gate layer 102 includes a bottom select gate 1024 on the side closest to the stop layer 30, a top select gate 1025 on the side furthest from the stop layer 30, and an intermediate gate 1026 located between the bottom select gate 1024 and the top select gate 1025. The bottom select gate 1024 may include a plurality of consecutive gate layers 102; in this embodiment, the gate layer 102 closest to the stop layer 30 is used as the bottom select gate 1024.

[0091] The step structure 12 faces downwards and the width of each step gradually decreases from the direction away from the stop layer 30, which is equivalent to the stack layer 10 below the step structure 12 being removed. Therefore, the insulating layer 20 located around the stack layer 10 also covers the step structure 12 to fill the space below the step structure 12.

[0092] The channel structure 40 includes a channel layer 41 extending from the stop layer 30 along the first direction and a storage layer 42 surrounding the channel layer 41. The channel layer 41 has a channel layer outer portion 410 extending from the stop layer 30 and not covered by the storage layer 42. The storage layer 42 includes a tunneling insulating layer 421 surrounding the channel layer 41, a charge trapping layer 422 surrounding the tunneling insulating layer 421, and a barrier insulating layer 423 surrounding the charge trapping layer 422. An exemplary material for the barrier insulating layer 423 and the tunneling insulating layer 421 is silicon oxide, and an exemplary material for the charge trapping layer 422 is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure. An exemplary structure for the channel layer 41 is polysilicon, but it is understood that other materials can be used for these layers.

[0093] The channel layer 41 has a channel layer sidewall 411 extending along the first direction, a first end 412 near the stop layer 30, and a second end 413 away from the stop layer 30. The storage layer 42 has a third end 424 near the stop layer 30, a fourth end 425 away from the stop layer 30, and a storage layer sidewall 426 located between the third end 424 and the fourth end 425.

[0094] In this embodiment, the outer portion 410 of the channel layer is the first end 412 of the channel layer 41 and the portion of the channel layer sidewall 411 connected to the first end 412. That is, the storage layer 42 surrounds the remaining surface of the channel layer 41 except for the outer portion 410. The first surface 301 of the stop layer 30 is flush with the third end 424 of the storage layer 42, and the common source layer 50 covers both the stop layer 30 and the outer portion 410 of the channel layer, so that the channel layers 41 of the multiple channel structures 40 achieve common source connection.

[0095] The semiconductor device 100 may further include a gate line gap structure 111 and an oxide layer 112 located between the gate line gap structure 111 and the stop layer 30. The gate line gap structure 111 extends through the stop layer 30 and the stacked layer 10 along the first direction. The oxide layer 112 can prevent the stop layer 30 from being etched when the interlayer sacrificial layer is removed through the gate line gap.

[0096] The semiconductor device 100 also includes word line contacts 60 extending through the insulating layer 20 along the first direction. The word line contacts 60 are connected to each of the gate layers 102, meaning that each gate layer 102 has a separate word line contact 60. Specifically, the word line contacts 60 are in contact with the first conductive layer 1022 or the second conductive layer 1023 in each gate layer 102.

[0097] The semiconductor device 100 also includes a virtual channel structure 70 extending along the first direction through the insulating layer 20, the step structure 12 and the stop layer 30. The material of the virtual channel structure 70 may include silicon oxide for supporting the stacked layer 10.

[0098] The semiconductor device 100 further includes a through contact 80 extending along the first direction through the stop layer 30 and the insulating layer 20. The through contact 80 can be made of various conductive materials. Optionally, the semiconductor device 100 may also include an isolation layer 81 surrounding the through contact 80, the isolation layer 81 serving to isolate the through contact 80 from other structures.

[0099] The semiconductor device 100 further includes a first dielectric layer 51 covering the common source layer 50 and an interconnect layer 52 covering the first dielectric layer 51. Conductive contacts are formed in the first dielectric layer 51. The conductive contacts include a first conductive contact 511 connected to one end of a through contact 80 near the stop layer 30, and a second conductive contact 512 connected to the common source layer 50. The through contact 80 is connected to the interconnect layer 52 via the first conductive contact 511, and the common source layer 50 is connected to the interconnect layer 52 via the second conductive contact 512. The interconnect layer 52 is made of a conductive material to conduct electricity between the common source layer 50, the interconnect layer 52, and the through contact 80.

[0100] The semiconductor device 100 further includes a peripheral circuit chip 90 bonded to the stacked layer 10 and the insulating layer 20 on the side away from the stop layer 30. The peripheral circuit chip 90 includes a substrate 91, a transistor device 92 located on the substrate 91, and a plurality of conductive channels 93 located on the transistor device 92. The peripheral circuit chip 90 has a first bonding contact 94 located on the conductive channel 93. The through contact 80 has a second bonding contact 232 at the end away from the stop layer 30, and the first bonding contact 94 is bonded to the second bonding contact 232 to electrically connect the common source layer 50 to the peripheral circuit chip 90. The word line contact 60 has a second bonding contact 232 at one end away from the stop layer 30, and the second end 413 of the channel layer 41 has the second bonding contact 232. The second bonding contact 232 is bonded to the first bonding contact 94 so that the transistor device 92 can apply an operating voltage to the word line contact 60 and the channel layer 41.

[0101] In the semiconductor device 100 provided in this embodiment of the invention, a stop layer 30 serves as an etch barrier layer forming the outer portion 410 of the channel layer. The stop layer 30 enables the etching of the memory layer 42 to automatically stop at its first surface 301, preventing excessive etching of the memory layer sidewalls 426 and blocking the etching of the stacked layer 10 and insulating layer 20 below the stop layer 30. Therefore, the distance from the bottom select gate 1024 to the common source layer 50 can be controlled, preventing the bottom select gate 1024 from being too close, which would result in a low breakdown voltage and cause it to break down. Furthermore, the stop layer 30 is retained in the final structure and does not need to be removed, simplifying the process and reducing costs. Since the common source layer 50 is polycrystalline silicon and the stop layer 30 is monocrystalline silicon and connected to the polycrystalline silicon, there is no grain boundary between the common source layer 50 (polycrystalline silicon) and the stop layer 30 (monocrystalline silicon). Therefore, when the common source layer 50 is activated after ion doping, the occurrence of voids or bubbles in the common source layer 50 can be reduced.

[0102] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in the second embodiment of the present invention. For the sake of brevity and ease of understanding, the same structures as in the first embodiment are referred to by the same reference numerals, and the same structures are not described again in the second embodiment.

[0103] Described with reference to the placement orientation of the semiconductor device 200 shown in the figure, the semiconductor device 200 includes a first substrate 201, a common source layer 50 on the first substrate 201, a stop layer 30 on the common source layer 50, a stacked layer 10 on the stop layer 30, and a channel structure 40 extending along a first direction through the stop layer 30 and the memory region stacked layer 11. The stacked layer 10 includes an interlayer insulating layer 101 and a gate layer 102 alternately stacked along the first direction. In this embodiment, a gate layer 102 near the stop layer 30 is used as a bottom select gate 1024.

[0104] The difference between this embodiment and the first embodiment lies in the position of the outer interface portion 410 of the channel layer. The outer interface portion 410 of the channel layer is part of the sidewall 411 of the channel layer, that is, the sidewall 426 of the storage layer has an opening near the third end 424 to expose the outer interface portion 410 of the channel layer. The common source layer 50 fills the opening, and the side of the common source layer 50 is connected to the outer interface portion 410 of the channel layer.

[0105] In this embodiment of the invention, the stop layer 30 serves as an etch barrier layer for etching the sidewall 426 of the memory layer, preventing further etching of the sidewall 426. Therefore, the stop layer 30 can control the distance between the bottom select gate 1024 and the first substrate 201, preventing the bottom select gate 1024 from being broken down due to insufficient distance. The stop layer 30 is retained in the final structure, which not only distinguishes it from existing technologies but also eliminates the need for removal, thus simplifying the process and reducing costs.

[0106] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating the method for fabricating a semiconductor device according to the first embodiment of the present invention. Please also refer to... Figures 4a-4n , Figures 4a-4n This is a schematic diagram of the fabrication process of the semiconductor device provided in the first embodiment of the invention. Taking the formation of semiconductor device 100 as an example, the fabrication method includes the following steps S1-S8.

[0107] Please see Figure 3 Steps S1-S2 and Figure 4a .

[0108] Step S1: Provide a first substrate 201.

[0109] The first substrate 201 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a multilayer structure, such as Si / SiGe.

[0110] Step S2: A sacrificial layer 501 is formed on the first substrate 201.

[0111] The sacrificial layer 501 can be sacrificial polysilicon (SAC Poly), and can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods. In this embodiment, before forming the sacrificial layer 501, the fabrication method further includes depositing a silicon dioxide layer 502 on the first substrate 201.

[0112] Please see Figure 3 Step S3 and Figures 4b-4d .

[0113] Step S3: Form a stop layer 30 on the sacrificial layer 501.

[0114] In one embodiment, the stop layer 30 is made of monocrystalline silicon. Specifically, step S3 may include: 1) as... Figure 4b As shown, a second substrate 202 is formed, the second substrate 202 including a substrate 2021, an insulator 2022 located on the substrate 2021, and a single-crystal silicon layer 2023 located on the insulator 2022; 2) as Figure 4c As shown, the single-crystal silicon layer 2023 of the second substrate 202 is bonded to the sacrificial layer 501 of the first substrate 201, and an oxide layer 2024 is formed at the bonding interface, that is, the oxide layer 2024 is located between the sacrificial layer 501 and the single-crystal silicon layer 2023; 3) as Figure 4d As shown, the substrate 2021 and the insulator 2022 in the second substrate 202 are removed to form the single crystal silicon layer 2023 as the stop layer 30 on the sacrificial layer 501 of the first substrate 201.

[0115] Please see Figure 3 Step S4 and Figure 4e .

[0116] Step S4: A stacked layer 10 is formed on the stop layer 30, the stacked layer 10 including a storage area stacked layer 11, and the stop layer 30 having a first surface 301 away from the stacked layer 10.

[0117] The stacked layer 10 includes interlayer insulating layers 101 and interlayer sacrificial layers 103 alternately stacked along the first direction. The stacked layer 10 includes a storage region stacked layer 11 and a stepped region stacked layer 13 located around the storage region stacked layer 11. It should be noted that the interlayer insulating layer 101 is in contact with the stop layer 30, and the topmost layer of the stacked layer 10 is also an interlayer insulating layer 101. These two interlayer insulating layers 101 can be thicker than the middle interlayer insulating layer 101.

[0118] Please refer to 5a. Figure 5a This is a top view of the stacked layer structure in a semiconductor device according to the first embodiment of the present invention. The stacked layer 10 includes a memory region stacked layer 11 and a stepped region stacked layer 13 located around the memory region stacked layer 11. The stepped region stacked layer 13 can be located on both sides of the memory region stacked layer 11 or around the periphery of the memory region stacked layer. The blank areas between the multiple stacked layers 10 can be dicing lines.

[0119] Please see Figure 5b , Figure 5b This is a top view of the stacked layer structure in a semiconductor device according to a third embodiment of the present invention. The stacked layer 10 includes a memory region stacked layer 11 and a stepped region stacked layer 13 located in the middle of the memory region stacked layer 11. The memory region stacked layer 11 is used to form a memory structure, and the stepped region stacked layer 13 is used to form a stepped structure.

[0120] Please see Figure 3 Step S5 and Figure 4f .

[0121] Step S5: Form a channel structure 40 that extends along a first direction through the storage stack layer 11, the stop layer 30, and a portion of the sacrificial layer 501, the channel structure 40 including a channel layer 41 extending along the first direction and a storage layer 42 surrounding the channel layer 41.

[0122] In this embodiment, the channel layer 41 extends into the sacrificial layer 501 along the first direction. Specifically, step S5 may include: 1) forming a channel hole that penetrates the stacked layer 10, the stop layer 30, and a portion of the sacrificial layer 501 along the first direction, the channel hole extending into the sacrificial layer 501, wherein "penetrating a portion of the sacrificial layer 501" means penetrating a portion of the sacrificial layer 501 along the first direction, rather than completely penetrating it; 2) sequentially forming a storage layer 42 and a channel layer 41 on the inner wall of the channel hole to form the channel structure 40. The step of forming the storage layer 42 includes sequentially forming a barrier insulating layer 423, a charge trapping layer 422, and a tunneling insulating layer 421 on the inner wall of the channel hole. An exemplary material for the barrier insulating layer 423 and the tunneling insulating layer 421 is silicon oxide, an exemplary material for the charge trapping layer 422 is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure, and an exemplary structure for the channel layer 41 is polysilicon.

[0123] In this embodiment, the channel layer 41 has a channel layer sidewall 411 extending along the first direction, a first end 412 near the stop layer 30, and a second end 413 away from the stop layer 30. The storage layer 42 has a fifth end 427 near the stop layer 30, a fourth end 425 away from the stop layer 30, and a storage layer sidewall 426 located between the fifth end 427 and the fourth end 425.

[0124] Before step S5, the fabrication method further includes: progressively etching the stepped region stacked layer 13 to form as shown in step S5. Figure 4f The step structure 12 shown; forming an insulating layer 20 covering the step structure 12 and the stop layer 30, the insulating layer 20 being located on the periphery of the stacked layer 10, the insulating layer 20 including a thinner first insulating layer 21 covering the step structure 12 and a second insulating layer 22 filling the step structure 12.

[0125] The preparation method also includes: 1) as follows Figure 4g As shown, a virtual channel structure 70 is formed that penetrates the insulating layer 20, the stepped structure 12, and the stop layer 30 along the first direction. 2) As Figure 4hAs shown, a gate line gap 110 is formed that penetrates the memory region stack layer 11 along a first direction. The interlayer sacrificial layer 103 is removed through the gate line gap 110. Then, a dielectric layer 1021, a first conductive layer 1022, and a second conductive layer 1023 are sequentially deposited at the original location of the interlayer sacrificial layer 103 to form a gate layer 102. The material of the dielectric layer 1021 may include a high-k dielectric layer (such as aluminum oxide), the material of the first conductive layer 1022 may include titanium nitride, and the material of the second conductive layer 1023 may include tungsten. Finally, silicon dioxide and polysilicon are sequentially filled into the gate line gap 110. 3) A word line contact 60 is formed that penetrates the insulating layer 20 along the first direction. The word line contact 60 is connected to each gate layer 102. Specifically, the word line contact 60 contacts the second conductive layer 1023 in each gate layer 102. 4) Form an isolation layer 81 that penetrates the insulating layer 20, the stop layer 30, and a portion of the sacrificial layer 501 along the first direction, and a through contact 80 surrounded by the isolation layer 81. 5) Form a second dielectric layer 23 on the stacked layer 10 and the insulating layer 20, and form conductive plugs 231 in the second dielectric layer 23 that connect to the channel layer 41, the word line contact 60, and the through contact 80 by etching and deposition processes.

[0126] Before removing the interlayer sacrificial layer 103 through the gate gap 110, a portion of the stop layer 30 can be oxidized into an oxide layer 112 through the gate gap 110. Additionally, a portion of the sacrificial layer 501 at the bottom of the gate gap 110 can also be oxidized into the oxide layer 112. Figure 4h (Not shown in the image), after forming the gate layer 102, the silicon dioxide and the polysilicon are filled into the gate line gap 110. This is because the stop layer 30 and the sacrificial layer 501 are also etched during the removal of the interlayer sacrificial layer 103, so oxidizing to form the oxide layer 112 first can protect the stop layer 30 and the sacrificial layer 501 from being etched.

[0127] Before the step of removing the sacrificial layer 501, the preparation method further includes: 1) as follows Figure 4i As shown, a peripheral circuit chip 90 is formed. The peripheral circuit chip 90 includes a substrate 91, a transistor device 92 located on the substrate 91, and a plurality of conductive channels 93 located on the transistor device 92. The peripheral circuit chip 90 has a first bonding contact 94 located on the conductive channel 93. 2) As shown Figure 4jAs shown, the peripheral circuit chip 90 is bonded to the stacked layer 10 and the insulating layer 20 on the side away from the stop layer 30. Specifically, the through contact 80 has a second bonding contact 232 at the end away from the stop layer 30, the word line contact 60 has a second bonding contact 232 at the end away from the stop layer 30, the second end 413 of the channel layer 41 has a second bonding contact 232, the second bonding contact 232 is connected to the conductive plug 231, and the first bonding contact 94 of the peripheral circuit chip 90 is bonded to a plurality of second bonding contacts 232; 3) as Figure 4k As shown, the first substrate 201 and the sacrificial layer 501 are flipped and placed above the stop layer 30; 4) as Figure 4l As shown, the first substrate 201 and the silicon dioxide layer 502 can then be removed using a chemical mechanical polishing process, and step S6 is then performed.

[0128] Step S6: Remove the sacrificial layer 501 to expose a portion of the storage layer 42 of the channel structure 40.

[0129] Tetramethylammonium hydroxide (TMAH) can be used for etching to remove the sacrificial layer 501. Since the channel structure 40 extends into the sacrificial layer 501, the channel structure 40 is exposed after removing the sacrificial layer 501, i.e., part of the storage layer 42 is exposed. The structure after step S6 is as follows. Figure 4l As shown.

[0130] Please see Figure 3 Step S7 and Figure 4m .

[0131] Step S7: Remove the exposed storage layer 42 to form a channel layer outer portion 410 extending out of the stop layer 30 and not covered by the storage layer 42.

[0132] Hydrofluoric acid can be used as an etchant to etch the oxide layer 2024 and Figure 4l The etch stops on the first surface 301 of the stop layer 30, exposing the memory layer 42 (ONO). The first surface 301 is flush with the third end 424 of the memory layer 42. After removing the exposed memory layer 42, the first end 412 of the channel layer 41 and a portion of the channel layer sidewall 411 connected to the first end 412 are exposed. Specifically, the channel layer external portion 410 consists of the first end 412 of the channel layer 41 and the portion of the channel layer sidewall 411 connected to the first end 412.

[0133] After forming the outer portion 410 of the channel layer, the fabrication method further includes: performing ion implantation on the channel layer 41 to form a channel doped region 414 at the first end 412 of the channel layer 41 and the channel layer sidewall 411 connected to the first end 412.

[0134] Please see Figure 3 Step S8 and Figure 4n .

[0135] Step S8: Form a common source layer 50 on the first surface 301 of the stop layer 30, wherein the common source layer 50 is connected to the outer portion 410 of the channel layer.

[0136] The common source layer 50 can be formed by depositing polycrystalline silicon on the first surface 301 of the stop layer 30 and the outer portion 410 of the channel layer. Then, doped ions are implanted into the common source layer 50, followed by activation of the doped ions. Laser annealing or high-temperature annealing processes can be used to further activate the doped ions. Since the common source layer 50 is polycrystalline silicon and the stop layer 30 is monocrystalline silicon and connected to the polycrystalline silicon, there are no grain boundaries between the common source layer 50 (polycrystalline silicon) and the stop layer 30 (monocrystalline silicon). Therefore, when the common source layer 50 is activated after ion doping, the occurrence of voids or bubbles in the common source layer 50 can be reduced.

[0137] After step S8, you can refer to Figure 1 The preparation method further includes: forming a first dielectric layer 51 covering the common source layer 50; forming a plurality of conductive contacts in the first dielectric layer 51, the plurality of conductive contacts including a first conductive contact 511 connected to one end of the through contact 80 near the stop layer 30 and a second conductive contact 512 connected to the common source layer 50; forming an interconnect layer 52 covering the first dielectric layer 51, the interconnect layer 52 being connected to the through contact 80 through the first conductive contact 511 and to the common source layer 50 through the second conductive contact 512.

[0138] The method for fabricating the semiconductor device 100 provided in this embodiment of the invention uses a stop layer 30 as an etching barrier layer to etch the memory layer 42 when forming the outer junction of the channel layer 410. This allows the etching process of the memory layer 42 to automatically stop at the first surface 301 of the stop layer 30, preventing excessive etching of the memory layer sidewall 426. Therefore, the distance from the bottom select gate 1024 to the common source layer 50 can be controlled, increasing the breakdown voltage of the bottom select gate 1024. Furthermore, the stop layer 30 is retained in the final structure and does not need to be removed, simplifying the process and reducing costs.

[0139] Please see Figure 6 , Figure 6This is a schematic flowchart of the semiconductor device fabrication method provided in the second embodiment of the present invention. Please also refer to... Figures 7a-7d , Figures 7a-7d This is a schematic diagram of the fabrication process of the semiconductor device provided in the second embodiment of the invention. This embodiment uses the formation of semiconductor device 200 as an example to illustrate the fabrication method, which includes the following steps S101-S109.

[0140] Step S101: Provide a first substrate 201.

[0141] Step S102: A sacrificial layer 501 is formed on the first substrate 201.

[0142] Step S103: Form a stop layer 30 on the sacrificial layer 501.

[0143] Step S104: A stacked layer 10 is formed on the stop layer 30, the stacked layer 10 including a storage area stacked layer 11, and the stop layer 30 having a first surface 301 away from the stacked layer 10.

[0144] like Figure 7a As shown, the stacked layer 10 includes interlayer insulating layers 101 and interlayer sacrificial layers 103 alternately stacked along the first direction. The stacked layer 10 also includes a storage region stacked layer 11 and a stepped structure 12 located around the periphery of the storage region stacked layer 11. One interlayer sacrificial layer 103 near the stop layer 30 will eventually be replaced with... Figure 2 The bottom select gate 1024 is in the middle.

[0145] Step S105: Form a channel structure 40 that extends along a first direction through the storage stack layer 11, the stop layer 30, and a portion of the sacrificial layer 501, the channel structure 40 including a channel layer 41 extending along the first direction and a storage layer 42 surrounding the channel layer 41.

[0146] like Figure 7a As shown, unlike the first embodiment, the channel structure 40 formed in step S105 extends into the first substrate 201 along a first direction, that is, both the storage layer 42 and the channel layer 41 extend into the first substrate 201. In this embodiment, the channel layer 41 has a channel layer sidewall 411 extending along the first direction, a first end 412 near the stop layer 30, and a second end 413 away from the stop layer 30. The storage layer 42 has a fifth end 427 near the stop layer 30, a fourth end 425 away from the stop layer 30, and a storage layer sidewall 426 located between the fifth end 427 and the fourth end 425.

[0147] Step S106: Form a gate line gap 110 that penetrates the storage area stack layer 11, stop layer 30 and sacrificial layer 501 along the first direction (e.g., Figure 7a (As shown).

[0148] Step S107: Remove the sacrificial layer 501 to expose a portion of the storage layer 42 of the channel structure 40.

[0149] like Figure 7b As shown, unlike the first embodiment, the sacrificial layer 501 is removed through the gate line gap 110. Since the sacrificial layer 501 is connected to the storage layer sidewall 426, removing the sacrificial layer 501 exposes part of the storage layer sidewall 426.

[0150] Step S108: Remove the exposed storage layer 42 to form a channel layer outer portion 410 extending out of the stop layer 30 and not covered by the storage layer 42.

[0151] like Figure 7c As shown, unlike the first embodiment, the exposed storage layer sidewall 426 is removed to form a channel layer external portion 410 and a cavity A connected to the channel layer external portion 410. The cavity A is located between the first substrate 201 and the stop layer 30. Further, the storage layer sidewall 426 is etched using the stop layer 30 and the first substrate 201 as etching barrier layers, exposing a portion of the channel layer sidewall 411 as the channel layer external portion 410.

[0152] Step S109: A common source layer 50 is formed on the first surface 301 of the stop layer 30, and the common source layer 50 is connected to the outer portion 410 of the channel layer.

[0153] like Figure 7d As shown, unlike the first embodiment, a common source layer 50 is filled in the cavity A. The common source layer 50 is located between the first substrate 201 and the stop layer 30, and the side of the common source layer 50 is connected to the outer portion 410 of the channel layer.

[0154] In the fabrication method of the semiconductor device 200, Figure 2 The methods for forming other structures such as the gate layer 102, word line contact 60, virtual channel structure 70, and through contact 80 in the semiconductor device 200 can all refer to the preparation method provided in the first embodiment.

[0155] The semiconductor device 200 fabrication method provided in this embodiment of the invention uses a stop layer 30 as an etch barrier layer to prevent the sidewalls 426 of the storage layer from being etched upwards. Therefore, the stop layer 30 can control the distance between the bottom select gate 1024 and the substrate, preventing the bottom select gate 1024 from being broken down due to insufficient distance. This stop layer 30 is retained in the final structure, which not only distinguishes it from existing technologies but also eliminates the need for removal, thus simplifying the process and reducing costs.

[0156] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Stacked layers; A stop layer located on the stacked layers, the stop layer having a first surface remote from the stacked layers; A channel structure extending through the stop layer and the stacked layer in a first direction, the channel structure including a channel layer and a storage layer surrounding the channel layer, the channel layer having a channel layer outer portion extending out of the stop layer and not covered by the storage layer; The channel layer has a channel layer sidewall extending along the first direction, and a first end and a second end connected to the channel layer sidewall, the first end being the side closer to the stop layer, and the second end being the side farther away from the stop layer; the outer portion of the channel layer includes the first end of the channel layer and a portion of the channel layer sidewall connected to the first end; A common source layer is located on the first surface of the stop layer, the common source layer covers the end and sidewall of the outer junction of the channel layer, the material of the stop layer is monocrystalline silicon, and the material of the common source layer is polycrystalline silicon.

2. The semiconductor device according to claim 1, characterized in that, The storage layer has a third end near the stop layer and a fourth end away from the stop layer, and the first surface of the stop layer is flush with the third end of the storage layer.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A gate wire slot structure that penetrates the stop layer and the stacked layer along the first direction; An oxide layer located between the gate line slot structure and the stop layer.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating layer is located around the stacked layers, and the stop layer is also located between the insulating layer and the common source layer; A through-contact that penetrates the stop layer and the insulating layer along the first direction.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: The peripheral circuit chip is bonded to the stacked layer and the insulating layer on the side away from the stop layer; The peripheral circuit chip has a first bonding contact, and the through contact has a second bonding contact at the end away from the stop layer, wherein the first bonding contact is bonded to the second bonding contact.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: An interconnect layer covering the common source layer, wherein the through contact is connected to the interconnect layer via a conductive contact at one end near the stop layer.

7. The semiconductor device according to claim 4, characterized in that, The stacked layer includes a memory region stacked layer and a stepped structure located around the periphery of the memory region stacked layer. The stacked layer includes an interlayer insulating layer and a gate layer alternately stacked along the first direction. The insulating layer covers the stepped structure and the stop layer. The semiconductor device further includes: A word line contact extends through the insulating layer along the first direction, and the word line contact is connected to each of the gate layers.

8. A method for fabricating a semiconductor device, characterized in that, include: Provide a first substrate; A stop layer is formed on the first substrate; A stacked structure is formed on the stop layer, the stop layer having a first surface remote from the stacked structure; A channel structure is formed that penetrates the stack structure and the stop layer along a first direction. The channel structure includes a channel layer extending along the first direction and a storage layer surrounding the channel layer. The channel layer has a channel layer sidewall extending along the first direction, and a first end and a second end connected to the channel layer sidewall. The first end is the side closer to the stop layer, and the second end is the side farther away from the stop layer. A channel layer outer portion is formed that extends beyond the stop layer and is not covered by the storage layer, the channel layer outer portion including a first end of the channel layer and a portion of the channel layer sidewall connected to the first end; A common source layer is formed on the first surface of the stop layer, the common source layer covering the end and sidewall of the outer portion of the channel layer, the material of the stop layer is monocrystalline silicon, and the material of the common source layer is polycrystalline silicon.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a stop layer on the first substrate includes: A second substrate is formed, the second substrate comprising a substrate, an oxide layer on the substrate, and a single-crystal silicon layer on the oxide layer; The single-crystal silicon layer of the second substrate is bonded to the first substrate; The substrate and the oxide layer in the second substrate are removed to form the single-crystal silicon layer on the first substrate as the stop layer.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a stop layer on the first substrate includes: An oxide layer, a polycrystalline silicon layer, and a conductive layer are sequentially formed on the first substrate; The conductive layer is heated to induce the polycrystalline silicon layer to transform into a monocrystalline silicon layer as the stop layer.

11. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a channel layer outer portion extending beyond the stop layer and not covered by the storage layer includes: A sacrificial layer is formed between the first substrate and the stop layer, and the channel structure also extends through a portion of the sacrificial layer; After the channel structure is formed, the sacrificial layer is removed to expose a portion of the storage layer of the channel structure; Remove the exposed storage layer to form the outer portion of the channel layer.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The channel layer extends into the sacrificial layer along the first direction, and the storage layer has a fifth end near the stop layer, a fourth end away from the stop layer, and a storage layer sidewall located between the fifth end and the fourth end. Prior to the step of removing the sacrificial layer, the preparation method further includes: Remove the first substrate; After the sacrificial layer is removed, the storage layer exposes the fifth end of the storage layer and a portion of the storage layer sidewall connected to the fifth end.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The step of removing the exposed storage layer includes: The exposed memory layer is etched, and the etching stops at the first surface of the stop layer, so that the first surface is flush with the third end of the memory layer; Wherein, after removing the exposed storage layer, the outer portion of the channel layer is the first end of the channel layer and the portion of the channel layer sidewall connected to the first end.

14. The method for fabricating a semiconductor device according to claim 8, characterized in that, The preparation method further includes: Forming peripheral circuit chips; The peripheral circuit chip is bonded to the side of the stacked structure away from the stop layer.

15. The method for fabricating a semiconductor device according to claim 11, characterized in that, The channel layer extends into the first substrate along the first direction, the channel layer has channel layer sidewalls extending along the first direction, and the memory layer has memory layer sidewalls extending along the first direction; wherein, Removing the sacrificial layer exposes part of the storage layer sidewall; After removing the exposed storage layer sidewalls, the outer interface of the channel layer is exposed. The outer interface of the channel layer is a portion of the channel layer sidewalls, and the side of the common source layer is connected to the outer interface of the channel layer.

16. The method for fabricating a semiconductor device according to claim 8, characterized in that, The method for fabricating the semiconductor device further includes: A gate wire slot structure is formed that penetrates the stop layer and the stacked structure along the first direction; An oxide layer is formed between the gate line slot structure and the stop layer.

17. The method for fabricating a semiconductor device according to claim 8, characterized in that, The method for fabricating the semiconductor device further includes: An insulating layer is formed on the stop layer, located around the periphery of the stacked structure; A through-contact is formed that penetrates the insulating layer and the stop layer along the first direction.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, The method for fabricating the semiconductor device further includes: An interconnect layer is formed covering the common source layer. The interconnect layer is connected to the common source layer and the through contact via conductive contacts. The through contact is connected to the interconnect layer via the conductive contacts at one end near the stop layer.

19. The method for fabricating a semiconductor device according to claim 17, characterized in that, The stacked structure includes a memory region stacked structure and a stepped structure located around the memory region stacked structure. The stacked structure includes an interlayer insulating layer and a gate layer alternately stacked along the first direction. The insulating layer covers the stepped structure and the stop layer. The fabrication method further includes: A word line contact is formed that penetrates the insulating layer along the first direction, and the word line contact is connected to each of the gate layers; A virtual channel structure is formed that penetrates the insulating layer, the stepped structure, and the stop layer along the first direction.

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