Method for manufacturing memory, memory and memory system

Abstract

The application provides a memory manufacturing method, a memory and a memory system. The memory manufacturing method comprises the following steps: forming a first stop layer on a substrate; forming a groove in the first stop layer, the groove penetrating through the first stop layer and extending into the substrate; forming a second stop layer on the first stop layer, the second stop layer covering the inner wall of the groove; forming a stack layer on the second stop layer, the stack layer being provided with a storage channel structure penetrating through the stack layer and extending into the substrate; forming a gate slit in the stack layer, the gate slit penetrating through the stack layer and the second stop layer in the groove and extending into the substrate; and forming a gate structure in the stack layer and a gate slit structure in the gate slit, so that the first stop layer can be prevented from warping in a gate replacement process, the stack layer is prevented from bulging, the filling uniformity of the gate material is improved, and the conductive performance of the gate is improved.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a memory, a memory, and a memory system. [Background Technology]

[0002] 3D NAND flash memory is an emerging type of memory that overcomes the limitations of 2D or planar NAND flash memory by stacking memory chips together. Unlike placing memory cells on a single side, 3D NAND technology vertically stacks multiple layers of memory cells. Based on this technology, storage devices with storage capacities several times greater than those of comparable NAND technologies can be created. This technology allows for higher storage capacities in a smaller space, resulting in significant cost savings, reduced power consumption, and substantial performance improvements.

[0003] However, as the number of stacked layers increases, the fabrication process for gates in memory becomes increasingly complex. During the gate material filling process, uneven filling thickness can easily occur, leading to increased gate resistance and affecting gate conductivity. [Summary of the Invention]

[0004] This invention provides a method for manufacturing a memory, a memory, and a memory system, which is beneficial for manufacturing gates with uniform thickness and improving the conductivity of the gates.

[0005] This invention provides a method for manufacturing a memory, comprising:

[0006] A first stop layer is formed on the substrate;

[0007] A groove is formed in the first stop layer, the groove penetrating the first stop layer and extending into the substrate;

[0008] A second stop layer is formed on the first stop layer, the second stop layer covering the inner wall of the groove;

[0009] A stack layer is formed on the second stop layer, and a memory channel structure is formed in the stack layer that extends through the stack layer and into the substrate;

[0010] A gate gap is formed in the stacked layer, the gate gap penetrating the stacked layer and the second stop layer within the groove, and extending into the substrate;

[0011] A gate structure is formed in the stacked layer, and a gate gap structure is formed in the gate gap.

[0012] Before forming the first stop layer on the substrate, the method further includes: forming a first spacer layer on the substrate, wherein the first stop layer is located on the first spacer layer;

[0013] After forming a first stop layer on the substrate, the method further includes forming a second spacer layer on the first stop layer, wherein the groove extends through the first spacer layer, the first stop layer and the second spacer layer and into the substrate.

[0014] The process further includes, after forming the first stop layer on the substrate, performing a doping process on the first stop layer.

[0015] After forming the first stop layer on the substrate, the method further includes:

[0016] The surface of the first stop layer is subjected to a nitrogen-containing surface treatment.

[0017] After forming the second stop layer on the first stop layer, the process further includes:

[0018] A third spacer layer is formed on the second stop layer, and the second stop layer and the third spacer layer fill the groove;

[0019] Remove a portion of the third spacer layer outside the groove, or remove all of the third spacer layer outside the groove.

[0020] The included angle between the sidewall and bottom wall of the groove is in the range of 100° to 120°.

[0021] After forming the second stop layer on the first stop layer, the process further includes:

[0022] The surface of the second stop layer is subjected to a nitrogen-containing surface treatment.

[0023] The materials of both the first stop layer and the second stop layer include polycrystalline silicon.

[0024] The oxidation rate of the first stopping layer is greater than that of the second stopping layer.

[0025] Wherein, the cross-sectional width of the groove is greater than the sum of the cross-sectional width of the gate gap located in the groove and the cross-sectional width of the second stop layer located in the groove.

[0026] The fabrication method further includes, after forming a stack layer on the second stopping layer:

[0027] A memory channel via is formed in the stack layer, the memory channel via penetrating the stack layer and extending into the substrate;

[0028] The first stop layer is oxidized through the storage channel holes to form necked channel holes;

[0029] A storage function layer and a channel layer are sequentially formed on the inner wall of the necked channel hole to obtain a storage channel structure.

[0030] The method further includes, after forming the gate structure and the gate gap structure in the stack layer through the gate gap:

[0031] A through-contact is formed on the stack layer, the through-contact extending through the stack layer and extending to the second stop layer;

[0032] Remove the substrate to expose the surface of the first stop layer facing away from the stacked layers;

[0033] The exposed surface is selectively etched to expose the end of the channel layer on the side of the first stop layer opposite to the stack layer;

[0034] A semiconductor layer is formed on the side of the first stop layer that is opposite to the stack layer after etching;

[0035] An interlayer dielectric layer is formed on the side of the semiconductor layer opposite to the stack layer;

[0036] A metal interconnect layer is formed on the side of the interlayer dielectric layer opposite to the stack layer, and the semiconductor layer and the through contact are electrically connected to the metal interconnect layer.

[0037] This invention also provides a memory, comprising:

[0038] Semiconductor layer;

[0039] A first stop layer is located on the semiconductor layer, and the first stop layer has a groove penetrating the first stop layer, with a portion of the semiconductor layer filling the groove;

[0040] A second stop layer is located on the first stop layer, and the second stop layer covers the sidewall of the groove;

[0041] A stacked structure located on the second stop layer, the stacked structure having a gate gap structure and a memory channel structure, the memory channel structure including a channel layer and a memory functional layer, the memory channel structure penetrating the stacked structure and the second stop layer, and the channel layer extending into the semiconductor layer; the gate gap structure penetrating the stacked structure and the semiconductor layer within the groove.

[0042] A second spacer layer is provided between the first stop layer and the second stop layer, and the groove penetrates through the first stop layer and the second spacer layer.

[0043] The included angle between the sidewall and bottom wall of the groove is in the range of 100° to 120°.

[0044] The surfaces of the first stop layer and / or the second stop layer have undergone nitrogen-containing surface treatment.

[0045] The oxidation rate of the first stopping layer is greater than that of the second stopping layer.

[0046] Wherein, the cross-sectional width of the groove is greater than the sum of the cross-sectional width of the gate slot structure located in the groove and the cross-sectional width of the second stop layer located in the groove.

[0047] The stack layer also includes a through contact, and the memory further includes an interlayer dielectric layer located on the side of the semiconductor layer opposite to the stack structure, and a metal interconnect layer located on the interlayer dielectric layer. The semiconductor layer and the through contact are electrically connected to the metal interconnect layer.

[0048] To address the aforementioned problems, embodiments of the present invention also provide a memory system, including at least one memory as described in any of the preceding claims, and a controller coupled to the memory, the controller being used to control the memory to perform data write and read operations.

[0049] The memory fabrication method, memory, and memory system provided in this invention involve forming a first stop layer on a substrate, then forming a groove in the first stop layer that penetrates the first stop layer and extends into the substrate, followed by forming a second stop layer on the first stop layer that covers the inner wall of the groove, and forming a stack layer on the second stop layer. A memory channel structure that penetrates the stack layer and extends into the substrate is formed in the stack layer. A gate gap is then formed in the stack layer, and a gate structure and a gate gap structure are formed in the gate gap. This prevents the first stop layer from lifting during the gate process, thus avoiding bulging of the stack layer, improving the uniformity of gate material filling, and enhancing the conductivity of the gate. [Attached Image Description]

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic flowchart of the method for manufacturing a memory provided in an embodiment of this application;

[0052] Figure 2aThis is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0053] Figure 2b This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0054] Figure 2c This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0055] Figure 2c' This is a cross-sectional view of the memory during the manufacturing process provided in another embodiment of this application.

[0056] Figure 2d This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0057] Figure 2d' This is a cross-sectional view of the memory during the manufacturing process provided in another embodiment of this application;

[0058] Figure 2e This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0059] Figure 2f This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0060] Figure 2g This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0061] Figure 2h This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0062] Figure 2h' This is a cross-sectional view of the memory during the manufacturing process provided in another embodiment of this application;

[0063] Figure 2i This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0064] Figure 2j This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0065] Figure 2k This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0066] Figure 2l This is a cross-sectional structural diagram of the memory under different process steps provided in the embodiments of this application;

[0067] Figure 2m This is a cross-sectional view of the memory provided in an embodiment of this application;

[0068] Figure 3 This is a schematic diagram of the memory system provided in an embodiment of this application.

Detailed Implementation Methods

[0069] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] In the description of this application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0071] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. “A plurality” means two or more. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0073] It is understood that the meanings of “on”, “above” and “above” in this application should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intermediary feature or layer (i.e., directly on something), but also that it is “on” something with an intermediary feature or layer.

[0074] In some embodiments, the gate structure of the memory can be fabricated using two methods. One method involves alternatingly stacking the gate dielectric layer to directly form a metal gate structure on the gate dielectric layer. The other method involves alternatingly stacking the gate dielectric layer and the gate sacrificial layer, then forming a gate gap. The gate sacrificial layer is then removed by dry or wet etching through the gate gap to create a void. Conductive material is then filled into the void to form the gate structure. In the second method, bulging is prone to occur at the bottom of the stacked layers during the process of removing the sacrificial layer to form the void, making it difficult to maintain flatness. The bulging becomes more severe with increasing number of stacked layers. Consequently, it is difficult to fill the void with conductive material evenly, resulting in significant differences in the overall thickness of the formed gate structure. In some areas, even breakpoints may occur, leading to increased resistance and poor conductivity in the fabricated gate structure.

[0075] This application provides a method for manufacturing a memory, a memory, and a memory system, which can at least partially solve the above-mentioned technical problems.

[0076] like Figure 1 As shown, Figure 1 A flowchart illustrating a method for manufacturing a memory according to an embodiment of this application is shown. The method includes the following steps S101-S106, wherein:

[0077] Step S101: Form a first stop layer on the substrate;

[0078] Step S102: A groove is formed in the first stop layer, the groove penetrating the first stop layer and extending into the substrate;

[0079] Step S103: A second stop layer is formed on the first stop layer, the second stop layer covering the inner wall of the groove;

[0080] Step S104: A stack layer is formed on the second stop layer, and a memory channel structure is formed in the stack layer that penetrates the stack layer and extends into the substrate.

[0081] Step S105: A gate gap is formed in the stacked layer, the gate gap penetrating the stacked layer and the second stop layer in the groove, and extending into the substrate;

[0082] Step S106: Form a gate structure in the stack layer and form a gate gap structure in the gate gap.

[0083] It should be understood that the steps shown in the above manufacturing method are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps in this process may be performed simultaneously or in a manner different from [the steps described above]. Figure 1 The execution is performed in the order shown.

[0084] Please see Figures 2a to 2m , Figures 2a to 2m This is a cross-sectional view of the memory 10 under different process steps in the above manufacturing method. The following will combine... Figures 2a to 2m Further describe steps S101-S106 above.

[0085] Step S101: Form a first stop layer 12 on the substrate 11.

[0086] Please see below. Figure 2a The substrate 11 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0087] In some embodiments, the material of the first stop layer 12 may include polycrystalline silicon. The first stop layer 12 may be formed on the substrate 11 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic vapor deposition (ALD), or any combination thereof.

[0088] Step S102: A groove H is formed in the first stop layer 12, the groove H passing through the first stop layer 12 and extending into the substrate 11.

[0089] Please see below. Figure 2b The groove H can be formed in the first stop layer 12 by wet or dry etching. In some embodiments, for example... Figure 2a In this process, an oxide layer may be disposed between the first stop layer 12 and the substrate 11. That is, before step S101 above, the method for fabricating the memory 10 further includes: forming a first spacer layer M1 on the substrate 11, with the first stop layer 12 located on the first spacer layer M1. In other words, a first spacer layer M1 is provided between the first stop layer 12 and the substrate 11.

[0090] In some embodiments, after step S101 described above, the method for fabricating the memory 10 further includes forming a second spacer layer M2 on the first stop layer 12. The first spacer layer M1 and the second spacer layer M2 are typically made of oxide materials, and their materials can be the same, such as both including silicon oxide, or they can be different.

[0091] At this time, the groove H penetrates the first spacer layer M1, the first stop layer 12 and the second spacer layer M2, and extends into the substrate 11.

[0092] Step S103: A second stop layer 13 is formed on the first stop layer 12, and the second stop layer 13 covers the inner wall of the groove H.

[0093] Please see below. Figure 2c The second stop layer 13 can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The second stop layer 13 can be made of the same material as the first stop layer 12, such as polycrystalline silicon.

[0094] It should be noted that, in order to minimize the impact on the second stop layer 13 during the subsequent oxidation treatment of the first stop layer 12, the second stop layer 13 and the first stop layer 12 should have different oxidation rates, and the oxidation rate of the first stop layer 12 should be greater than that of the second stop layer 13. In some embodiments, the different oxidation rates can be achieved by doping, for example, by doping the first stop layer 12 while leaving the second stop layer 13 undoped. That is, after step S101 above, the method for fabricating the memory 10 further includes: doping the first stop layer 12. This doping can be p-type doping. In some embodiments, the doping process can be ion implantation, and after doping, lattice damage to the material caused by ion implantation can be repaired using, for example, laser annealing.

[0095] In some embodiments, after step S103, the method of manufacturing the memory further includes: forming a third spacer layer M3 on the second stop layer 13, the second stop layer 13 and the third spacer layer M3 filling the groove H; removing a portion of the third spacer layer M3 outside the groove H, or removing all of the third spacer layer M3 outside the groove H.

[0096] The third spacer layer M3 can be planarized by chemical mechanical polishing (CMP) to remove part of the third spacer layer M3 outside the groove H or to remove all of the third spacer layer M3 outside the groove H.

[0097] The material of the third spacer layer M3 may include oxides, for example, see [link to relevant documentation]. Figure 2c' The silicon oxide layer, or a combination of oxides and nitrides, as shown in the example below. Figure 2c The structure consists of silicon oxide layer M31, silicon nitride layer M32, and silicon oxide layer M33, also known as an ONO structure. The specific configuration depends on the capabilities of the subsequent chemical mechanical polishing (CMP) process. For example, some CMP processes require a nitride as the second stop layer for polishing; in this case, the third spacer layer M3 can be an ONO structure. The structure after polishing can be found in [reference needed]. Figure 2d Some CMP processes use polysilicon as the second stop layer for polishing. In this case, the third spacer layer M3 can be a silicon oxide layer. The structure after polishing can be found in [reference needed]. Figure 2d' .

[0098] Step S104: A stack layer 14 is formed on the second stop layer 13, and a memory channel structure 1411 is formed in the stack layer 14, extending through the stack layer 14 and into the substrate 11.

[0099] Please see below. Figure 2f The stacked layer 14 may include multiple gate spacer layers 142 and gate sacrificial layers 143 stacked together. The stacked layer 14 may be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. In the manufacturing process of the stacked layer 14, different numbers of stacked layers correspond to different stacking heights. For example, the stacked layer 14 may have 8, 32, 64, or 128 layers. The more layers the stacked layer 14 has, the higher the integration density and the more memory cells it forms. The number of stacked layers and the stacking height of the stacked layer 14 can be designed according to actual storage requirements. This application does not impose specific limitations on this.

[0100] The thicknesses of the multiple gate spacer layers 142 may be the same or different, and the thicknesses of the multiple gate sacrificial layers 143 may be the same or different, and can be set according to specific process requirements. The material of the gate spacer layers 142 may include silicon oxide, and the material of the gate sacrificial layers 143 may include silicon nitride.

[0101] In some implementations, please refer to Figures 2e-2f The stacked layer 14 may also have dummy channel structures 1412 extending through the stacked layer 14 and into the substrate 11. The storage channel structures 1411 and dummy channel structures 1412 serve as channel structures 141 and are spaced apart from each other. The number and arrangement of the storage channel structures 1411 and dummy channel structures 1412 can be fabricated according to actual storage requirements. The region on the substrate 11 corresponding to the storage channel structure 1411 extending through the stacked layer 14 can be called storage region A, which can be used to implement the storage function of the memory 10. The dummy channel structure 1412 can be formed in the step region B, mainly for providing mechanical support.

[0102] Specifically, after forming the stack layer 14 on the second stop layer 13, the method for manufacturing the memory 10 may further include:

[0103] A storage channel via (not shown) is formed in the stack layer 14, which extends through the stack layer 14 and into the substrate 11;

[0104] The first stop layer 12 is oxidized through the storage channel hole to form a necked channel hole 1411a;

[0105] A storage function layer 1411b and a channel layer 1411c are sequentially formed on the inner wall of the constricted channel hole 1411a to obtain a storage channel structure 1411.

[0106] The oxidation treatment of the first stop layer 12 may include wet oxidation. The necked-down channel hole 1411a can be considered as a storage channel hole that, after oxidation of the first stop layer 12, results in an increase in the volume of the first stop layer 12 at the oxidation location, leading to a smaller aperture at that location and thus a sealing effect. Compared to the storage channel hole, the necked-down channel hole 1411a has a smaller aperture at the sealing location. Therefore, when forming the storage channel structure 1411, most of the storage functional layer 1411b and the channel layer 1411c will be deposited above the sealing location. Thus, the bottom of the storage channel structure 1411 can be considered to have changed from the bottom of the original storage channel hole to the sealing location, thereby increasing the critical dimension of the bottom of the storage channel structure 1411.

[0107] The storage functional layer 1411b may include a barrier layer, a charge trapping layer, and a tunneling oxide layer (not labeled in the figure). In addition to the storage functional layer 1411b and the channel layer 1411c, the storage channel vias are also filled with a dielectric material (not shown in the figure), such as silicon oxide. In some embodiments, one or more air gaps may be formed during the dielectric material filling process by controlling the channel filling process to alleviate structural stress.

[0108] The storage channel via can be formed using, for example, dry / wet etching processes. A barrier layer, a charge trapping layer, a tunneling oxide layer (i.e., storage functional layer 1411b), a channel layer 1411c, and a dielectric material can be sequentially deposited along the inner wall of the necked channel via 1411a using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The materials for the barrier layer, charge trapping layer, tunneling oxide layer, and channel layer 1411c can be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, to form an "ONOP" structure.

[0109] It should be explained that since the first stop layer 12 is doped while the second stop layer 13 is not, they have different oxidation rates. Therefore, when the first stop layer 12 is subjected to wet oxidation through the storage channel hole, the oxidation process can be controlled so that the first stop layer 12 around the storage channel hole is completely oxidized into oxide, while only a very small amount of the second stop layer 13 is oxidized, or even not oxidized at all.

[0110] Furthermore, when a dummy channel structure 1412 is also formed in the stack layer 14, the method of manufacturing the memory 10 may further include:

[0111] A dummy channel via (not labeled in the figure) is formed on the stack layer 14, which penetrates the stack layer 14 and extends into the substrate 11;

[0112] The dummy channel hole is filled with dielectric material to obtain the dummy channel structure 1412.

[0113] The dummy channel vias can be formed using, for example, dry / wet etching processes. Dielectric material can be filled into the dummy channel vias using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. In some embodiments, one or more air gaps can be formed during the dielectric material filling process by controlling the channel filling process to alleviate structural stress.

[0114] In some embodiments, the dummy channel structure 1412 is fabricated after the storage channel structure 1411, but in other embodiments, the order in which they are fabricated is not limited.

[0115] Step S105: A gate gap 144a is formed in the stacked layer 14. The gate gap 144a penetrates the stacked layer 14 and the second stop layer 13 in the groove H, and extends into the substrate 11.

[0116] Among them, Figure 2g In this process, the gate gap 144a can be formed using, for example, a dry / wet etching process. The gate gap 144a and the channel structure 141 are spaced apart, and their extension depth in the substrate 11 may be the same as or different from the extension depth of the channel structure 141 in the substrate 11.

[0117] It should be noted that the cross-sectional width L of the groove H should be greater than the cross-sectional width L1 of the gate gap 144a in the groove H, and at least greater than the sum of the cross-sectional width L1 of the gate gap 144a (equivalent to the gate gap structure 144 formed later) in the groove H and the cross-sectional width of the second stop layer 13 in the groove H. In this way, it can be ensured that the gate gap 144a only contacts the second stop layer 13 located on the bottom wall of the groove H, and does not directly contact the second stop layer 13 located on the side wall of the groove H or outside the groove H, nor does it directly contact the first stop layer 12. Therefore, when the gate sacrificial layer 143 is removed through the gate gap 144a for gate replacement, liquid and air will not directly contact the second stop layer 13 and the first stop layer 12 located on the side wall of the groove H or outside the groove H through the gate gap 144a, and thus will not affect the second stop layer 13 and the first stop layer 12 located on the side wall of the groove H or outside the groove H, such as causing them to oxidize, resulting in the oxidation site lifting due to volume increase.

[0118] Even assuming the gate gap 144a directly contacts the second stop layer 13 located on the sidewall of the recess H, for example, during the formation of the gate gap 144a, the alignment accuracy might be low, causing the gate gap 144a to shift in position within the recess H. This would result in the second stop layer 13 on the sidewall of the recess H being closer to the gate gap 144a, or even in direct contact. Consequently, during the subsequent gate replacement process, the entry of liquid and air would cause the second stop layer 13 on the sidewall of the recess H to oxidize and expand in volume. However, since this portion of the second stop layer 13 is located within the recess H, its volume change would not affect the second stop layer 13 outside the recess H (it can be considered that the stack layer 14 is mainly supported by the second stop layer 13 outside the recess H), preventing it from lifting and thus not affecting the stack layer 14. Furthermore, the design of the recess H also helps to improve the stress accumulation of the first stop layer 12 and the second stop layer 13, further preventing the first stop layer 12 and the second stop layer 13 from lifting due to localized stress accumulation. In summary, the groove H in this embodiment can prevent the first stop layer 12 and the second stop layer 13 under the stack layer 14 from lifting during etching, thereby preventing the stack layer 14 from bulging and solving the problems caused by related technologies.

[0119] In some embodiments, the surfaces of the first stop layer 12 and the second stop layer 13 may also undergo a nitrogen-containing surface treatment. That is, after step S101 above, the method of manufacturing the memory further includes: performing a nitrogen-containing surface treatment on the surface of the first stop layer 12. After step S103 above, the method of manufacturing the memory further includes: performing a nitrogen-containing surface treatment on the surface of the second stop layer 13. The main function of the nitrogen-containing surface treatment is to generate nitrides on the surface of the workpiece being treated. For example, when performing a nitrogen-containing surface treatment on polysilicon, silicon nitride will be generated on the surface of the polysilicon. Nitrogen nitrides are difficult to oxidize in the oxidation process, thereby further avoiding the warping phenomenon of the upper surfaces of the first stop layer 12 and the second stop layer 13 due to oxidation in the gate replacement process. The nitrogen-containing surface treatment may include nitriding (NH3 Treatment), which is a chemical thermal treatment process in which nitrogen atoms diffuse into the surface layer of a workpiece in a certain medium at a certain temperature.

[0120] In some embodiments, the sidewalls of the groove H can be configured as gentle slopes, allowing nitrogen atoms to penetrate more easily compared to vertical sidewalls, thus further enhancing the nitriding effect. The slope of the gentle slope can be set to 60°-80°, that is, the angle q between the sidewall and bottom wall of the groove H (see [reference]). Figure 2b The range is 100° to 120°.

[0121] Step S106: A gate structure 145 is formed in the stack layer 14, and a gate gap structure 144 is formed in the gate gap 144a.

[0122] In some implementations, please refer to Figure 2h-2i The formation of the gate structure 145 may specifically include the following steps:

[0123] The gate sacrificial layer 143 is removed through the gate gap 144a to form a void 145a;

[0124] The gap 145a is filled with conductive material to form a gate structure 145.

[0125] The stacked layer 14 after forming the gate structure 145 can be regarded as the stacked structure 14' to distinguish the two. All the gate sacrificial layers 143 in the stacked layer 14 can be removed using, for example, a wet etching process to form multiple voids 145a. During this process, if a film layer made of the same material as the gate sacrificial layer 143, such as a silicon nitride layer, exists in the recess H, it can be removed as well. For example, please refer to [link to relevant documentation]. Figure 2h In other embodiments, when there is no silicon nitride layer in the groove H, such as as described above... Figure 2d' The cross-sectional structure of the structure after removing the gate sacrificial layer 143 can be found in the diagram. Figure 2h' .

[0126] The conductive material can be any one or a combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides. The gate structure 145 can be formed in the void 145a using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0127] It should be noted that, please continue to see Figure 2i Since the stacked layer 14 is mainly located on the silicon oxide layer M33 (the third spacer layer M3), and the silicon oxide layer M33 is located on the second stop layer 13, the thickness of the silicon oxide layer M33 will not change when the second stop layer 13 outside the groove H is not oxidized during the gate replacement process. The silicon oxide layer M33 can also be regarded as the gate spacer layer of the bottom selected gate (BSG), which can ensure the uniformity of the thickness of the gate spacer layer, avoid its thickness from increasing, and thus affect the filling uniformity of the BSG when filling the gate material, thereby improving the performance of the gate structure 145.

[0128] In some implementations, please refer to [link / reference]. Figure 2h-2i The formation of the gate gap structure 144 may specifically include the following steps:

[0129] A dielectric layer 144b and a conductive layer 144c are sequentially formed on the inner wall of the gate gap 144a to form a gate gap structure 144.

[0130] The dielectric layer 144b can be deposited from one or more dielectric materials, such as silicon oxide, while the conductive layer 144c can be made of polysilicon. In other embodiments, the gate gap structure 144 may be filled only with dielectric material, depending on design requirements. One or more air gaps can be formed during the channel filling process to reduce structural stress by controlling the channel filling process. The gate gap structure 144 can effectively reduce deformation of the memory region A and provide good support for the memory region A.

[0131] In addition, please see Figure 2j-2m Following step S106, the method for manufacturing the memory 10 further includes:

[0132] A through contact 146 is formed on the stack layer 14, the through contact 146 penetrates the stack layer 14 and extends to the second stop layer 13;

[0133] Remove the substrate 11 to expose the surface of the first stop layer 12 facing away from the stack layer 14;

[0134] Selective etching is performed on the exposed surface to expose the end of the channel layer 1411c on the side of the first stop layer 12 opposite to the stack layer 14;

[0135] A semiconductor layer 15 is formed on the side of the first stop layer 12 that is opposite to the stack layer 14 after etching;

[0136] An interlayer dielectric layer 16 is formed on the side of the semiconductor layer 15 opposite to the stack layer 14;

[0137] A metal interconnect layer 17 is formed on the side of the interlayer dielectric layer 16 away from the stack layer 14, and the semiconductor layer 15 and the through contact 146 are electrically connected to the metal interconnect layer 17.

[0138] Among them, the through contact 146 is usually set in the outer area C (see above for area division). Figure 2f This can be formed using through-silicon-via (TSV) technology. For example, a through-hole is first formed vertically through the stack layer 14 and extending to the second stop layer 13 using a dry / wet etching process, and then a conductive material, such as at least one of tungsten, cobalt, copper, or aluminum, is filled into the through-hole using a thin film deposition process to form a through contact 146.

[0139] Please see Figures 2j-2k The selective etching here mainly includes the etching of ONO and other film layers. Since the first stop layer 12 has been wet-oxidized when the storage channel structure 1411 was fabricated, when selective etching is performed, the part outside the bottom storage channel structure 1411 (which is almost all oxide) can be etched with oxide, which greatly saves the etching process.

[0140] It should be noted that by adding the second stop layer 13, the etching can be stopped at the second stop layer 13. This not only better exposes the bottom of the channel layer 1411c in the memory channel structure 1411 so that the subsequent semiconductor layer 15 can wrap the bottom of the channel layer 1411c, but also helps to control the process uniformity during the removal of the substrate 11 and ensures the uniformity of the channel layer 1411c after removing the memory functional layer 1411b in the memory channel structure 1411.

[0141] In some implementations, please refer to Figure 2l The semiconductor layer 15 is made of polycrystalline silicon. It can be formed on the side of the first stop layer 12 away from the stack layer 14 using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. After doping, it is processed using a process such as laser annealing to obtain the semiconductor layer 15. The semiconductor layer 15 is in contact with the bottom of the channel layer 1411c, thereby realizing the electrical connection between the storage channel structure 1411 and the semiconductor layer 15.

[0142] In some implementations, please refer to Figure 2mThe material of the interlayer dielectric layer 16 can be one or more dielectric materials, such as silicon oxide. The material of the metal interconnect layer 17 can include conductive materials such as tungsten, cobalt, copper, and aluminum. The through contact 146 may not be in contact with the semiconductor layer 15. The semiconductor layer 15 and the metal interconnect layer 17, as well as the through contact 146 and the metal interconnect layer 17, can be connected through contact N, which is made of a conductive material.

[0143] In summary, the memory fabrication method provided in this embodiment, by forming a first stop layer 12 on a substrate 11, then forming a groove H in the first stop layer 12, the groove H penetrating the first stop layer 12 and extending into the substrate 11, then forming a second stop layer 13 on the first stop layer 12, the second stop layer 13 covering the inner wall of the groove H, and forming a stack layer 14 on the second stop layer 13, the stack layer 14 forming a memory channel structure 1411 penetrating the stack layer 14 and extending into the substrate 11, then forming a gate gap 144a in the stack layer 14, and through the gate gap 144a, forming a gate structure 145 and a gate gap structure 144 in the stack layer 14, can prevent the first stop layer 12 from lifting during the gate replacement process, thereby avoiding bulging of the stack layer 14, which is beneficial to the uniformity of gate material filling and improves the conductivity of the gate.

[0144] Based on the above-described methods for fabricating the memory, this application also provides a memory fabricated using any of the methods described above. Please refer to [link to relevant documentation]. Figure 2m The memory 10 includes: a semiconductor layer 15; a first stop layer 12 located on the semiconductor layer 15, the first stop layer 12 having a recess H extending through the first stop layer 12, and a portion of the semiconductor layer 15 filling the recess H; a second stop layer 13 located on the first stop layer 12, and the second stop layer 13 covering the sidewall of the recess H; a stack structure 14' located on the second stop layer 13, the stack structure 14' having a gate gap structure 144 and a memory channel structure 1411, wherein the memory channel structure 1411 includes a channel layer 1411b and a memory function layer 1411c, the memory channel structure 1411 extending through the stack structure 14' and the second stop layer 13, and the channel layer 1411b extending into the semiconductor layer 15; the gate gap structure 144 extending through the stack structure 14' and the semiconductor layer 15 within the recess H.

[0145] It should be noted that the first stop layer 12 does not cover the entire semiconductor layer 15, and the upper surface of the semiconductor layer 15 is not flat, but has protrusions. This is mainly because during the fabrication of the memory 10, a portion of the first stop layer 12 is removed and used to fill the semiconductor layer 15. For example, the first stop layer 12 around the memory channel structure 1411 is first oxidized to become oxide, and these oxides are subsequently removed in selective etching (see details). Figures 2d-2k After that, the semiconductor layer 15 is formed, that is, the first stop layer 12 around the memory channel structure 1411 is removed. The space obtained after removal will form a protrusion when the semiconductor layer 15 is formed, so that the surface of the semiconductor layer 15 is not a flat surface.

[0146] In some embodiments, a second spacer layer M2 is further provided between the first stop layer 12 and the second stop layer 13, and the groove H penetrates through the first stop layer 12 and the second spacer layer M2.

[0147] In some embodiments, the included angle between the sidewall and bottom wall of the groove H ranges from 100° to 120°.

[0148] In some embodiments, the surfaces of the first stop layer 12 and / or the second stop layer 13 are treated with a nitrogen-containing surface treatment.

[0149] In some embodiments, both the first stop layer 12 and the second stop layer 13 are made of polycrystalline silicon.

[0150] In some embodiments, the oxidation rate of the first stop layer 12 should be greater than the oxidation rate of the second stop layer 13.

[0151] In some embodiments, the cross-sectional width of the groove H is greater than the sum of the cross-sectional width of the gate slot structure 144 located in the groove H and the cross-sectional width of the second stop layer 13 located in the groove H.

[0152] In some embodiments, the stack structure 14' is further provided with a through contact 146, and the memory 10 also includes an interlayer dielectric layer 16 located on the side of the semiconductor layer 15 away from the stack structure 14', and a metal interconnect layer 17 located on the interlayer dielectric layer 16, wherein the semiconductor layer 15 and the through contact 146 are electrically connected to the metal interconnect layer 17 respectively.

[0153] It is easy to understand that since the content and structure involved in the description of manufacturing methods S101-S106 above can be fully or partially applied to the memory described here, related or similar content will not be repeated.

[0154] In addition, please see Figure 3This application also provides a memory system 100, which includes at least one of the aforementioned types of memory 10 and a controller 20 coupled to the memory 10. The controller 20 is used to control the memory 10 to perform data write and read operations. The controller 20 is also connected to an external host, which can transmit user instructions and stored data to the controller 20. The user instructions may include write instructions, erase instructions, and read instructions, etc. The controller 20 can determine which storage location in the memory 10 to write, erase, and read based on these instructions.

[0155] The memory also includes peripheral circuitry 18, which is configured to perform read, write, erase, and verification operations on the memory cells in the memory channel structure. Peripheral circuitry 18 may include word line drivers, bit line drivers, column decoders, sensing circuits, data buffers, program verification logic, and erase verification circuits, etc., which can perform the above operations according to the acquired computer program instructions.

[0156] In the examples of this application, memory 10 is not limited to three-dimensional NAND memory. Without departing from the disclosure or teachings of this application, memory 10 may be implemented as various other types of non-volatile memory that can retain the stored data when the power is disconnected.

[0157] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a memory, characterized in that, include: A first stop layer is formed on the substrate; A groove is formed in the first stop layer, the groove penetrating the first stop layer and extending into the substrate; A second stop layer is formed on the first stop layer, the second stop layer covering the inner wall of the groove; A stack layer is formed on the second stopping layer; A memory channel via is formed in the stack layer, the memory channel via penetrating the stack layer and extending into the substrate; The first stop layer is oxidized through the storage channel holes to form necked channel holes; A storage function layer and a channel layer are sequentially formed on the inner wall of the necked channel hole to obtain a storage channel structure; A gate gap is formed in the stacked layer, the gate gap penetrating the stacked layer and the second stop layer within the groove, and extending into the substrate; A gate structure is formed in the stacked layer, and a gate gap structure is formed in the gate gap.

2. The method for manufacturing a memory according to claim 1, characterized in that, Before forming the first stop layer on the substrate, the method further includes: forming a first spacer layer on the substrate, wherein the first stop layer is located on the first spacer layer; After forming a first stop layer on the substrate, the method further includes forming a second spacer layer on the first stop layer, wherein the groove extends through the first spacer layer, the first stop layer and the second spacer layer and into the substrate.

3. The method for manufacturing a memory according to claim 1, characterized in that, After forming the first stop layer on the substrate, the method further includes: performing a doping process on the first stop layer.

4. The method for manufacturing a memory according to claim 1, characterized in that, After forming the first stop layer on the substrate, the method further includes: The surface of the first stop layer is subjected to a nitrogen-containing surface treatment.

5. The method for manufacturing a memory according to claim 1, characterized in that, After forming the second stop layer on the first stop layer, the process further includes: A third spacer layer is formed on the second stop layer, and the second stop layer and the third spacer layer fill the groove; Remove a portion of the third spacer layer outside the groove, or remove all of the third spacer layer outside the groove.

6. The method for manufacturing a memory according to claim 1, characterized in that, The included angle between the sidewall and bottom wall of the groove is in the range of 100°~120°.

7. The method for manufacturing a memory according to claim 1, characterized in that, After forming the second stop layer on the first stop layer, the process further includes: The surface of the second stop layer is subjected to a nitrogen-containing surface treatment.

8. The method for manufacturing a memory according to claim 1, characterized in that, Both the first stop layer and the second stop layer are made of polycrystalline silicon.

9. The method for manufacturing a memory according to claim 1, characterized in that, The oxidation rate of the first stopping layer is greater than that of the second stopping layer.

10. The method for manufacturing a memory according to claim 1, characterized in that, The cross-sectional width of the groove is greater than the sum of the cross-sectional width of the gate gap located in the groove and the cross-sectional width of the second stop layer located in the groove.

11. The method for manufacturing a memory according to claim 10, characterized in that, After forming the gate structure in the stacked layer and the gate gap structure in the gate gap, the method further includes: A through-contact is formed on the stack layer, the through-contact extending through the stack layer and extending to the second stop layer; Remove the substrate to expose the surface of the first stop layer facing away from the stacked layers; The exposed surface is selectively etched to expose the end of the channel layer on the side of the first stop layer opposite to the stack layer; A semiconductor layer is formed on the side of the first stop layer that is opposite to the stack layer after etching; An interlayer dielectric layer is formed on the side of the semiconductor layer opposite to the stack layer; A metal interconnect layer is formed on the side of the interlayer dielectric layer opposite to the stack layer, and the semiconductor layer and the through contact are electrically connected to the metal interconnect layer.

12. A memory, characterized in that, include: Semiconductor layer; A first stop layer is located on the semiconductor layer, and the first stop layer has a groove penetrating the first stop layer, with a portion of the semiconductor layer filling the groove; A second stop layer is located on the first stop layer, and the second stop layer covers the sidewall of the groove; A stacked structure located on the second stop layer, the stacked structure having a gate gap structure and a necked channel via, the memory channel structure including a channel layer and a memory functional layer, the necked channel via penetrating the stacked structure and the second stop layer and extending into the substrate, the inner wall of the necked channel via being sequentially covered by the memory functional layer and the channel layer, the memory functional layer and the channel layer together constituting the memory channel structure; the gate gap structure penetrating the stacked structure and the semiconductor layer within the recess.

13. The memory according to claim 12, characterized in that, A second spacer layer is provided between the first stop layer and the second stop layer, and the groove penetrates through the first stop layer and the second spacer layer.

14. The memory according to claim 12, characterized in that, The included angle between the sidewall and bottom wall of the groove is in the range of 100°~120°.

15. The memory according to claim 12, characterized in that, The surfaces of the first stop layer and / or the second stop layer have undergone nitrogen-containing surface treatment.

16. The memory according to claim 12, characterized in that, The oxidation rate of the first stopping layer is greater than that of the second stopping layer.

17. The memory according to claim 12, characterized in that, The cross-sectional width of the groove is greater than the sum of the cross-sectional width of the gate slot structure located in the groove and the cross-sectional width of the second stop layer located in the groove.

18. The memory according to claim 12, characterized in that, The stack structure also includes a through contact, and the memory further includes an interlayer dielectric layer located on the side of the semiconductor layer opposite to the stack structure, and a metal interconnect layer located on the interlayer dielectric layer. The semiconductor layer and the through contact are electrically connected to the metal interconnect layer, respectively.

19. A memory system, characterized in that, It includes at least one memory as described in any one of claims 12-18, and a controller coupled to the memory, the controller being used to control the memory to perform data write and read operations.

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