Three-dimensional memory

Abstract

The application provides a three-dimensional memory, comprising: a storage array structure, comprising a first storage array structure and a second storage array structure arranged along a first direction; a stepped structure located between the first storage array structure and the second storage array structure, comprising: a bridge structure connecting the first storage array structure and the second storage array structure; and a first stepped group arranged on one side of the bridge structure along a second direction perpendicular to the first direction, comprising a plurality of steps located at different heights, each step being electrically connected to at least one of the first storage array structure and the second storage array structure through the bridge structure; wherein a step near the middle of the bridge structure in the plurality of steps is located at a first height, and the first height is the maximum value in the different heights.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory. Background Technology

[0002] In some three-dimensional memories, a ladder structure for word line outgoings is located in the middle of the storage plane, enabling, for example, a line decoder to drive word lines bidirectionally in opposite directions from the middle position of the storage plane, thereby reducing resistance in the load and connecting word lines separated by the ladder structure via a bridging structure. Summary of the Invention

[0003] This application provides a three-dimensional memory, comprising: a memory array structure including a first memory array structure and a second memory array structure disposed along a first direction; a stepped structure located between the first memory array structure and the second memory array structure, including: a bridging structure connecting the first memory array structure and the second memory array structure; and a first stepped group disposed along a second direction perpendicular to the first direction on one side of the bridging structure, including multiple steps located at different heights, each step being electrically connected to at least one of the first memory array structure and the second memory array structure through the bridging structure; wherein, the step closest to the middle of the bridging structure among the multiple steps is located at a first height, the first height being the maximum value among the different heights.

[0004] In some implementations, the multiple steps are divided into multiple pairs of steps that are inclined toward each other.

[0005] In some implementations, multiple steps in the first step group are asymmetrically distributed relative to the second direction.

[0006] In some implementations, each step includes multiple steps, and in a first set of steps, the total thickness of the multiple steps in each step does not overlap with each other in the height direction.

[0007] In some implementations, along the direction away from the center of the bridging structure, the height of each step between the step near the center of the bridging structure and the first memory array structure decreases sequentially, and the height of each step between the step near the center of the bridging structure and the second memory array structure decreases sequentially.

[0008] In some embodiments, the three-dimensional memory further includes a second set of steps disposed along a second direction on the other side of the bridging structure, wherein the first set of steps and the second set of steps are asymmetrically distributed with respect to the bridging structure.

[0009] In some embodiments, along a direction away from the center of the bridging structure, the steps near the center of the bridging structure have the same inclination orientation as the steps between the first memory array structure and the steps between the second memory array structure. In some embodiments, the three-dimensional memory further includes a semiconductor layer, and the bridging structure includes alternating stacked dielectric layers and conductive layers, wherein the cross-sectional dimension of the conductive layer in a direction perpendicular to the first direction is inversely proportional to the distance between the conductive layer and the semiconductor layer.

[0010] In some embodiments, the staircase includes multiple steps, which are electrically connected to at least one of the first and second memory array structures via a bridging structure.

[0011] According to some embodiments of the present application, the three-dimensional memory, by setting a step with a first height near the middle of the bridging structure, can reduce the load resistance when the step is electrically connected to the first memory array structure and the second memory array structure, alleviate the resistance delay phenomenon, and facilitate the synchronous control of the first memory array structure and the second memory array structure through the word line contacts on the step. Attached Figure Description

[0012] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0013] Figure 1 This is a top view schematic diagram of a three-dimensional memory according to an embodiment of this application;

[0014] Figure 2 It is based on Figure 1 A perspective schematic diagram of the stepped structure of a three-dimensional memory.

[0015] Figure 3 It is based on Figure 1 A cross-sectional schematic diagram of the bridging structure of the three-dimensional memory is shown;

[0016] Figure 4 It is based on Figure 2 A perspective view of the step structure during the fabrication process is shown.

[0017] Figure 5A This is a perspective view of the stepped structure of a three-dimensional memory according to another embodiment of this application;

[0018] Figure 5B yes Figure 5A A front view schematic diagram of the stepped structure is shown; and

[0019] Figures 6A to 6D This is a front view schematic diagram of multiple steps according to some embodiments of this application. Detailed Implementation

[0020] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0021] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0022] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0023] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0024] As used herein, when a semiconductor layer is located on the lowest plane of a three-dimensional memory, whether one component (e.g., a layer or device) of the three-dimensional memory is "above," "on top of," or "below" another component (e.g., a layer or device) is in the vertical direction. That is, relative to the vertical direction in which the semiconductor layer of the three-dimensional memory extends. The same concept is used throughout this application to describe spatial relationships.

[0025] It should be noted that the x-axis, y-axis, and z-axis shown in the various figures of this application are used to further illustrate the spatial relationships between the various structures in the three-dimensional memory. In an exemplary embodiment, the x-axis direction, as referred to below, may be a first direction of the three-dimensional memory 100, such as the word line direction; the y-axis direction may be a second direction perpendicular to the first direction, such as the bit line direction; and the z-axis direction is perpendicular to both the x-axis and y-axis directions, such as the height direction of the three-dimensional memory. The same concepts used to describe spatial relationships are applied throughout this application.

[0026] Figure 1This is a top view schematic diagram of a three-dimensional memory 100 according to an embodiment of this application. Figure 2 yes Figure 1 A perspective view of the stepped structure 130 of the three-dimensional memory 100 is shown. Figure 3 yes Figure 1 A cross-sectional schematic diagram of the bridging structure 135 of the three-dimensional memory 100 is shown.

[0027] like Figure 1 As shown, the three-dimensional memory 100 includes a first memory array structure 110, a second memory array structure 120, and a stepped structure 130. The first memory array structure 110 and the second memory array 120 are arranged along the x-axis direction. In an exemplary embodiment, the first memory array 110 may include a first stacked structure (not shown) of multiple dielectric layers (e.g., first dielectric layers) and multiple conductive layers (e.g., first conductive layers) alternately stacked in the z-axis direction. The material of the first conductive layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), polycrystalline silicon (e.g., doped polycrystalline silicon), silicides, or any combination thereof. The material of the first dielectric layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Exemplarily, the material of the first conductive layer may be tungsten, and the material of the first dielectric layer may be silicon oxide. The number of pairs of first dielectric layers and first conductive layers may be, for example, 32, 64, 96, or 128. Exemplarily, the number of pairs of first dielectric layers and first conductive layers may be positively correlated with the number of memory cells in the three-dimensional memory 100.

[0028] In an exemplary embodiment, the first memory array structure 110 may include, for example, a plurality of channel structures (e.g., 111) extending through the first stacked structure along the z-axis direction. Exemplarily, the channel structure 111 may have a generally cylindrical, frustum-shaped, or prism-like outer contour shape. Exemplarily, the channel structure 111 may include a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) sequentially disposed from the outside in. In this application, the charge blocking layer, charge trapping layer, and tunneling layer may, for example, be referred to as memory functional layers. Exemplarily, the materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide. The material of the channel layer may include, for example, polysilicon.

[0029] In an exemplary embodiment, the storage function layer and the channel layer in the channel structure 111, together with a portion corresponding to a first conductive layer in the first stacked structure and the first conductive layer, constitute a memory cell. The first conductive layer may, for example, serve as a control gate of a memory cell or a word line (e.g., a first word line) of multiple memory cells. In some embodiments, multiple memory cells arranged along the extension direction of the channel structure 111 are arranged in series, for example, in the z-axis direction, and share the channel layer. Exemplarily, under the voltage control of the first conductive layer, each memory cell causes charge carriers (e.g., electrons) in the channel layer to enter the charge trapping layer, or causes charge carriers in the charge trapping layer to retreat back to the channel layer, thereby placing the memory cell in a programmed state or an erased state (unprogrammed state).

[0030] In an exemplary embodiment, multiple channel structures (e.g., 111) may be distributed in a two-dimensional array relative to the xy plane, thereby causing multiple memory cells to be distributed in a three-dimensional array relative to the xy plane. As described above, the multiple channel structures (e.g., 111) and the first stacked structure may be referred to as "first memory array structure 110".

[0031] In an exemplary embodiment, the second memory array structure 120 may include a second stacked structure (not shown) of multiple dielectric layers (e.g., second dielectric layer / second word line) and multiple conductive layers (e.g., second conductive layer) alternately stacked in the z-axis direction. It is understood that since the second memory array structure 120 may have a similar internal structure to the first memory array structure 110, further details are omitted here.

[0032] In an exemplary embodiment, the first memory array structure 110 and the second memory array structure 120 may be divided into a plurality of memory blocks 101 by a plurality of gate slot structures (e.g., first gate slot structure 151) that are parallel to each other in the y-axis direction. Exemplarily, each memory block 101 may be further divided into a plurality of finger-shaped memory regions 102 by some of a plurality of gate slot structures (e.g., second gate slot structure 152) that are parallel to each other in the y-axis direction and have "H" cutouts 153.

[0033] like Figure 1As shown, the stepped structure 130 is located between the first memory array structure 110 and the second memory array structure 120. In an exemplary embodiment, as will be described below, the stepped structure 130 may include a bridging structure 135 for (physically and electrically) connecting the first memory array structure 110 and the second memory array structure 120, and a first step group 103-1 and a second step group 130-2 disposed on both sides of the bridging structure 135 along the y-axis direction. Exemplarily, the three-dimensional memory 100 may also include a plurality of word line contacts (e.g., 112) in corresponding regions of the first step group 103-1 and the second step group 103-2 of the stepped structure 130 to land at each step in each step of the stepped structure 130.

[0034] The following is combined Figure 2 The stepped structure 130 is illustrated by way of example.

[0035] In an exemplary implementation, such as Figure 2 As shown, in the stepped structure 130, multiple steps (e.g., 131-1, 131-2, 132-1, 132-2, 133-1, 133-2, and 134-1, 134-2) in the first stepped group 103-1 on one side of the bridging structure 135 are arranged (e.g., aligned) along the x-axis and located at different heights. For example, step 131-1 is located at height H. 131-1 At this location, staircase 131-2 is situated at height H. 131-2 At this location, staircase 132-1 is situated at height H. 132-1 At this location, staircase 132-2 is situated at height H. 132-2 At this location, step 133-1 is situated at height H. 133-1 At this location, step 133-2 is situated at height H. 133-2 At this location, step 134-1 is situated at height H. 134-1 At this location, staircase 134-2 is situated at height H. 134-2 Place.

[0036] The structure of the staircase is further illustrated below using step 131-1 as an example. In an exemplary embodiment, step 131-1 may include a plurality of dielectric layers (e.g., third dielectric layers) and a plurality of conductive layers (e.g., third conductive layers) 137 alternately stacked in the z-axis direction. Each third dielectric layer and third conductive layer in step 131-1 may correspond one-to-one with each first dielectric layer and first conductive layer in the first stacked structure at the same height. For example, each third dielectric layer and third conductive layer 137 in step 131-1 may be physically connected to each first dielectric layer and second conductive layer in the first stacked structure at the same height to achieve electrical connection.

[0037] In an exemplary embodiment, the staircase 131-1 includes multiple steps. It should be noted that, in this application, a step may refer to a structure having two staggered (or aligned) horizontal first surfaces (e.g., first surfaces parallel to the xy plane) and a second surface vertically (or substantially vertically) connecting the two horizontal first surfaces. Exemplarily, the first surface of a step may be the surface of a third conductive layer. Exemplarily, the offset distance of the two first surfaces in a step of the staircase 131-1 in the z-axis direction may, for example, be the sum of the thicknesses of a pair of third dielectric layers and a third conductive layer. Optionally, the second surfaces in adjacent steps of the staircase 131-1 may be offset by the same distance in the x-axis direction. Exemplarily, the first surface in each step may serve as a word line contact 112 extending along the z-axis direction (see reference). Figure 1 The "landing zone" of the step, in other words, the word line contact 112 contacts and electrically connects to the third conductive layer on the first surface of each step, for leading out the third conductive layer. Optionally, each of the plurality of steps 131-1, 131-2, 132-1, 132-2, 133-1, 133-2 and 134-1, 134-2 may have the same number of steps.

[0038] It is understood that, since each step comprises multiple steps, the height of the step as referred to in this application can be referenced to the height of the same step at the same opposite horizontal plane in the z-axis direction (e.g., the horizontal plane where the lowest plane of the first stacked structure in the first storage array structure 110 is located in the z-axis direction), such as the height of the top step or the height of the bottom step. In this application, the height of the top step in each step is referred to as the height of the step.

[0039] In an exemplary embodiment, the multiple steps 131-1, 131-2, 132-1, 132-2, 133-1, 133-2, 134-1 and 134-2 in the first step group 103-1 can be divided into multiple step pairs, such as the first step pair 131-1 / 131-2, the second step pair 132-1 / 132-2, the third step pair 133-1 / 133-2 and the fourth step pair 134-1 / 134-2. For example, each step pair 131-1 / 131-2, 132-1 / 132-2, 133-1 / 133-2 and 134-1 / 134-2 may have an inclined orientation facing each other. For example, in the first step pair 131-1 / 131-2, the inclined orientation of step 131-1 is the positive x-axis direction, and the inclined orientation of step 131-2 is the negative x-axis direction.

[0040] Figure 4 yes Figure 2 A perspective view of the step structure 130 during its fabrication process is shown. (See diagram below.) Figure 4As shown, multiple step pairs (e.g., first step pair 131-1' / 131-2') located at the same height in the first step group 103-1' are first formed by a trim-etch process, and then each step in the multiple step pairs (e.g., first step pair 131-1' / 131-2') is located at a different height by multiple chop processes (see reference). Figure 2 For example, multiple step pairs (e.g., first step pair 131-1' / 131-2') located at the same height can be formed in the same trimming-etching process through mask design, thereby simplifying the manufacturing process of multiple steps, such as in the first step group 103-1'. Furthermore, compared to forming the step structure individually through a trimming-etching process, the number of trimming-etching cycles can be reduced by using multiple trimming processes, improving production efficiency. Meanwhile, when the total number of steps in multiple steps is large, forming the step structure individually through a trimming-etching process requires a thicker photoresist layer, posing a challenge to the photolithography process. In this application, by providing multiple step pairs tilted towards each other and located at different heights in the first step group 103-1', the manufacturing difficulty of the step structure is also reduced.

[0041] Refer again Figure 2 The bridging structure 135 can connect the first memory array structure 110 and the second memory array structure 120 in the x-axis direction; for example, the bridging structure 135 extends along the x-axis direction. In an exemplary embodiment, the bridging structure 135 may include a conductive layer (e.g., a fourth conductive layer 1352) corresponding one-to-one with the conductive layers (e.g., the first conductive layer and the second conductive layer) in the first memory array structure 110 and the second memory array structure 120. Figure 3 The first conductive layer in the first memory array structure 110 and the second conductive layer in the second memory array structure 120 are physically connected through the fourth conductive layer 1352 in the bridging structure 135, so that the first conductive layer and its corresponding second conductive layer are electrically connected through the corresponding fourth conductive layer 1352. The fourth dielectric layer 1351 is located between adjacent fourth conductive layers (e.g., 1352) to provide electrical isolation between adjacent fourth conductive layers (e.g., 1352).

[0042] In an exemplary embodiment, selection step structures 136-1 and 136-2 are located between the first memory array structure 110 and the step structure 130, and between the step structure 130 and the second memory array structure 120, respectively. Exemplarily, the selection gate step structures 136-1 and 136-2 allow the conductive contacts of the top selection gate to land at each step of its respective step.

[0043] Figure 3 yes Figure 1 A schematic cross-sectional view of the bridging structure 135 of the three-dimensional memory 100 is shown. Exemplarily, Figure 3 The bridging structure 135 shown can be, for example, cut in a direction perpendicular to the x-axis. Figure 3 As shown, exemplarily, the bridging structure 135 may be located on one side of the semiconductor layer 141. For example, when the semiconductor layer 141 is at its lowest horizontal plane in the z-axis direction, the bridging structure 135 may be located above the semiconductor layer 141. It should be noted that the material of the semiconductor layer 141 includes, but is not limited to, semiconductor materials such as silicon (e.g., monocrystalline silicon or polycrystalline silicon). Exemplarily, the dimension of the bridging structure 135 in the y-axis direction is inversely proportional to the distance between the bridging structure 135 and the semiconductor layer 141. Specifically, the cross-sectional dimensions of each fourth conductive layer (e.g., 1352) in the bridging structure 135 in the direction perpendicular to the x-axis are inversely proportional to the distance between the current fourth conductive layer (e.g., 1352) and the semiconductor layer 141. As described above, in cases where multiple steps at different heights are formed, for example, by combining trimming-etching and reduction processes, the bridging structure 135 can be formed from the retained portion that has not undergone trimming-etching and reduction processes. This structure of the bridging structure 135 helps reduce the manufacturing difficulty of multiple steps, such as in the first step group 103-1, and provides good compatibility with the manufacturing processes of multiple steps. Furthermore, according to this exemplary embodiment, the load resistance of the bridging structure 135 in the x-axis direction gradually increases along a direction away from the semiconductor layer 141 (e.g., the positive z-axis direction).

[0044] In an exemplary implementation, such as Figure 3 As shown, the dummy channel structure 113 penetrates multiple fourth dielectric layers 1351 and multiple fourth conductive layers 1352 in the bridging structure 135 along the z-axis direction. Exemplarily, the dummy channel structure 113 may have an outer contour structure similar to that of the channel structure 111 and may be used, for example, to provide mechanical support and / or load balancing. Exemplarily, in the bridging structure 135, multiple dummy channel structures (e.g., 113 (reference...)...) Figure 1 It can be distributed in a two-dimensional array on the xy plane.

[0045] Refer again Figure 2 In one exemplary embodiment, in the first step group 103-1, the third conductive layer corresponding to each step in the step 131-2 can be electrically connected to the first memory array structure 110 and the second memory array structure 120 via a fourth conductive layer 1352 extending in the negative x-axis direction and the positive x-axis direction, respectively, through the bridging structure 135. For example... Figure 2 The dashed arrow in the middle represents the current path when the third conductive layer in step 131-2 is electrically connected to the first memory array structure 110 and the second memory array structure 120.

[0046] In another exemplary embodiment, the third conductive layer corresponding to each step in the staircase 131-1 can be electrically connected to the second memory array structure 120 via a fourth conductive layer 1352 extending in the positive x-axis direction through the bridging structure 135. However, the third conductive layer corresponding to each step in the staircase 131-1 may not be electrically connected to the first memory array structure 110 via the bridging structure 135, because the third conductive layer of the staircase 131-1 extending in the negative x-axis direction and the first conductive layer in the first memory array structure 110 are not disconnected.

[0047] like Figure 2 As shown, in the first set of steps 103-1, step 132-2, which is close to the middle of the bridging structure 135 (e.g., approximately the middle part of the bridging structure 135 in the y-axis direction) among the multiple steps 131-1, 131-2, 132-1, 132-2, 133-1, 133-2, 134-1, and 134-2, is located at a height H. 132-2 This is the maximum height among the other steps in the first stair group 103-1. For example, for the multiple steps 131-1, 131-2, 132-1, 132-2, 133-1, 133-2, 134-1, and 134-2 in the first stair group 103-1, the height of step 132-2 is higher than the heights of steps 131-1, 131-2, 132-1, 133-1, 133-2, 134-1, and 134-2. For instance, the height of the top step in step 132-2 is higher than the height of the top steps of steps 131-1, 131-2, 132-1, 133-1, 133-2, 134-1, and 134-2. In this application, the height H of step 132-2, which is located near the middle of the bridging structure 135, is... 132-2 It can be called the highest altitude.

[0048] In an exemplary embodiment, as described above, when multiple steps 131-1, 131-2, 132-1, 132-2, 133-1, 133-2, 134-1, and 134-2 are divided into multiple pairs of steps with mutually facing inclined orientations, the number of multiple steps can be even, as referenced. Figure 2 In another exemplary embodiment, the number of steps may also be odd. In other words, this application is not limited to the case where multiple steps in, for example, the first set of steps 103-1 are divided into multiple pairs of steps, but the scope of protection of this application covers all embodiments in which the first height of the step located in the middle of the bridging structure 135 in, for example, the first set of steps 103-1 is higher than the height of the other steps.

[0049] In the bridging structure of some related three-dimensional memory technologies, the arrangement of multiple steps in the step group on one side of the bridging structure results in a large load resistance and severe resistance delay when multiple steps are electrically connected to the first and second memory array structures through the bridging structure. This is not conducive to the synchronous control of the first and second memory array structures through the word line contacts on each step of each step.

[0050] According to some exemplary embodiments of this application, a step 132-2 at a first height is disposed in the middle of a bridging structure 135. When the third conductive layer in each step of the step 132-2 is electrically connected to the first memory array structure 110 and the second memory array structure 120 via the bridging structure 135, the distance that the current flows through the fourth conductive layer 1352 at the top of the bridging structure 135 can be shortened to about half, for example. This can reduce the load resistance when the step 132-2 is electrically connected to the first memory array structure 110 and the second memory array structure 120, alleviate the resistance delay phenomenon, and facilitate the synchronous control of the first memory array structure 110 and the second memory array structure 120 through word line contacts on the step, such as the step 132-2 at the first height.

[0051] Figure 5A This is a perspective view of a stepped structure 230 of a three-dimensional memory according to another embodiment of this application. Figure 5A As shown, in the first step group 203-1, located in the first storage array structure 110 (reference) Figure 1 The multiple steps 232-1, 231-2 between steps 232-2 and steps 232-2, as well as the height H of the (top step) where 231-1 is located. 232-1 H 231-2 and H 231-1 Decreasing sequentially. Similarly, located in the second memory array structure 120 (reference) Figure 1 The height H of the (top step) where multiple steps 233-1, 233-2, 234-1, and 234-2 are located between step 232-2 and step 233-2. 233-1 H 233-2 H 234-1 and H 234-2 The height of the multiple steps decreases sequentially. According to the arrangement of the multiple steps in this exemplary embodiment, the height of the multiple steps gradually decreases from the center of the bridging structure to both sides, which further balances the load resistance when each step is electrically connected to the first and second memory array structures, and further balances the resistance delay phenomenon.

[0052] In an exemplary embodiment, Figure 5B for Figure 5A The diagram shown is a front view of the stepped structure 230 of the three-dimensional memory, as follows. Figure 5B As shown, the total thickness of multiple steps in each step of the first step group 203-1 has a corresponding distance in the z-axis direction. For example, the total thickness of multiple steps in step 231-1 corresponds to a distance D in the z-axis direction. 231-1 The total thickness of the multiple steps from 231-2 to 234-2, along the z-axis, corresponds to the distances D respectively. 231-2 D 232-1 D 232-2 D 233-1 D 233-2 D 234-1 and D 234-2 Various distances D 231-1 ~D 234-2 They do not overlap in the z-axis direction, that is, the distances D are not overlapping. 231-1 ~D 234-2 Any two of them do not overlap in the z-axis direction. As described above, each step of each staircase is used to lead out the third conductive layer, and then to lead out the first memory array structure 110 and the second memory array structure 120 (see reference). Figure 1 The first and second letter lines in the example. According to the arrangement of multiple steps in this exemplary embodiment, the repetitive extension of the same third conductive layer by each step in each step can be avoided, which helps to reduce the space occupied by the step structure and save manufacturing area.

[0053] In the exemplary implementation, refer again Figure 5A The multiple steps in the first step group 203-1 are asymmetrically distributed with respect to the y-axis direction. The arrangement of the multiple steps according to this exemplary embodiment helps to balance the mechanical stress of the multiple steps in the first step group 203-1. Simultaneously, by ensuring that the total thickness of the multiple steps in each step of the first step group 203-1 does not overlap in the z-axis direction, it is possible to achieve both saving manufacturing area and balancing mechanical stress.

[0054] In the exemplary implementation, refer again Figure 5A For the first step group 203-1 and the second step group 203-2 on both sides of the bridging structure 235 along the y-axis direction, the first step group 203-1 and the second step group 203-2 can be arranged asymmetrically with respect to the bridging structure 235. For example, in the first step group 203-1 and the second step group 203-2, two steps within the same x-axis coordinate range can be located at different heights. According to the arrangement of the step groups in this exemplary embodiment, it is beneficial to distribute the mechanical stress introduced by the step structure 230 more evenly. Figures 6A to 6DThis is a front view schematic diagram of a stepped assembly according to some embodiments of this application. It will be understood that a stepped assembly located between the first memory array structure 110 and the second memory array structure 120 may further include, for example... Figures 6A to 6D The various arrangement forms shown are illustrated.

[0055] In an exemplary implementation, such as Figure 6A As shown, the side near step 331 along the negative x-axis can be a first storage array structure (not shown), and the side near step 338 along the positive x-axis can be a second storage array structure (not shown). Step 335 is located near the middle of the bridging structure (not shown) and at a height H. 335 The other steps in this set of steps, 331, 332, 333, 334, 336, 337, and 338, are located at height H. 331 H 332 H 333 H 334 H 336 H 337 and H 338 Location. Height H 335 For height H 331 ~H 338 The maximum value in the value. In other words, step 335, located near the center of the bridging structure, is at its highest point. In this example, along the negative x-axis direction, the inclination directions of each step 331, 332, 333, and 334 between step 335 and the first memory array structure are all in the negative x-axis direction; along the positive x-axis direction, the inclination directions of each step 336, 337, and 338 between step 335 and the second memory array structure are all in the positive x-axis direction. Optionally, the inclination direction of step 335 near the center of the bridging structure can be in the positive x-axis direction.

[0056] In an exemplary implementation, such as Figure 6B As shown, the side near step 431 along the negative x-axis can be a first storage array structure (not shown), and the side near step 438 along the positive x-axis can be a second storage array structure (not shown). Step 434 is located near the middle of the bridging structure (not shown) and at a height H. 434 The other steps in this set of steps, 431, 432, 433, 435, 436, 437, and 438, are located at height H. 431 H 432 H 433 H 435 H 436 H 437 and H 438 Location. Height H 434 For height H 431 ~H 438The maximum value in the value. In other words, step 434, located near the middle of the bridging structure, is at its highest point. In this example, along the negative x-axis direction, the inclination directions of each step 431, 432, and 433 between step 434 and the first memory array structure are all in the negative x-axis direction; along the positive x-axis direction, the inclination directions of each step 435, 436, 437, and 438 between step 434 and the second memory array structure are all in the positive x-axis direction. Optionally, the inclination direction of step 434, located near the middle of the bridging structure, can be in the negative x-axis direction.

[0057] In an exemplary implementation, such as Figure 6C As shown, the side near step 531 along the negative x-axis can be a first storage array structure (not shown), and the side near step 538 along the positive x-axis can be a second storage array structure (not shown). Step 534 is located near the middle of the bridging structure (not shown) and at a height H. 534 The other steps in this set of steps, 531, 532, 533, 535, 536, 537, and 538, are located at height H. 531 H 532 H 533 H 535 H 536 H 537 and H 538 Location. Height H 534 For height H 531 ~H 538 The maximum value in the value. In other words, step 534, located near the middle of the bridging structure, is at its highest point. In this example, along the negative x-axis direction, the inclination directions of each step 531, 532, and 533 between step 534 and the first memory array structure are all in the negative x-axis direction; along the positive x-axis direction, the inclination directions of each step 535, 536, 537, and 538 between step 534 and the second memory array structure are all in the negative x-axis direction. Optionally, the inclination direction of step 534 near the middle of the bridging structure can be in the negative x-axis direction.

[0058] In an exemplary implementation, such as Figure 6D As shown, the side near step 631 along the negative x-axis can be a first memory array structure (not shown), and the side near step 638 along the positive x-axis can be a second memory array structure (not shown). Step 635 is located near the middle of the bridging structure (not shown) and at a height H. 635 The other steps in this set of steps, 631, 632, 633, 634, 636, 637, and 638, are located at height H. 631 H 632 H 633 H 634 H636 H 637 and H 638 Location. Height H 635 For height H 631 ~H 638 The maximum value in the value. In other words, step 635, located near the middle of the bridging structure, is at its highest point. In this example, along the negative x-axis direction, the tilt directions of each step 631, 632, 633, and 634 between step 635 and the first memory array structure are all along the positive x-axis direction; along the positive x-axis direction, the tilt directions of each step 636, 637, and 638 between step 635 and the second memory array structure are all along the positive x-axis direction. Optionally, the tilt direction of step 635, located near the middle of the bridging structure, can be along the positive x-axis direction.

[0059] It is understood that although this application schematically describes the arrangement of multiple steps in a stair group, the arrangement of multiple steps in a stair group is not limited thereto. Embodiments in which the first height of the step near the middle of the bridging structure is higher than the height of the other steps are all within the protection scope of this application.

[0060] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, including: The storage array structure includes a first storage array structure and a second storage array structure disposed along a first direction; A stepped structure, located between the first storage array structure and the second storage array structure, includes: A bridging structure connects the first memory array structure and the second memory array structure, the bridging structure comprising alternating stacked dielectric layers and conductive layers; and A first set of steps is disposed on one side of the bridging structure along a second direction perpendicular to the first direction, including multiple steps located at different heights, each step being electrically connected to at least one of the first storage array structure and the second storage array structure through the bridging structure; A semiconductor layer, wherein the bridging structure is provided on the semiconductor layer, wherein the conductive layer closest to the semiconductor layer in the bridging structure is the bottom conductive layer, and the conductive layer furthest from the semiconductor layer in the bridging structure is the top conductive layer, wherein the cross-sectional dimension of the top conductive layer in the direction perpendicular to the first direction is smaller than the cross-sectional dimension of the bottom conductive layer in the direction perpendicular to the first direction; Among the plurality of steps, the step closest to the middle of the bridging structure is located at a first height, which is the maximum value among the different heights.

2. The three-dimensional memory according to claim 1, wherein, The multiple steps are divided into multiple pairs of steps that are inclined toward each other.

3. The three-dimensional memory according to claim 1, wherein, The plurality of steps in the first step group are asymmetrically distributed with respect to the second direction.

4. The three-dimensional memory according to claim 1 or 3, wherein, Each of the steps includes multiple steps, and in the first set of steps, the total thickness of the multiple steps in each of the steps does not overlap with each other in the height direction.

5. The three-dimensional memory according to claim 1 or 2, wherein, Along the direction away from the center of the bridging structure, the height of each step between the step near the center of the bridging structure and the first storage array structure decreases sequentially, and the height of each step between the step near the center of the bridging structure and the second storage array structure decreases sequentially.

6. The three-dimensional memory according to claim 1, wherein, The three-dimensional memory further includes a second step group disposed along the second direction on the other side of the bridging structure, wherein the first step group and the second step group are asymmetrically distributed with respect to the bridging structure.

7. The three-dimensional memory according to claim 1, wherein, Along a direction away from the center of the bridging structure, the steps near the center of the bridging structure and the steps between the first storage array structure have the same inclination direction, and the steps near the center of the bridging structure and the steps between the second storage array structure have the same inclination direction.

8. The three-dimensional memory according to claim 1, wherein, The cross-sectional dimension of the conductive layer perpendicular to the first direction is inversely proportional to the distance between the conductive layer and the semiconductor layer.

9. The three-dimensional memory according to claim 1, wherein, The staircase includes multiple steps, which are electrically connected to at least one of the first storage array structure and the second storage array structure via the bridging structure.

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