Display panel and display device using the display panel

Abstract

This disclosure relates to a display panel and a display device using the display panel. The display panel includes a first region and a second region. The first region includes a plurality of first pixels, and the second region includes a plurality of light-transmitting portions and a plurality of second pixels. The plurality of second pixels are configured such that the light-transmitting portions are located between the plurality of second pixels. The light-transmitting portions include circular or elliptical light-transmitting portions arranged in a Z-shape along a first direction and a second direction intersecting the first direction in the second region.

Description

Technical Field

[0001] This disclosure relates to display panels having partially different resolutions or pixels per inch (PPI) and display devices using the display panels. Background Technology

[0002] Electroluminescent display devices are broadly classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (OLEDs) and possess advantages such as fast response time, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, OLEDs are formed within each pixel. Because organic light-emitting display devices not only have a fast response time and excellent luminous efficiency, brightness, and viewing angle, but also can represent black and grayscale as perfect black, they offer excellent contrast and color gamut.

[0003] The multimedia capabilities of mobile devices are improving. For example, cameras are now placed in smartphones by default, and their resolution has increased to the level of traditional digital cameras. The front-facing camera in smartphones limits screen design, making screen design difficult. To reduce the space occupied by the camera, smartphones have adopted screen designs including notches or punch-holes; however, the screen size is still limited by the camera, preventing full-screen displays. Summary of the Invention

[0004] To achieve full-screen display, the camera module can be positioned to overlap with the display panel screen. To increase the quality of the images captured by the camera module, the transmittance of the display panel overlapping the camera module should be increased; however, due to pixel circuitry and wiring, it is difficult to design for improving transmittance.

[0005] This disclosure aims to address the aforementioned necessity and / or problems.

[0006] This disclosure relates to a display panel capable of achieving full-screen display, increasing the transmittance of the display panel in the sensing area that receives light, and improving the quality of the image image formed through the sensing area, as well as a display device using the display panel.

[0007] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0008] According to one aspect of this disclosure, a display panel is provided, comprising: a first region including a plurality of first pixels; and a second region including a plurality of light-transmitting portions and a plurality of second pixels, wherein the plurality of second pixels are configured such that the light-transmitting portions are located between the plurality of second pixels. The light-transmitting portions include circular or elliptical light-transmitting portions arranged in a zigzag pattern along a first direction and a second direction intersecting the first direction in the second region.

[0009] According to another aspect of this disclosure, a display device is provided, comprising: a display panel; one or more sensor modules disposed below a second region of the display panel and below a back surface of the display panel to perform photoelectric conversion on light received through the second region; and a display panel driving unit configured to write pixel data to pixels in a first region and pixels in a second region. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0011] Figure 1 This is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present disclosure;

[0012] Figure 2 This is a plan view of an area on a display panel where a sensor module is installed;

[0013] Figure 3 This is an illustration of the pixel settings for the first region;

[0014] Figure 4 This is an example of the pixel settings for the second region;

[0015] Figures 5 to 7 This is a diagram illustrating various implementation methods for the second region;

[0016] Figure 8 This is a diagram illustrating an experimental method in which a sensor module disposed in a second area of ​​a display panel captures a light source through the second area;

[0017] Figures 9A to 9C This is an illustration of light source images captured through various circular light-transmitting parts;

[0018] Figure 10 and Figure 11 This is an example of an image of a light source captured through a rectangular light-transmitting section;

[0019] Figure 12 This is an example of an image of a light source captured through an octagonal light-transmitting section;

[0020] Figures 13A to 13E This is a diagram illustrating the glare trend of the imaging image based on different size intervals and placement methods when the circular light-transmitting portion is placed in the second region;

[0021] Figures 14A to 14H This is a diagram illustrating the glare trend of the imaging image based on different size intervals and placement methods when the elliptical light-transmitting portion is placed in the second region;

[0022] Figure 15 This is a diagram illustrating a laser beam irradiated in a laser ablation process and a schematic cross-sectional structure of a display panel according to an embodiment of the present disclosure;

[0023] Figure 16 This is a block diagram illustrating a display panel and a display panel driving unit according to one embodiment of the present disclosure;

[0024] Figure 17 This is an example Figure 16 The block diagram showing the configuration of the driver IC is shown.

[0025] Figure 18 This is a circuit diagram illustrating an example of a pixel circuit;

[0026] Figure 19 This is an example Figure 18 Waveform diagram of the driving method of the pixel circuit shown;

[0027] Figure 20 This is a cross-sectional view illustrating in detail the cross-sectional structure of a circuit layer according to one embodiment of the present disclosure;

[0028] Figure 21 This is a plan view illustrating the pattern of the second metal layer;

[0029] Figure 22 This is a plan view illustrating the pattern of the third metal layer;

[0030] Figure 23 This is a plan view illustrating the pattern of the fourth metal layer;

[0031] Figure 24 This is a plan view illustrating the pattern of the fifth metal layer; and

[0032] Figure 25 This is a plan view illustrating the stacked structure of the second to fifth metal layers. Detailed Implementation

[0033] The advantages and features of this disclosure, as well as the methods for implementing this disclosure, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various different forms. Rather, the embodiments described herein will make the disclosure complete and allow those skilled in the art to fully understand the scope of this disclosure. This disclosure is limited only to the scope of the appended claims.

[0034] The shapes, dimensions, ratios, angles, quantities, etc., illustrated in the accompanying drawings for describing embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the disclosure.

[0035] Terms such as “comprising,” “including,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless the term is used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0036] The component is interpreted to include the normal error range, even if not explicitly stated otherwise.

[0037] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two components, one or more components may be located between the two components, unless the term is used with the terms “immediately” or “directly.”

[0038] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the ordinal number preceding the component or the component name.

[0039] Throughout the specification, the same reference numerals refer to the same elements.

[0040] The following implementations may be combined or integrated with each other in part or in whole, and may be linked and operated in technically different ways. The implementations may be performed independently or in connection with each other.

[0041] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0042] Reference Figure 1 and Figure 2 The display panel 100 includes a screen for reproducing the input image. The screen can be divided into a first area DA and a second area CA with different resolutions or pixels per inch (PPI).

[0043] Each of the first region DA and the second region CA includes a pixel array, wherein pixels are configured to be written with pixel data for inputting an image. The first region DA is the main display area occupying most of the screen. The second region CA includes a sensing area in which pixels are configured with a lower pixel per inch (PPI) compared to the first region DA.

[0044] like Figure 2 As shown, one or more sensor modules SS1 and SS2 facing the second region CA can be disposed below the back surface of the display panel 100. For example, an imaging module (or camera module) including an image sensor, an infrared sensor module, an illuminance sensor module, etc., can be disposed below the second region CA of the display panel 100. Sensor modules SS1 and SS2 perform photoelectric conversion on the light received through the second region CA to output electrical signals. The second region CA may include a light-transmitting portion disposed at a location where the PPI is reduced to ensure increased light transmittance of the guiding sensor modules SS1 and SS2.

[0045] Since the first region DA and the second region CA include pixels, the input image can be displayed in the first region DA and the second region CA.

[0046] Each pixel in the first region DA and the second region CA includes sub-pixels of different colors to achieve the color of the image. The sub-pixels include red sub-pixels (hereinafter referred to as "R sub-pixels"), green sub-pixels (hereinafter referred to as "G sub-pixels"), and blue sub-pixels (hereinafter referred to as "B sub-pixels"). Although not shown, each pixel P may also include white sub-pixels (hereinafter referred to as "W sub-pixels"). Each sub-pixel may include pixel circuitry for driving light-emitting elements.

[0047] An image quality compensation algorithm can be applied to compensate for the brightness and color coordinates of pixels in a second region CA that has a lower PPI compared to the first region DA.

[0048] In the display device of this disclosure, since the pixels are disposed in the second region CA in which the sensor is located, the display area of ​​the screen is not limited by the sensor module. Therefore, the display device of this disclosure can realize a full-screen display.

[0049] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a circuit layer 12 disposed on a substrate and a light-emitting element layer 14 disposed on the circuit layer 12. A polarizer 18 may be disposed on the light-emitting element layer 14, and a cover glass 20 may be disposed on the polarizer 18.

[0050] Circuit layer 12 may include pixel circuits connected to lines such as data lines, gating lines, power lines, etc., and gating drive units connected to the gating lines. Circuit layer 12 may include circuit elements such as transistors implemented with thin-film transistors (TFTs), capacitors, etc. The lines and circuit elements of circuit layer 12 may be implemented using multiple insulating layers, two or more metal layers spaced apart from each other by the insulating layers therebetween, and active layers including semiconductor materials.

[0051] The light-emitting element layer 14 may include light-emitting elements driven by pixel circuitry. The light-emitting elements may be implemented using an organic light-emitting diode (OLED). An OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) and then form excitons, thus emitting visible light from the emissive layer (EML). The light-emitting element layer 14 may be disposed on pixels that selectively emit red, green, and blue wavelengths, and may also include a color filter array.

[0052] The light-emitting element layer 14 can be covered by a protective film, and the protective film can be covered by an encapsulation layer. The protective layer and encapsulation layer can have a structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the channels for moisture or oxygen are longer than those in a single layer, thus effectively blocking the penetration of moisture or oxygen that could affect the light-emitting element layer 14.

[0053] Polarizing plate 18 can be attached to the encapsulation layer. Polarizing plate 18 improves the outdoor visibility of the display device. Polarizing plate 18 reduces light reflected from the surface of display panel 100 and blocks light reflected from the metal of circuit layer 12 to improve pixel brightness. Polarizing plate 18 can be implemented using a circular polarizing plate or a polarizing plate that combines a linear polarizing plate and a phase retardation film.

[0054] Figure 3 This is a diagram illustrating an example of pixels set in the first region DA. Figure 4 This is an example diagram illustrating the pixels and light-transmitting portion of the second region CA. Figure 3 and Figure 4 The lines connecting to the pixels are omitted.

[0055] Reference Figure 3The first region DA comprises pixels arranged with a high PPI. Each pixel may include R sub-pixels, G sub-pixels, and B sub-pixels, or sub-pixels of two colors. Each pixel may also include W sub-pixels (omitted in the figure).

[0056] For each color, subpixels can have different luminous efficiencies of their light-emitting elements. With this in mind, the size of the subpixels can vary for each color. For example, among the R, G, and B subpixels, the B subpixel can be the largest and the G subpixel can be the smallest.

[0057] The pixels repeat in a first direction (X-axis), a second direction perpendicular to the first direction (Y-axis), and the tilt angle directions between the first and second directions (θx and θy axes). θx and θy represent the tilt axis directions in which the X-axis and Y-axis are rotated by 45°, respectively.

[0058] Reference Figure 4 The second region CA comprises multiple pixel groups PG, grouped by one or more pixels. Pixel groups PG are spaced apart by a predetermined distance. A light-transmitting portion AG is disposed in the space between the pixel groups PG. The light-transmitting portion AG may comprise a transparent medium with high transmittance and no metal, allowing light to enter with minimal loss. In other words, the light-transmitting portion AG may be formed of a transparent insulating material that does not contain metal lines or pixels. Because the light-transmitting portion AG is disposed between the pixel groups PG, the PPI of the second region CA becomes lower than that of the first region DA.

[0059] Each pixel group PG may include one or two pixels, or it may include three or four subpixels R, G, and B. In addition, each pixel group PG may also include one or more W subpixels.

[0060] like Figure 4 As shown, each pixel group PG set in the second region CA can include four sub-pixels. Pixel group PG can include two pixels, PIX1 and PIX2. The first pixel PIX1 can be composed of R sub-pixels and G sub-pixels, and the second pixel PIX2 can be composed of B sub-pixels and G sub-pixels, but this disclosure is not limited thereto. Insufficient color representation in each of the first pixel PIX1 and the second pixel PIX2 can be compensated for by averaging the corresponding color data between adjacent pixels using a sub-pixel rendering algorithm. White can be represented by combining the R sub-pixels, G sub-pixels, and B sub-pixels of the first pixel PIX1 and the second pixel PIX2.

[0061] The light-transmitting portion AG can have various shapes, but it can be circular or elliptical to obtain an image with minimized glare and increased transmittance. The pixel group PG can be designed as rhombus or square to enlarge the light-transmitting portion AG, which is circular or nearly circular and elliptical.

[0062] like Figure 1 As shown, each pixel group PG includes a circuit layer 12 on which pixel circuits for each sub-pixel are disposed, and a light-emitting element layer 14 connected to the circuit layer 12. The circuit layer 12 and the light-emitting element layer 14 may at least partially overlap each other or may be spatially separated. The circuit layer 12 of the pixel group PG may be configured as a rhombus or a square. Figures 5 to 7 This is a diagram illustrating various implementations of the second region CA.

[0063] Reference Figure 5 The second region CA includes rectangular pixel groups PG and rectangular light-transmitting portions AG spaced apart from each other, with the pixel groups PG interposed between the rectangular light-transmitting portions AG. The rectangular light-transmitting portions AG can be designed to be relatively large, but glare and grid patterns can be strongly seen in the image.

[0064] Reference Figure 6 The second region CA includes rectangular pixel groups PG and circular light-transmitting portions AG spaced apart from each other, with the pixel groups PG interposed between the circular light-transmitting portions AG.

[0065] Because the rectangular pixel group PG restricts the size of the circular light-transmitting portion AG, it is difficult to increase the transmittance of the second region CA. When the size of each circular light-transmitting portion AG is small, not only will the transmittance decrease, but glare will also be seen in the image.

[0066] exist Figure 6 In the example, due to the rectangular pixel group PG, the X-axis margin (xm) between the pixel group PG and the light-transmitting part AG becomes narrower. Therefore, to ensure the X-axis margin (xm), the size of the circular light-transmitting part AG is reduced. On the other hand, the Y-axis margin (ym) is free. The light-transmitting part AG can be designed to have a large ellipse in the Y-axis direction, but in this case, glare can be strongly seen in the image.

[0067] Reference Figure 7 The second region CA includes square or rhomboid pixel groups PG and circular light-transmitting portions AG spaced apart from each other, with the pixel groups PG interposed between the circular light-transmitting portions AG. When the large circular light-transmitting portions AG are arranged in a Z-shape along the first direction (X-axis) and the second direction (Y-axis), the quality of the image obtained from the sensor module can be improved by reducing glare and grid patterns in the image.

[0068] The use of square or diamond-shaped pixel groups PG allows for sufficient space to be ensured for designing the circular light-transmitting portion AG, while also ensuring minimum X-axis margin (xm) and minimum Y-axis margin (ym) between the pixel group PG and the circular light-transmitting portion AG. In this embodiment, while ensuring minimum X-axis margin (xm) and minimum Y-axis margin (ym) between the pixel group PG and the circular light-transmitting portion AG, the light-transmitting portion AG can be enlarged and glare and grid patterns in the image can be reduced.

[0069] The inventors of this application confirmed the quality of the image by imaging light passing through various types of light-transmitting portions in the second region CA of the display panel 100. In this experiment, such as... Figure 8 As shown, when the display panel 100 and the light source 81 are separated by a predetermined distance, the light source 81, which is lit, is captured by the imaging module SS.

[0070] Figures 9A to 9C This is an illustration of light source images captured through various circular light-transmitting parts. For example... Figure 9A and Figure 9B As shown, when the circular light-transmitting portion AG is arranged in a zigzag pattern along each of the first direction (X-axis) and the second direction (Y-axis), the size of the light-transmitting portion is large and the gap is small, resulting in a faint glare phenomenon and a grid pattern. However, when the circular light-transmitting portion AG is arranged in a straight line along each of the first direction (X-axis) and the second direction (Y-axis), as... Figure 9C The grid pattern is clearly visible.

[0071] Figure 10 and Figure 11 This is an example of an image of a light source captured through a rectangular light-transmitting section. Figure 12 This is an example diagram illustrating an image of a light source captured through an octagonal light-transmitting section. For example... Figure 10 and Figure 11 As shown, in the rectangular light-transmitting section AG, glare and a grid pattern are strongly displayed in the first direction (X-axis) and the second direction (Y-axis). Figure 12 As shown, in the octagonal light-transmitting section AG, glare and grid patterns are strongly displayed in the first direction (X-axis), the second direction (Y-axis), and the tilt angle direction (θx and θy axes).

[0072] Figures 13A to 13E This is a diagram illustrating the glare trends of the imaging image, showing different variations depending on the size interval and arrangement method when the circular light-transmitting portion is positioned in the second region CA. For example... Figures 13A to 13C As shown, when the circular light-transmitting portion AG is set in a grid pattern along straight lines in the first direction (X-axis) and the second direction (Y-axis), the grid pattern and glare diffused from the light source along radial straight lines are seen in the imaging image. In contrast, as Figure 13D and Figure 13EAs shown, when the circular light-transmitting part AG is arranged in a Z-shape along the first direction (X-axis) and the second direction (Y-axis), the quality of the image is improved because the grid pattern and glare phenomenon are enhanced.

[0073] The inventor of this application is based on Figures 14A to 14H Experimental results confirm that even when the elliptical light-transmitting portion is set in a Z-shape, the grid pattern and glare in the image are improved. Therefore, in this disclosure, the quality of the image is improved by setting the circular or elliptical light-transmitting portion AG in a Z-shape in the second region CA of the display panel 100.

[0074] Figures 14A to 14H This diagram illustrates the glare trends of the imaging image, showing different variations depending on the size interval and arrangement method when the elliptical light-transmitting portion is positioned in the second region CA. The diameters of the elliptical light-transmitting portion AG differ in the first direction (X-axis) and the second direction (Y-axis). Figure 14A The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.11:1 and an image obtained through the light-transmitting section AG. Figure 14A The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.11 and an image obtained through the light-transmitting section AG. Figure 14B The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.2:1 and an image obtained through the light-transmitting section AG. Figure 14B The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.2 and an image obtained through the light-transmitting section AG. Figure 14C The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.29:1 and an image obtained through the light-transmitting section AG. Figure 14C The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.29 and the image obtained through the light-transmitting section AG. Experimental results confirm that when the ratio of the minimum to the maximum diameter in the elliptical light-transmitting section is 1:1.3 or smaller, the glare reduction effect is greater than satisfactory. When the ratio of the minimum to the maximum diameter is greater than 1:1.3, the glare phenomenon does not achieve the expected effect.

[0075] Figure 14D The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.41:1 and an image obtained through the light-transmitting section AG. Figure 14D The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.41 and an image obtained through the light-transmitting section AG. Figure 14E The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.51:1 and an image obtained through the light-transmitting section AG. Figure 14EThe figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.51 and an image obtained through the light-transmitting section AG. Figure 14F The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.61:1 and an image obtained through the light-transmitting section AG. Figure 14F The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.61 and an image obtained through the light-transmitting section AG. Figure 14G The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.73:1 and an image obtained through the light-transmitting section AG. Figure 14G The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.73 and an image obtained through the light-transmitting section AG. Figure 14H The figure above illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1.79:1 and an image obtained through the light-transmitting section AG. Figure 14H The figure below illustrates an elliptical light-transmitting section AG with an x:y diameter ratio of 1:1.79 and an image obtained through the light-transmitting section AG.

[0076] All metal electrode material is removed from the light-transmitting portion AG. The metal, which serves as the cathode of the OLED light-emitting element, is uniformly deposited across the entire screen and removed from the light-transmitting portion AG by a laser ablation process. In the laser ablation process, the cathode layer within the light-transmitting portion AG of the second region CA can be removed. In the laser ablation process, the cathode layer can be melted and removed by irradiating it with a laser beam. The wavelength of the laser beam applied in the laser ablation process is selected to have a high absorption coefficient for the cathode material. In this disclosure, as... Figure 15 As shown, since the light-shielding layer of the exposed light-transmitting portion AG is formed on the display panel 100, and a laser beam larger than that of the light-transmitting portion AG is irradiated onto the display panel 100 during the laser ablation process, a circular or elliptical light-transmitting portion AG can be formed in... Figure 7 The larger of the narrow X-axis margin (xm) and narrow Y-axis margin (ym) shown is used.

[0077] Figure 15 This is a diagram illustrating a laser beam irradiated in a laser ablation process and a schematic cross-sectional structure of a display panel 100 according to one embodiment of the present disclosure.

[0078] Reference Figure 15 The display panel 100 includes a light-shielding layer LS that blocks the laser beam and a metal layer ML that is exposed to the laser beam through an opening OP from which the light-shielding layer LS is removed.

[0079] A light-shielding layer LS is deposited over the entire first region DA and the entire second region CA, and then patterned in a photolithography process. The light-shielding layer LS can be formed over the entire screen area of ​​the display panel 100, or it can be formed in the pixel areas of the first region DA and the second region CA, excluding the light-transmitting portion AG, as well as in the first region DA and the second region CA. The light-shielding layer LS is removed from the opening OP that exposes the light-transmitting portion AG of the second region CA, thereby defining the light-transmitting portion AG as a circular or elliptical light-transmitting portion AG. The pixel area includes the area in the first region DA and the second region CA where pixel circuitry is disposed.

[0080] The metal layer ML is one of the metal layers required to drive the pixels of the display panel 100, and it is a metal layer that should be removed from the light-transmitting portion AG of the second region CA. For example, the metal layer ML may be the cathode layer of the light-emitting element OLED or a metal layer formed on a layer different from the cathode layer. When the metal layer ML is a metal that should be partially removed in the laser ablation process, the wavelength of the laser beam LB is determined to be in a wavelength band with a high absorption coefficient for that metal.

[0081] In laser processing, the light-shielding layer LS should protect the metal layer ML, located in areas other than the light-transmitting portion of the second region CA, from the laser beam LB generated during the laser ablation process. Therefore, the light-shielding layer LS should be selected from a material with a low absorption coefficient at the wavelength of the laser beam LB.

[0082] When the metal layer ML is a Mg / Ag alloy thin film layer used as a cathode, Mg is easily removed when exposed to a laser beam with a wavelength of 1064 nm because Mg has a high absorption coefficient at 1064 nm. On the other hand, amorphous silicon (a-Si) or molybdenum (Mo) has a low absorption coefficient at 1064 nm. Therefore, when removing the Mg / Ag alloy thin film layer with a laser beam LB with a wavelength of 1064 nm, by placing a light-shielding layer LS made of a material such as amorphous silicon (a-Si) or molybdenum (Mo) with a low absorption coefficient at 1064 nm below the metal layer ML, the Mg / Ag alloy layer can be protected from the influence of the laser beam with a wavelength of 1064 nm in areas other than the light-transmitting part.

[0083] When a light-shielding layer LS is formed on the display panel 100, the metal layer ML can be protected from the laser beam LB generated during the laser ablation process in areas other than the light-transmitting portion. Therefore, the laser beam LB can irradiate the display panel 100 in the shape of a broad line beam or a block beam during the laser ablation process. The length of the beam spot BSPOT of the laser beam LB irradiating the display panel 100 in the shape of a line beam or a block beam can be at least greater than or equal to the length of the second region CA in one direction (X-axis or Y-axis direction). When the beam spot BSPOT is greater than the second region CA, only the metal layer ML in the light-transmitting portion exposed by removing the opening OP of the light-shielding layer LS is exposed to the laser beam and then removed. However, the metal layer ML in areas other than the light-transmitting portion is protected by the light-shielding layer LS and is not affected by the laser beam, therefore it is not removed.

[0084] Laser ablation equipment can use a beam shaper or homogenizer (BSH) to generate linear or block beams with uniform laser beam intensity. Linear and block beams can be generated depending on the structure of the beam shaper (BSH), and the size of the laser beam (LB) can be adjusted according to the distance between the beam shaper (BSH) and the substrate of the display panel 100.

[0085] Figure 16 This is a block diagram illustrating a display panel and a display panel driver according to one embodiment of the present disclosure. Figure 17 This is an example Figure 16 The block diagram shown illustrates the configuration of the driver IC (D-ic).

[0086] Reference Figure 16 and Figure 17 The display device includes a display panel 100 in which a pixel array is disposed on a screen, a display panel driver, etc.

[0087] The pixel array of the display panel 100 includes data lines DL, gating lines GL intersecting the data lines DL, and pixels P arranged in a matrix form defined by the data lines DL and the gating lines GL. The pixel array may also include power lines, for example... Figure 18 The VDD line PL1, the Vini line PL2, and the VSS line PL3 are shown.

[0088] The pixel array can be divided into a circuit layer 12 and a light-emitting element layer 14, such as Figure 1 As shown. The touch sensor array can be disposed on the light-emitting element layer 14. As described above, each pixel of the pixel array can include two to four sub-pixels. Each sub-pixel includes pixel circuitry disposed on the circuitry layer 12.

[0089] The pixel array of the display panel 100 includes a first region DA and a second region CA.

[0090] Each sub-pixel in the first region DA and the second region CA includes a pixel circuit. The pixel circuit may include a driving element that supplies current to the light-emitting element OLED, multiple switching elements that sample the threshold voltage of the driving element and switch the current path of the pixel circuit, a capacitor that holds the gate voltage of the driving element, etc. The pixel circuit is disposed below the light-emitting element.

[0091] The second region CA includes a light-transmitting portion AG disposed between pixel groups and a sensor module 400 disposed below the second region CA.

[0092] The display panel driver writes pixel data of the input image to pixel P. The display panel driver includes a data driver 306 that provides data voltage to the data line DL and a gating driver 120 that sequentially provides gating pulses to the gating line GL. The data driver 306 can be integrated into the driver IC D-ic. The display panel driver may also include a touch sensor driver (not shown in the figure).

[0093] The driver IC D-ic can be attached to the display panel 100. The driver IC D-ic receives pixel data and timing signals of the input image from the host system 200 to provide data voltages of pixel data to the pixels and to synchronize the data driver unit 306 and the strobe driver unit 120.

[0094] The driver IC D-ic is connected to the data line DL via a data output channel to provide the data voltages Vdata1 to Vdata6 for pixel data DATA to the data line DL. The driver IC D-ic can output a gating timing signal for controlling the gating drive unit 120 via a gating timing signal output channel. The gating timing signal generated from the timing controller 303 may include a gating start pulse VST, a gating shift clock CLK, etc. The gating start pulse VST and the gating shift clock CLK oscillate between the gating on voltage VGL and the gating off voltage VGH. The gating timing signals VST and CLK output from the level shifter 307 are applied to the gating drive unit 120 to control the shifting operation of the gating drive unit 120.

[0095] The gating drive unit 120 may include a shift register formed on the circuit layer of the display panel 100 together with the pixel array. Under the control of the timing controller 303, the shift register of the gating drive unit 120 sequentially provides gating signals to the gating line GL. The gating signals may include a scan pulse and an EM pulse. The shift register may include a scan drive unit that outputs the scan pulse and an EM drive unit that outputs the EM pulse. Figure 17 In this context, GVST and GCLK are gating timing signals input to the scan driver section. EVST and ECLK are gating timing signals input to the EM driver section.

[0096] The driver IC D-ic can be connected to the host system 200, the first memory 301, and the display panel 100. The driver IC D-ic includes a data receiving and calculation unit 308, a timing controller 303, a data driving unit 306, a gamma-compensated voltage generator 305, a power supply 304, a second memory 302, etc.

[0097] The data receiving and computing unit 308 includes a receiving unit that receives pixel data as a digital signal input from the host system 200, and a data computing unit that processes the pixel data input through the receiving unit to improve image quality. The data computing unit may include: a data recovery unit that decodes and recovers the compressed pixel data; and an optical compensation unit that adds a predetermined optical compensation value to the pixel data. The optical compensation value is set to compensate for changes in screen brightness measured based on images captured during the manufacturing process.

[0098] The timing controller 303 provides pixel data of the input image received from the host system 200 to the data driver 306. The timing controller 303 generates a gating timing signal for controlling the gating driver 120 and a source timing signal for controlling the data driver 306, so as to control the operation timing of the gating driver 120 and the data driver 306.

[0099] The data driver unit 306 converts digital data, including pixel data received from the timing controller 303 via a digital-to-analog converter (DAC), into a gamma-compensated voltage to output a data voltage. The data voltage output from the data driver unit 306 is provided to the data line DL of the pixel array through an output buffer connected to the data channel of the driver IC D-ic.

[0100] The gamma compensation voltage generator 305 divides the gamma reference voltage from the power supply 304 using a voltage divider circuit to generate a gamma compensation voltage for each grayscale level. The gamma compensation voltage is an analog voltage, in which a voltage is set for each grayscale level of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 is provided to the data drive unit 306.

[0101] Power supply 304 uses a DC-DC converter to generate the power required to drive the pixel array, gating drive unit 120, and driver IC D-ic of display panel 100. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, etc. Power supply 304 can adjust the DC input voltage from host system 200 to generate DC power supplies such as gamma reference voltage, gating on voltage VGL, gating off voltage VGH, pixel drive voltage VDD, low-level power supply voltage VSS, and initialization voltage Vini. The gamma reference voltage is provided to gamma compensation voltage generator 305. The gating on voltage VGL and gating off voltage VGH are provided to level shifter 307 and gating drive unit 120. Pixel power supplies such as pixel drive voltage VDD, low-level power supply voltage VSS, and initialization voltage Vini are typically provided to pixel P. The initialization voltage Vini is set to a DC voltage lower than pixel drive voltage VDD and lower than the threshold voltage of the OLED light-emitting element to initialize the main node of the pixel circuit and limit the emission of the OLED light-emitting element.

[0102] The second memory 302 stores compensation values, register setting data, etc., received from the first memory 301 when power is supplied to the driver IC D-ic. The compensation values ​​can be applied to various algorithms to improve image quality. The compensation values ​​may include optical compensation values. The register setting data defines the operation of the data driver unit 306, the timing controller 303, the gamma compensation voltage generator 305, etc. The first memory 301 may include flash memory. The second memory 302 may include static random access memory (SRAM).

[0103] The host system 200 can be implemented using an application processor (AP). The host system 200 can send pixel data of the input image to the driver IC D-ic via a Mobile Industrial Processor Interface (MIPI). The host system 200 can be connected to the driver IC D-ic via a flexible printed circuit (e.g., a flexible printed circuit (FPC)).

[0104] Display panel 100 can be implemented using a flexible panel suitable for flexible displays. Flexible displays can change screen size by rolling, folding, and bending the flexible panel, and can be easily manufactured in various designs. Flexible displays can be implemented as rollable displays, foldable displays, bendable displays, sliding displays, etc. The flexible panel can be manufactured as a plastic OLED panel. A plastic OLED panel can include a backplane and a pixel array bonded to an organic thin film. A touch sensor array can be formed on the pixel array.

[0105] The backsheet can be a polyethylene terephthalate (PET) substrate. The pixel array and touch sensor array can be formed on the organic thin film. The backsheet can prevent moisture from penetrating towards the organic thin film, thus preventing the pixel array from being exposed to moisture. The organic thin film can be a polyimide (PI) substrate. A multilayer buffer film (not shown) made of insulating material can be formed on the organic thin film. The circuit layer 12 and the light-emitting element layer 14 can be stacked on the organic thin film.

[0106] In the display device disclosed herein, the pixel circuit may include a plurality of transistors. The transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors, LTPS TFTs including low-temperature polycrystalline silicon (LTPS), etc. Each transistor may be implemented as a p-channel TFT or an n-channel TFT.

[0107] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor (NMOS), since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0108] The gating signal oscillates between a gating on voltage and a gating off voltage. The gating on voltage is set to a voltage higher than the transistor's threshold voltage, and the gating off voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the gating on voltage and turns off in response to the gating off voltage. In the case of an n-channel transistor, the gating on voltage can be a high gating voltage VGH / VEH, and the gating off voltage can be a low gating voltage VGL / VEL. In the case of a p-channel transistor, the gating on voltage can be a low gating voltage VGL / VEL, and the gating off voltage can be a high gating voltage VGH / VEH.

[0109] Figure 18 This is a circuit diagram illustrating an example of a pixel circuit. The pixel circuit can be implemented using the same circuit in the first region DA and the second region CA. Figure 19 It is an instance driver Figure 18 The waveform diagram shows the pixel circuit method.

[0110] Reference Figure 18 and Figure 19 The pixel circuit includes an OLED light-emitting element, a driving element DT that provides current to the OLED light-emitting element, and a switching circuit that switches the voltage applied to the OLED light-emitting element and the driving element DT.

[0111] The switching circuit is connected to the power lines PL1, PL2, and PL3, the data line DL, and the gate lines GL1, GL2, and GL3, which are subjected to the pixel driving voltage ELVDD, the low-potential power supply voltage ELVSS, and the initialization voltage Vini. It switches the voltages applied to the light-emitting element OLED and the driving element DT in response to the scan pulses SCAN(N-1) and SCAN(N) and the EM pulse EM(N).

[0112] The switching circuit includes an internal compensation circuit that uses first switching elements M1 to sixth switching elements M6 to sample the threshold voltage Vth of the driving element DT and applies the data voltage Vdata of the pixel data to the driving element DT. Each of the driving element DT and the switching elements M1 to M6 can be implemented using a p-channel TFT.

[0113] The driving period of a pixel circuit can be divided into the initialization period Tini, the sampling period Tsam, and the emission period Tem, such as Figure 19 As shown. For each frame period, an initialization period Tini and a sampling period Tsam are defined in the scan pulse synchronized with the data voltage Vdata. Therefore, after the pixel circuits are initialized sequentially through a pixel row according to the scan pulses applied to the scan lines, the threshold voltage Vth of the driving element DT is sampled.

[0114] The Nth scan pulse SCAN(N) is generated as a gating voltage VGL during the sampling period Tsam and applied to the Nth scan line GL1. The Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata applied to the pixel in the Nth pixel row. The (N-1)th scan pulse SCAN(N-1) is generated as a gating voltage VGL during the initialization period Tini before the sampling period and applied to the (N-1)th scan line GL2. The (N-1)th scan pulse SCAN(N-1) is generated before the Nth scan pulse SCAN(N) and synchronized with the data voltage Vdata applied to the pixel in the (N-1)th pixel row. The EM pulse EM(N) is generated as a gating voltage VGH during the initialization period Tini and the sampling period Tsam and applied to the EM line GL3. The EM pulse EM(N) can be applied to the pixel in both the (N-1)th pixel row and the pixel in the Nth pixel row simultaneously.

[0115] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) of the turn-on voltage VGL is applied to the (N-1)th scan line GL2, and the EM pulse of the turn-off voltage VGH is applied to the EM line GL3. In this case, the Nth scan line GL1 is the turn-off voltage VGH. During the initialization period Tini, the fifth switching element M5 is turned on according to the turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to initialize the pixel circuit of the first region DA.

[0116] During the sampling period Tsam, the Nth scan pulse SCAN(N) of the turn-on voltage VGL is applied to the Nth scan line GL1. In this case, the (N-1)th scan line GL2 and the EM line GL3 are turned off by the turn-off voltage VGH. During the sampling period Tsam, since the first switching element M1 and the second switching element M2 are turned on according to the turn-on voltage VGL of the Nth scan pulse SCAN(N), the driving element DT is turned on, the threshold voltage Vth of the driving element DT is sampled, and the data voltage Vdata compensated by the threshold voltage Vth is stored in the capacitor Cst1. At the same time, the sixth switching element M6 is turned on during the sampling period Tsam to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the emission of the light-emitting element OLED.

[0117] When the emission period Tem begins, EM line GL3 is inverted to the turn-on voltage VGL. During the emission period Tem, scan lines GL1 and GL2 maintain the turn-off voltage VGH. During the emission period Tem, the OLED can emit light because the third switching element M3 and the fourth switching element M4 are turned on. During the emission period Tem, in order to accurately represent the brightness of low grayscale, the voltage level of the EM pulse EM(N) can be inverted between the turn-on voltage VGL and the turn-off voltage VGH with a predetermined duty cycle. In this case, the third switching element M3 and the fourth switching element M4 can be repeatedly turned on / off according to the duty cycle of the EM pulse EM(N) during the emission period Tem.

[0118] The anode of the OLED is connected to a fourth node n4 between the fourth switching element M4 and the sixth switching element M6. The fourth node n4 is connected to the anode of the OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the OLED is connected to the VSS line PL3, which is supplied with a low-potential power supply voltage ELVSS. The OLED emits light using a current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the OLED is switched by the third switching element M3 and the fourth switching element M4.

[0119] Storage capacitor Cst1 is connected between VDD line PL1 and second node n2.

[0120] After the sampling period ends, the data voltage Vdata, compensated by the sampling threshold voltage Vth of the driving element DT, is charged in the storage capacitor Cst1. Since the data voltage Vdata in each sub-pixel is compensated by the threshold voltage Vth of the driving element DT, the characteristic changes of the driving element DT are compensated in the sub-pixel.

[0121] The first switching element M1 is turned on in response to the turn-on voltage VGL of the Nth scan pulse SCAN(N) to connect the second node n2 and the third node n3. The second node n2 is connected to the gate electrode of the driving element DT, the first electrode of the capacitor Cst1, and the first electrode of the first switching element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. The gate electrode of the first switching element M1 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the first switching element M1 is connected to the second node n2, and the second electrode of the first switching element M1 is connected to the third node n3.

[0122] Because the first switching element M1 is turned on during a very short horizontal period (1H) of the Nth scan signal SCAN(N) generated in a frame time period as the turn-on voltage VGL, leakage current may occur in the off state. In order to suppress the leakage current of the first switching element M1, the first switching element M1 can be implemented with a transistor having a dual-gate structure in which two transistors M1a and M1b are connected in series.

[0123] The second switching element M2 is turned on in response to the turn-on voltage VGL of the Nth scan pulse SCAN(N) to provide a data voltage Vdata to the first node n1. The gate electrode of the second switching element M2 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the second switching element M2 is connected to the first node n1. The second electrode of the second switching element M2 is connected to the data line DL of the first region DA to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0124] The third switching element M3 is turned on in response to the turn-on voltage VGL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. The gate electrode of the third switching element M3 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the third switching element M3 is connected to the VDD line PL1. The second electrode of the third switching element M3 is connected to the first node n1.

[0125] The fourth switching element M4 is turned on in response to the turn-on voltage VGL of the EM pulse EM(N) to connect the third node n3 to the anode of the light-emitting element OLED. The gate electrode of the fourth switching element M4 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the fourth switching element M4 is connected to the third node n3, and the second electrode is connected to the fourth node n4.

[0126] The fifth switching element M5 is turned on in response to the turn-on voltage VGL of the (N-1)th scan pulse SCAN(N-1), connecting the second node n2 to the Vini line PL2. The gate electrode of the fifth switching element M5 is connected to the (N-1)th scan line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the fifth switching element M5 is connected to the second node n2, and the second electrode is connected to the Vini line PL2. To suppress leakage current in the fifth switching element M5, the fifth switching element M5 is implemented using a transistor with a dual-gate structure in which two transistors are connected in series.

[0127] The sixth switching element M6 is turned on in response to the turn-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode is connected to the fourth node n4.

[0128] In another embodiment, the gate electrodes of the fifth switching element M5 and the sixth switching element M6 can be connected together to the (N-1)th scan line GL2 to which the (N-1)th scan pulse SCAN(N-1) is applied. In this case, the fifth switching element M5 and the sixth switching element M6 can be simultaneously turned on in response to the (N-1)th scan pulse SCAN(N-1).

[0129] The driving element DT drives the OLED by controlling the current flowing through the OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0130] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the turn-on voltage VGL. The Nth scan pulse SCAN(N) and the EM pulse EM(N) maintain the turn-off voltage VGH during the initialization period Tini. Therefore, since the fifth switching element M5 is turned on during the initialization period Tini, the second node n2 and the fourth node n4 are initialized to the initialization voltage Vini. A hold period Th can be set between the initialization period Tini and the sampling period Tsam. During the hold period, the voltages of scan lines GL1 and GL2 and the EM line GL3 are the turn-off voltage VGH.

[0131] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the turn-on voltage VGL. The pulse of the Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel row. The (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) maintain the turn-off voltage VGH during the sampling period Tsam. Therefore, the first switching element M1 and the second switching element M2 are turned on during the sampling period Tsam.

[0132] During the sampling period Tsam, the gate voltage DTG of the driving element DT increases due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is off, the gate voltage DTG of the driving element DT is Vdata - |Vth|. Therefore, the data voltage Vdata, compensated for the threshold voltage Vth, is stored in the capacitor Cst1, and then during the emission period Tem, the gate-source voltage Vgs of the driving element DT is ELVDD - Vdata + |Vth|. Therefore, the current Ioled flowing through the light-emitting element OLED during the emission period Tem is not affected by the threshold voltage Vth of the driving element DT, because the current Ioled is Ioled = K(Vgs - |Vth|). 2 =K(ELVDD-Vdata) 2 This will be described below. Furthermore, a data write period Twr can be set between the sampling period Tsam and the emission period Tem. During the data write period Twr, all switching elements M1 to M6 remain off.

[0133] When the EM pulse EM(N) is at the turn-on voltage VGL during the emission period Tem, the OLED emits light because current flows between ELVDD and the OLED. During the emission period Tem, the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) maintain the turn-off voltage VGH. During the emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on according to the turn-on voltage VGL of the EM pulse EM(N). When the EM pulse EM(N) is at the turn-on voltage VGL, current flows through the OLED because the third switching element M3 and the fourth switching element M4 are turned on. In this case, the current Ioled flowing through the OLED via the driving element DT is Ioled = K(ELVDD - Vdata). 2 K is a constant value determined by the charge mobility, parasitic capacitance, and channel ratio (W / L) of the driving element DT.

[0134] In the pixel circuit, as the data voltage Vdata output from the first data driving unit decreases, the current Ioled flowing through the light-emitting element OLED increases. Therefore, the first data driving unit outputs the data voltage Vdata as a negative gamma compensation voltage, which decreases as the gray level increases.

[0135] Figure 20 This is a cross-sectional view illustrating in detail the cross-sectional structure of circuit layer 12 according to one embodiment of the present disclosure. It should be noted that the cross-sectional structure of circuit layer 12 is not limited to... Figure 20 .exist Figure 20 In this context, the TFT can be a transistor used as a driving element DT or a fourth switching element M4 in the pixel circuit.

[0136] Reference Figure 20 Circuit layer 12, light-emitting element layer 14, etc., can be stacked on substrates PI1 and PI2. Substrates PI1 and PI2 can include a first PI substrate PI1 and a second PI substrate PI2. An inorganic film IPD can be formed between the first PI substrate PI1 and the second PI substrate PI2. The inorganic film IPD blocks moisture penetration.

[0137] A first buffer layer BUF1 can be formed on a second PI substrate PI2. The first buffer layer BUF1 can be formed from a multilayer insulating film in which two or more oxide films SiO2 and nitride films SiNx are stacked. A first metal layer can be formed on the first buffer layer BUF1. A second buffer layer BUF2 can be formed on the first metal layer. The second buffer layer BUF2 can be formed from an inorganic insulating material and can be formed from one or more insulating layers.

[0138] A first metal layer is patterned in a photolithography process. The first metal layer may include a light-shielding layer LS. The light-shielding layer LS may be disposed below the transistor TFT and the capacitor Cst1.

[0139] The light-shielding layer LS can prevent ghosting defects in the imaging image caused by reflecting light reflected from the sensor module back to the sensor module. Furthermore, as mentioned above, since the light-shielding layer LS is selected as a material with a low absorption rate relative to the laser wavelength in the laser ablation process, the cathode can be retained in an area other than the light-transmitting portion AG to avoid the influence of the laser beam.

[0140] Compared to the cathode layer of the OLED light-emitting element, which is to be removed in the second region CA, the light-shielding layer LS can be formed from one of the materials, each having a lower absorption coefficient for the laser wavelength used in the laser ablation process, such as amorphous silicon (a-Si) and molybdenum (Mo). When the light-shielding layer LS is formed from amorphous silicon (a-Si), it effectively prevents ghosting in the imaging image by absorbing light reflected by the sensor module.

[0141] The first metal layer may further include a bottom shielding metal layer BSM formed on the light-shielding layer LS. The bottom shielding metal layer BSM may be formed of a copper / molybdenum titanium alloy (Cu / MoTi) in which copper (Cu) and molybdenum titanium alloy (MoTi) are stacked, but is not limited thereto.

[0142] The light-shielding layer LS and the bottom shielding metal layer BSM can be formed from a metal (e.g., molybdenum (Mo)) that has a low absorption coefficient for the laser wavelength used in the laser ablation process. In this case, since the light-shielding layer LS and the bottom shielding metal layer BSM can be implemented with a single metal layer, the bottom shielding metal layer BSM can be omitted.

[0143] When at least one of the light-shielding layer LS and the bottom shielding metal layer BSM is formed of metal, external light is blocked, preventing light from illuminating the semiconductor channel of the transistor TFT, thus preventing degradation and leakage current of the transistor TFT caused by external light. Applying a DC voltage, such as the pixel driving voltage ELVDD, to the light-shielding layer LS and the bottom shielding metal layer BSM blocks ions that affect the active layer ACT of the transistor TFT, thereby suppressing threshold voltage variations. The bottom shielding metal layer BSM can be disposed below the transistor TFT in the sub-pixel, and the light-shielding layer LS can be disposed in the first region DA and the second region CA, excluding the light-transmitting portion AG. As a result, the bottom shielding metal layer BSM and the light-shielding layer LS can have different planar pattern shapes and cross-sectional pattern shapes.

[0144] The active layer ACT is formed from semiconductor material deposited on the second buffer layer BUF2 and can be patterned using photolithography. The active layer ACT includes the semiconductor channels for the pixel circuitry. A portion of the active layer ACT can be metallized by ion doping. The metallized portion can connect the nodes of the transistors and pixel circuitry.

[0145] A gate insulating layer GI can be formed on the second buffer layer BUF2 to cover the active layer ACT. The gate insulating layer GI can be formed of an inorganic insulating material. A second metal layer can be formed on the gate insulating layer GI. The second metal layer can be patterned using a photolithography process. The second metal layer may include gate lines and gate electrode patterns GATE, the lower electrode of the storage capacitor Cst1, etc.

[0146] A first interlayer insulating layer ILD1 can be formed on the gate insulating layer GI to cover the second metal layer. A third metal layer can be formed on the first interlayer insulating layer ILD1, and a second interlayer insulating layer ILD2 can cover the third metal layer. The third metal layer can be patterned by photolithography. The third metal layer may include the upper electrode of the storage capacitor Cst1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may include inorganic or organic insulating materials.

[0147] A fourth metal layer can be formed on the second interlayer insulating layer ILD2, and an inorganic insulating layer PAS and a first planarization layer PLN1 can be stacked on it. A fifth metal layer can be formed on the first planarization layer PLN1.

[0148] Some patterns of the fourth metal layer can be connected to the third metal layer through contact holes passing through the first planarization layer PLN1 and the inorganic insulating layer PAS. The first planarization layer PLN1 and the second planarization layer PLN2 can be formed of an organic insulating material that flattens the surface.

[0149] The fourth metal layer may include the first and second electrodes of the transistor TFT, which are connected to the active pattern of the transistor TFT through contact holes passing through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The data lines DL and power lines PL1, PL2 and PL3 may be implemented as the third metal layer pattern TM1, the fourth metal layer pattern SD1 or the fifth metal layer pattern SD2.

[0150] The anode AND of the OLED light-emitting element can be formed on the second planarization layer PLN2. The anode AND can be connected to the electrode of the transistor TFT, which is used as a switching element or a driving element, through contact holes in the second planarization layer PLN2. The anode AND can be formed of a transparent or translucent electrode material.

[0151] The pixel-defining film (BNK) can cover the edge of the anode AND of an OLED. The BNK is patterned to define a light-emitting region (or opening region) through which light travels from each pixel to the outside. Spacers (SPCs) can be formed on the BNK. Both the BNK and SPC can be formed using the same organic insulating material. The SPCs ensure a gap between the fine metal mask (FMM) and the anode AND, preventing the FMM from contacting the anode AND during the deposition process of the organic compound EL.

[0152] Organic compounds (omitted in the figure) are formed in the light-emitting region of each pixel defined by the pixel-defining film (BNK). The cathode of the OLED light-emitting element can be formed on the entire surface of the display panel 100 to cover the pixel-defining film (BNK), the spacer (SPC), and the organic compounds. The cathode can be connected to the VSS line PL3 formed by any of the underlying metal layers.

[0153] At least one of the pixel circuit and signal lines DL and GL, as well as the power lines PL1, PL2, and PL3 connected to the pixel circuit, may include a curved pattern defining a circular or elliptical light-transmitting portion AG, such as Figures 21 to 24 As shown. Figure 21 This is a plan view illustrating the pattern of the second metal layer. The second metal layer may include gate lines GL1, GL2, and GL3. Gate lines GL1, GL2, and GL3 may include a curved pattern that bends along the outer periphery of a circular or elliptical light-transmitting portion AG. Figure 22 This is a plan view illustrating the pattern of the third metal layer. The third metal layer may include a Vini line PL2. The Vini line PL2 may include a curved pattern that bends along the outer periphery of the circular or elliptical light-transmitting portion AG. Figure 23 This is a plan view illustrating the pattern of the fourth metal layer. Figure 24 This is a plan view illustrating the pattern of the fifth metal layer. The fourth and fifth metal layers may include data lines DL. The data lines DL may include a curved pattern that bends along the outer periphery of a circular or elliptical light-transmitting portion AG. Figure 25 This is a plan view illustrating the stacked structure of the second to fifth metal layers.

[0154] like Figures 21 to 25 As shown, when the metal pattern formed on two or more circuit layers is designed as a curved pattern along the outer periphery of a circular or elliptical light-transmitting portion, the light-transmitting portion can be defined as circular or elliptical without the need for a light-shielding layer LS. Therefore, when a curved pattern defining a circular or elliptical light-transmitting portion AG is applied to the metal layer, the light-shielding layer LS can be removed; however, the light-shielding layer LS can absorb light reflected by the sensor module. Therefore, the curved pattern design of the light-shielding layer LS and the metal layer can be applied together.

[0155] In this disclosure, since the sensor is mounted on the screen displaying the image, a full-screen display can be achieved.

[0156] In this disclosure, since the pixels in some areas of the screen on which the sensor is mounted are set at a low pixel per inch (PPI) and are provided with light-transmitting parts, not only can the transmittance of light incident on the sensor through the display panel be increased, but the quality of the image can also be improved by setting the circular or elliptical light-transmitting parts in a Z-shape to reduce glare in the image obtained from the sensor.

[0157] The effects of this disclosure are not limited to those described above, and other effects not mentioned can be clearly understood by those skilled in the art based on the disclosure of the claims.

[0158] The purpose, means, and effects of this disclosure described above do not specifically address the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0159] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the scope of their equivalents should be interpreted as falling within the scope of the present disclosure.

[0160] Cross-reference of related applications

[0161] This application claims priority and benefit to Korean Patent Application No. 10-2020-0135390, filed on October 19, 2020, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, the display panel comprising: A first region, the first region including a plurality of first pixels; as well as The second region includes a plurality of light-transmitting portions and a plurality of second pixels, wherein the plurality of second pixels are configured such that the light-transmitting portions are located between the plurality of second pixels. The light-transmitting portion includes a circular or elliptical light-transmitting portion arranged in a Z-shape along a first direction and a second direction intersecting the first direction in the second region. The plurality of second pixels are divided into a plurality of pixel groups, each of the plurality of pixel groups including a circuit layer. The circuit layer includes a light-shielding layer, a bottom shielding metal layer on the light-shielding layer, and a second metal layer above the bottom shielding metal layer. Wherein, the light-shielding layer, the bottom shielding metal layer, and the second metal layer are not disposed in the plurality of light-transmitting portions, and A DC voltage is applied to the light-shielding layer and the bottom shielding metal layer.

2. The display panel according to claim 1, wherein, The second pixel included in the second region has a lower PPI than the first pixel included in the first region.

3. The display panel according to claim 1, wherein, The light-transmitting portions are spaced apart from each other, and the pixel groups are located between the light-transmitting portions. The circuit layer is configured as a square or rhombus shape.

4. The display panel according to claim 3, wherein, Each of the pixel groups comprises one or two pixels, or three or four sub-pixels.

5. The display panel according to claim 1, wherein, The ratio of the minimum diameter to the maximum diameter of each of the elliptical light-transmitting sections is 1:1.3 or less.

6. The display panel according to claim 4, wherein, Each sub-pixel in the pixel group includes a pixel circuit disposed on the circuit layer, and The pixel circuit includes a light-emitting element, a transistor configured to provide current to the light-emitting element, and a capacitor connected to the gate electrode of a driving element.

7. The display panel according to claim 6, wherein, The light-shielding layer comprises amorphous silicon (a-Si) or molybdenum (Mo).

8. The display panel according to claim 6, wherein, The circuit layer further includes another metal layer, which includes signal lines and power lines connected to the pixel circuitry of the sub-pixel. One or more of the signal lines and the power lines include a curved pattern that bends along the outer periphery of the circular or elliptical light-transmitting portion.

9. The display panel according to claim 8, wherein, The other metal layer is not disposed in the circular or elliptical light-transmitting part.

10. A display device, the display device comprising: The display panel includes a first region and a second region. The first region is provided with a plurality of first pixels, and the second region is provided with a plurality of light-transmitting parts and a plurality of second pixels. The plurality of second pixels are configured such that the light-transmitting parts are located between the plurality of second pixels. One or more sensor modules, wherein the one or more sensor modules are disposed below the second area of ​​the display panel; as well as The display panel driving unit is configured to write pixel data to pixels in the first region and the second region. The light-transmitting portion includes a circular or elliptical light-transmitting portion arranged in a Z-shape along a first direction and a second direction intersecting the first direction in the second region. The plurality of second pixels are divided into a plurality of pixel groups, each of the plurality of pixel groups including a circuit layer. The circuit layer includes a light-shielding layer, a bottom shielding metal layer on the light-shielding layer, and a second metal layer above the bottom shielding metal layer. Wherein, the light-shielding layer, the bottom shielding metal layer, and the second metal layer are not disposed in the plurality of light-transmitting portions, and A DC voltage is applied to the light-shielding layer and the bottom shielding metal layer.

11. The display device according to claim 10, wherein, The one or more sensor modules include one or more of a camera module, an infrared sensor module, and an illuminance sensor module, and The one or more sensor modules completely overlap with the second area of ​​the display panel.

12. The display device according to claim 10, wherein, The second pixel included in the second region has a lower PPI than the first pixel included in the first region.

13. The display device according to claim 10, wherein, The ratio of the minimum diameter to the maximum diameter of each of the elliptical light-transmitting sections is 1:1.3 or less.

14. The display device according to claim 10, wherein, The light-transmitting portions are spaced apart from each other, and the pixel groups are located between the light-transmitting portions.

15. The display device according to claim 14, wherein, Each of the pixel groups in the second region includes one or two pixels, or three or four sub-pixels. Each subpixel includes pixel circuitry, and The pixel circuit includes a light-emitting element, a transistor configured to provide current to the light-emitting element, and a capacitor connected to the gate electrode of a driving element.

16. The display device according to claim 15, wherein, The light-shielding layer comprises amorphous silicon (a-Si) or molybdenum (Mo).

17. The display device according to claim 15, wherein, The second region also includes another metal layer, which includes signal lines and power lines connected to the pixel circuitry of the sub-pixel. One or more of the signal lines and the power lines include a curved pattern that bends along the outer periphery of the circular or elliptical light-transmitting portion.

18. The display device according to claim 17, wherein, The other metal layer is not disposed in the circular or elliptical light-transmitting part.

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