Display device

Abstract

A display device is provided. The display device includes a first connection electrode extending in a first direction and electrically connected to a first power line to which a first voltage is applied, a second connection electrode spaced apart from the first connection electrode and electrically connected to a second power line to which a second voltage is applied, a first electrode extending from the first connection electrode, a second electrode extending from the second connection electrode and disposed in parallel with the first electrode at a predetermined distance from the first electrode, and a plurality of light emitting elements having a first end portion electrically connected to the first electrode and a second end portion electrically connected to the second electrode, wherein the first electrode and the second electrode include a curved portion.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to a display device, and more specifically, to a display device comprising ultra-small light-emitting elements, each ultra-small light-emitting element having a small size ranging from nanometer to micrometer. Background Technology

[0002] Recently, techniques have been developed for fabricating ultra-miniature light-emitting elements using materials with reliable inorganic crystal structures and for manufacturing light-emitting devices using these elements. For example, techniques have been developed for constructing light sources using ultra-miniature light-emitting elements with small dimensions corresponding to a range from nanometer to micrometer sizes. Such light-emitting devices can be used in various electronic devices such as display devices and lighting devices.

[0003] To use ultra-miniature light-emitting elements (LEDs) for lighting, displays, and other applications, it is necessary to connect the ultra-miniature LEDs to electrodes configured to apply electrical voltage to them. Various studies have been conducted on the arrangement of the ultra-miniature LEDs and electrodes, considering the intended application, minimizing electrode space, and manufacturing methods.

[0004] Methods for fabricating ultra-miniature light-emitting elements and electrodes can be categorized into methods that directly grow the ultra-miniature light-emitting elements on the electrodes and methods that grow the ultra-miniature light-emitting elements separately and independently, and then mount them on the electrodes. In the latter case, if the light-emitting element has a normal size, it is possible to vertically erect the element and connect it to the electrode. However, if the light-emitting element is a nanoscale ultra-miniature element, it is difficult to vertically erect it on the electrode. Summary of the Invention

[0005] Technical issues

[0006] The purpose of this disclosure is to provide a display device in which the alignment of ultra-small light-emitting elements can be improved.

[0007] Another object of this disclosure is to provide a display device with an improved viewing angle.

[0008] This disclosure is not limited to the purposes described above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] Technical solution

[0010] A display device according to embodiments of the present disclosure may include: a first connecting electrode extending in a first direction and electrically connected to a first power line to which a first power source is applied; a second connecting electrode spaced apart from the first connecting electrode and electrically connected to a second power line to which a second power source is applied; a first electrode extending from the first connecting electrode; a second electrode extending from the second connecting electrode and disposed parallel to the first electrode and having a predetermined distance between the second electrode and the first electrode; and a plurality of light-emitting elements, each including a first end electrically connected to the first electrode and a second end electrically connected to the second electrode. Each of the first electrode and the second electrode may include a bent portion.

[0011] The first electrode and the second electrode can extend from the first connecting electrode and the second connecting electrode in a second direction intersecting the first direction, respectively.

[0012] The curved portion may have a shape that protrudes in the first direction.

[0013] Each of the first and second electrodes may have a curved or zigzag shape.

[0014] Each of the first and second electrodes can have a shape formed by connecting multiple quadrant arcs.

[0015] Each of the first and second electrodes may have a connecting portion having a shape formed by connecting multiple quadrant arcs. Inflection points are included in the connecting portion.

[0016] Each of the multiple light-emitting elements may include a rod-shaped light-emitting diode with dimensions ranging from nanometer to micrometer.

[0017] At least some of the multiple light-emitting elements can be aligned such that their longitudinal direction corresponds to the normal direction relative to the direction in which the first electrode and the second electrode extend.

[0018] The first electrode or the second electrode may include portions with different widths.

[0019] The display device may include at least one island electrode disposed between the first electrode and the second electrode, but not directly connected to the first connecting electrode or the second connecting electrode.

[0020] Some of the multiple light-emitting elements may be disposed between the first electrode and at least one island electrode. Others of the multiple light-emitting elements may be disposed between the second electrode and at least one island electrode.

[0021] At least one island electrode may be arranged parallel to the first electrode and the second electrode, and there is a predetermined distance between the at least one island electrode and the first electrode and between the at least one island electrode and the second electrode.

[0022] At least one island electrode may include a curved portion.

[0023] Multiple light-emitting elements can be connected in series and in parallel.

[0024] Each of the first electrode and the second electrode may further include a linear portion extending in a second direction intersecting the first direction.

[0025] A display device according to embodiments of the present disclosure may include: a substrate including an emitting region; a first electrode disposed in the emitting region of the substrate; a second electrode disposed on the same layer as the first electrode in the emitting region of the substrate, and configured to face the first electrode, and spaced apart from and electrically isolated from the first electrode; and a plurality of light-emitting elements disposed between the first electrode and the second electrode in a plan view. Each of the first electrode and the second electrode may include a curved portion in a plan view.

[0026] The display device may further include: a first contact electrode configured to connect a first end of each of a plurality of light-emitting elements to a first electrode; and a second contact electrode configured to connect a second end of each of a plurality of light-emitting elements to a second electrode.

[0027] The display device may further include a first island electrode and a second island electrode disposed between the first electrode and the second electrode. The distances between the first electrode, the first island electrode, the second island electrode, and the second electrode may be equal to each other.

[0028] The first electrode, the first island electrode, the second island electrode, and the second electrode can be arranged parallel to each other.

[0029] Each of the first island electrode and the second island electrode may include a curved portion.

[0030] Details of the various embodiments are included in the detailed description and accompanying drawings.

[0031] Beneficial effects

[0032] In the display device according to embodiments of the present disclosure, the alignment of the ultra-small light-emitting elements can be improved, and the viewing angle can be improved.

[0033] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein. Attached Figure Description

[0034] Figure 1a and Figure 1b These are perspective views and cross-sectional views illustrating light-emitting elements according to embodiments of the present disclosure.

[0035] Figure 2a and Figure 2bThese are perspective views and cross-sectional views illustrating light-emitting elements according to embodiments of the present disclosure.

[0036] Figure 3a and Figure 3b These are perspective views and cross-sectional views illustrating light-emitting elements according to embodiments of the present disclosure.

[0037] Figure 4 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0038] Figure 5 It is shown that it includes Figure 4 A circuit diagram of an example of a sub-pixel in a display device.

[0039] Figures 6a to 6d It is shown that it includes Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0040] Figure 7 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device.

[0041] Figure 8 It is shown Figure 7 A planar diagram of the first sub-pixel in the sub-pixels.

[0042] Figures 9a to 9d It shows along Figure 8 A cross-sectional view of an example of a unit pixel intercepted by line I-I'.

[0043] Figure 10 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device.

[0044] Figure 11 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device.

[0045] Figure 12 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device.

[0046] Figure 13 It is used to describe Figure 12 A view showing the shapes of the first and second electrodes.

[0047] Figure 14 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device.

[0048] Figures 15 to 17 It is shown that it includes Figure 4A plan view of other examples of subpixels in a display device.

[0049] Figure 18 and Figure 19 It is shown that it includes Figure 4 A plan view of other examples of subpixels in a display device.

[0050] Figures 20a to 20d It is shown that it includes Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0051] Figures 21 to 30 It is shown Figures 20a to 20d The example can be applied to a planar graph of various examples of its sub-pixels (or unit pixels).

[0052] Figure 31 It is shown that it includes Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0053] Figure 32 It is shown Figure 31 A planar diagram of examples of subpixels. Detailed Implementation

[0054] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become clear from the embodiments described in detail later with the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art, and the invention will be defined solely by the appended claims.

[0055] It will be understood that if an element or layer is referred to as being "on" another element or layer, then that element or layer may be directly on, directly connected to, or directly bonded to said other element or layer, or there may be one or more intervening elements or layers. The same reference numerals always refer to the same element.

[0056] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. In this disclosure, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0057] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used to denote the same or similar elements.

[0058] Figure 1a and Figure 1b These are perspective views and cross-sectional views illustrating a light-emitting element according to an embodiment of the present disclosure. Although in Figure 1a and Figure 1b The diagram shows a cylindrical rod-shaped light-emitting element (LD), but the types and / or shapes of light-emitting elements (LDs) according to this disclosure are not limited thereto.

[0059] Reference Figure 1a and Figure 1b The light-emitting element (LD) may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light-emitting element (LD) may be composed of a stack formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 in one direction.

[0060] In an embodiment, the light-emitting element (LD) may be arranged in the form of a rod extending in one direction. The light-emitting element (LD) may have one end and the remaining end relative to one direction.

[0061] In an embodiment, one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on one end of the light-emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the remaining end of the light-emitting element LD.

[0062] In an embodiment, the light-emitting element LD may be a rod-shaped light-emitting diode manufactured in the form of a rod. Here, the term "rod shape" includes rod-shaped and strip-shaped shapes such as cylindrical and prismatic shapes that are longer in the longitudinal direction than in the width direction (i.e., with an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross-section).

[0063] In embodiments, the light-emitting element (LD) can have small dimensions ranging from nanometers to micrometers (e.g., diameter D and / or length L ranging from nanometers to micrometers). However, the size of the light-emitting element (LD) is not limited to this. For example, the size of the light-emitting element (LD) can be varied in various ways depending on the design conditions of various devices (e.g., display devices that use light-emitting devices with light-emitting elements (LDs) as light sources).

[0064] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer comprising one of the semiconductor materials selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the materials used to form the first conductive semiconductor layer 11 are not limited to these, and various other materials may be used to form the first conductive semiconductor layer 11.

[0065] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and may have a single quantum well structure or a multiple quantum well structure. In embodiments, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In embodiments, materials such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0066] If a threshold voltage or a higher voltage is applied to the opposite ends of the light-emitting element (LD), the LD can emit light through the recombination of electron-hole pairs in the active layer 12. Since the light emission of the LD can be controlled based on the aforementioned principle, the LD can be used as a light source for pixels in various light-emitting devices and display devices.

[0067] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the materials used to form the second conductive semiconductor layer 13 are not limited to these, and the second conductive semiconductor layer 13 may be formed from various other materials.

[0068] In an embodiment, the light-emitting element LD may further include an insulating film INF disposed on the surface of the light-emitting element LD. The insulating film INF may be formed on the surface of the light-emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround a region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow opposing ends of the light-emitting element LD with different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on opposing ends of the light-emitting element LD relative to the longitudinal direction, for example, exposing both surfaces (i.e., the upper surface and the lower surface) of the cylinder instead of covering them.

[0069] In the embodiments, the insulating film INF may include at least one insulating material selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed from various known insulating materials.

[0070] In embodiments, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may also include additional components. For example, the light-emitting element LD may also include one or more phosphor layers, one or more active layers, one or more semiconductor layers, and / or one or more electrode layers disposed on one end of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13.

[0071] Figure 2a and Figure 2b These are perspective views and cross-sectional views illustrating light-emitting elements according to embodiments of the present disclosure. Figure 3a and Figure 3b These are perspective views and cross-sectional views illustrating light-emitting elements according to embodiments of the present disclosure.

[0072] Reference Figure 2a and Figure 2b The light-emitting element LD may also include at least one electrode layer 14 disposed on one end of the second conductive semiconductor layer 13.

[0073] Reference Figure 3a and Figure 3b The light-emitting element LD may also include at least one electrode layer 15 disposed on one end of the first conductive semiconductor layer 11.

[0074] Each of electrode layers 14 and 15 can be an ohmic contact electrode, but is not limited thereto. Furthermore, each of electrode layers 14 and 15 can comprise a metal or a conductive metal oxide. For example, each of electrode layers 14 and 15 can be formed alone or in combination of transparent electrode materials such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)). Electrode layers 14 and 15 can be substantially transparent or translucent. Thus, light generated from the light-emitting element LD can be emitted to the outside after passing through electrode layers 14 and 15.

[0075] In embodiments, the insulating film INF may at least partially surround the outer surfaces of electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of electrode layers 14 and 15. Furthermore, the insulating film INF may be formed to expose opposing ends with different polarities of the light-emitting element LD, for example, it may expose at least one region of each of electrode layers 14 and 15. However, this disclosure is not limited thereto, and the insulating film INF may not be provided.

[0076] If the insulating film INF is disposed on the surface of the light-emitting element LD (e.g., on the surface of the active layer 12), a short circuit between the active layer 12 and at least one electrode (e.g., at least one of the contact electrodes connected to the opposite ends of the light-emitting element LD) can be prevented. Therefore, the electrical stability of the light-emitting element LD can be ensured.

[0077] Furthermore, an insulating film (INF) can be formed on the surface of the light-emitting element (LD), thereby minimizing surface defects and improving the LD's lifespan and efficiency. Additionally, the INF film prevents unwanted short circuits between LDs even when multiple LDs are arranged close together.

[0078] In this embodiment, the light-emitting element (LD) can be manufactured using a surface treatment process (e.g., coating). For example, when multiple LDs are mixed with a fluid solution (or solvent) to be supplied to each light-emitting area (e.g., the light-emitting area of ​​each pixel), the LDs can be uniformly dispersed without unevenly agglomerating in the solution. Here, the light-emitting area is the region in which light is emitted by the LD. The light-emitting area can be distinguished from the non-emitting area in which no light is emitted.

[0079] In some embodiments, the insulating film INF itself may be formed from a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed from a hydrophobic material may be formed on the insulating film INF. In embodiments, the hydrophobic material may be a fluorinated material to exhibit hydrophobicity. In embodiments, the hydrophobic material may be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. Furthermore, the hydrophobic material may be a commercially available fluorinated material, such as Teflon. TM Or Cytop TM Or the corresponding materials.

[0080] The light-emitting device including the light-emitting element LD described above can be used in various devices that include display devices requiring a light source. For example, at least one ultra-miniature light-emitting element LD (e.g., multiple ultra-miniature light-emitting element LDs, each having a size ranging from nanometers to micrometers) can be disposed in each pixel area of ​​a display panel to form the light source (or light source unit) of the corresponding pixel using the ultra-miniature light-emitting element LD. Furthermore, the application of the light-emitting element LD according to this disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices requiring a light source (such as lighting devices).

[0081] Figure 4 This is a plan view illustrating a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (specifically, a display panel PNL disposed in the display device) is shown as a reference that can be used. Figures 1a to 3b The described light-emitting element (LD) is an example of a device used as a light source. According to an embodiment, Figure 4 The structure of the display panel PNL is simply shown with emphasis on the display area DA. In some embodiments, although not shown, at least one drive circuit component (e.g., at least one of a scan driver and a data driver) and / or multiple lines may be further provided in the display panel PNL.

[0082] Reference Figure 4 The display panel PNL may include a substrate layer (or base) SUB1 and pixels PXL disposed on the substrate layer SUB1. Specifically, the display panel PNL and the substrate layer SUB1 may include a display area DA configured to display an image and a non-display area NDA other than the display area DA.

[0083] In this embodiment, the display area DA can be located in the central area of ​​the display panel PNL, and the non-display area NDA can be located along the boundary of the display panel PNL in a manner that surrounds the display area DA. The positions of the display area DA and the non-display area NDA are not limited to this, and their positions can be changed.

[0084] The substrate layer SUB1 can form the substrate portion of the display panel PNL. For example, the substrate layer SUB1 can form the substrate portion of the lower panel (e.g., the lower plate of the display panel PNL).

[0085] In the embodiments, the substrate layer SUB1 can be a rigid substrate or a flexible substrate, and its material or properties are not specifically limited. For example, the substrate layer SUB1 can be a rigid substrate made of glass or tempered glass, or a flexible substrate formed of a thin film made of plastic or metal. Furthermore, the substrate layer SUB1 can be a transparent substrate, but is not limited thereto. For example, the substrate layer SUB1 can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0086] The area on the substrate layer SUB1 where pixel PXL is disposed is defined as display area DA, while the other areas are defined as non-display area NDA. For example, the substrate layer SUB1 may include display area DA and non-display area NDA, where display area DA includes a plurality of pixel areas in which pixel PXL is formed, and non-display area NDA is disposed around display area DA. Various lines and / or internal circuitry connected to pixel PXL in display area DA may be disposed in non-display area NDA.

[0087] Pixel PXL may include at least one light-emitting element LD driven by a corresponding scan signal and a corresponding data signal (e.g., according to...). Figures 1a to 3b (At least one rod-shaped light-emitting diode in any of the embodiments shown). For example, a pixel PXL may include a plurality of rod-shaped light-emitting diodes, each having a small size ranging from nanometer to micrometer, and connected in parallel with each other. The plurality of rod-shaped light-emitting diodes may form the light source of the pixel PXL.

[0088] Furthermore, a pixel PXL may include multiple sub-pixels. For example, a pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit different colors of light. For example, the first sub-pixel SPX1 may be a red sub-pixel for emitting red light, the second sub-pixel SPX2 may be a green sub-pixel for emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel for emitting blue light. However, there are no specific limitations on the color, type, and / or number of sub-pixels forming each pixel PXL. For example, the color of the light emitted from each sub-pixel can be changed in various ways. Although in Figure 4 An embodiment in which pixels PXL are arranged in a stripe shape in display area DA is shown, but this disclosure is not limited thereto. For example, pixels PXL can be arranged in various known pixel array configurations.

[0089] In an embodiment, each of the sub-pixels SPX1, SPX2, and SPX3 may include multiple unit pixels.

[0090] Figure 5 It is shown that it includes Figure 4 A circuit diagram of an example of a sub-pixel in a display device. Figure 5 It shows that it includes Figure 4 The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 in the display device. Since the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are substantially identical to each other, except that they are connected to the corresponding data lines Dj, Dj+1, and Dj+2 respectively, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be described based on the first sub-pixel SPX1.

[0091] The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be respectively located in the region separated by scan lines Si-1 and Si (i is a positive integer) and data lines Dj, Dj+1, and Dj+2 (j is a positive integer). For example, the first sub-pixel SPX1 can be located in the region defined by the (i-1)th scan line Si-1 and the ith scan line Si, and the jth data line Dj and the (j+1)th data line Dj+1. However, the arrangement of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is not limited to this.

[0092] The first sub-pixel SPX1 can be connected to scan line Si and data line Dj, and can also be connected to a first power line and a second power line. Here, a first power supply VDD can be applied to the first power line, and a second power supply VSS can be applied to the second power line. Each of the first and second power lines can be a common line connecting multiple sub-pixels. The first power supply VDD and the second power supply VSS can have different potentials to allow the first sub-pixel SPX1 to emit light. The first power supply VDD can have a higher voltage level than the second power supply VSS.

[0093] In an embodiment, the first sub-pixel SPX1 may include at least one unit pixel SSPX1 to SSPXk (k is a natural number greater than 1).

[0094] Each of the unit pixels SSPX1 to SSPXk can be connected to the scan line Si and the data line Dj, and can also be connected to the first power line and the second power line. Each of the unit pixels SSPX1 to SSPXk can emit light with a brightness corresponding to the data signal transmitted through the data line Dj in response to the scan signal transmitted through the scan line Si. The unit pixels SSPX1 to SSPXk can include substantially the same pixel structure or pixel circuitry.

[0095] In other words, the first sub-pixel SPX1 may include unit pixels SSPX1 to SSPXk that independently emit light in response to a scan signal and a data signal.

[0096] In embodiments, each of the unit pixels SSPX1 to SSPXk (or sub-pixels SPX1 to SPX3) may be formed by an active pixel. However, the type, structure, and / or driving scheme of the unit pixels applicable to the display device according to this disclosure are not specifically limited. For example, the unit pixels may be formed by pixels of a display device having various known passive or active structures.

[0097] Figures 6a to 6d It is shown that it includes Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0098] Figure 6a The first unit pixel SSPX1 to the kth unit pixel SSPXk shown can have substantially the same or similar structures. Figures 6b to 6d The unit pixel SSPX shown can be set in Figure 6a Any one of the first unit pixels SSPX1 to the kth unit pixel SSPXk in the first sub-pixel SPX1. Therefore, in Figures 6a to 6d In the description, the first unit pixel SSPX1 to the kth unit pixel SSPXk will be collectively referred to as "unit pixel SSPX".

[0099] First, refer to Figure 6a The unit pixel SSPX may include a light source unit LSU that emits light with a brightness corresponding to the data signal. The unit pixel SSPX may also optionally include a pixel circuit PXC configured to drive the light source unit LSU.

[0100] In an embodiment, the light source unit LSU may include a plurality of light-emitting elements (LDs) electrically connected to each other between a first power supply VDD and a second power supply VSS. In an embodiment, the light-emitting elements (LDs) may be connected in parallel, but this disclosure is not limited thereto. For example, the plurality of light-emitting elements (LDs) may be connected between the first power supply VDD and the second power supply VSS in a series / parallel combination structure.

[0101] The first power supply VDD and the second power supply VSS can have different potentials to allow the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. Here, at least during the light-emitting period of the unit pixel SSPX (or the first sub-pixel SPX1), the potential difference between the first power supply VDD and the second power supply VSS can be set to the threshold voltage of the light-emitting element LD or greater.

[0102] Despite Figure 6a The illustration shows an embodiment in which light-emitting elements (LDs) are connected in parallel in the same direction (e.g., in the forward direction) between a first power supply VDD and a second power supply VSS, but the disclosure is not limited thereto. For example, some of the LDs may be connected to each other in the forward direction between the first power supply VDD and the second power supply VSS to form corresponding effective light sources, and other LDs may be connected to each other in the reverse direction. Alternatively, a unit pixel SSPX may include only a single LD (e.g., a single effective light source connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0103] According to an embodiment, one end of each of the light-emitting elements (LDs) can be commonly connected to the corresponding pixel circuit (PXC) via a first electrode, and can be connected to a first power supply (VDD) via the pixel circuit (PXC) and a first power line. The remaining end of each of the light-emitting elements (LDs) can be commonly connected to a second power supply (VSS) via a second electrode and a second power line.

[0104] The light source unit (LSU) can emit light with a brightness corresponding to the driving current supplied to it through the corresponding pixel circuit (PXC). Therefore, light can be emitted in the display area DA (refer to...). Figure 4 The pre-defined image is displayed in the image.

[0105] The pixel circuit PXC can be connected to the scan line Si and data line Dj of the corresponding sub-pixel (i.e., the first sub-pixel SPX1). For example, if the first sub-pixel SPX1 is located in the i-th row and j-th column of the display area DA, then the pixel circuit PXC of the unit pixel SSPX can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0106] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0107] A first transistor (or driving transistor) T1 can be connected between the first power supply VDD and the light source unit LSU. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0108] The second transistor (or switching transistor) T2 can be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 can be connected to the scan line Si.

[0109] In response to a scan signal supplied with a gate turn-on voltage (e.g., a low voltage) from scan line Si, the second transistor T2 can be turned on to electrically connect the first node N1 to the data line Dj.

[0110] During each frame period, the data signal for the corresponding frame can be supplied to the data line Dj. The data signal can be transmitted to the first node N1 via the second transistor T2. Consequently, the voltage corresponding to the data signal can be charged into the storage capacitor Cst.

[0111] The first electrode of the storage capacitor Cst can be connected to the first power supply VDD, and its second electrode can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period, and the charged voltage is maintained until the data signal of the subsequent frame is supplied.

[0112] although Figure 6a The illustration shows that all transistors (e.g., first transistor T1 and second transistor T2) included in the pixel circuit PXC are formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0113] For example, such as Figure 6b As shown, both the first transistor T1 and the second transistor T2 can be formed of N-type transistors. In this case, during each frame period, the gate turn-on voltage of the scan signal used to write the data signal supplied to the data line Dj into the unit pixel SSPX can be a high-level voltage. Similarly, the voltage of the data signal used to turn on the first transistor T1 can be a voltage with a voltage similar to that of the first transistor T1. Figure 6a The voltage waveform is the opposite of the waveform in the embodiment. For example, in Figure 6b In one embodiment, as the grayscale value to be represented increases, the voltage level of the data signal to be supplied can increase.

[0114] Apart from the fact that the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) vary depending on the type of transistor, Figure 6b The unit pixel SSPX shown is similar in construction and operation to Figure 6a The unit pixels of SSPX are basically similar. Therefore, the omission of... Figure 6b Detailed description of the unit pixel SSPX.

[0115] The structure of pixel circuits (PXC) is not limited to Figure 6a and Figure 6b The embodiment shown. In other words, the pixel circuit PXC can be formed from a known pixel circuit, which can have various structures and / or operate through various driving schemes. For example, the pixel circuit PXC can be used with... Figure 6c The embodiments shown are constructed in the same manner.

[0116] Reference Figure 6c The pixel circuit PXC can be connected not only to the corresponding scan line Si, but also to at least another scan line (or control line). For example, a sub-pixel SPX set in the i-th row in the display area DA (see...) Figure 7 The pixel circuit PXC of a sub-pixel (or the unit pixel SSPX included in the sub-pixel SPX) can also be connected to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In embodiments, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint.

[0117] In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0118] A first transistor T1 can be connected between a first power supply VDD and a light source unit LSU. The first electrode (e.g., the source electrode) of the first transistor T1 can be connected to the first power supply VDD via a fifth transistor T5, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to an electrode of the light source unit LSU (e.g., the first electrode of the corresponding sub-pixel SPX) via a sixth transistor T6. The gate electrode of the first transistor T1 can be connected to a first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0119] A second transistor T2 can be connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the corresponding scan line Si. When a scan signal with a gate on-state voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0120] The third transistor T3 can be connected between the second electrode (e.g., the drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the corresponding scan line Si. When a scan signal with a gate turn-on voltage is supplied from the scan line Si, the third transistor T3 can be turned on, causing the first transistor T1 to be connected in the form of a diode.

[0121] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the previous scan line (e.g., the (i-1)th scan line Si-1). When a scan signal with a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on, allowing the voltage of the initialization power supply Vint to be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint can be the minimum voltage of the data signal or less.

[0122] The fifth transistor T5 can be connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the corresponding emitter control line (e.g., the i-th emitter control line Ei). The fifth transistor T5 can be turned off when an emitter control signal with a gate cutoff voltage (e.g., a high voltage) is supplied to the emitter control line Ei, and can be turned on under other conditions.

[0123] The sixth transistor T6 can be connected between the first transistor T1 and the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 can be connected to the corresponding emission control line (e.g., the i-th emission control line Ei). The sixth transistor T6 can be turned off when the emission control signal with a gate cutoff voltage is supplied to the emission control line Ei, and can be turned on under other conditions.

[0124] A seventh transistor T7 can be connected between the first electrode of the light source unit LSU and the initialization power supply Vint (or a third power line configured to transmit initialization power). The gate electrode of the seventh transistor T7 can be connected to any of the scan lines in subsequent stages (e.g., to the (i+1)th scan line Si+1). When a scan signal with a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on, allowing the voltage of the initialization power supply Vint to be supplied to the first electrode of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU can be initialized.

[0125] The control signal used to control the operation of the seventh transistor T7 can be changed in different ways. For example, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal line (i.e., the i-th scan line Si). In this case, when a scan signal with a gate on-state voltage is supplied to the i-th scan line Si, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU.

[0126] A storage capacitor Cst can be connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0127] although Figure 6c The transistors included in the pixel circuit PXC (e.g., first transistor T1 to seventh transistor T7) are shown to be formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to seventh transistor T7 may be changed to an N-type transistor.

[0128] In this embodiment, in addition to the data line Dj, the pixel circuit PXC can also be connected to another line.

[0129] Reference Figure 6d The pixel circuit PXC can be connected to the sensing line SENj. The pixel circuit PXC may include first transistors T1 to third transistors T3 and a storage capacitor Cst. Because the first transistor T1, second transistor T2, and storage capacitor Cst are related to the reference... Figure 6b The first transistor T1 and the second transistor T2, as well as the storage capacitor Cst, are substantially the same or similar, therefore, their repeated descriptions will be omitted.

[0130] The third transistor T3 can be connected between the sensing line SENj and the second node N2. The gate electrode of the third transistor T3 can be connected to a second scan line S2 that is different from the first scan line S1 (e.g., a scan line Si+1 that is different from the i-th scan line Si).

[0131] The light source unit LSU can be connected between the second node N2 and the second power line (i.e., the power line to which the second power supply VSS is applied).

[0132] The third transistor T3 can be turned on in response to a scan signal of the gate turn-on voltage transmitted from the second scan line S2, so as to electrically connect the sensing line SENj to the second node N2.

[0133] For example, if the third transistor T3 is turned on using the drive current flowing in the first transistor T1 corresponding to the reference voltage, the drive current flowing through the first transistor T1 can be provided to an external sensing device through the third transistor T3 and the sensing line SENj, and a signal based on the drive current corresponding to the characteristics (e.g., Vth) of the first transistor T1 can be output to an external device through the sensing line SENj.

[0134] Furthermore, the structures applicable to the unit pixel SSPX of this disclosure are not limited to... Figures 6a to 6d The embodiment shown illustrates that the unit pixel SSPX can have various known structures. For example, the pixel circuit PXC included in the unit pixel SSPX can be formed by a known pixel circuit, which can have various structures and / or operate through various driving schemes. The unit pixel SSPX can be formed in a passive light-emitting display panel, etc. In this case, the pixel circuit PXC can be omitted, and each of the first and second electrodes of the light source unit LSU can be directly connected to the scan line Si, data line Dj, power line, and / or control line.

[0135] Figure 7 It is shown that it includes Figure 4 A plan view of an example of a subpixel in a display device. Figure 8 It is shown Figure 7 A planar diagram of the first sub-pixel in the sub-pixels. Figure 7 A light source unit LSU (reference) is shown, which includes sub-pixels SPX1 to SPX3. Figures 6a to 6d The structure of sub-pixels SPX1 to SPX3 (or light-emitting element layer) is described. Since the first sub-pixels SPX1 to the third sub-pixels SPX3 are substantially identical to each other, the light source unit LSU will be described based on the first sub-pixel SPX1. The sub-pixel region SPA includes the first sub-pixel region SPA1, the second sub-pixel region SPA2, and the third sub-pixel region SPA3, and the first sub-pixel region SPA1, the second sub-pixel region SPA2, and the third sub-pixel region SPA3 are substantially identical to each other. The emission region EMA includes the first sub-emission region EMA1, the second sub-emission region EMA2, and the third sub-emission region EMA3, and the first sub-emission region EMA1, the second sub-emission region EMA2, and the third sub-emission region EMA3 are substantially identical to each other. Therefore, the first sub-emission region EMA1 in the first sub-pixel region SPA1 will be described in detail. Furthermore, the unit pixel in each sub-pixel can receive the same electrical signal. Therefore, in this embodiment, an example in which each of the sub-pixels includes one unit pixel will be described.

[0136] Reference Figure 7 and Figure 8The first sub-pixel SPX1 may include a first electrode ELT1 and a second electrode ELT2 disposed at positions spaced apart from each other in the first sub-pixel region SPA1, and at least one light-emitting element LD connected between the first electrode ELT1 and the second electrode ELT2.

[0137] In this embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, respectively included in the first sub-pixels SPX1 to the third sub-pixels SPX3, can emit light of the same or different colors. For example, each first light-emitting element LD1 can be a red light-emitting diode configured to emit red light. Each second light-emitting element LD2 can be a green light-emitting diode configured to emit green light. Each third light-emitting element LD3 can be a blue light-emitting diode configured to emit blue light.

[0138] For example, all of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be formed by a blue light-emitting diode configured to emit blue light. In this case, in order to form a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of the light emitted from the corresponding sub-pixel SPX can be provided on at least some of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0139] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at spaced-apart locations in the first sub-pixel region SPA1, such that at least some regions of them face each other. For example, the first electrode ELT1 and the second electrode ELT2 may typically be arranged alternately in the first direction DR1, spaced apart from each other by a predetermined distance and arranged parallel to each other.

[0140] In an embodiment, a light-emitting region may be defined by each sub-pixel region. The light-emitting regions may be distinguished by non-light-emitting regions. Although not clearly shown, a pixel-defining layer (or dam, light-blocking pattern) for preventing light emitted from the light-emitting element LD from transmitting to another region may be disposed in the non-light-emitting region to overlap with it.

[0141] In an embodiment, the first electrode ELT1 may be connected to the first connecting electrode CNL1. The first electrode ELT1 may be integrally connected to the first connecting electrode CNL1. For example, the first electrode ELT1 may be formed by at least one branch branching from the first connecting electrode CNL1. In other words, the first electrode ELT1 may extend from the first connecting electrode CNL1 (or the first connecting line). If the first electrode ELT1 and the first connecting electrode CNL1 are integrally formed with each other, the first connecting electrode CNL1 can be considered as a region of the first electrode ELT1. However, this disclosure is not limited thereto.

[0142] The first connecting electrode CNL1 can be connected to the reference. Figure 6a , Figure 6c and Figure 6d The first electric field line described (i.e., the electric field line to which the first power source VDD is applied).

[0143] In an embodiment, the second electrode ELT2 can be connected to the second connecting electrode CNL2. The second electrode ELT2 can be integrally connected to the second connecting electrode CNL2. For example, the second electrode ELT2 can be formed by at least one branch branching from the second connecting electrode CNL2. In other words, the second electrode ELT2 can extend from the second connecting electrode CNL2 (or the second connecting line) in the second direction DR2. If the second electrode ELT2 and the second connecting electrode CNL2 are integrally formed with each other, the second connecting electrode CNL2 can be considered as a region of the second electrode ELT2.

[0144] The second connecting electrode CNL2 can be connected to the reference. Figure 6a , Figure 6c and Figure 6d The second power line described (i.e., the power line to which the second power source VSS is applied).

[0145] The first connecting electrode CNL1 and the second connecting electrode CNL2 can be spaced apart from each other by a predetermined distance. The first electrode ELT1 and the second electrode ELT2 can be formed between the first connecting electrode CNL1 and the second connecting electrode CNL2.

[0146] The first connection electrode CNL1 can be connected to the pixel circuit PXC (or the first transistor T1). For example, the first connection electrode CNL1 can be connected to the pixel circuit PXC (or the first transistor T1) through the contact hole CH.

[0147] In the embodiments, each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. Although not clearly shown, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode and a first conductive capping layer, and the second electrode may have a multi-layer structure including a second reflective electrode and a second conductive capping layer.

[0148] Both the first electrode ELT1 and the second electrode ELT2 can have a curved shape. For example, if both the first connecting electrode CNL1 and the second connecting electrode CNL2 have a shape extending in a first direction DR1, then the first electrode ELT1 and the second electrode ELT2 can typically extend in a second direction DR2 intersecting the first direction DR1 and bend in the first direction DR1. Both the first electrode ELT1 and the second electrode ELT2 can have a curved shape (e.g., a "U" shape or an "S" shape) or a zigzag shape (e.g., a "V" shape or a "W" shape). In other words, each of the first electrode ELT1 and the second electrode ELT2 can typically extend in only one direction (e.g., the second direction DR2) and have a curved portion protruding from at least a portion of itself in a direction intersecting the extension direction (e.g., the first direction DR1), rather than having a linear shape extending in only one direction (e.g., the second direction DR2). The curved portion can be formed by a curve or by a combination of linear lines extending in two different directions.

[0149] However, this disclosure is not limited thereto. For example, the shape and / or arrangement of the first electrode ELT1 and the second electrode ELT2 can be changed in various ways.

[0150] Reference Figure 8 The first partition wall PW1 can be disposed below the first electrode ELT1 and superimposed on a region of the first electrode ELT1. The second partition wall PW2 can be disposed below the second electrode ELT2 and superimposed on a region of the second electrode ELT2. The first partition wall PW1 and the second partition wall PW2 can be disposed at positions spaced apart from each other in the first sub-emission region EMA1, and the regions of the first electrode ELT1 and the second electrode ELT2 can protrude upwards. For example, the first electrode ELT1 can be disposed on the first partition wall PW1 and protrude in the height direction (or thickness direction) of the substrate layer SUB1 through the first partition wall PW1. The second electrode ELT2 can be disposed on the second partition wall PW2 and protrude in the height direction of the substrate layer SUB1 through the second partition wall PW2. The first partition wall PW1 and the second partition wall PW2 may also include curved portions corresponding to the shapes of the first electrode ELT1 and the second electrode ELT2 superimposed with the first partition wall PW1 and the second partition wall PW2.

[0151] In an embodiment, at least one light-emitting element (LD) (e.g., multiple light-emitting elements LD) may be arranged between a first electrode ELT1 and a second electrode ELT2. Multiple light-emitting elements LD may be connected in parallel to each other in a first sub-emission region EMA1, where the first electrode ELT1 and the second electrode ELT2 are positioned facing each other.

[0152] although Figure 8 The diagram shows the light-emitting element (LD) aligned in the normal direction relative to the first electrode ELT1 and the second electrode ELT2 along their extending directions (the longitudinal direction of the LD is aligned in the normal direction relative to the first electrode ELT1 and the second electrode ELT2 along their extending directions), but the alignment direction of the LD is not limited to this. For example, at least one of the LDs can be aligned in a diagonal direction relative to the extending direction and the normal direction of the first electrode ELT1 and the second electrode ELT2.

[0153] Each of the light-emitting elements (LDs) can be electrically connected between a first electrode ELT1 and a second electrode ELT2. For example, the corresponding first end EP1 of the light-emitting element LD (see...) Figure 9a It can be electrically connected to the first electrode ELT1. The corresponding second end EP2 of the light-emitting element LD (see...) Figure 9a It can be electrically connected to the second electrode ELT2.

[0154] In one embodiment, the first end of each of the light-emitting elements (LDs) can be electrically connected to the first electrode ELT1 via at least one contact electrode (e.g., the first contact electrode CNE1), rather than being directly disposed on the first electrode ELT1. However, this disclosure is not limited thereto. For example, in an embodiment of this disclosure, the first end of the light-emitting element (LD) can directly contact and be electrically connected to the first electrode ELT1.

[0155] Similarly, the second end of each of the light-emitting elements LD can be electrically connected to the second electrode ELT2 via at least one contact electrode (e.g., the second contact electrode CNE2), rather than being directly disposed on the second electrode ELT2. However, this disclosure is not limited thereto. For example, in embodiments of this disclosure, the second end of each of the light-emitting elements LD can directly contact and be electrically connected to the second electrode ELT2.

[0156] In an embodiment, each of the light-emitting elements (LDs) can be formed of a light-emitting diode (LED) made of a material having an inorganic crystal structure and having an ultra-small size, for example, ranging from the nanometer scale to the micrometer scale. For example, each of the light-emitting elements (LDs) can be as follows: Figures 1a to 3b Any of the examples shown are ultra-small light-emitting diodes with dimensions ranging from nanometers to micrometers. However, the types of light-emitting elements (LDs) that can be applied to this disclosure are not limited to these. For example, a light-emitting element (LD) can be formed by a growth scheme and is, for example, a light-emitting diode with a core-shell structure having dimensions ranging from nanometers to micrometers.

[0157] In an embodiment, the light-emitting element (LD) can be prepared in a predetermined solution by diffusion and then supplied to the emission region EMA of each sub-pixel SPX via an inkjet printing scheme or a slot coating scheme. Furthermore, the LD can be supplied to the emission region EMA simultaneously. For example, the LD can be mixed with a volatile solvent and supplied to the emission region EMA. Here, if a predetermined voltage is supplied to the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, thereby enabling the LD to self-align between the first electrode ELT1 and the second electrode ELT2. After the LD has been aligned, the solvent can be removed by an evaporation scheme or other methods. In this way, the LD can be reliably arranged between the first electrode ELT1 and the second electrode ELT2. Furthermore, since the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the first end and the second end of the LD, respectively, the LD can be reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0158] Since no separate circuit elements or lines are provided between the first electrode ELT1 and the second electrode ELT2 and the substrate layer SUB1, interference caused by circuit elements, conductive patterns, etc., can be prevented during the formation of an electric field between the first electrode ELT1 and the second electrode ELT2. Therefore, the alignment efficiency of the light-emitting element LD can be improved.

[0159] In an embodiment, a first contact electrode CNE1 may be formed on a first end of the light-emitting element LD and at least one region of the first electrode ELT1 corresponding to the first contact electrode CNE1, thereby physically and / or electrically connecting the first end of the light-emitting element LD to the first electrode ELT1. Similarly, a second contact electrode CNE2 may be formed on a second end EP2 of the light-emitting element LD and at least one region of the second electrode ELT2 corresponding to the second contact electrode CNE2, thereby physically and / or electrically connecting the second end of the light-emitting element LD to the second electrode ELT2.

[0160] Light-emitting elements (LDs) disposed in the emission region EMA can be grouped to form light sources for corresponding unit pixels (and sub-pixels SPX). If a driving current flows through at least one sub-pixel SPX during each frame period, the light-emitting elements (LDs) connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX can emit light with a brightness corresponding to the driving current.

[0161] The light emitted from each light-emitting element (LD) can be directional. The first electrode ELT1 and the second electrode ELT2 can have curved portions, rather than extending in only one direction. Therefore, the light-emitting elements (LDs) aligned in the normal direction relative to the direction in which the first electrode ELT1 and the second electrode ELT2 extend can be positioned in various directions depending on the alignment position. This improves the viewing angle of the display device.

[0162] Figures 9a to 9d It shows along Figure 8 A cross-sectional view of an example of a unit pixel intercepted by line I-I'. Figures 9a to 9d Each is illustrated as any one of the sub-pixel regions SPA (e.g., the first sub-pixel region SPA1) formed in the display panel PNL. In embodiments, the cross-sectional structures of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 described above may be substantially the same or similar to each other. Therefore, for illustrative purposes, in Figures 9a to 9d In this context, the structure of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be described together based on the first sub-pixel SPX1.

[0163] Reference Figure 9a The pixel circuit layer (PCL) and the display element layer (LDL) can be sequentially disposed on the substrate layer (SUB1) in each sub-pixel region (SPA). In an embodiment, the pixel circuit layer (PCL) and the display element layer (LDL) can be formed in the entire display area (DA) of the display panel (PNL).

[0164] In an embodiment, the pixel circuit layer PCL may include circuit elements of the pixel circuit PXC constituting the sub-pixel SPX. The display element layer LDL may include the light-emitting element LD of the sub-pixel SPX (or unit pixel SSPX).

[0165] For example, in the first sub-pixel region SPA1 on the substrate layer SUB1, a pixel circuit layer PCL including circuit elements of the pixel circuit PXC constituting the corresponding first sub-pixel SPX1 and a display element layer LDL including at least one light-emitting element LD (e.g., multiple first light-emitting elements LD1) disposed in the first sub-pixel SPX1 can be sequentially disposed on one surface of the substrate layer SUB1.

[0166] In an embodiment, the pixel circuit layer PCL may include multiple circuit elements of a pixel circuit PXC formed in the first sub-pixel region SPA1 and forming the first sub-pixel SPX1 (or the first unit pixel SSPX1). For example, the pixel circuit layer PCL may include multiple transistors disposed in the first sub-pixel region SPA1 (e.g., Figure 6a The first transistor T1 and the second transistor T2). Although Figure 9aNot shown, but the pixel circuit layer PCL may include a storage capacitor Cst disposed in the sub-pixel region SPA, and various signal lines connected to the pixel circuit PXC (e.g., Figure 5 The scan line Si and data line Dj shown are shown, as well as various power lines connected to the pixel circuit PXC and / or the light-emitting element LD (e.g., a first power line (not shown) and a second power line configured to transmit the voltage of a first power supply VDD and the voltage of a second power supply VSS, respectively).

[0167] In embodiments, the plurality of transistors disposed in the pixel circuit PXC (e.g., first transistor T1 and second transistor T2) may have substantially the same or similar cross-sectional structures. However, this disclosure is not limited thereto. In embodiments, at least some of the plurality of transistors may have different types and / or structures.

[0168] Furthermore, the pixel circuit layer PCL may include multiple insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV, which are stacked sequentially on one surface of the substrate layer SUB1.

[0169] In this embodiment, the buffer layer BFL prevents impurities from diffusing into the circuit elements. The buffer layer BFL can be formed as a single layer or as a multilayer having at least two layers. In the case of a multilayer structure, the individual layers can be formed from the same material or different materials. In this embodiment, the buffer layer BFL can be omitted.

[0170] In an embodiment, each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Although Figure 9a The illustration shows that each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but this disclosure is not limited thereto. For example, in embodiments of this disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 disposed in at least one transistor disposed in each sub-pixel region SPA may be integrally formed with the corresponding semiconductor layer SCL.

[0171] The semiconductor layer SCL can be disposed on the buffer layer BFL. For example, the semiconductor layer SCL can be disposed between the gate insulating layer GI and the substrate layer SUB1 on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0172] In this embodiment, the semiconductor layer SCL can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region of the semiconductor layer SCL can be an intrinsic semiconductor of an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL can be a semiconductor pattern doped with a predetermined impurity.

[0173] The gate electrode GE can be disposed on the semiconductor layer SCL and the gate insulating layer GI is disposed between the gate electrode GE and the semiconductor layer SCL. For example, the gate electrode GE can be disposed between the gate insulating layer GI and the interlayer insulating layer ILD, and stacked with at least one region of the semiconductor layer SCL.

[0174] The first transistor electrode ET1 and the second transistor electrode ET2 can be disposed above the semiconductor layer SCL and the gate electrode GE, with at least one interlayer insulating layer ILD located between the first transistor electrode ET1 and the second transistor electrode ET2 and the semiconductor layer SCL and the gate electrode GE. For example, the first transistor electrode ET1 and the second transistor electrode ET2 can be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 can be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 can be connected to a first region and a second region of the semiconductor layer SCL, respectively, through contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0175] In an embodiment, at least one transistor (e.g., ) is disposed in the pixel circuit PXC. Figure 6a Either the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 shown can be electrically connected to the first electrode ELT1 of the light source unit LSU disposed on the passivation layer PSV through the contact hole CH passing through the passivation layer PSV.

[0176] Although not shown, in embodiments, at least one signal line and / or power line connected to the sub-pixel SPX may be disposed on the same layer as the layer of one electrode in each of the circuit elements forming the pixel circuit PXC. For example, a second power line may be disposed on the same layer as the layer of the gate electrode GE of each of the first transistor T1 and the second transistor T2. However, the structure and / or location of the second power line, etc., may be changed in various ways.

[0177] The display element layer (LDL) may include a first partition wall (PW1) and a second partition wall (PW2), a first electrode (ELT1) and a second electrode (ELT2), a first insulating layer (INS1), a light-emitting element (LD), a second insulating layer (INS2), a first contact electrode (CNE1) and a second contact electrode (CNE2), and a third insulating layer (INS3) sequentially disposed and / or formed on the pixel circuit layer (PCL).

[0178] The first separator wall PW1 and the second separator wall PW2 can be disposed on the pixel circuit layer PCL. The first separator wall PW1 and the second separator wall PW2 can be disposed at positions spaced apart from each other in the first sub-emitting region EMA1. The first separator wall PW1 and the second separator wall PW2 can protrude in the height direction on the pixel circuit layer PCL. In an embodiment, the first separator wall PW1 and the second separator wall PW2 can have substantially the same height, but this disclosure is not limited thereto.

[0179] In this embodiment, the first partition wall PW1 may be disposed between the pixel circuit layer PCL and the first electrode ELT1. The first partition wall PW1 may be configured to be adjacent to the first end EP1 of the light-emitting element LD. For example, one sidewall of the first partition wall PW1 may be positioned adjacent to the first end EP1 of the light-emitting element LD and configured to face the first end EP1.

[0180] In this embodiment, the second partition wall PW2 may be disposed between the pixel circuit layer PCL and the second electrode ELT2. The second partition wall PW2 may be configured to be adjacent to the second end EP2 of the light-emitting element LD. For example, one sidewall of the second partition wall PW2 may be positioned adjacent to the second end EP2 of the light-emitting element LD and configured to face the second end EP2.

[0181] In embodiments, each of the first partition wall PW1 and the second partition wall PW2 can have various shapes. For example, as Figure 9a As shown, each of the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-sectional shape with a decreasing width from its bottom to its top. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. Alternatively, as... Figure 9bAs shown, each of the first partition wall PW1 and the second partition wall PW2 may have a semi-circular or semi-elliptical cross-section with a decreasing width from its bottom to its top. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side. In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 can be varied in various ways, rather than being specifically limited. In embodiments, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or its position changed.

[0182] Each of the first separator PW1 and the second separator PW2 may include an insulating material having inorganic and / or organic materials. For example, the first separator PW1 and the second separator PW2 may include at least one inorganic layer, which includes various inorganic insulating materials known to those skilled in the art (such as SiN). x or SiO x Alternatively, the first separator PW1 and the second separator PW2 may comprise at least one organic layer containing various known organic insulating materials and / or a photoresist layer, or may form a single-layer insulator or a multi-layer insulator containing a combination of organic and inorganic materials. In other words, the constituent materials of the first separator PW1 and the second separator PW2 may be varied.

[0183] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 can be used as a reflective member. For example, the first partition wall PW1 and the second partition wall PW2, as well as the first electrode ELT1 and the second electrode ELT2 disposed thereon, can be used as a reflector to guide the light emitted from each light-emitting element LD in a desired direction, thereby enhancing the light efficiency of the pixel PXL.

[0184] The first electrode ELT1 and the second electrode ELT2 can be disposed on the first partition wall PW1 and the second partition wall PW2, respectively. The first electrode ELT1 and the second electrode ELT2 can be disposed at positions spaced apart from each other in the first sub-emission region EMA1.

[0185] In an embodiment, the first electrode ELT1 and the second electrode ELT2, respectively disposed on the first partition wall PW1 and the second partition wall PW2, may have shapes corresponding to the corresponding shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ELT1 and the second electrode ELT2 may have inclined surfaces or curved surfaces corresponding to the first partition wall PW1 and the second partition wall PW2, respectively, and protrude in the height direction (or thickness direction) of the display element layer LDL.

[0186] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti or alloys thereof), a conductive oxide (such as ITO, IZO, ZnO or ITZO), and a conductive polymer (such as PEDOT); however, it is not limited thereto.

[0187] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. Each of the first electrode ELT1 and the second electrode ELT2 may optionally further include at least one of at least one transparent electrode layer and at least one conductive capping layer, wherein the at least one transparent electrode layer is disposed on the upper and / or lower portion of the reflective electrode layer, and the at least one conductive capping layer covers the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0188] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be formed of a conductive material having uniform reflectivity. For example, the reflective electrode layer may include at least one of metals and alloys thereof, such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr; however, this disclosure is not limited thereto. In other words, the reflective electrode layer can be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2, including a reflective electrode layer, enables light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light-emitting elements LD to travel more reliably in the direction in which the image is displayed (e.g., in the frontal direction). Specifically, if the first electrode ELT1 and the second electrode ELT2 respectively have inclined or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, and are respectively positioned facing the first end EP1 and the second end EP2 of the light-emitting element LD, then the light emitted from the first end EP1 and the second end EP2 of each light-emitting element LD can be reflected by the first electrode ELT1 and the second electrode ELT2. Therefore, it travels more reliably in the front direction of the display panel PNL (e.g., in the upward direction of the substrate layer SUB1). Thus, the efficiency of the light emitted from the light-emitting element LD can be improved.

[0189] Furthermore, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but this disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure, which has an ITO / Ag / ITO stacked structure. Thus, if the first electrode ELT1 and the second electrode ELT2 are each formed with a multilayer structure of at least two layers, the voltage drop due to signal delay (RC delay) can be minimized. Therefore, the desired voltage can be efficiently transmitted to the light-emitting element LD.

[0190] Furthermore, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, it is possible to prevent the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive capping layer may be optionally included in the first electrode ELT1 and the second electrode ELT2, and may be omitted according to embodiments. Furthermore, the conductive capping layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component disposed on the first electrode ELT1 and the second electrode ELT2.

[0191] The first insulating layer INS1 may be disposed on a region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover a region of each of the first electrode ELT1 and the second electrode ELT2, and may include an opening exposing another region of each of the first electrode ELT1 and the second electrode ELT2.

[0192] In an embodiment, the first insulating layer INS1 may initially be formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is supplied and aligned on the first insulating layer INS1, as... Figure 9a As shown, the first insulating layer INS1 may be partially open to expose the first electrode ELT1 and the second electrode ELT2. Alternatively, the first insulating layer INS1 may be patterned as a separate pattern, which is partially disposed under the light-emitting element LD after the supply and alignment of the light-emitting element LD have been completed.

[0193] In other words, the first insulating layer INS1 can be placed between the first electrode ELT1 and the second electrode ELT2 and the light-emitting element LD, and can expose at least one area of ​​each of the first electrode ELT1 and the second electrode ELT2. After the first electrode ELT1 and the second electrode ELT2 are formed, the first insulating layer INS1 can be formed to cover the first electrode ELT1 and the second electrode ELT2, thereby preventing damage to the first electrode ELT1 and the second electrode ELT2 or preventing metal from depositing in subsequent processes. Furthermore, the first insulating layer INS1 can stably support each light-emitting element LD. In embodiments, the first insulating layer INS1 can be omitted.

[0194] The light-emitting element LD can be supplied to and aligned in the emitting region EMA in which the first insulating layer INS1 is formed. For example, multiple light-emitting elements LD can be supplied to the emitting region EMA by inkjet method or the like, and the light-emitting elements LD can be aligned between the first electrode ELT1 and the second electrode ELT2 by applying a predetermined alignment voltage (or alignment signal) to the first electrode ELT1 and the second electrode ELT2.

[0195] The dam BNK can be disposed on the first insulating layer INS1. For example, the dam BNK can be formed between other sub-pixels to surround the emission region EMA of the sub-pixel SPX, so that a pixel defining layer for defining the emission region EMA of the sub-pixel SPX can be formed.

[0196] In an embodiment, the dam BNK can be formed with a second height greater than the first height of the first partition wall PW1 and the second partition wall PW2. In this case, during the step of supplying the light-emitting element LD to each emission region EMA, the dam BNK can serve as a dam structure configured to prevent the solution mixed with the light-emitting element LD from entering the emission region EMA of the adjacent sub-pixel SPX, or to control the amount of solution such that a constant amount of solution is supplied to each emission region EMA.

[0197] A dam BNK can be formed to prevent light emitted from each emission region EMA from entering adjacent emission regions EMA and causing optical interference. To this end, a dam BNK can be formed to prevent light emitted from the light-emitting element LD of each sub-pixel SPX from passing through the dam BNK.

[0198] In some embodiments, the embankment BNK may not be located in the sub-transmission areas EMA1 and EMA2 (see reference). Figure 7 (between), but this disclosure is not limited thereto.

[0199] The second insulating layer INS2 can be disposed on the light-emitting element LD (specifically, the light-emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2), and can expose the first end EP1 and the second end EP2 of the light-emitting element LD. For example, the second insulating layer INS2 can be disposed only partially on some areas of the light-emitting element LD, without covering the first end EP1 and the second end EP2 of the light-emitting element LD. The second insulating layer INS2 can be formed in an independent pattern in each emitting region EMA, but this disclosure is not limited thereto. Furthermore, as Figure 9a As shown, if there is a space between the first insulating layer INS1 and the light-emitting element LD before the second insulating layer INS2 is formed, the space can be filled with the second insulating layer INS2. Therefore, the light-emitting element LD can be supported more stably.

[0200] The first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the first electrode ELT1, the second electrode ELT2, and the first end EP1 and the second end EP2 of the light-emitting element LD. In an embodiment, as shown... Figure 9a As shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed in the same layer. In this case, although the first contact electrode CNE1 and the second contact electrode CNE2 are formed using the same conductive material and the same process, this disclosure is not limited thereto.

[0201] The first contact electrode CNE1 and the second contact electrode CNE2 can respectively connect the first end EP1 and the second end EP2 of the light-emitting element LD to the first electrode ELT1 and the second electrode ELT2.

[0202] For example, the first contact electrode CNE1 can be disposed on the first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 can be disposed on a region of the first electrode ELT1 not covered by the first insulating layer INS1 to contact the first electrode ELT1. Furthermore, the first contact electrode CNE1 can be disposed on a first end EP1 of at least one light-emitting element adjacent to the first electrode ELT1 (e.g., disposed on the corresponding first end EP1 of a plurality of light-emitting elements LD), such that the first contact electrode CNE1 can contact the first end EP1. In other words, the first contact electrode CNE1 can be disposed to cover at least one region of the first end EP1 of the light-emitting element LD and the corresponding first electrode ELT1. Therefore, the first end EP1 of the light-emitting element LD can be electrically connected to the first electrode ELT1.

[0203] Similarly, the second contact electrode CNE2 can be disposed on the second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 can be disposed on a region of the second electrode ELT2 that is not covered by the first insulating layer INS1 to contact the second electrode ELT2. Furthermore, the second contact electrode CNE2 can be disposed on the second end EP2 of at least one light-emitting element adjacent to the second electrode ELT2 (e.g., disposed on the second end EP2 of multiple light-emitting elements LD), such that the second contact electrode CNE2 can contact the second end EP2. In other words, the second contact electrode CNE2 can be disposed to cover at least one region of the second end EP2 of the light-emitting element LD and the corresponding second electrode ELT2. Therefore, the second end EP2 of the light-emitting element LD can be electrically connected to the second electrode ELT2.

[0204] The third insulating layer INS3 can be formed and / or disposed on a surface of the substrate layer SUB1 on which the first separator wall PW1 and the second separator wall PW2, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the dam BNK are formed, such that the third insulating layer INS3 can cover the first separator wall PW1 and the second separator wall PW2, the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the dam BNK. The third insulating layer INS3 may include a thin film encapsulation layer, which includes at least one inorganic layer and / or an organic layer, but this disclosure is not limited thereto. In some embodiments, at least one outer coating layer (not shown) may be further disposed on the third insulating layer INS3.

[0205] In the embodiments, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may have a single-layer structure or a multi-layer structure, and includes at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include various types of known organic / inorganic insulating materials and SiN. x Furthermore, the constituent materials of each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 are not specifically limited. The first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may comprise different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may comprise the same insulating material.

[0206] In this embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed in different layers.

[0207] Reference Figure 9c The first contact electrode CNE1 can be disposed in the sub-pixel region SPA in which the second insulating layer INS2 is disposed. In an embodiment, the first contact electrode CNE1 can be disposed on the first electrode ELT1 disposed in the corresponding sub-pixel region SPA, such that the first contact electrode CNE1 contacts a region of the first electrode ELT1. Furthermore, the first contact electrode CNE1 can be disposed on the first end EP1 of at least one light-emitting element LD disposed in the corresponding sub-pixel region SPA, such that the first contact electrode CNE1 contacts the first end EP1. Due to the first contact electrode CNE1, the first end EP1 of at least one light-emitting element LD disposed in the sub-pixel region SPA can be electrically connected to the first electrode ELT1 disposed in the corresponding sub-pixel region SPA.

[0208] A fourth insulating layer INS4 can be disposed in the sub-pixel region SPA in which the first contact electrode CNE1 is disposed. In an embodiment, the fourth insulating layer INS4 can cover the second insulating layer INS2 and the first contact electrode CNE1 disposed in the corresponding sub-pixel region SPA.

[0209] In embodiments, the fourth insulating layer INS4 may have a single-layer or multi-layer structure, and may include at least one inorganic and / or organic insulating material in a manner similar to that of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. For example, the fourth insulating layer INS4 may include various types of known organic / inorganic insulating materials (including SiN). x Furthermore, the fourth insulating layer INS4 may include an insulating material that is different from the insulating material of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3, or may include an insulating material that is the same as the insulating material of at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0210] The second contact electrode CNE2 can be disposed in each sub-pixel region SPA in which the fourth insulating layer INS4 is disposed. In an embodiment, the second contact electrode CNE2 can be disposed on the second electrode ELT2 disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts a region of the second electrode ELT2. Furthermore, the second contact electrode CNE2 can be disposed on the second end EP2 of at least one light-emitting element LD disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts the second end EP2. Due to the second contact electrode CNE2, the second end EP2 of at least one light-emitting element LD disposed in each sub-pixel region SPA can be electrically connected to the second electrode ELT2 disposed in the corresponding sub-pixel region SPA.

[0211] In embodiments, each of the first partition wall PW1 and the second partition wall PW2 can have various shapes. For example, as Figure 9c As shown, each of the first partition wall PW1 and the second partition wall PW2 can have a trapezoidal cross-sectional shape with a decreasing width from its bottom to its top. Alternatively, as... Figure 9d As shown, each of the first partition wall PW1 and the second partition wall PW2 may have a semi-circular or semi-elliptical cross-section with a decreasing width from its bottom to its top.

[0212] Next, a display device according to another embodiment will be described. Hereinafter, the light source unit LSU will be described with the first sub-pixel SPX1 as the center. Furthermore, details will be omitted here. Figures 1a to 9d The components shown are described repeatedly, and the same or similar reference numerals are used.

[0213] Figure 10 It is shown that it includes Figure 4 A plan view of another example of subpixels in a display device. Besides the emission area EMA, Figure 10 The first sub-pixel SPX1 can be with Figure 7 The first sub-pixel SPX1 is essentially the same. Therefore, its repeated description will be omitted.

[0214] Reference Figure 10 According to this embodiment, both the first electrode ELT1 and the second electrode ELT2 can have a zigzag shape. Both the first electrode ELT1 and the second electrode ELT2 can include linear portions STR1 and STR2 extending diagonally relative to the first direction DR1 and the second direction DR2. The first electrode ELT1 and the second electrode ELT2 can also include linear portions STR1 and STR2 extending in different directions. Two adjacent linear portions STR1 and STR2 extending in different directions can meet to form a curved portion.

[0215] The light-emitting elements (LDs) can be aligned in the normal direction relative to the first electrode ELT1 and the second electrode ELT2 along their extension direction, and their alignment direction can be changed according to their alignment position. Therefore, the viewing angle of the display device can be improved.

[0216] Figure 11 It is shown that it includes Figure 4 A plan view of another example of a subpixel in a display device.

[0217] Reference Figure 11According to this embodiment, both the first electrode ELT1 and the second electrode ELT2 may include linear portions STR1 and STR2 extending in a diagonal direction relative to the first direction DR1 and the second direction DR2, and a linear portion STR3 extending in the second direction DR2. Both the first electrode ELT1 and the second electrode ELT2 may include a linear portion STR3, each of which extends in the second direction DR2 between two linear portions STR1 and STR2 extending in the diagonal direction.

[0218] The alignment direction of the light-emitting element (LD) can be changed according to its alignment position. Therefore, the viewing angle of the display device can be improved in the same manner as in the aforementioned embodiments.

[0219] Figure 12 It is shown that it includes Figure 4 A plan view of another example of a subpixel in a display device. Figure 13 It is used to describe Figure 12 A view showing the shapes of the first and second electrodes.

[0220] Reference Figure 12 and Figure 13 According to this embodiment, both the first electrode ELT1 and the second electrode ELT2 can have a curved shape including an inflection point INFL. In both the first electrode ELT1 and the second electrode ELT2, the curved portions between adjacent inflection points INFL can have an arc shape. For example, each of the first electrode ELT1 and the second electrode ELT2 can have a shape formed by dividing an electrode with a ring shape into two or four identical parts and recombining the divided parts. A portion HARC (ARC3 and ARC4) of each of the first electrode ELT1 and the second electrode ELT2 can have a semi-circular arc shape, and the remaining portions ARC1 and ARC2 can both have a quadrant arc shape. Each of the first electrode ELT1 and the second electrode ELT2 can have a shape in which the opposite ends of the shape are formed by portions ARC1 and ARC2, each having a quadrant arc shape, and portions HARC (ARC3 and ARC4) having a semi-circular arc shape are connected between portions ARC1 and ARC2, each having a quadrant arc shape.

[0221] The alignment direction of the light-emitting element (LD) can be changed according to its alignment position. Therefore, the viewing angle of the display device can be improved in the same manner as in the aforementioned embodiments.

[0222] Figure 14 It is shown that it includes Figure 4 A plan view of another example of a subpixel in a display device.

[0223] Reference Figure 14According to this embodiment, each of the first electrode ELT1 and the second electrode ELT2 is connected to... Figure 12 The difference in the embodiments is that each of its opposite ends is formed by a quadrant arc-shaped portion, and a plurality of semi-circular arc-shaped portions are connected between the opposite ends.

[0224] According to this embodiment, the first electrode ELT1 and the second electrode ELT2 can each have a repeated connection on the second direction DR2. Figure 12 The shape is formed by the first electrode ELT1 and the second electrode ELT2.

[0225] The alignment direction of the light-emitting element (LD) can be changed according to its alignment position. Therefore, the viewing angle of the display device can be improved in the same manner as in the aforementioned embodiments. In this embodiment, the size of the emission area of ​​the sub-pixel can be adjusted.

[0226] Figures 15 to 17 It is shown that it includes Figure 4 A plan view of other examples of subpixels in a display device. The light-emitting elements are omitted from the illustration in the figures.

[0227] Reference Figures 15 to 17 According to the embodiment, both the first electrode ELT1 and the second electrode ELT2 may have portions with different widths. For example, the opposite ends of each of the first electrode ELT1 and the second electrode ELT2 and / or the portions therein that form inflection points may be wider than their adjacent portions.

[0228] The alignment direction of the light-emitting element can be changed according to its alignment position. Therefore, the viewing angle of the display device can be improved in the same manner as in the aforementioned embodiments. Figure 17 As shown in the embodiments, the size of the emission region of a sub-pixel can be adjusted by repeatedly connecting the first electrode ELT1 and the second electrode ELT2.

[0229] Figure 18 and Figure 19 It is shown that it includes Figure 4 A plan view of other examples of subpixels in a display device. The light-emitting elements are omitted from the illustration in the figures.

[0230] According to this embodiment, both the first electrode ELT1 and the second electrode ELT2 can be applied... Figure 12 and Figure 13 The embodiments have various shapes by connecting the quadrant arc-shaped parts. Figure 18 and Figure 19 The shapes shown are for illustrative purposes only and are not limited to the shapes shown.

[0231] Figures 20a to 20d It is shown that it includes Figure 5 A circuit diagram of another example of a unit pixel in a sub-pixel.

[0232] Reference Figures 20a to 20d The setting of the light source unit (LSU) is different. Figures 6a to 6d The circuit diagram setup. The light-emitting elements (LDs) in each light source unit (LSU) can be connected in series and parallel combinations.

[0233] Each light source unit (LSU) may include light-emitting elements (LDs) connected in series with each other. Because the LDs are connected in series, voltage distribution efficiency can be improved, and the capacitance design of the first transistor (or driving transistor) T1 can be optimized. Furthermore, since the LDs can be connected in a combination of series and parallel configurations, power losses attributable to line resistance can be reduced. Although an example of three LDs connected in series is shown in the figures, the number of LDs is not limited to this.

[0234] In the following text, it will be described Figures 20a to 20d The circuit diagram can be applied to the shape of the electrodes in its emission region. In the following embodiments, an example in which each of the sub-pixels includes a unit pixel will be described.

[0235] Figures 21 to 30 It is shown Figures 20a to 20d The example can be applied to a planar graph of various examples of its sub-pixels (or unit pixels). Figures 21 to 30 The first and second electrodes can have the same characteristics as... Figure 7 , Figures 10 to 12 and Figures 14 to 19 The shapes are the same as those of the shapes, so that their repeated descriptions will be omitted.

[0236] In this embodiment, the first electrode ELT1 and the second electrode ELT2 can be defined as electrodes that extend from the first connecting electrode CNL1 and the second connecting electrode CNL2 or are directly connected to the first connecting electrode CNL1 and the second connecting electrode CNL2, respectively.

[0237] The first electrode ELT1 and the second electrode ELT2 can be spaced apart from each other by a predetermined distance and arranged parallel to each other. At least one island electrode ILT1, ILT2 can be disposed between the first electrode ELT1 and the second electrode ELT2. In this embodiment, an example in which two island electrodes ILT1 and ILT2 (i.e., the first island electrode ILT1 and the second island electrode ILT2) are disposed between the first electrode ELT1 and the second electrode ELT2 will be described. The embodiment is not limited to the number or shape of the island electrodes ILT1 and ILT2.

[0238] The first island electrode ILT1 and the second island electrode ILT2 can be disposed between the first electrode ELT1 and the second electrode ELT2, such that the first electrode ELT1, the second electrode ELT2, the first island electrode ILT1 and the second island electrode ILT2 are spaced apart from each other by a predetermined distance and are parallel to each other.

[0239] In this embodiment, the distances between the first electrode ELT1, the second electrode ELT2, the first island electrode ILT1, and the second island electrode ILT2 can be the same.

[0240] In an embodiment, the first island electrode ILT1 and the second island electrode ILT2 may be disposed on the same layer as the first electrode ILT1 and the second electrode ILT2. The first island electrode ILT1 and the second island electrode ILT2 may be patterned together with the first electrode ILT1 and the second electrode ILT2.

[0241] The first island electrode ILT1 and the second island electrode ILT2 are not directly connected to the first connecting electrode CNL1 and the second connecting electrode CNL2, but can be electrically connected to the first connecting electrode CNL1 and the second connecting electrode CNL2 through a light-emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2.

[0242] The alignment direction of the light-emitting element (LD) can be changed according to its alignment position. Therefore, the viewing angle of the display device can be improved in the same manner as in the aforementioned embodiments. Furthermore, the display device can have the aforementioned effects obtained by connecting the light-emitting elements (LD) in a series and parallel combination structure.

[0243] Figure 31 It is shown that it includes Figure 5 A circuit diagram of another example of a unit pixel in a sub-pixel. Figure 32 It is shown Figure 31 A planar view of an example of a subpixel. In this embodiment, an example in which each subpixel comprises three unit pixels will be described.

[0244] Reference Figure 31 The sub-pixel SPX may include light-emitting elements LD1 to LDk configured to emit light at a brightness corresponding to the data signal. Furthermore, the sub-pixel SPX may include a common circuit PXC_C and sub-pixel circuits PXC_S1 to PXC_Sk configured to independently drive each light-emitting element LD1 to LDk.

[0245] The common circuit PXC_C of sub-pixel SPX can provide data signals from data line Dj to sub-pixel circuits PXC_S1 to PXC_Sk in response to the scan signal provided from scan line S1.

[0246] The common circuit PXC_C may include a second transistor T2.

[0247] Each of the sub-pixel circuits PXC_S1 to PXC_Sk can store a data signal provided from the common circuit PXC_C and provide a drive current corresponding to the stored data signal to the corresponding light-emitting element (i.e., one of the light-emitting elements LD1 to LDk).

[0248] In an embodiment, sub-pixel circuits PXC_S1 to PXC_Sk may include reference... Figure 6d The first transistor T1, the third transistor T3, and the storage capacitor Cst are the same as the first transistor T1_1 to T1_k, the third transistor T3_1 to T3_k, and the storage capacitor Cst1 to Cstk.

[0249] For example, the first sub-pixel circuit PXC_S1 can provide a first driving current to the first light-emitting element string LDS1 (or the first sub-light source unit) corresponding to the data signal provided from the common circuit PXC_C. Similarly, the second sub-pixel circuit PXC_S2 can provide a second driving current to the second light-emitting element string LDS2 corresponding to the data signal provided from the common circuit PXC_C. The k-th sub-pixel circuit PXC_Sk can provide a k-th driving current to the k-th light-emitting element string LDSk corresponding to the data signal provided from the common circuit PXC_C. An example is shown in which each light-emitting element string includes four light-emitting elements connected in series with each other.

[0250] The sub-pixel circuits PXC_S1 to PXC_Sk can store data signals in storage capacitors Cst1 to Cstk respectively, and provide the driving current corresponding to the corresponding data signal to the corresponding light-emitting element (i.e., the corresponding light-emitting element among light-emitting elements LD1 to LDk). Therefore, light-emitting elements LD1 to LDk can emit light more uniformly.

[0251] Reference Figure 32 The emission area EMA can be divided into the first sub-emission area EMA_S1 to the third sub-emission area EMA_S3.

[0252] In an embodiment, the first electrode ELT1 may be disposed in each of the sub-emission regions EMA_S1, EMA_S2, and EMA_S3. The second electrode ELT2 may be disposed throughout the entire emission region EMA (i.e., across the sub-emission regions). The first island electrode ILT1 and the second island electrode ILT2 may be disposed between the first electrode ELT1 and the second electrode ELT2 in the corresponding sub-emission region (e.g., in the first sub-emission region EMA_S1).

[0253] The first electrode ELT1, the second electrode ELT2, and the island electrodes ILT1 and ILT2 can all have a single-layer structure or a multi-layer structure. In addition, each of the first electrode ELT1, the second electrode ELT2, and the island electrodes ILT1 and ILT2 can protrude in the upward direction (or the height or thickness direction of the substrate layer SUB1) through a partition wall that is configured to be stacked with the corresponding electrode.

[0254] Each light-emitting element (LD) can be disposed between two adjacent electrodes in the first electrode ELT1, the second electrode ELT2, and the island electrodes ILT1 and ILT2, and electrically connected to each of the two adjacent electrodes. For example, the LD can be disposed between the first electrode ELT1 and the first island electrode ILT1 adjacent to the first electrode ELT1. The first end of the LD can be electrically connected to the first electrode ELT1, and the second end of the LD can be electrically connected to the first island electrode ILT1. Similarly, the LD can be disposed between the first island electrode ILT1 and the second island electrode ILT2 adjacent to the first island electrode ILT1. The first end of the LD can be electrically connected to the first island electrode ILT1, and the second end of the LD can be electrically connected to the second island electrode ILT2. Similarly, the LD can be disposed between the second island electrode ILT2 and the second electrode adjacent to the second island electrode ILT2. The first end of the LD can be electrically connected to the second island electrode ILT2, and the second end of the LD can be electrically connected to the second electrode. In this way, the light-emitting element LD in the first sub-emission region EMA_S1 can be connected in series between the first electrode ELT1 and the second electrode ELT2.

[0255] The first electrode ELT1, the second electrode ELT2, and the island electrodes ILT1 and ILT2 can all extend with curved portions. Each of the first electrode ELT1, the second electrode ELT2, and the island electrodes ILT1 and ILT2 can be arranged in various shapes in the same manner as in the embodiments described above.

[0256] although Figure 32 The diagram illustrates a series connection of light-emitting elements (LDs) within a sub-emission region (e.g., a first sub-emission region EMA_S1), but the LDs are not limited to this. For example, within a sub-emission region, at least some of the LDs can be connected in parallel with other LDs. In other words, in... Figure 32 In this process, the light-emitting elements (LDs) in a sub-emitting region can be arranged in a series / parallel combination connection structure.

[0257] Although embodiments of this disclosure have been disclosed, those skilled in the art will understand that this disclosure can be implemented in other specific forms without departing from the scope and spirit of the disclosure as described in the claims. Therefore, it should be understood that the exemplary embodiments are for illustrative purposes only and do not limit the scope of this disclosure.

Claims

1. A display device, the display device comprising: A first connecting electrode extends in a first direction and is electrically connected to a first power line to which a first power source applies; The second connecting electrode is spaced apart from the first connecting electrode in a second direction intersecting the first direction, and is electrically connected to a second power line to which the second power source applies; Multiple first electrodes extend from the first connecting electrode in the second direction; A plurality of second electrodes extend from the second connecting electrode in the second direction and are arranged parallel to the plurality of first electrodes, with each of the plurality of second electrodes having a predetermined distance between it and a corresponding first electrode among the plurality of first electrodes; as well as Each of the multiple light-emitting elements includes a first end electrically connected to a corresponding first electrode among the multiple first electrodes and a second end electrically connected to a corresponding second electrode among the multiple second electrodes. Each of the plurality of first electrodes and the plurality of second electrodes includes a bent portion.

2. The display device according to claim 1, wherein, The curved portion has a shape that protrudes in the first direction.

3. The display device according to claim 2, wherein, Each of the plurality of first electrodes and the plurality of second electrodes has a curved shape or a zigzag shape.

4. The display device according to claim 3, wherein, Each of the plurality of first electrodes and the plurality of second electrodes has a shape formed by connecting a plurality of quadrant arcs.

5. The display device according to claim 3, in, Each of the plurality of first electrodes and the plurality of second electrodes includes a connecting portion having a shape formed by connecting a plurality of quadrant arcs, and The inflection point is included in the connecting portion.

6. The display device according to claim 1, wherein, Each of the plurality of light-emitting elements includes a rod-shaped light-emitting diode having dimensions ranging from nanometer to micrometer.

7. The display device according to claim 6, wherein, At least some of the plurality of light-emitting elements are aligned such that their longitudinal direction corresponds to the normal direction of the direction in which the corresponding first electrode of the plurality of first electrodes and the corresponding second electrode of the plurality of second electrodes extend.

8. The display device according to claim 1, wherein, The plurality of first electrodes or the plurality of second electrodes include portions with different widths.

9. The display device according to claim 1, wherein the display device comprises at least one island electrode disposed between each of the plurality of first electrodes and a corresponding second electrode of the plurality of second electrodes, but not directly connected to the first connecting electrode or the second connecting electrode. in, Some of the plurality of light-emitting elements are disposed between each of the plurality of first electrodes and the at least one island electrode, and Among them, some other light-emitting elements are disposed between the corresponding second electrode and the at least one island electrode in the plurality of second electrodes.

10. The display device according to claim 9, wherein, The at least one island electrode is arranged parallel to the plurality of first electrodes and the plurality of second electrodes, and there is a predetermined distance between the at least one island electrode and each of the plurality of first electrodes and between the at least one island electrode and the corresponding second electrode of the plurality of second electrodes.

11. The display device according to claim 10, wherein, The at least one island electrode includes a curved portion.

12. The display device according to claim 9, wherein, The multiple light-emitting elements are connected in series and in parallel.

13. The display device according to claim 1, wherein, Each of the plurality of first electrodes and the plurality of second electrodes further includes a linear portion extending upward in a third direction intersecting the first direction and the second direction.

14. A display device, the display device comprising: The substrate, including the emission area; A first connecting electrode extends in a first direction and is electrically connected to a first power line to which a first power source applies; The second connecting electrode is spaced apart from the first connecting electrode in a second direction intersecting the first direction, and is electrically connected to a second power line to which the second power source applies; A plurality of first electrodes extend from the first connecting electrode in the second direction and are disposed in the emission region of the substrate; A plurality of second electrodes, extending from the second connecting electrode in the second direction, are disposed on the same layer as the plurality of first electrodes in the emission region of the substrate, and are configured to face the plurality of first electrodes respectively, and are spaced apart from and electrically isolated from the plurality of first electrodes respectively; as well as In a plan view, multiple light-emitting elements are disposed between a corresponding first electrode among the multiple first electrodes and a corresponding second electrode among the multiple second electrodes. Each of the plurality of first electrodes and the plurality of second electrodes includes a curved portion in the plan view.

15. The display device according to claim 14, further comprising: The first contact electrode is configured to connect a first end of each of the plurality of light-emitting elements to each of the plurality of first electrodes; as well as The second contact electrode is configured to connect the second end of each of the plurality of light-emitting elements to each of the plurality of second electrodes.

16. The display device according to claim 14, further comprising a first island electrode and a second island electrode disposed between each of the plurality of first electrodes and a corresponding second electrode of the plurality of second electrodes. in, The distances between each of the plurality of first electrodes, the first island electrode, the second island electrode, and the corresponding second electrode among the plurality of second electrodes are equal. Wherein, the first island electrode and the second island electrode are not directly connected to the first connecting electrode and the second connecting electrode, and The plurality of light-emitting elements are disposed between two adjacent electrodes in each of the plurality of first electrodes, the first island electrode, the second island electrode, and the corresponding second electrode in the plurality of second electrodes, and are electrically connected to each of the two adjacent electrodes.

17. The display device according to claim 16, wherein, The plurality of first electrodes, the first island electrode, the second island electrode, and the plurality of second electrodes are arranged parallel to each other.

18. The display device according to claim 17, wherein, Each of the first island electrode and the second island electrode includes a curved portion.

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