Contact arrangement and electronic assembly

Abstract

A contact arrangement and an electronic assembly are disclosed. The contact arrangement includes a plurality of contact groups. At least one of the contact groups includes a plurality of common contacts, a plurality of dedicated contacts, and a plurality of ground contacts. The common contacts pass signals corresponding to a first mode and a second mode in the first mode and the second mode. The dedicated contacts pass signals corresponding to the first mode only and do not pass signals corresponding to the second mode. The ground contacts surround the common contacts and the dedicated contacts.

Description

Technical Field

[0001] The present invention relates to a contact arrangement, and more particularly to a contact arrangement and an electronic assembly using the contact arrangement. Background Technology

[0002] Due to varying market applications, memory modules come in various specifications. These specifications include DDR RDIM for servers, DDR UDIM for desktop computers, and LPDDR for handheld devices and laptops, among others. Depending on the operating speed, these different memory module specifications are also categorized as first-generation, second-generation, etc. Currently, the mainstream memory module specifications include DDR4 RDIM, DDR4 UDIM, DDR5 UDIM, and LPDDR5. Different memory modules have different packaging requirements, necessitating individual design, which increases design costs. Summary of the Invention

[0003] This invention provides a contact arrangement that can transmit signals in multiple different memory module modes.

[0004] The present invention provides an electronic assembly whose contact arrangement can transmit signals in multiple different memory module modes.

[0005] The contact arrangement of the present invention includes multiple contact groups. At least one of these contact groups includes multiple common contacts, multiple dedicated contacts, and multiple ground contacts. The common contacts transmit signals corresponding to the first mode and the second mode in a first mode and a second mode, respectively. The dedicated contacts transmit only signals corresponding to the first mode and do not transmit signals corresponding to the second mode. The ground contacts surround the common contacts and the dedicated contacts.

[0006] The electronic assembly of the present invention includes a circuit board having the above-described contact arrangement.

[0007] Based on the above, in this invention, while simultaneously supporting multiple different memory module specifications, signals of different modes (specifications) are transmitted through multiple common contacts, signals of a certain mode (specification) are transmitted through one or more dedicated contacts, and grounding contacts surround these common contacts and these dedicated contacts to ensure signal transmission quality. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an electronic assembly according to an embodiment of the present invention;

[0009] Figure 2 for Figure 1 A schematic diagram of the chip package;

[0010] Figure 3This is a schematic diagram of a contact arrangement according to an embodiment of the present invention;

[0011] Figure 4 for Figure 3 A schematic diagram of the connection point arrangement and wiring;

[0012] Figure 5A A multiplexed table diagram of data signals;

[0013] Figure 5B for Figure 4 An enlarged view of a portion of the contact arrangement related to the data signal;

[0014] Figure 5C An enlarged view of a portion of a contact arrangement according to another embodiment of the present invention;

[0015] Figure 6 for Figure 4 An enlarged view of a portion of the contact arrangement related to the control signal;

[0016] Figure 7A A multiplexing table diagram of clock pulse signals;

[0017] Figure 7B for Figure 4 An enlarged view of a portion of the contact arrangement related to the clock pulse signal;

[0018] Figure 8A A schematic diagram of the circuit layout for the first conductive layer;

[0019] Figure 8B This is a schematic diagram of the circuit layout for a non-first conductive layer.

[0020] Symbol Explanation

[0021] 50: Chip package

[0022] 52: Chip

[0023] 54: Packaging substrate

[0024] 60: Motherboard

[0025] 70: Memory Module

[0026] 100: Node Arrangement

[0027] 110: Connection Point Group

[0028] 112, 112g, 112p: Shared contact

[0029] 112a, 112b: Common contact differential pair

[0030] 114, 114c, 114d: Dedicated contacts

[0031] 114a, 114b, 114e: Dedicated contact differential pairs

[0032] 116: Grounding contact

[0033] A: Electronic Assembly

[0034] C: Contact

[0035] M: Conductive dielectric

[0036] L: Line layer

[0037] V: Conductive channel

[0038] T: Wiring Detailed Implementation

[0039] Please refer to Figure 1 and Figure 2 The chip package 50, serving as a memory driving element, includes a chip 52 and a packaging substrate 54. The chip 52 is mounted to the packaging substrate 54. A plurality of memory modules 70 located on the motherboard 60 are driven by mounting or assembling the chip package 50 to a motherboard 60 of a computer (or similar device). These memory modules 70 may have various specifications, including DDR4 UDIM, DDR4 RIDM, DDR5, or LPDDR5, but are not limited thereto. The printed circuit boards (PCBs) of the packaging substrate 54 and the motherboard 60 can each be considered as wiring boards. In this embodiment, the electronic assembly A may include the chip package 50 and the motherboard 60, or it may include memory modules 70. Alternatively, the chip package 50 may also be considered as an electronic assembly composed of the chip 52 and the packaging substrate 54.

[0040] This invention provides a contact arrangement 100, which can be applied to Figure 1 The pad arrangement of the chip package 50 or the pad arrangement of the motherboard 60 can also serve as a conductive medium arrangement between the chip package 50 and the motherboard 60. The conductive medium M in the aforementioned arrangement can be, for example, a conductive pad, a conductive ball, a conductive pin, or a conductive elastic terminal, but is not limited thereto. Furthermore, the contact arrangement of the packaging substrate 54 of the chip package 50 is a mirror image of the contact arrangement of the motherboard 60, so as to provide an electrical connection. Please refer to... Figure 3 and Figure 4 In this embodiment, the contact arrangement 100 can be formed by the circuit layer L of the circuit board (e.g., Figure 1 The motherboard 60 circuit layer L or Figure 2 The packaging substrate 54 is composed of multiple exposed portions of the circuit layer L). Besides Figure 3 In addition to the 100-point arrangement of the contacts, Figure 4In the middle, multiple traces T formed by the line layer L are represented by dashed lines.

[0041] Please refer to Figure 4 The contact arrangement 100 consists of multiple contacts C and includes multiple contact groups 110. At least one contact group 110 includes multiple common contacts 112, multiple dedicated contacts 114, and multiple ground contacts 116. These common contacts 112 can transmit signals corresponding to the first mode and the second mode in a first mode and a second mode. The first mode is, for example, one of the modes (specifications) of the memory module 70 of DDR4 UDIM, DDR4 RIDM, DDR5, and LPDDR5, and the second mode is, for example, another of the modes (specifications) of the memory module 70 of DDR4 UDIM, DDR4 RIDM, DDR5, and LPDDR5, that is, the first mode and the second mode are modes (specifications) of two different memory module 70s. These dedicated contacts 114 (non-common contacts) can transmit only the signals corresponding to the first mode and not the signals corresponding to the second mode. Alternatively, these dedicated contacts 114 (non-common contacts) can transmit only the signals corresponding to the second mode and not the signals corresponding to the first mode. These grounding contacts 116 surround these common contacts 112 and these dedicated contacts 114.

[0042] The contact arrangement 100 of this invention can simultaneously support the modes (specifications) of memory modules 70 such as DDR4 UDIM, DDR4 RIDM, DDR5, or LPDDR5. The signals corresponding to these modes (specifications) can be mainly divided into three types: clock pulse (CLK / Clock) signals, data (Data / Strobe) signals, and control (Control / CMD) signals. The three contact groups 110 to which they belong are as follows: Figure 4 As shown in the box. The individual descriptions of these contact groups 110 are as follows.

[0043] Please refer to Figure 5A and Figure 5B Within the same contact group 110, these shared contacts 112 are used to transmit data signals (Data / Strobe) for DDR4 UDIM, DDR4 RDIM, DDR5, or LPDDR5. Two of these shared contacts 112 form a shared contact differential pair 112a (e.g., Figure 5APin positions A1 and A2 are used to transmit differential data signals for DDR4 UDIM, DDR4 RDIM, DDR5, or LPDDR5. Furthermore, two of these dedicated contacts 114 form a dedicated contact differential pair 114a. The dedicated contact differential pair 114a only transmits the corresponding data signals in DDR4 RDIM or LPDDR5 mode. When the memory module is in DDR4 UDIM or DDR5 mode, the dedicated contact differential pair 114a is in a no-signal state (NC) (e.g., ...). Figure 5A (Pin positions A3 and A4). Additionally, two of these shared contacts 112 within the same contact group 110 (i.e., shared contact 112g) are grounded to serve as a reference loop for the signal. In this embodiment, these grounded contacts 116 are generally located around the periphery of a contact group 110, surrounding the shared contact differential pair 112a and the dedicated contact differential pair 114a. These grounded contacts 116 are connected to each other via traces T and are also connected to the shared contact 112g used for grounding via traces T.

[0044] Please refer to Figure 5B In this embodiment, the total number of these shared contacts 112 and these dedicated contacts 114 in the same contact group 110 is at least 12. Please refer to... Figure 5C In another embodiment, the total number of these shared contacts 112 and these dedicated contacts 114 in the same contact group 110 is 14. Figure 5B and Figure 5C In this embodiment, the contact group 110 includes a common contact differential pair 112a and two dedicated contact differential pairs 114a and 114b. The two dedicated contact differential pairs 114a and 114b only transmit the corresponding data signals in DDR4 UDIM or LPDDR5 mode. In DDR4 UDIM or DDR5 mode, the dedicated contact differential pairs 114a and 114b are in a no-signal state (NC).

[0045] Please refer to Figure 6Within the same contact group 110, these shared contacts 112 transmit corresponding control signals (Control / CMD) in DDR4 (DDR4UDIM or DDR4RDIM) and DDR5 (or LPDDR5) modes. In one embodiment, at least one of the dedicated contacts 114 in the same contact group 110 is a dedicated DDR5 (or LPDDR5) contact 114c. In DDR5 (or LPDDR5) mode, this dedicated contact 114c only transmits the corresponding DDR5 (or LPDDR5) control signals. In other words, in DDR4 (DDR4 UDIM or DDR4 RDIM) mode, this dedicated contact 114c is in a no-signal state (NC). In another embodiment, at least one of the dedicated contacts 114 in the same contact group 110 is a dedicated DDR4 (DDR4 UDIM or DDR4RDIM) contact 114d. In DDR4 (DDR4 UDIM or DDR4 RDIM) mode, this dedicated contact 114d only transmits the corresponding DDR4 (DDR4 UDIM or DDR4 RDIM) control signal. In other words, in DDR5 (or LPDDR5) mode, this dedicated contact 114d is in a no-signal state (NC). In another embodiment, at least two of these dedicated contacts 114, 114c and 114d, transmit the corresponding control signal in DDR4UDIM, DDR4 RDIM, DDR5, or LPDDR5 modes, respectively. Additionally, two of these common contacts 112 (i.e., common contact 112p) are in a power-on state and can serve as a reference loop for signals. In this embodiment, these ground contacts 116 are generally located around the contact group 110, surrounding the common contacts 112, dedicated contacts 114c, 114d, and the common contact 112p for power supply; these ground contacts 116 are interconnected via traces T.

[0046] Please refer to Figure 7A and Figure 7B Within the same contact group 110, these shared contacts 112 are used to transmit clock pulse signals (CLK / Clock) for DDR4 (DDR4UDIM, DDR4RDIM) and DDR5 (or LPDDR5). Within the same contact group 110, two of these shared contacts 112 can be a shared contact differential pair 112b (e.g., Figure 7A Pin positions B1 and B2 are used to transmit differential pairs of clock pulse signals for DDR4 (DDR4 UDIM or DDR4 RDIM) and DDR5 (or LPDDR5). Two of these common contacts 112 can be in a power-on state (112p) to isolate clock pulse signals together with these ground contacts 116. Two of these dedicated contacts 114 can be a dedicated contact differential pair 114e (e.g., Figure 7A The dedicated differential contact pair 114e transmits the corresponding clock pulse signal only in DDR5 (or LPDDR5) mode (pin positions B3 and B4). When the memory module is in DDR4 (DDR4 UDIM or DDR4 RDIM) mode, the dedicated differential contact pair 114e is in a no-signal (NC) state. In this embodiment, these ground contacts 116 are generally located around a contact group 110, surrounding the common differential contact pair 112c or the dedicated differential contact pair 114e, and these ground contacts 116 can be connected to each other via traces T. In this embodiment, these ground contacts 116 are generally located around a contact group 110, surrounding the dedicated differential contact pair 114e and the common power contact 112p. In this embodiment, these ground contacts 116 are generally located around a contact group 110, surrounding the common differential contact pair 112c and the common power contact 112p.

[0047] Please refer to Figure 7B In this embodiment, these contact groups 110 include a contact group 110 having a dedicated contact differential pair 114e and a contact group 110 having a shared contact differential pair 112c, and the contact group 110 having the shared contact differential pair 112b is farther from the shape center of these contact groups 110 relative to the contact group 110 having the dedicated contact differential pair 114e. In other words, the contact group 110 having the shared contact differential pair 112c is in a relatively peripheral region. Furthermore, in another embodiment not shown, the contact group 110 may simultaneously include a shared contact differential pair 112b and a dedicated contact differential pair 114e, and the shared contact differential pair 112b is farther from the shape center of the contact group 110 relative to the dedicated contact differential pair 114e.

[0048] Please refer to Figure 1 , Figure 2 , Figure 8A and Figure 8B The circuit board (e.g., package substrate 54 or motherboard 60) includes multiple circuit layers L and multiple conductive channels V, which connect at least two of the circuit layers L. Except for the circuit layer L closest to the surface, each of the remaining circuit layers L has only a single trace T between two adjacent conductive channels V.

[0049] In summary, in this invention, while simultaneously supporting multiple different memory module specifications, signals of different modes (specifications) are transmitted through multiple common contacts, and signals of a certain mode (specification) are transmitted through one or more dedicated contacts. Furthermore, grounding contacts surround these common contacts and these dedicated contacts to ensure signal transmission quality.

Claims

1. A contact arrangement adapted to be arranged on a circuit board, wherein the circuit board includes a packaging substrate or a motherboard, the contact arrangement comprising: Multiple contact groups, of which at least one contact group includes: Multiple shared contacts transmit signals corresponding to the first mode and the second mode in a first mode and a second mode, wherein the first mode and the second mode are two different memory modes; Multiple dedicated contacts transmit signals corresponding to only one of the first mode and the second mode, and do not transmit signals corresponding to the other of the first mode and the second mode; and Multiple grounding points, surrounding these common points and these dedicated points.

2. The contact arrangement as described in claim 1, wherein two of the shared contacts are shared contact differential pairs to transmit data signals of DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5.

3. The contact arrangement as described in claim 1, wherein two of the dedicated contacts are dedicated contact differential pairs, and the dedicated contact differential pairs transmit corresponding data signals in DDR4 RDIM or LPDDR5 mode, and are in a no-signal state in DDR4 UDIM or DDR5 mode.

4. The contact arrangement as described in claim 1, wherein two of the shared contacts are grounded to serve as a reference loop for the signal.

5. The contact arrangement as described in claim 1, wherein the total number of the common contacts and the dedicated contacts is at least 12.

6. The contact arrangement as described in claim 1, wherein the total number of the common contacts and the dedicated contacts is 14, four of the dedicated contacts are two pairs of dedicated contact differential pairs, and the dedicated contact differential pairs transmit the corresponding data signals in DDR4 RDIM or LPDDR5 mode, and are in a no-signal state in DDR4 UDIM or DDR5 mode.

7. The contact arrangement as described in claim 1, wherein the first mode is either DDR4 RDIM or LPDDR5, and the second mode is either DDR4 UDIM or DDR5.

8. The contact arrangement as described in claim 1, wherein the shared contacts transmit corresponding control signals in DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5 modes.

9. The contact arrangement as claimed in claim 1, wherein at least one of the dedicated contacts transmits a corresponding control signal in DDR5 or LPDDR5 mode and is in a no-signal state in DDR4 UDIM or DDR4 RIDM mode.

10. The contact arrangement as claimed in claim 1, wherein at least one of the dedicated contacts transmits a corresponding control signal in DDR4 UDIM or DDR4 RIDM mode and is in a no-signal state in DDR5 or LPDDR5 mode.

11. The contact arrangement of claim 1, wherein the dedicated contacts include at least a first dedicated contact and a second dedicated contact, the first dedicated contact being for one of DDR4 UDIM and DDR4 RIDM modes, and the second dedicated contact being for one of DDR5 or LPDDR5 modes.

12. The contact arrangement as claimed in claim 1, wherein two of the shared contacts are in a power-on state to serve as a reference loop for the signal.

13. The contact arrangement as described in claim 1, wherein two of the shared contacts are a shared contact differential pair, and the shared contact differential pair transmits the corresponding clock pulse signal in DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5 mode.

14. The contact arrangement as claimed in claim 1, wherein two of the shared contacts are in a power-on state to isolate clock pulse signals together with the ground contacts.

15. The contact arrangement as described in claim 1, wherein two of the dedicated contacts are dedicated contact differential pairs, and the dedicated contact differential pairs transmit the corresponding clock pulse signal in DDR5 or LPDDR5 mode, and are in a no-signal state in DDR4 UDIM or DDR4 RIDM mode.

16. The contact arrangement of claim 1, wherein the contact groups include a first contact group having a dedicated contact differential pair and a second contact group having a shared contact differential pair, and the second contact group having the shared contact differential pair is further away from the shape center of the contact groups than the first contact group having the dedicated contact differential pair.

17. The contact arrangement as claimed in claim 1, wherein the contact group includes a common contact differential pair and a dedicated contact differential pair, and the common contact differential pair is further away from the shape center of the contact group relative to the dedicated contact differential pair.

18. The contact arrangement of claim 1, wherein the circuit board includes a plurality of circuit layers and a plurality of conductive vias, the conductive vias connecting at least two of the circuit layers, and each of the remaining circuit layers, except for the circuit layer closest to the surface, has only a single trace between adjacent two of the conductive vias.

19. An electronic assembly, comprising: A circuit board, comprising a packaging substrate or a motherboard, and having a contact arrangement including: Multiple contact groups, of which at least one contact group includes: Multiple shared contacts transmit signals corresponding to the first mode and the second mode in a first mode and a second mode, wherein the first mode and the second mode are two different memory modes; Multiple dedicated contacts transmit signals corresponding to only one of the first mode and the second mode, and do not transmit signals corresponding to the other of the first mode and the second mode; and Multiple grounding points, surrounding these common points and these dedicated points.

20. The electronic assembly of claim 19, further comprising: The chip is installed on the circuit board.

21. The electronic assembly of claim 19, further comprising: The chip package is installed onto the circuit board.

22. The electronic assembly of claim 19, wherein the circuit board includes a plurality of circuit layers and a plurality of conductive vias, the conductive vias connecting at least two of the circuit layers, and each of the remaining circuit layers, except for the circuit layer closest to the surface, has only a single trace between adjacent pairs of the conductive vias.

23. The electronic assembly of claim 19, wherein two of the common contacts are a common contact differential pair for transmitting DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5 data signals.

24. The electronic assembly of claim 19, wherein two of the dedicated contacts are dedicated contact differential pairs, and the dedicated contact differential pairs transmit corresponding data signals in DDR4 RDIM or LPDDR5 mode, and are in a no-signal state in DDR4 UDIM or DDR5 mode.

25. The electronic assembly of claim 19, wherein the common contacts transmit corresponding control signals in DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5 modes.

26. The electronic assembly of claim 19, wherein at least one of the dedicated contacts transmits a corresponding control signal in DDR5 or LPDDR5 mode and is in a no-signal state in DDR4 UDIM or DDR4 RIDM mode.

27. The electronic assembly of claim 19, wherein at least one of the dedicated contacts transmits a corresponding control signal in DDR4 UDIM or DDR4 RIDM mode and is in a no-signal state in DDR5 or LPDDR5 mode.

28. The electronic assembly of claim 19, wherein the dedicated contacts include at least a first dedicated contact and a second dedicated contact, the first dedicated contact being for one of DDR4 UDIM and DDR4 RIDM modes, and the second dedicated contact being for one of DDR5 or LPDDR5 modes.

29. The electronic assembly of claim 19, wherein two of the common contacts are a common contact differential pair, and the common contact differential pair transmits the corresponding clock pulse signal in DDR4 UDIM, DDR4 RIDM, DDR5 or LPDDR5 mode.

30. The electronic assembly of claim 19, wherein two of the dedicated contacts are dedicated contact differential pairs, and the dedicated contact differential pairs transmit corresponding clock pulse signals in DDR5 or LPDDR5 mode and are in a no-signal state in DDR4 UDIM or DDR4 RIDM mode.

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