A method of manufacturing a semiconductor device
By forming dielectric and sacrificial layers on the substrate during semiconductor manufacturing, the problem of film damage caused by cleaning processes is solved, ensuring the stability of device performance and improving electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-21
- Publication Date
- 2026-07-21
AI Technical Summary
In semiconductor manufacturing, cleaning processes can thin or damage the film layers in other areas of the substrate, leading to deterioration of device performance.
The method involves forming a first dielectric layer and a first sacrificial layer on a substrate, removing the first sacrificial layer in the second region and the native oxide layer in the first region by cleaning without damaging the dielectric layer in the second region and other regions, and then forming the first and second film layers. A second sacrificial layer is then formed by a rapid thermal oxidation process to protect the film layers.
This avoids the device performance degradation caused by dielectric thinning or damage, and improves the reliability and electrical performance of semiconductor devices.
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Figure CN114400182B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for fabricating a semiconductor device. Background Technology
[0002] Currently, in the manufacture of semiconductor devices, a stress layer can be deposited on the surface of a predetermined region of the substrate to improve the carrier mobility of the transistor to be formed in that region. Furthermore, before depositing the stress layer, a cleaning process is performed on the substrate to remove the native oxide layer and impurities from the surface of the predetermined region.
[0003] However, this cleaning process can thin or damage the film layer located in other areas of the substrate, causing the device that is finally formed in those other areas to degrade in performance. Summary of the Invention
[0004] This disclosure provides a method for fabricating a semiconductor device, the method comprising: providing a substrate, the substrate including a first region and a second region; sequentially forming a first dielectric layer and a first sacrificial layer on the substrate; removing the first dielectric layer and the first sacrificial layer located on the first region to expose the substrate on the first region; cleaning the substrate to remove the first sacrificial layer located on the second region and to remove the native oxide layer located on the first region; and sequentially forming a first film layer and a second film layer on the first region.
[0005] In the above scheme, after forming the second film layer, the method further includes: performing a rapid thermal oxidation process on the second film layer to form a second sacrificial layer.
[0006] In the above scheme, after forming the second sacrificial layer, the method further includes:
[0007] Remove the second sacrificial layer in the first region and remove the first dielectric layer on the second region to expose the first film layer and the substrate located on the second region, respectively.
[0008] A second dielectric layer is formed on the first region and the second region.
[0009] In the above scheme, the substrate on the first film layer and the second region is subjected to rapid thermal oxidation and / or rapid thermal nitriding treatment to form the second dielectric layer on the first region and the second region, respectively.
[0010] In the above scheme, the first film layer includes a silicon-germanium layer, and the second film layer includes a silicon layer.
[0011] In the above scheme, the first film layer and the second film layer are formed sequentially in the same thin film deposition process, and the material of the first film layer is different from that of the second film layer.
[0012] In the above scheme, the thickness of the first film layer is... to Between; the thickness of the second film layer is between to between.
[0013] In the above scheme, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer.
[0014] In the above scheme, the first dielectric layer is formed by thermal oxidation, and the first sacrificial layer is formed by atomic layer deposition.
[0015] In the above scheme, the thickness of the first dielectric layer is... to Between, the thickness of the first sacrificial layer is to between.
[0016] In the above scheme, the substrate further includes a third region and a fourth region; forming a first dielectric layer and a first sacrificial layer sequentially on the substrate includes: forming the first dielectric layer and the first sacrificial layer sequentially on the third region and the fourth region.
[0017] In the above scheme, the first sacrificial layer on the third region and the fourth region is removed when the substrate is cleaned.
[0018] In the above scheme, the substrate includes a core region and a peripheral region; wherein the first region and the second region are located on the core region, and the third region and the fourth region are located on the peripheral region.
[0019] In the above scheme, before forming the first dielectric layer and the first sacrificial layer on the first region and the second region, the method further includes:
[0020] An insulating stack is formed on the core area and the peripheral area, the insulating stack comprising a first oxide layer, a nitride layer and a second oxide layer stacked sequentially from bottom to top;
[0021] Remove the first oxide layer, the nitride layer, and the second oxide layer from the core area and the peripheral area.
[0022] In the above scheme, the first region is used to form a first PMOS structure, and the second region is used to form a first NMOS structure.
[0023] The method for fabricating a semiconductor device provided in this disclosure includes: providing a substrate, the substrate including a first region and a second region; sequentially forming a first dielectric layer and a first sacrificial layer on the substrate; removing the first dielectric layer and the first sacrificial layer located on the first region to expose the substrate on the first region; cleaning the substrate to remove the first sacrificial layer located on the second region and to remove the native oxide layer located on the first region; and sequentially forming a first film layer and a second film layer on the first region. In this disclosure, when cleaning the substrate, the cleaning solution only consumes the first sacrificial layer on the second region and the native oxide layer on the first region, without thinning or damaging the first dielectric layer on the second region or other regions of the substrate. Thus, the performance degradation of the semiconductor device caused by thinning or damage to the first dielectric layer can be avoided.
[0024] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;
[0027] Figures 2 to 11 A process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation
[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0034] In traditional semiconductor device fabrication processes, a stress layer is typically deposited over the region of the substrate where the transistor will be formed to improve carrier mobility. Simultaneously, to enhance the quality of the final stress layer, a cleaning process is performed on the substrate before deposition to remove native oxide layers or other impurities on the substrate surface.
[0035] However, during the cleaning process, the cleaning solution used will inevitably thin or damage the film layer located in other areas of the substrate, resulting in a deterioration in the performance of the device ultimately formed in other areas.
[0036] Based on this, the following technical solutions are proposed for embodiments of this disclosure:
[0037] This disclosure provides a method for fabricating a semiconductor device, such as... Figure 1 As shown, the method includes the following steps:
[0038] Step 310: Provide a substrate, the substrate comprising a first region and a second region;
[0039] Step 320: A first dielectric layer and a first sacrificial layer are sequentially formed on the substrate;
[0040] Step 330: Remove the first dielectric layer and the first sacrificial layer located on the first region to expose the substrate on the first region;
[0041] Step 340: Clean the substrate to remove the first sacrificial layer located on the second region and the native oxide layer located on the first region;
[0042] Step 350: Form a first film layer and a second film layer sequentially on the first region.
[0043] In this embodiment of the present disclosure, when cleaning the substrate, the cleaning solution only consumes the first sacrificial layer on the second region and the native oxide layer on the first region, without thinning or damaging the first dielectric layer on the second region or other regions of the substrate. This avoids the problem of device performance degradation caused by thinning or damage to the first dielectric layer.
[0044] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.
[0045] Figures 2 to 11 A process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of this disclosure.
[0046] First, such as Figure 2 As shown, step 310 is performed, providing a substrate 20, which includes a first region and a second region.
[0047] In some embodiments, the substrate 20 further includes a third region and a fourth region. For example... Figure 2 As shown, the third region is located adjacent to the second region, and the fourth region is located immediately adjacent to the third region. However, this is not a limitation; the first, second, third, and fourth regions can be arranged arbitrarily, and other regions can also be arranged between the first, second, third, and fourth regions.
[0048] See also Figure 2 As can be seen, the substrate 20 includes a core region and a peripheral region; wherein the first region and the second region are located on the core region, and the third region and the fourth region are located on the peripheral region.
[0049] In actual manufacturing, the substrate 20 further includes an array region in which word lines WL are formed. The word lines WL may include, from bottom to top, an insulating layer 201, a conductive layer 202, and a capping layer 203. The insulating layer 201 and the capping layer 203 may be made of the same material, specifically including, but not limited to, oxides, nitrides, and oxynitrides. However, they are not limited to these; the materials of the insulating layer 201 and the capping layer 203 may also be different, depending on actual requirements. The conductive layer 202 may be made of, but not limited to, a polysilicon layer, a metal silicide, or a metal layer.
[0050] In this embodiment, the substrate may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.
[0051] Then, as Figure 5 As shown, in step 320, a first dielectric layer 210 and a first sacrificial layer 220 are sequentially formed on the substrate. The first dielectric layer 210 and the first sacrificial layer 220 cover the first region and the second region. The first sacrificial layer 220 also protects the first dielectric layer 210 from damage caused by the cleaning solution during the cleaning process.
[0052] In some embodiments, the first dielectric layer 210 and the first sacrificial layer 220 are sequentially formed on the substrate, including: sequentially forming the first dielectric layer 210 and the first sacrificial layer 220 on the third region and the fourth region. The first dielectric layer 210 can be used as the gate dielectric layer of a transistor formed in the third region and the fourth region.
[0053] See also Figure 5 The first dielectric layer 210 and the first sacrificial layer 220 are sequentially formed on the substrate 20, and the method further includes forming the first sacrificial layer 220 above the array region.
[0054] The material of the first dielectric layer 210 may include, but is not limited to, oxides, nitrides, or oxynitrides, such as silicon oxide or silicon oxynitride. In actual processes, the material of the first sacrificial layer 220 may be the same as that of the first dielectric layer 210, such as silicon oxide; however, it is not limited to this, and the type of material of the first sacrificial layer 220 may be selected according to actual needs.
[0055] Optionally, the first dielectric layer 210 is formed by thermal oxidation, and the first sacrificial layer 220 is formed by atomic layer deposition. Specifically, the atomic layer deposition used to form the first sacrificial layer 220 can be plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD). When silicon oxide is used as the first sacrificial layer 220, a silicon-containing gas (such as silane (SiH4) or tetraethyl orthosilicate (TEOS)) and an oxygen-containing gas (such as oxygen) are introduced into the reaction chamber. At a temperature not exceeding 1000°C, the silicon-containing gas and the oxygen-containing gas react with each other to generate the silicon oxide. The deposition parameters of the atomic layer deposition process are highly controllable. Therefore, the thickness of the first sacrificial layer 220 formed by this deposition process can be precisely controlled. Consequently, during subsequent cleaning processes, it can be ensured that the first sacrificial layer 220 is removed while effectively protecting the first dielectric layer 210 below it from damage or thinning.
[0056] In some specific embodiments, the thickness of the first dielectric layer 210 is... to Between, for example: between, between, between, Between and Between, etc.; the thickness of the first sacrificial layer 220 is in to Between, for example between, between, between, between, Between and Between, etc.
[0057] Understandably, before forming the first dielectric layer 210 and the first sacrificial layer 220 on the first region and the second region, the method further includes:
[0058] An insulating stack ST is formed on the core region and the peripheral region. The insulating stack ST includes a first oxide layer 230, a nitride layer 240, and a second oxide layer 250 stacked sequentially from bottom to top. (See details...) Figure 3 ;
[0059] For details on removing the first oxide layer 230, the nitride layer 240, and the second oxide layer 250 from the core area and the peripheral area, please refer to [link to documentation]. Figure 4 .
[0060] In some embodiments, before forming the first dielectric layer 210 and the first sacrificial layer 220 on the first region and the second region, the method further includes:
[0061] While forming an insulating stack ST on the core region and the peripheral region, the insulating stack ST is also formed on the array region. The insulating stack ST includes a first oxide layer 230, a nitride layer 240, and a second oxide layer 250 stacked sequentially from bottom to top. Figure 3 As shown;
[0062] Remove the second oxide layer 250 above the array region to expose the nitride layer 240, as shown below. Figure 4 As shown.
[0063] The nitriding layer 240 can be used to protect the array region from damage or contamination during subsequent process execution.
[0064] Here, the material of the first oxide layer 230 may include, but is not limited to, an oxide layer (e.g., a silicon oxide layer); the material of the nitride layer 240 may include, but is not limited to, silicon nitride; the material of the second oxide layer 250 may be the same as that of the first oxide layer 230, such as an oxide layer (e.g., a silicon oxide layer), but is not limited thereto. The material of the second oxide layer 250 may also be other insulating materials, without further restrictions.
[0065] The first oxide layer 230, the nitride layer 240 and the second oxide layer 250 can be formed using one or more thin film deposition processes; the various thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or combinations thereof.
[0066] Next, as Figure 6 As shown, step 330 is performed to remove the first dielectric layer 210 and the first sacrificial layer 220 located on the first region to expose the substrate 20 on the first region.
[0067] Specifically, removing the first dielectric layer 210 and the first sacrificial layer 220 located in the first region includes: forming a mask material layer (not shown) on the substrate 20; then, performing processes such as exposure and development on the mask material layer (not shown) to form a mask pattern (not shown); finally, using the mask pattern (not shown) as a mask, removing the first dielectric layer 210 and the first sacrificial layer 220 located in the first region to expose the substrate 20 in the first region.
[0068] Optionally, the material forming the mask material layer can be photoresist. The process for removing the first dielectric layer 210 and the first sacrificial layer 220 located on the first region can be a dry etching process or a wet etching process, without further restrictions.
[0069] Then, as Figure 7 As shown, step 340 is performed to clean the substrate 20 to remove the first sacrificial layer 220 located on the second region and the native oxide layer located on the first region.
[0070] In some embodiments, the first sacrificial layer 220 on the third region and the fourth region is removed when the substrate 20 is cleaned.
[0071] Understandably, the first sacrificial layer 220 of the array region is removed during the cleaning of the substrate 20.
[0072] The native oxide layer, for example, is composed of silicon dioxide and is formed by the oxidation of the exposed substrate in air. A hydrofluoric acid post-treatment process (HF-last) can be used, in which hydrofluoric acid is used to etch away the native oxide layer on the surface of the semiconductor substrate. If the native oxide layer is not removed, the subsequently formed first film layer will be deposited on top of it. The native oxide layer acts as an insulator, thus degrading the performance of the semiconductor device.
[0073] The substrate is subjected to a cleaning process, including: using various chemical reagents and organic solvents to react and dissolve the impurity particles and their own oxides adsorbed on the substrate surface, or using physical methods such as ultrasound, heating, and brushing to desorb the impurities from the surface of the substrate being cleaned, and then rinsing with a large amount of high-purity hot and cold deionized water to obtain a surface that meets the cleanliness requirements.
[0074] In actual manufacturing processes, when cleaning the substrate 20, the chemical reagents and organic solvents not only react with and dissolve the native oxides on the substrate 20 in the first region, but also react with or dissolve the pre-formed films in the second, third, fourth, and array regions. In other words, when no other films are formed above the first dielectric layer 210 and the nitride layer 240 as sacrificial layers, the chemical reagents and organic solvents will react with or dissolve the first dielectric layer 210 and the nitride layer 240, causing damage or thinning to these layers, ultimately leading to performance degradation of the device ultimately formed in that region.
[0075] In this embodiment, a first sacrificial layer 220 is formed above the first dielectric layer 210. The first sacrificial layer 220 is a film layer with a preset thickness formed by atomic layer deposition. The thickness can be adjusted according to actual needs (e.g., to ensure removability and effective protection of the underlying structure, but not limited thereto), and is not restricted here. During the cleaning process of the substrate 20, the chemical reagents and organic solvents can react with the first sacrificial layer 220 located above the second region, the third region, the fourth region, and the array region, and ultimately remove the first sacrificial layer 220. That is, in this embodiment, during the cleaning process, the first sacrificial layer 220 can effectively prevent the cleaning solution from directly contacting or reacting with the first dielectric layer 210 located above the second region, the third region, and the fourth region, thereby effectively protecting the first dielectric layer 210 from damage or thinning. At the same time, the first sacrificial layer 220 can also protect the nitride layer 240 located above the array region from damage or thinning.
[0076] Finally, as Figure 8 As shown, step 350 is performed to sequentially form a first film layer 211 and a second film layer 212a on the first region.
[0077] Here, the material of the first film layer 211 is different from the material of the second film layer 212a. Optionally, the first film layer 211 includes a silicon-germanium layer, and the second film layer 212a includes a silicon layer. The silicon-germanium layer can be used to improve the carrier mobility and adjust parameters such as the threshold voltage of the semiconductor device subsequently formed in the first region, thereby improving the electrical performance of the semiconductor device. Since the second film layer 212a is located on the first film layer 211, it can prevent the first film layer 211 from being oxidized.
[0078] In some embodiments, the thickness of the first film layer 211 is... to Between, for example: between, between, between, between, Between, etc.; the thickness of the second film layer 212a is in to Between, for example: between, between, between, between, between, between, Between, etc.
[0079] The first film layer 211 and the second film layer 212a can be formed using one or more thin film deposition processes; these processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. However, they are not limited thereto, the first film layer 211 can also be formed using a selective epitaxial deposition process.
[0080] In some embodiments, the first film layer 211 and the second film layer 212a are formed sequentially in the same thin film deposition process. This thin film deposition process can be, for example, chemical vapor deposition (CVD). Specifically, when forming the first film layer 211, a silicon-containing gas (such as silane (SiH4), dichlorosilane (DSC), or silane (Si2H6)) and a germanium-containing gas (such as GeH4) are introduced into the reaction chamber. At a temperature not exceeding 1000°C, the silicon-containing gas and the germanium-containing gas react with each other to form the first film layer 211. When forming the second film layer 212a, the introduction of the germanium-containing gas (such as GeH4) into the reaction chamber is stopped, and only the silicon-containing gas (such as silane (SiH4), dichlorosilane (DSC), or silane (Si2H6)) is introduced. At a temperature not exceeding 1000°C, the silicon-containing gas forms the second film layer 212a on the surface of the first film layer 211. Optionally, during the formation of the first film layer 211 and the second film layer 212a, a doping gas may be introduced into the reaction chamber to improve the conductivity of the first film layer 211 and the second film layer 212a.
[0081] like Figure 9 As shown, after forming the second film layer 212a, the method further includes performing a rapid thermal oxidation process on the second film layer 212a to form a second sacrificial layer 212. In some embodiments, when the second film layer 212a is a silicon layer, the second sacrificial layer 212 may be a silicon oxide layer.
[0082] During the rapid thermal oxidation process of the second film layer 212a, the degree of oxidation of the final formed second sacrificial layer 212 can be controlled by controlling the temperature, pressure, gas flow rate and time, so as to prevent the second film layer 212a from being over-oxidized or under-oxidized.
[0083] Thus, when the semiconductor device requires subsequent photolithography processing, the second sacrificial layer 212 can effectively protect the first film layer 211 located beneath it, preventing the first film layer 211 from directly contacting the photoresist. This avoids the consumption or interface damage of the first film layer 211 by the removal solution during the photoresist removal process, thereby improving the reliability of the final semiconductor device. Optionally, the removal solution may include, but is not limited to, ammonia, hydrogen peroxide, and water.
[0084] In some embodiments, after forming the second sacrificial layer 212, the method further includes:
[0085] Remove the second sacrificial layer 212 in the first region and remove the first dielectric layer 210 on the second region to expose the first film layer 211 and the substrate 20 located on the second region, respectively. See details in [link to relevant documentation]. Figure 10 ;
[0086] A second dielectric layer 213 is formed on the first region and the second region, such as Figure 11 As shown. The second dielectric layer 213 can be used as the gate dielectric layer of transistors formed in the first region and the second region.
[0087] Understandably, the material of the second dielectric layer 213 can be the same as that of the first dielectric layer 210. Specifically, the material of the second dielectric layer 213 can be an oxide layer, such as silicon oxide, silicon oxynitride, etc. However, it is not limited to this, and other insulating materials can also be used as the material of the second dielectric layer 213.
[0088] In some specific embodiments, forming the second dielectric layer 213 includes: performing rapid thermal oxidation and / or rapid thermal nitriding on the first film layer 211 and the substrate 20 on the second region to form the second dielectric layer 213 on the first region and the second region, respectively. Optionally, the rapid thermal oxidation process is performed in an atmosphere containing oxygen (such as oxygen gas or nitrous oxide) at a temperature not exceeding 1100°C (e.g., 800°C-1000°C); the rapid thermal nitriding process is performed in an atmosphere containing nitrogen (such as nitrogen gas or ammonia gas) at a temperature not exceeding 1100°C (e.g., 800°C-1000°C).
[0089] When performing a rapid thermal oxidation and / or rapid thermal nitridation process, depending on different parameter settings, the finally formed second dielectric layer 213 can be a stacked structure including silicon nitride, silicon oxynitride, and silicon oxide. However, it is not limited thereto. The composition of the second dielectric layer 213 can also include other materials that can be formed by the rapid thermal oxidation and / or rapid thermal nitridation process, which is not limited herein. The first film layer 211 is oxidized by the rapid thermal oxidation and / or rapid thermal nitridation process to prevent chemical impurities from entering the first film layer 211, which is beneficial to improving the quality of the first film layer 211 and the second dielectric layer 213.
[0090] According to the difference in requirements for the electrical parameters or other parameters of the devices formed in the core region and the peripheral region, the thickness of the second dielectric layer 213 can be different from the thickness of the first dielectric layer 210. In the embodiments of the present disclosure, the thickness d1 of the second dielectric layer 213 is less than the thickness d2 of the first dielectric layer 210, that is, d1 < d2, as Figure 11 shown. In this way, the devices formed in the core region can achieve a smaller equivalent oxide thickness (EOT) and lower threshold voltage control.
[0091] In some embodiments, the first region can be used to form the first PMOS structure of a semiconductor device, and the second region can be used to form the first NMOS structure of a semiconductor device. However, it is not limited thereto. The transistor types formed in the first region and the second region can also be the same or opposite to the specific situation described above. In the embodiments of the present disclosure, the specific types of transistors formed in the first region and the second region are not overly limited. In actual processes, specific configurations can be made according to requirements.
[0092] Similarly, the third region can be used to form the second PMOS structure of a semiconductor device, and the fourth region can be used to form the second NMOS structure of a semiconductor device. However, it is not limited thereto. The transistor types formed in the third region and the fourth region can also be the same or opposite to the specific situation described above. In the embodiments of the present disclosure, the specific types of transistors formed in the third region and the fourth region are not overly limited. In actual processes, specific configurations can be made according to requirements.
[0093] Optionally, after forming the second dielectric layer 213, the method further includes: forming a gate layer over the first region, the second region, the third region, and the fourth region; and forming a bit line structure over the array region.
[0094] The embodiments of the present disclosure also provide a semiconductor device, as Figure 8 shown, the device includes:
[0095] Substrate 20, the substrate 20 including a first region and a second region;
[0096] The first film layer 211 and the second film layer 212a are sequentially stacked on the first region;
[0097] The first dielectric layer 210 is located on the second region.
[0098] In some embodiments, the substrate 20 further includes a third region and a fourth region. The third region is disposed adjacent to the second region, and the fourth region is disposed immediately adjacent to the third region. However, this is not a limitation; the first, second, third, and fourth regions can be arbitrarily arranged, and other regions may exist between the first, second, third, and fourth regions.
[0099] from Figure 8 As can be seen, the substrate 20 includes a core region and a peripheral region; wherein the first region and the second region are located on the core region, and the third region and the fourth region are located on the peripheral region.
[0100] In subsequent processes, the second film layer 212a will be oxidized into the second sacrificial layer 212 in a rapid thermal oxidation process, such as... Figure 9 As shown. When the semiconductor device needs to undergo photolithography, the second sacrificial layer 212 can better protect the first film layer 211 located below it, preventing the first film layer 211 from directly contacting the photoresist. This avoids the consumption or interface damage of the first film layer 211 by the removal solution during the photoresist removal process, thereby improving the reliability of the finally formed semiconductor device.
[0101] The material of the first film layer 211 is different from the material of the second film layer 212a. Optionally, the first film layer 211 includes a silicon-germanium layer, and the second film layer 212a includes a silicon layer. The silicon-germanium layer can be used to improve the carrier mobility and adjust parameters such as the threshold voltage of the semiconductor device subsequently formed in the first region, thereby improving the electrical performance of the semiconductor device.
[0102] In some embodiments, the thickness of the first film layer 211 is... to Between, for example: between, between, between, between, Between, etc.; the thickness of the second film layer 212a is in to Between, for example: between, between, between, between, between, between, Between, etc.
[0103] In this embodiment of the disclosure, in addition to being disposed in the second region, the first dielectric layer 210 is also disposed in the third region and the fourth region. The first dielectric layer 210 can be used as the gate dielectric layer of a transistor formed in the third and fourth regions. The material of the first dielectric layer 210 may include, but is not limited to, oxides, nitrides, or oxynitrides, such as silicon oxide, silicon oxynitride, etc.
[0104] Understandably, the substrate 20 also includes an array region. The array region is provided with word lines WL, which may include, from bottom to top, an insulating layer 201, a conductive layer 202, and a capping layer 203. Above the word lines WL, a first oxide layer 230 and a nitride layer 240 are sequentially disposed. The nitride layer 240 can be used to protect the structure located below the nitride layer 240 from contamination or damage during process execution.
[0105] This disclosure also provides a semiconductor device, such as... Figure 11 As shown, the semiconductor device includes:
[0106] Substrate 20, the substrate 20 including a first region and a second region;
[0107] The first film layer 211 is located on the first region;
[0108] The second dielectric layer 213 is located on the first region and the second region, and covers the first film layer 211.
[0109] The first film layer 211 includes a silicon-germanium layer, which can be used to improve the carrier mobility of the semiconductor device subsequently formed in the first region, adjust the threshold voltage of the semiconductor device, and other parameters, thereby improving the electrical performance of the semiconductor device.
[0110] In some embodiments, the thickness of the first film layer 211 is... to Between, for example: between, between, between, between, Between, etc.
[0111] The second dielectric layer 213 can be used as the gate dielectric layer of a transistor formed in the first region and the second region. The material of the second dielectric layer 213 can be an oxide layer, such as silicon oxide, silicon oxynitride, etc. However, it is not limited to this, and the second dielectric layer 213 can also be a stacked structure including silicon nitride, silicon oxynitride, and silicon oxide.
[0112] In some embodiments, the substrate 20 further includes a third region and a fourth region, on which a first dielectric layer 210 is formed. The first dielectric layer 210 can be used as a gate dielectric layer for transistors formed in the third and fourth regions. The material of the first dielectric layer 210 may include, but is not limited to, oxides, nitrides, or oxynitrides. Optionally, the material of the first dielectric layer 210 may be an oxide layer, such as silicon oxide or silicon oxynitride.
[0113] from Figure 11 As can be seen, the substrate 20 includes a core region and a peripheral region; wherein the first region and the second region are located on the core region, and the third region and the fourth region are located on the peripheral region.
[0114] Understandably, the substrate 20 also includes an array region. The array region is provided with word lines WL, which may include, from bottom to top, an insulating layer 201, a conductive layer 202, and a capping layer 203. Above the word lines WL, a first oxide layer 230 and a nitride layer 240 are sequentially disposed. The nitride layer 240 can be used to protect the structure located below the nitride layer 240 from contamination or damage during process execution.
[0115] Depending on the differences in the electrical or other parameter requirements of the devices ultimately installed in the core region and the peripheral region, the thickness of the second dielectric layer 213 may differ from the thickness of the first dielectric layer 210. In this embodiment, the thickness d1 of the second dielectric layer 213 is less than the thickness d2 of the first dielectric layer 210, i.e., d1 <d2。
[0116] In some embodiments, the first region may be provided with a first PMOS structure of a semiconductor device, and the second region may be provided with a first NMOS structure of a semiconductor device. However, this is not a limitation; the transistor types provided in the first and second regions may be the same or the opposite of those described above. In this disclosure, the specific types of transistors provided in the first and second regions are not subject to excessive restrictions. In actual processes, specific configurations can be made according to requirements.
[0117] Similarly, the third region may have a second PMOS structure for semiconductor devices, and the fourth region may have a second NMOS structure for semiconductor devices. However, this is not a limitation; the transistor types in the third and fourth regions may be the same or the opposite of those described above. In this embodiment, the specific types of transistors in the third and fourth regions are not subject to excessive restrictions. In actual manufacturing processes, specific configurations can be made according to requirements.
[0118] Optionally, the semiconductor device further includes: a gate layer located above the first region, the second region, the third region, and the fourth region; and a bit line structure located above the array region.
[0119] It should be understood that the semiconductor device can be formed using one of the semiconductor device fabrication methods provided in the above embodiments.
[0120] In summary, in this embodiment, a first sacrificial layer is first formed so that during the cleaning process, the cleaning solution only consumes the first sacrificial layer above the substrate, without thinning or damaging the first dielectric layer located in the second, third, and fourth regions, thereby improving the electrical or other performance of the semiconductor device ultimately formed in the aforementioned regions. Furthermore, forming a second sacrificial layer on the first film layer prevents direct contact between the first film layer and the photoresist or photoresist cleaning solution, effectively protecting the first film layer and improving the reliability of the semiconductor device.
[0121] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.
[0122] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method includes: A substrate is provided, the substrate comprising a first region and a second region; A first dielectric layer and a first sacrificial layer are sequentially formed on the substrate; Remove the first dielectric layer and the first sacrificial layer located on the first region to expose the substrate on the first region; The substrate is cleaned to remove the first sacrificial layer located on the second region and the native oxide layer located on the first region; A first film layer and a second film layer are sequentially formed on the first region.
2. The method according to claim 1, characterized in that, After forming the second film layer, the method further includes performing a rapid thermal oxidation process on the second film layer to oxidize the second film layer completely into a second sacrificial layer.
3. The method according to claim 2, characterized in that, After forming the second sacrificial layer, the method further includes: Remove the second sacrificial layer in the first region and remove the first dielectric layer on the second region to expose the first film layer and the substrate located on the second region, respectively. A second dielectric layer is formed on the first region and the second region.
4. The method according to claim 3, characterized in that, The substrate on the first film layer and the second region is subjected to rapid thermal oxidation and / or rapid thermal nitriding to form the second dielectric layer on the first region and the second region, respectively.
5. The method according to claim 1, characterized in that, The first film layer includes a silicon-germanium layer, and the second film layer includes a silicon layer.
6. The method according to claim 1, characterized in that, The first film layer and the second film layer are formed sequentially in the same thin film deposition process, and the material of the first film layer is different from that of the second film layer.
7. The method according to claim 1, characterized in that, The thickness of the first film layer is between 10 Å and 1000 Å; the thickness of the second film layer is between 5 Å and 500 Å.
8. The method according to claim 3, characterized in that, The thickness of the second dielectric layer is less than the thickness of the first dielectric layer.
9. The method according to claim 1, characterized in that, The first dielectric layer is formed by thermal oxidation, and the first sacrificial layer is formed by atomic layer deposition.
10. The method according to claim 1, characterized in that, The thickness of the first dielectric layer is between 10 Å and 200 Å, and the thickness of the first sacrificial layer is between 10 Å and 500 Å.
11. The method according to claim 1, characterized in that, The substrate further includes a third region and a fourth region; a first dielectric layer and a first sacrificial layer are sequentially formed on the substrate, including: the first dielectric layer and the first sacrificial layer are sequentially formed on the third region and the fourth region.
12. The method according to claim 11, characterized in that, During the cleaning of the substrate, the first sacrificial layer on the third and fourth regions is removed.
13. The method according to claim 11, characterized in that, The substrate includes a core region and a peripheral region; wherein the first region and the second region are located on the core region, and the third region and the fourth region are located on the peripheral region.
14. The method according to claim 13, characterized in that, Before forming the first dielectric layer and the first sacrificial layer on the first region and the second region, the method further includes: An insulating stack is formed on the core area and the peripheral area, the insulating stack comprising a first oxide layer, a nitride layer and a second oxide layer stacked sequentially from bottom to top; Remove the first oxide layer, the nitride layer, and the second oxide layer from the core area and the peripheral area.
15. The method according to claim 1, characterized in that, The first region is used to form a first PMOS structure, and the second region is used to form a first NMOS structure.