A semiconductor structure, a forming method and a control method of a semiconductor machine

Abstract

Embodiments of the present application disclose a semiconductor structure, a forming method and a control method of a semiconductor machine. The forming method comprises the following steps: providing a wafer, the wafer comprising opposite front and back surfaces, the front surface being used for forming a semiconductor device; forming a stress adjusting structure covering the back surface, the stress adjusting structure comprising a first functional layer and a second functional layer, wherein the first functional layer is used for adjusting a warping degree of the wafer, and the second functional layer is used for adjusting an amount of electric charges in the first functional layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for forming it, and a method for controlling a semiconductor machine. Background Technology

[0002] With the development of semiconductor chip manufacturing technology, the integration density of semiconductor devices is increasing, and the number of chips fabricated on a single wafer is growing. During semiconductor manufacturing, the varying stresses of different thin-film materials deposited on the wafer can cause wafer warping, leading to numerous problems. These include wafer instability in the equipment, wafer breakage, and reduced pattern registration accuracy. Furthermore, it increases the difficulty of wafer mounting, affecting some process steps. All of these issues result in unstable product performance and reduced product yield and output. With the continuous increase in the number of layers in 3D NAND memory devices, the wafer warping problem is becoming increasingly severe. Summary of the Invention

[0003] In view of this, the main objective of this application is to provide a semiconductor structure, a method for forming it, and a method for controlling a semiconductor machine.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] This application provides a method for forming a semiconductor structure, the method comprising:

[0006] A wafer is provided, the wafer including opposing front and back sides, the front side being used to form a semiconductor device;

[0007] A stress-adjusting structure is formed covering the back side, the stress-adjusting structure including a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer.

[0008] In the above scheme, the second functional layer includes a first sub-layer of the second functional layer, which is used to block the charge in the wafer from entering the first functional layer in order to regulate the amount of charge in the first functional layer;

[0009] Forming a stress-regulating structure covering the back side, comprising:

[0010] The second functional layer, the first sublayer, and the first functional layer, covering the back side, are formed sequentially;

[0011] The first sublayer of the second functional layer is located between the first functional layer and the wafer.

[0012] In the above scheme, the second functional layer further includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer;

[0013] Forming a stress-regulating structure covering the back side, comprising:

[0014] A second functional layer and a second sublayer are formed on the first functional layer.

[0015] In the above scheme, the first functional layer is at least one of silicon nitride and silicon oxynitride;

[0016] The first sub-layer of the second functional layer is an insulating layer;

[0017] The second functional layer and the second sub-layer are doped silicon layers.

[0018] In the above scheme, the second functional layer includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer.

[0019] Forming a stress-regulating structure covering the back side, comprising:

[0020] A first functional layer and a second sublayer of the second functional layer are sequentially formed to cover the back side;

[0021] The first functional layer is located between the second sublayer of the second functional layer and the wafer.

[0022] In the above scheme, the first functional layer is at least one of silicon nitride and silicon oxynitride;

[0023] The second functional layer and the second sub-layer are doped silicon layers.

[0024] This application embodiment also provides a semiconductor structure, including: a wafer, the wafer including opposing front and back sides, the front side being used to form a semiconductor device;

[0025] A stress-adjusting structure is located on the back side of the wafer. The stress-adjusting structure includes a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer.

[0026] In the above scheme, the second functional layer includes a first sub-layer of the second functional layer, which is used to block the charge in the wafer from entering the first functional layer in order to regulate the amount of charge in the first functional layer;

[0027] The first sublayer of the second functional layer is located between the first functional layer and the wafer.

[0028] In the above scheme, the second functional layer further includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer. The first functional layer is located between the first sub-layer of the second functional layer and the second sub-layer of the second functional layer.

[0029] In the above scheme, the first functional layer is at least one of silicon nitride and silicon oxynitride;

[0030] The first sub-layer of the second functional layer is an insulating layer;

[0031] The second functional layer and the second sub-layer are doped silicon layers.

[0032] In the above scheme, the second functional layer includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer.

[0033] The first functional layer is located between the second sublayer of the second functional layer and the wafer.

[0034] In the above scheme, the first functional layer is at least one of silicon nitride and silicon oxynitride;

[0035] The second functional layer and the second sub-layer are doped silicon layers.

[0036] This application embodiment also provides a control method for a semiconductor machine tool, the method being applied to a semiconductor structure as described in any of the above solutions, the semiconductor machine tool including an electrostatic chuck, the method comprising:

[0037] The semiconductor structure is placed on the electrostatic chuck.

[0038] A voltage is applied to the electrostatic chuck to cause the semiconductor structure to adhere to the electrostatic chuck;

[0039] The semiconductor structure is processed using semiconductor technology.

[0040] The applied voltage to the electrostatic chuck is reduced to zero in order to remove the semiconductor structure, which has undergone semiconductor processing, from the electrostatic chuck.

[0041] In the above scheme, the semiconductor process includes plasma etching and plasma deposition.

[0042] The semiconductor structure, formation method, and semiconductor equipment control method provided in this application embodiment include, on one hand, a method comprising: providing a wafer including a front side and a back side, the front side being used to form a semiconductor device; forming a stress adjustment structure covering the back side; the stress adjustment structure including a first functional layer and a second functional layer; wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer; on the other hand, the semiconductor structure is formed by the method provided in this application embodiment. Thus, in addition to adjusting the wafer warpage, a second functional layer is added to adjust the amount of charge in the first functional layer. That is, by setting the first and second functional layers, while adjusting the wafer warpage, the amount of charge in the first functional layer located on the back side of the wafer for adjusting warpage can also be adjusted, reducing the electrostatic adsorption between the first functional layer and the electrostatic chuck (ESC), and reducing the risk of equipment alarms or wafer fragmentation. Attached Figure Description

[0043] Figure 1 This is a schematic diagram illustrating the electrostatic attraction between a wafer and an electrostatic chuck.

[0044] Figure 2 A schematic diagram illustrating the implementation flow of the semiconductor structure formation method provided in the embodiments of this application;

[0045] Figure 3 A schematic diagram of the wafer backside stress adjustment structure provided in the embodiments of this application;

[0046] Figure 4 A schematic diagram illustrating the implementation flow of a method for forming a semiconductor structure according to another embodiment of this application;

[0047] Figure 5 A schematic diagram of a wafer backside stress adjustment structure provided in another embodiment of this application;

[0048] Figure 6 A schematic diagram illustrating the implementation flow of a method for forming a semiconductor structure according to another embodiment of this application;

[0049] Figure 7 A schematic diagram of a wafer backside stress adjustment structure provided in another embodiment of this application.

[0050] Figure 8 This is a schematic diagram illustrating the implementation flow of the control method for a semiconductor machine provided in an embodiment of this application.

[0051] The above figures include the following reference numerals:

[0052] 10-Wafer; 11-Silicon nitride thin film; 12-Electrostatic chuck; 13-Electrode; 30-Wafer; 31-Second functional layer first sublayer; 32-First functional layer; 50-Wafer; 51-First functional layer; 52-Second functional layer second sublayer; 70-Wafer; 71-Second functional layer first sublayer; 72-First functional layer; 73-Second functional layer second sublayer. Detailed Implementation

[0053] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0054] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0055] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0056] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces.

[0057] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0058] Figure 1This diagram illustrates the electrostatic adsorption between a wafer and an electrostatic chuck. With the development of semiconductor chip manufacturing technology, the integration density of semiconductor devices is increasing, and the number of chips fabricated on a single wafer is growing. During semiconductor manufacturing, the varying stresses of different thin-film materials deposited on the wafer can cause wafer warping, leading to numerous problems. These include wafer instability in the machine, wafer breakage, and reduced pattern alignment accuracy. Furthermore, it increases the difficulty of wafer adsorption, affecting some process steps. All of these problems result in unstable product performance and reduced product yield and output. With the continuous increase in the number of layers in 3D NAND memory devices, wafer warping is becoming increasingly severe. Therefore, as... Figure 1 As shown, wafer 10 includes a front side and a back side. The front side is used to form semiconductor devices. Depending on the degree of wafer warpage, a silicon nitride thin film 11 is grown on the back side of wafer 10 to balance wafer stress and adjust wafer warpage. This is a common method for adjusting wafer warpage. Figure 1 As shown, when the wafer is placed on the electrostatic chuck 12, due to the high trap density between the silicon nitride film 11 and the wafer 10 interface, the silicon nitride film easily traps charges under the electric field of the electrostatic chuck 12. This results in a large electrostatic adsorption between the silicon nitride film 11 and the electrostatic chuck 12 during the de-chuck process after the process is completed, which can easily lead to de-chuck failure, resulting in machine alarms or wafer fragments.

[0059] Based on this, embodiments of this application provide a method for forming a semiconductor structure. Figure 2 This is a schematic diagram illustrating the implementation flow of the method for forming a semiconductor structure provided in an embodiment of this application. Figure 2 As shown, the method includes the following steps:

[0060] Step 201: Provide a wafer, the wafer including opposing front and back sides, the front side being used to form a semiconductor device;

[0061] Step 202: Form a stress adjustment structure covering the back side, the stress adjustment structure including a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge in the first functional layer.

[0062] In this embodiment, a stress adjustment structure is formed on the back side of the wafer. The stress adjustment structure includes a first functional layer and a second functional layer. The first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge in the first functional layer. Thus, in addition to adjusting the wafer warpage, a second functional layer is added to adjust the amount of charge in the first functional layer. That is, by setting the first and second functional layers, while adjusting the wafer warpage, the amount of charge in the first functional layer located on the back side of the wafer for adjusting the warpage can also be adjusted, reducing the electrostatic adsorption between the first functional layer and the ESC, and reducing the risk of machine alarms or wafer fragmentation.

[0063] In this embodiment of the application, the second functional layer includes a first sub-layer of the second functional layer, and step 202 includes sequentially forming the first sub-layer of the second functional layer and the first functional layer covering the back side. Figure 3 It shows the way Figure 2 A schematic diagram of the wafer backside stress-adjusting structure formed by the method shown. (See diagram below.) Figure 3 As shown, wafer 30 includes a front side and a back side; a stress adjustment structure is located on the back side of wafer 30, the stress adjustment structure includes a first functional layer 32 and a second functional layer first sub-layer 31; wherein, the first functional layer 32 is used to adjust the warpage of the wafer, and the second functional layer first sub-layer 31 is used to block the charge in the wafer from entering the first functional layer so as to adjust the amount of charge in the first functional layer 32.

[0064] In this embodiment, the first sub-layer 31 of the second functional layer is located between the first functional layer 32 and the wafer 30. The charge isolation function of the first sub-layer 31 of the second functional layer prevents charges within the wafer 30 from entering the first functional layer 32.

[0065] In this embodiment, the wafer 30 can be a single-crystal silicon wafer. In other embodiments, the wafer can also be a wafer made of other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI), etc. The front side of the wafer is used to form semiconductor devices.

[0066] In some embodiments, the wafer 30 may be a semiconductor substrate. The semiconductor substrate may be a substrate of a single-element semiconductor material (e.g., a silicon substrate, germanium substrate, etc.), a substrate of a composite semiconductor material (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, germanium-on-insulator (GeOI) substrate, etc. The front side of the semiconductor substrate is used to form semiconductor devices.

[0067] Here, the semiconductor device includes a memory array and contact structures. The memory array may include structures such as transistors, word lines, and bit lines. The contact structures may include conductive contact structures and metal layers formed on the memory array, and these contact structures are used to electrically lead out the memory array. For example, the contact structures can be used to control signal transmission at one or more source and / or drain terminals of transistors and structures such as word lines and bit lines.

[0068] In this embodiment, the material of the first functional layer 32 includes at least one of silicon nitride, silicon oxynitride, polycrystalline silicon, and amorphous carbon; the first sub-layer 31 of the second functional layer includes an insulating layer, and in some embodiments, the first sub-layer 31 of the second functional layer can be any one of silicon oxide and aluminum oxide.

[0069] In practical applications, the first functional layer 32 and the first sub-layer 31 of the second functional layer can be formed by deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0070] In one specific embodiment, a layer with a thickness ranging from [thickness range missing] is first formed on the back side of the wafer. A silicon oxide layer (the first sublayer of the second functional layer) is formed, and then a silicon nitride layer (the first functional layer) is formed on the silicon oxide layer. The silicon oxide layer between the wafer and the silicon nitride layer can isolate charges, thereby preventing charges in the wafer from being pulled into the silicon nitride layer under the influence of the ESC electric field, thus reducing the amount of charge trapped in the silicon nitride layer. In this way, the electrostatic adsorption between the silicon nitride layer and the ESC is reduced, reducing the risk of machine alarms or wafer fragmentation.

[0071] It should be noted that in practical applications, the thickness of the silicon nitride layer (first functional layer) can be determined according to the degree of wafer warpage, thereby allowing for targeted adjustments to the wafer warpage.

[0072] In another embodiment of this application, a different method for forming a semiconductor structure is provided. Figure 4 This is a schematic diagram illustrating the implementation flow of the method for forming a semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the method includes the following steps:

[0073] Step 401: Provide a wafer, the wafer including opposing front and back sides, the front side being used to form a semiconductor device;

[0074] Step 402: Form a stress adjustment structure covering the back side, the stress adjustment structure including a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge in the first functional layer.

[0075] In this embodiment, a stress-adjusting structure is formed on the back side of the wafer. The stress-adjusting structure includes a first functional layer and a second functional layer. The first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to remove the charge within the first functional layer. Thus, in addition to adjusting the wafer warpage, a second functional layer is added to adjust the charge within the first functional layer. That is, by setting the first and second functional layers, while adjusting the wafer warpage, the charge within the first functional layer can also be adjusted through the second functional layer. This reduces the electrostatic adsorption between the first functional layer and the ESC, reducing the risk of machine alarms or wafer fragmentation.

[0076] In this embodiment of the application, the second functional layer includes a second sub-layer of the second functional layer, and step 402 above includes sequentially forming a first functional layer and a second sub-layer of the second functional layer covering the back side. Figure 5 It shows the way Figure 4 A schematic diagram of the wafer backside stress-adjusting structure formed by the method shown. (See diagram below.) Figure 5 As shown, wafer 50 includes a front side and a back side; a stress adjustment structure is located on the back side of wafer 50, the stress adjustment structure includes a first functional layer 51 and a second functional layer second sub-layer 52; wherein, the first functional layer 51 is used to adjust the warpage of the wafer, and the second functional layer second sub-layer 52 is used to discharge the charge in the first functional layer to adjust the amount of charge in the first functional layer 51.

[0077] In this embodiment, the first functional layer 51 is located between the second functional layer second sub-layer 52 and the wafer 50. The high conductivity of the second functional layer second sub-layer 52 facilitates the removal of charge from the first functional layer 51.

[0078] In this embodiment, the wafer 50 can be a single-crystal silicon wafer. In other embodiments, the wafer can also be a wafer made of other semiconductor materials, such as germanium, germanium-silicon, silicon-on-insulator, etc. The front side of the wafer is used to form a semiconductor device.

[0079] In some embodiments, the wafer may be a semiconductor substrate. The front side of the semiconductor substrate is used to form semiconductor devices.

[0080] In this embodiment of the application, the material of the first functional layer 51 includes at least one of silicon nitride and silicon oxynitride; the second sub-layer 52 of the second functional layer is a doped silicon layer, which can be formed by doping the polycrystalline silicon layer with any one or more of boron, phosphorus, gallium, selenium or arsenic.

[0081] In practical applications, a first functional layer and a second functional layer and a second sub-layer can be formed by a deposition process. The formation process of the second functional layer and the second sub-layer can also be to first form a polycrystalline silicon layer by a deposition process, and then form a doped silicon layer by an ion implantation process.

[0082] In one specific embodiment, a silicon nitride layer (first functional layer) is first formed on the back side of the wafer, and then a layer with a thickness ranging from [missing information] is formed on the silicon nitride layer. The polysilicon layer (second sublayer of the second functional layer) is doped with boron, phosphorus, gallium, selenium, or arsenic ions to increase its conductivity. After the ESC process, the highly conductive second sublayer of the second functional layer can quickly conduct away the charges trapped in the first functional layer. This reduces electrostatic attraction between the first functional layer and the ESC, minimizing the risk of machine alarms or wafer fragmentation.

[0083] It should be noted that in practical applications, the thickness of the silicon nitride layer (first functional layer) can be determined according to the degree of wafer warpage, thereby allowing for targeted adjustments to the wafer warpage.

[0084] In another embodiment of this application, the stress adjustment structure on the back side of the wafer includes a first sublayer of a second functional layer, a first functional layer, and a second sublayer of a second functional layer sequentially formed on the back side of the wafer. Figure 6 This is a schematic diagram illustrating the implementation flow of the method for forming a semiconductor structure provided in an embodiment of this application. Figure 6 As shown, the method includes the following steps:

[0085] Step 601: Provide a wafer, the wafer including opposing front and back sides, the front side being used to form a semiconductor device;

[0086] Step 602: Sequentially form a first sublayer of the second functional layer, a first functional layer, and a second sublayer of the second functional layer covering the back side; wherein, the first functional layer is used to adjust the warpage of the wafer, the first sublayer of the second functional layer is used to block the charge in the wafer from entering the first functional layer, and the second sublayer of the second functional layer is used to discharge the charge in the first functional layer.

[0087] This application embodiment forms a stress adjustment structure on the back side of the wafer. The stress adjustment structure includes a first functional layer, a second functional layer, and a third functional layer. The first functional layer is used to adjust the warpage of the wafer, and the first sub-layer and the second sub-layer of the second functional layer are used to adjust the amount of charge within the first functional layer. Thus, in addition to adjusting the wafer warpage, a first sub-layer of the second functional layer is added to prevent the charge within the wafer from entering the first functional layer, and a second sub-layer of the second functional layer is added to discharge the charge within the first functional layer. That is, by setting the first functional layer, the first sub-layer of the second functional layer, and the second sub-layer of the second functional layer, the amount of charge in the first functional layer located on the back side of the wafer for adjusting the warpage can be adjusted while simultaneously adjusting the wafer warpage. This greatly reduces the electrostatic adsorption between the first functional layer and the ESC, reducing the risk of machine alarms or wafer fragmentation.

[0088] Figure 7 It shows the way Figure 6 A schematic diagram of the wafer backside stress-adjusting structure formed by the method shown. (See diagram below.) Figure 7 As shown, wafer 70 includes a front side and a back side; a stress adjustment structure is located on the back side of wafer 70, the stress adjustment structure includes a first sublayer 71 of a second functional layer, a first functional layer 72, and a second sublayer 73 of a second functional layer; wherein, the first functional layer 72 is used to adjust the warpage of the wafer, and the first sublayer 71 and the second sublayer 73 of the second functional layer are used to adjust the amount of charge in the first functional layer 72.

[0089] In this embodiment, the first sublayer 71 of the second functional layer is located between the first functional layer 72 and the wafer 70 to prevent charges within the wafer from entering the first functional layer. The first functional layer 72 is located between the first sublayer 71 and the second sublayer 73 of the second functional layer, such that the second sublayer 73 can be used to discharge charges within the first functional layer.

[0090] In one embodiment, the wafer 70 can be a single-crystal silicon wafer. In other embodiments, the wafer can also be a wafer made of other semiconductor materials, such as germanium, germanium-silicon, silicon-on-insulator, etc. The front side of the wafer is used to form a semiconductor device.

[0091] In some embodiments, the wafer may be a semiconductor substrate. The front side of the semiconductor substrate is used to form semiconductor devices.

[0092] In this embodiment, the material of the first functional layer 72 includes at least one of silicon nitride and silicon oxynitride; the first sub-layer 71 of the second functional layer includes an insulating layer, and in some embodiments, the first sub-layer 71 of the second functional layer can be any one of silicon oxide and aluminum oxide; the second sub-layer 73 of the second functional layer is a doped silicon layer, which can be formed by doping the polycrystalline silicon layer with any one or more of boron, phosphorus, gallium, selenium or arsenic.

[0093] In practical applications, a first functional layer, a first sublayer of a second functional layer, and a second sublayer of a second functional layer can be formed through a deposition process. The formation process of the second sublayer of the second functional layer can also be to first form a polycrystalline silicon layer through a deposition process, and then form a doped silicon layer through an ion implantation process.

[0094] In one specific embodiment, a layer with a thickness ranging from [thickness range missing] is first formed on the back side of the wafer. A silicon oxide layer (the first sublayer of the second functional layer) is formed, then a silicon nitride layer (the first functional layer) is formed on the silicon oxide layer, and finally a layer with a thickness ranging from [thickness range missing] is formed on the silicon nitride layer. The polysilicon layer (second functional layer, second sublayer) may or may not contain doped ions such as boron, phosphorus, gallium, selenium, or arsenic. It can prevent charges in the wafer from entering the silicon nitride layer under the influence of the ESC electric field, and the outermost highly conductive polysilicon layer can quickly conduct away the charges captured in the silicon nitride layer after the ESC process is completed.

[0095] In some embodiments, the silicon oxide layer (first sublayer of the second functional layer) and the polysilicon layer (second sublayer of the second functional layer) can have the same thickness. In practical applications, the thicknesses of the first and second sublayers of the second functional layer can be set according to the thickness of the silicon nitride layer (first functional layer) and the amount of charge trapped therein. Since the first sublayer of the second functional layer can prevent charges in the wafer from entering the first functional layer, and the second sublayer of the second functional layer can conduct away charges in the silicon nitride layer, when the first sublayer of the second functional layer is thicker, the second sublayer of the second functional layer can be made thinner; and when the second sublayer of the second functional layer is thicker, the first sublayer of the second functional layer can be made thinner, so as to minimize the total thickness of the first and second sublayers of the second functional layer.

[0096] This application also provides a method for controlling a semiconductor machine, which is applied to the semiconductor structure described in any of the above embodiments, wherein the semiconductor machine includes an electrostatic chuck. Figure 8 This is a schematic diagram illustrating the implementation flow of the control method for a semiconductor machine provided in an embodiment of this application. Figure 8 As shown, the control method includes the following steps:

[0097] Step S801: Place the semiconductor structure on the electrostatic chuck;

[0098] Step S802: Apply voltage to the electrostatic chuck to cause the semiconductor structure to adhere to the electrostatic chuck;

[0099] In step S802 above, the voltage is typically applied to the electrodes of the electrostatic chuck, wherein the semiconductor structure is attracted to the electrostatic chuck by electrostatic force.

[0100] Step S803: Perform semiconductor process processing on the semiconductor structure, the semiconductor process processing including plasma etching and plasma deposition.

[0101] Step S804: Reduce the applied voltage of the electrostatic chuck to zero to remove the semiconductor structure after semiconductor processing from the electrostatic chuck.

[0102] In step S804 above, since the control method is applied to the semiconductor structure in any one of the embodiments of this application, the situation where the semiconductor structure "sticks" to the surface of the electrostatic chuck and is difficult to release after the voltage is cut off is avoided. Furthermore, the electrostatic adsorption between the semiconductor structure and the electrostatic chuck is reduced during the removal of electrostatic adsorption after the process is completed, thereby reducing the risk of machine alarms or wafer fragments.

[0103] This application provides a semiconductor structure, a method for forming the semiconductor, and a method for controlling a semiconductor machine. The semiconductor structure includes: a wafer with opposing front and back sides, the front side being used to form a semiconductor device; and a stress-adjusting structure located on the back side of the wafer, the stress-adjusting structure including a first functional layer and a second functional layer; wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer. This application, based on achieving wafer warpage adjustment, adds a second functional layer to adjust the amount of charge in the first functional layer. That is, by setting the first and second functional layers, while adjusting the wafer warpage, the amount of charge in the first functional layer located on the back side of the wafer for adjusting warpage can be adjusted simultaneously, reducing the electrostatic adsorption between the first functional layer and the electrostatic chuck (ESC) during the electrostatic discharge process after the process is completed, thus reducing the risk of machine alarms or wafer fragmentation.

[0104] It should be understood that the phrases "an embodiment" or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A wafer is provided, the wafer including opposing front and back sides, the front side being used to form a semiconductor device; A stress-adjusting structure is formed covering the back side, the stress-adjusting structure including a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer.

2. The method as described in claim 1, characterized in that, The second functional layer includes a first sub-layer of the second functional layer, which is used to block the charge in the wafer from entering the first functional layer in order to regulate the amount of charge in the first functional layer; Forming a stress-regulating structure covering the back side, comprising: The second functional layer, the first sublayer, and the first functional layer, covering the back side, are formed sequentially; The first sublayer of the second functional layer is located between the first functional layer and the wafer.

3. The method as described in claim 2, characterized in that, The second functional layer further includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer; Forming a stress-regulating structure covering the back side, comprising: A second functional layer and a second sub-layer are then formed on the first functional layer.

4. The method as described in claim 3, characterized in that, The first functional layer includes at least one of silicon nitride and silicon oxynitride; The first sub-layer of the second functional layer is an insulating layer; The second functional layer and the second sub-layer are doped silicon layers.

5. The method as described in claim 1, characterized in that, The second functional layer includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer; Forming a stress-regulating structure covering the back side, comprising: A first functional layer and a second functional layer, and a second sublayer, are sequentially formed to cover the back side. The first functional layer is located between the second sublayer of the second functional layer and the wafer.

6. The method as described in claim 5, characterized in that, The first functional layer includes at least one of silicon nitride and silicon oxynitride; The second functional layer and the second sub-layer are doped silicon layers.

7. A semiconductor structure, characterized in that, include: A wafer, the wafer including opposing front and back sides, the front side being used to form a semiconductor device; A stress-adjusting structure is located on the back side of the wafer. The stress-adjusting structure includes a first functional layer and a second functional layer, wherein the first functional layer is used to adjust the warpage of the wafer, and the second functional layer is used to adjust the amount of charge within the first functional layer.

8. The structure as described in claim 7, characterized in that, The second functional layer includes a first sub-layer of the second functional layer, which is used to block the charge in the wafer from entering the first functional layer in order to regulate the amount of charge in the first functional layer; The first sublayer of the second functional layer is located between the first functional layer and the wafer.

9. The structure as described in claim 8, characterized in that, The second functional layer further includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer. The first functional layer is located between the first sub-layer of the second functional layer and the second sub-layer of the second functional layer.

10. The structure as described in claim 9, characterized in that, The first functional layer includes at least one of silicon nitride and silicon oxynitride; The first sub-layer of the second functional layer is an insulating layer; The second functional layer and the second sub-layer are doped silicon layers.

11. The structure as described in claim 7, characterized in that, The second functional layer includes a second sub-layer of the second functional layer, which is used to export the charge in the first functional layer to adjust the amount of charge in the first functional layer; The first functional layer is located between the second sublayer of the second functional layer and the wafer.

12. The structure as described in claim 11, characterized in that, The first functional layer includes at least one of silicon nitride and silicon oxynitride; The second functional layer and the second sub-layer are doped silicon layers.

13. A control method for a semiconductor machine, characterized in that, The method is applied to the semiconductor structure according to any one of claims 7 to 12, wherein the semiconductor equipment includes an electrostatic chuck, and the method comprises: The semiconductor structure is placed on the electrostatic chuck. A voltage is applied to the electrostatic chuck to cause the semiconductor structure to adhere to the electrostatic chuck; The semiconductor structure is processed using semiconductor technology. The applied voltage to the electrostatic chuck is reduced to zero in order to remove the semiconductor structure, which has undergone semiconductor processing, from the electrostatic chuck.

14. The method as described in claim 13, characterized in that, The semiconductor process includes plasma etching and plasma deposition.

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