A semiconductor structure and its fabrication method

Abstract

This disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate, the substrate including a trench structure; sequentially forming a first isolation layer, a second isolation layer, and a third isolation layer on the bottom and sidewalls of the trench structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate to form a side trench; etching the third isolation layer such that the upper surface of the third isolation layer is lower than the upper surface of the second isolation layer, thereby causing the top of the second isolation layer to protrude beyond the first and third isolation layers to form a protrusion structure; and etching the second isolation layer to remove the protrusion structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the manufacturing of integrated circuits, tens of thousands of active devices (such as PMOS and NMOS) are integrated simultaneously on a substrate material. To prevent these devices from interfering with each other, isolation techniques are used to isolate the active devices from one another.

[0003] However, current isolation technologies still have shortcomings, and how to optimize the isolation effect is a technical problem that urgently needs to be solved at this stage. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, including:

[0005] A substrate is provided, the substrate including a groove structure;

[0006] A first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the bottom and sidewalls of the groove structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate, thereby forming a side trench;

[0007] The third isolation layer is etched such that the upper surface of the third isolation layer is lower than the upper surface of the second isolation layer, thereby causing the top of the second isolation layer to protrude from the first and third isolation layers to form a raised structure.

[0008] The second isolation layer is etched to remove the protruding structure.

[0009] In some embodiments, etching the second isolation layer to remove the protrusion structure includes:

[0010] The second isolation layer is etched using a wet etching process, wherein the wet etching agent in the wet etching process includes phosphoric acid.

[0011] In some embodiments, the temperature of the wet etching process is controlled between 155 degrees Celsius and 165 degrees Celsius.

[0012] In some embodiments, etching the third isolation layer includes:

[0013] The third isolation layer is etched using a gas etching process, wherein the gas includes hydrogen and oxygen.

[0014] In some embodiments, etching the third isolation layer further includes:

[0015] This makes the upper surface of the third isolation layer flush with the upper surface of the first isolation layer.

[0016] In some embodiments, after forming the first isolation layer, the second isolation layer, and the third isolation layer, the method further includes:

[0017] A silicon-germanium layer is formed on the surface of the substrate located on one side of the groove structure.

[0018] In some embodiments, after etching the third isolation layer, the method further includes:

[0019] A protective layer is formed on the surface of the silicon-germanium layer and on the surface of the substrate located on the other side of the groove structure.

[0020] In some embodiments, after etching the second isolation layer, the method further includes:

[0021] Remove the protective layer.

[0022] In some embodiments, the preparation method includes:

[0023] The protective layer was removed using a hydrofluoric acid solution.

[0024] In some embodiments, after removing the protective layer, the method further includes:

[0025] A high-k dielectric layer is deposited on top of the substrate;

[0026] A first gate stack is formed on a high-k dielectric layer on one side of the groove structure where the silicon-germanium layer is formed, and a second gate stack is formed on a high-k dielectric layer on the other side of the groove structure. The first gate stack and the second gate stack are made of different materials.

[0027] In some embodiments, the preparation method includes:

[0028] The first gate stack includes a stacked structure of titanium nitride, aluminum oxide and titanium nitride, and the second gate stack includes a stacked structure of lanthanum oxide and titanium nitride.

[0029] In some embodiments, prior to depositing a high-k dielectric layer over the substrate, the method further includes:

[0030] An interface layer is formed on the surface of the silicon-germanium layer and on the surface of the substrate located on the other side of the groove structure.

[0031] In some embodiments, a PMOS is formed on one side of the groove structure where the silicon-germanium layer is formed, and an NMOS is formed on the other side of the groove structure.

[0032] This disclosure also provides a semiconductor structure, including:

[0033] Substrate, the substrate including a groove structure;

[0034] An insulating dielectric material is provided, which fills the groove structure. The insulating dielectric material includes a first insulating layer, a second insulating layer, and a third insulating layer sequentially covering the bottom surface and sidewalls of the groove structure.

[0035] The upper surface of the isolation dielectric is lower than the upper surface of the substrate, and the upper surfaces of the first isolation layer and the second isolation layer are flush.

[0036] In some embodiments, the upper surfaces of the first isolation layer, the second isolation layer, and the third isolation layer are flush.

[0037] In some embodiments, the semiconductor structure further includes:

[0038] A silicon-germanium layer, the silicon-germanium layer being located on the surface of the substrate on one side of the groove structure.

[0039] In some embodiments, the semiconductor structure further includes:

[0040] PMOS, wherein the PMOS is located on one side of the groove structure, and the channel of the PMOS includes a silicon-germanium layer;

[0041] The NMOS is located on the other side of the groove structure.

[0042] This disclosure forms a raised structure of the second isolation layer by etching the third isolation layer, and then etches away the raised structure, thereby eliminating the side trench and avoiding the side trench from affecting the electrical characteristics of the device. At the same time, it reduces the process difficulty of subsequent metal wiring and film deposition.

[0043] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 2a-2m This is a schematic diagram of the semiconductor structure in the fabrication process according to an embodiment of the present disclosure;

[0047] Figure 3This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0048] Figure label:

[0049] 201-Substrate; 203-Groove structure; 204-Isolation dielectric; 205-First isolation layer; 207-Second isolation layer; 209-Third isolation layer; 211-Side trench; 213-First oxide layer; 214-Silicon nitride layer; 215-Second oxide layer; 216-Third oxide layer; 217-Silicon germanium layer; 219-Bump structure; 221-Protective layer; 223-Interface layer; 225-High-K dielectric layer; 227-Titanium nitride; 229-Aluminum oxide; 231-Lanium oxide; 233-First gate stack; 235-Second gate stack. Detailed Implementation

[0050] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] With the advancement of Moore's Law, shallow trench isolation (STI) technology has become increasingly widely used for fabricating insulating structures between active regions. However, due to process limitations, the area adjacent to the active region in an STI structure tends to recess downwards, forming a trench. Forming semiconductor devices on substrates with trenches can easily generate parasitic currents, affecting the electrical characteristics of the semiconductor devices. Furthermore, the presence of trenches increases the difficulty of subsequent semiconductor device fabrication processes, such as causing the deposited conductive layer to fracture, leading to semiconductor device failure.

[0056] Based on this, the present disclosure provides a method for fabricating a semiconductor structure, as shown in the attached figure. Figure 1 The method includes:

[0057] Step 101: Provide a substrate, the substrate including a groove structure.

[0058] Step 102: A first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the bottom and sidewall of the groove structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate, thereby forming a side trench.

[0059] Step 103: Etch the third isolation layer so that the upper surface of the third isolation layer is lower than the upper surface of the second isolation layer, thereby causing the top of the second isolation layer to protrude from the first and third isolation layers to form a raised structure.

[0060] Step 104: Etch the second isolation layer to remove the protrusion structure.

[0061] In this embodiment of the disclosure, the protrusion structure of the second isolation layer is formed by etching the third isolation layer, and then the protrusion structure is removed by etching, thereby eliminating the side trench and avoiding the side trench from affecting the electrical characteristics of the device. At the same time, it reduces the process difficulty of subsequent metal wiring and film deposition.

[0062] The following is in conjunction with the appendix Figure 2a-2m The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0063] First, perform step 101, as shown in the attached document. Figure 2a As shown, a substrate 201 is provided, the substrate including a trench structure 203. The substrate 201 includes, but is not limited to, silicon, silicon-germanium, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), or other suitable semiconductor substrates. The trench structure 203 can be formed, for example, by photolithography and etching processes to fundamentally isolate the active region of the device. In some embodiments, the sidewalls and bottom surface of the trench structure have rounded corners, which helps to improve the filling quality and electrical characteristics of the isolation structure.

[0064] Next, proceed to step 102, referring to the appendix. Figures 2b-2e A first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 are sequentially formed on the bottom and sidewall of the groove structure 203, wherein the upper surface of the first isolation layer 205 is lower than the upper surface of the second isolation layer 207 and the substrate 201, thereby forming a side groove 211.

[0065] In some embodiments, see Appendix Figures 2b-2c A first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 are sequentially formed on the bottom and sidewall of the groove structure, including: depositing the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 sequentially on the substrate; and planarizing the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 with the surface of the substrate as a stop layer.

[0066] Specifically, firstly, as shown in the attached document... Figure 2bAs shown, a first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 are sequentially deposited on the substrate. The first isolation layer 205 can be made of an oxide material, for example, silicon oxide. In practice, it can be fabricated using an oxidation process, where the substrate is placed in a high-temperature oxidation apparatus, and an oxide layer is grown using the principle of thermal oxidation. The first isolation layer 205 primarily serves to directly protect the active region and simultaneously repair damage to the etched surfaces of the substrate recesses. The second isolation layer 207 can be made of a nitride material, for example, silicon nitride. In practice, a low-pressure chemical vapor deposition (LPCVD) method can be used, introducing ammonia and silicon tetrachloride to form a silicon nitride layer on top of the first isolation layer 205. The third isolation layer 209 can be made of an insulating dielectric material, for example, an oxide. In practice, wet oxidation, dry oxidation, or spin-on dielectric (SOD) processes can be used to form the insulating medium. Spin-on dielectric (SOD) processes have advantages such as good insulation performance and strong hole-filling ability. Using SOD to fill the trenches between microelectronic circuits can reduce the space occupied by the isolation area while keeping the device performance unchanged, thereby realizing high-density circuit technology and improving circuit efficiency.

[0067] Next, as attached Figure 2c As shown, the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 are planarized. The planarization process can be, for example, chemical mechanical polishing (CMP), where the substrate plane can serve as a stop layer for the CMP process.

[0068] In some embodiments, as shown in the appendix Figure 2d As shown, after forming the first, second, and third isolation layers, the process further includes forming a mask layer over the substrate. The mask layer comprises a stacked structure of a first oxide layer 213, a silicon nitride layer 214, and a second oxide layer 215. The mask is used to protect other areas of the substrate, for example, in a semiconductor memory device comprising a core region and a peripheral region, preventing subsequent processes in the peripheral region from affecting the components in the core region. Specifically, the steps of forming the first oxide layer 213, the silicon nitride layer 214, and the second oxide layer 215 are performed before the process of growing the gate in the peripheral region.

[0069] In some embodiments, as shown in the appendix Figure 2e-2gAs shown, after forming the first, second, and third isolation layers, the method further includes forming a silicon-germanium (SiGe) layer 217 on the surface of the substrate located on one side of the groove structure. The silicon-germanium layer is used to form the channel of the PMOS. The stress mechanism of the silicon-germanium layer has a significant effect on improving the drive current. Due to the stress effect, the silicon-germanium layer can improve the mobility of channel carriers, which is beneficial for adjusting the threshold voltage.

[0070] Specifically, firstly, refer to the appendix. Figure 2e A third oxide layer 216 is formed on the substrate surface on both sides of the groove structure. For example, the third oxide layer can be formed on the substrate by a thermal oxidation process. In some specific embodiments, the thickness of the third oxide layer is relatively thick, for example, 30-60 nm, such as 32 nm, 42 nm, 55 nm, 58 nm, etc.

[0071] Next, refer to the appendix Figure 2f The third oxide layer 216 on the surface of the substrate located on one side of the groove structure is etched to expose the substrate, and a silicon-germanium (SiGe) layer 217 is formed on the surface of the substrate located on one side of the groove structure. In practice, the third oxide layer 216 on one side of the groove structure can be removed by dry etching or wet etching processes, and the silicon-germanium layer 217 can be deposited by chemical vapor deposition (CVD), selective vapor deposition, or other techniques.

[0072] In the above process, the step of planarizing the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 (see...) Figure 2c During the process of removing the mask layer and removing the third oxide layer 216 on the substrate surface on one side of the groove structure, the first isolation layer 205 will be over-etched, causing the lower surface of the first isolation layer 205 to sink and creating a side trench 211 (e.g. Figure 2e (As shown). In particular, due to the relatively thick thickness of the third oxide layer 216, the process of removing the third oxide layer 216 will further increase the aspect ratio of the trench, exacerbating the adverse effects of the trench on device performance. The trenches generated in the above steps will be eliminated or improved in subsequent process steps, thereby reducing the adverse effects of the trenches.

[0073] After growing the silicon-germanium layer 217, refer to the attached document. Figure 2g The third oxide layer 216 on the surface of the substrate located on the other side of the groove structure is etched away to expose the substrate in preparation for subsequent deposition of a high-k dielectric layer and gate stack.

[0074] Next, proceed to step 103, as shown in the attached document. Figure 2hAs shown, the third isolation layer 209 is etched so that its upper surface is lower than that of the second isolation layer, thereby causing the top of the second isolation layer 207 to protrude from the first isolation layer 205 and the third isolation layer 209 to form a protrusion structure 219. By etching the third isolation layer 209, the second isolation layer is fully exposed to form the protrusion structure 219, which increases the surface area of ​​the second isolation layer in contact with the outside world. This facilitates an efficient and uniform reduction of the height of the upper surface of the second isolation layer, and makes it easier to control the etching rate of the second isolation layer, preventing over-etching. At the same time, it reduces the surface height of the third isolation layer, making the surface of the insulating dielectric filled in the groove smoother.

[0075] In some embodiments, the third isolation layer is etched using a gas etching process, wherein the gas includes hydrogen and oxygen. Specifically, the sample can be placed in a WET certas instrument, and a certain flow rate of hydrogen and oxygen can be introduced into the instrument to achieve etching. Since gas etching causes less contamination to the substrate and the etching rate is controllable, the height difference between the first and third isolation layers is easily adjusted.

[0076] In some embodiments, etching the third isolation layer further includes making the upper surface of the third isolation layer flush with the upper surface of the first isolation layer. After removing the protrusion structure, the surface of the isolation dielectric composed of the first, second, and third isolation layers becomes flatter, reducing the process difficulty of subsequent deposition of the high-k dielectric layer and gate stack. Because the opening above the first isolation layer 205 is narrow, the etching gas has difficulty etching the first isolation layer. Therefore, the etching rate of the third isolation layer is greater than that of the first isolation layer. By controlling parameters such as etching time, it is possible to make the upper surface of the first isolation layer flush with the upper surface of the second isolation layer after etching.

[0077] Finally, proceed to step 104, referring to the appendix. Figure 2i-2j The second isolation layer 207 is etched to remove the protrusion structure 219.

[0078] In some embodiments, etching the second isolation layer 207 to remove the protrusion structure 219 includes: etching the second isolation layer 207 using a wet etching process, wherein the wet etchant in the wet etching process includes phosphoric acid. The wet etching process is simple to operate, has low equipment requirements, and is easy to implement for mass production. For example, when the second isolation layer is silicon nitride, phosphoric acid has good uniformity and a high etching selectivity for the second isolation layer, thus having minimal impact on the first and third isolation layers when removing the protrusion structure 219. In actual operation, the temperature of the wet etching process is controlled between 155 degrees Celsius and 165 degrees Celsius, for example, 157 degrees Celsius, 162 degrees Celsius, etc. Too low a temperature in the wet etching process will lead to reduced etching efficiency or incomplete removal of the second isolation layer, while too high a temperature may lead to over-etching.

[0079] In some embodiments, the process parameters for etching the second isolation layer 207 are controlled such that the upper surface of the second isolation layer 207 is flush with the upper surfaces of the first isolation layer 205 and the third isolation layer 209. By setting the upper surfaces of the first isolation layer, the second isolation layer, and the third isolation layer to be flush, the process difficulty of subsequent metal wiring and film deposition can be reduced.

[0080] In some embodiments, as shown in the appendix Figure 2i As shown, after etching the third isolation layer 209, the process further includes forming a protective layer 221 on the surface of the silicon-germanium layer 217 and on the surface of the substrate located on the other side of the trench structure. The protective layer can be made of an oxide material, for example, silicon oxide. In practice, the substrate can be placed in a high-temperature pure oxygen chamber, and a certain amount of pure oxygen can be introduced to form a thermal oxide layer on the surface of the silicon-germanium layer 217 and on the surface of the substrate located on the other side of the trench structure using high-temperature oxidation. The thickness of the thermal oxide layer can be, for example, 2–3 nm. The protective layer can protect the silicon-germanium layer and the substrate during the subsequent process of etching the second isolation layer with phosphoric acid, preventing phosphoric acid contamination of the substrate and protecting the trench area.

[0081] In some embodiments, as shown in the appendix Figure 2k As shown, after etching the second isolation layer 207, the process further includes removing the protective layer 221. Removing the protective layer exposes the channel region, preparing for subsequent deposition of a high-k dielectric layer and gate stack. In practice, a hydrofluoric acid solution can be used to remove the protective layer. Hydrofluoric acid offers good uniformity and high etch selectivity for oxide protective layers.

[0082] In some embodiments, as shown in the appendix Figure 2l-2mAs shown, after removing the protective layer, the process further includes: depositing a high-k dielectric layer 225 on top of the substrate; forming a first gate stack 233 on the high-k dielectric layer 225 located on one side of the groove structure where the silicon-germanium layer 217 is formed; and forming a second gate stack 235 on the high-k dielectric layer 225 located on the other side of the groove structure. The first gate stack 233 and the second gate stack 235 are made of different materials. The material of the high-k dielectric layer 225 may include, but is not limited to, BaZrO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, La2O3, Si3N4, oxides of nitride, or other suitable materials. The high-k dielectric layer 225 can be formed using suitable processes such as CVD, ALD, or PVD. The thickness of the high-k dielectric layer 225 can range from 2 nm to 10 nm. By employing high-k metal gate (HKMG) technology, the equivalent oxide thickness (EOT) of the device is reduced, significantly decreasing gate leakage and achieving the high-performance requirement of reduced leakage. In practice, the first gate stack 233 comprises a stacked structure of titanium nitride 227, aluminum oxide 229, and titanium nitride 227, while the second gate stack 235 comprises a stacked structure of lanthanum oxide 231 and titanium nitride 227. Specifically, for example, the second gate stack can be deposited over a high-k dielectric layer, and then the second gate stack above the high-k dielectric layer on the side where the silicon-germanium layer is formed in the trench structure can be removed by mask etching before depositing the first gate stack. In other embodiments, a patterned first mask layer can be used to shield one side. Titanium nitride and aluminum oxide are sequentially deposited over a high-k dielectric layer on the side where the silicon-germanium layer is formed. Then, the first mask layer is removed, and a second mask layer is formed over the aluminum oxide stack. Lanthanum oxide is formed over a high-k dielectric layer on the other side of the groove structure. The second mask layer is then removed, and titanium nitride is deposited simultaneously over the aluminum oxide and lanthanum oxide to form a first gate stack and a second gate stack. By setting different gate stack materials, the performance parameters of the subsequently formed PMOS and NMOS can be controlled, and the work function value of the gate material can be freely set and adjusted to fully control the threshold voltage.

[0083] In some embodiments, as shown in the appendix Figure 2lAs shown, before depositing the high-k dielectric layer 225 on the substrate, the method further includes forming an interface layer 223 (IL) on the surface of the silicon-germanium layer 217 and on the surface of the substrate located on the other side of the groove structure. The interface layer 223 can be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. Suitable processes such as CVD, ALD, or PVD can be used to form the interface layer; for example, it can be formed by high-temperature pure oxygen thermal oxidation. The thickness of the interface layer can range from 0.8 nm to 1.5 nm, for example, 1 nm. The interface layer can increase the adhesion between the high-k dielectric layer and the substrate or silicon-germanium layer and has the function of preventing leakage current.

[0084] In some embodiments, a PMOS (P-type metal-oxide-semiconductor) is formed on one side of the groove structure where the silicon-germanium layer is formed, and an NMOS (N-type metal-oxide-semiconductor) is formed on the other side of the groove structure. In practice, the PMOS can be formed first and then the NMOS, or vice versa. Thus, a CMOS (complementary metal-oxide-semiconductor) integrated circuit is constructed from the PMOS and NMOS. The metal atoms in the PMOS form dipoles at the interface between the high-k dielectric layer and the IL, working together with the SiGe structure as a channel to effectively regulate the threshold voltage of the PMOS. Furthermore, by eliminating the side channel, discontinuities and damage to the channel surface of the device are avoided during the subsequent growth of the high-k dielectric layer and the work function metal, preventing CMOS performance drift and instability.

[0085] This disclosure also provides a semiconductor structure, as shown in the attached figure. Figure 3 As shown, the semiconductor structure includes: a substrate 201, the substrate including a trench structure 203; and an isolation dielectric 204 filling the trench structure 203. The isolation dielectric 204 includes a first isolation layer 205, a second isolation layer 207, and a third isolation layer 209 sequentially covering the bottom surface and sidewalls of the trench structure 203. The upper surface of the isolation dielectric 204 is lower than the upper surface of the substrate 201, and the upper surfaces of the first isolation layer 205 and the second isolation layer 207 are flush. Because the upper surfaces of the first isolation layer 205 and the second isolation layer 207 are flush, there are no side trenches, avoiding the impact of side trenches on the electrical characteristics of the device, and reducing the difficulty of subsequent processes, such as cleaning, metal wiring, and film deposition.

[0086] In some embodiments, the upper surfaces of the first isolation layer 205, the second isolation layer 207, and the third isolation layer 209 are flush. This makes the surface of the isolation dielectric more flat, reducing the process difficulty of subsequent deposition of high-k dielectric layers and gate stacking.

[0087] In some embodiments, as shown in the appendix Figure 3 As shown, the semiconductor structure further includes a silicon-germanium layer 217, which is located on the surface of the substrate on one side of the groove structure 203. The silicon-germanium layer is used to form the channel of the PMOS. The stress mechanism of the silicon-germanium layer has a significant effect on improving the drive current. Due to the stress effect, the silicon-germanium layer can improve the mobility of channel carriers, which is beneficial for adjusting the threshold voltage. In actual operation, the silicon-germanium layer can be selectively grown by epitaxy (EPI).

[0088] In some embodiments, as shown in the appendix Figure 3 As shown, the semiconductor structure further includes an interface layer 223, which is located on the surface of the silicon-germanium layer 217 and on the surface of the substrate on the other side of the groove structure. The interface layer 223 can be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interface layer can be formed using suitable processes such as CVD, ALD, or PVD, for example, by high-temperature pure oxygen thermal oxidation. The thickness of the interface layer can range from 0.8 nm to 1.5 nm, for example, 1 nm. The interface layer can increase the adhesion between the high-k dielectric layer and the substrate or silicon-germanium layer and has the function of preventing leakage current.

[0089] In some embodiments, the semiconductor structure further includes: a PMOS located on one side of the recessed structure, the PMOS having a channel comprising a silicon-germanium layer; and an NMOS located on the other side of the recessed structure. Thus, a CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit is constructed from PMOS and NMOS. The metal atoms in the PMOS form dipoles at the interface between the high-k dielectric layer and the IL layer, working in conjunction with the SiGe structure as a channel to effectively regulate the threshold voltage of the PMOS. Furthermore, by eliminating the side channel, discontinuities and damage to the channel surface of the device are avoided during subsequent high-k dielectric layer growth and work function metal growth, preventing CMOS performance drift and instability.

[0090] In summary, this disclosure eliminates the side trench by etching the third isolation layer to form the protrusion structure of the second isolation layer, and then etching away the protrusion structure, thereby avoiding the side trench from affecting the electrical characteristics of the device, and reducing the process difficulty of subsequent metal wiring and film deposition.

[0091] It should be noted that the semiconductor structure and its formation method provided in this disclosure can be applied to any integrated circuit including this structure. The technical features described in each embodiment can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described formation method steps without departing from the scope of protection of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0092] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a groove structure; A first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the bottom and sidewalls of the groove structure, wherein the upper surface of the first isolation layer is lower than the upper surface of the second isolation layer and the substrate, thereby forming a side trench; The third isolation layer is etched such that the upper surface of the third isolation layer is lower than the upper surface of the second isolation layer, thereby causing the top of the second isolation layer to protrude from the first and third isolation layers to form a raised structure. The second isolation layer is etched to remove the protrusion structure; After forming the first, second, and third isolation layers, the following is also included: A silicon-germanium layer is formed on the surface of the substrate located on one side of the groove structure; After etching the third isolation layer, the process also includes: A protective layer is formed on the surface of the silicon-germanium layer and on the surface of the substrate located on the other side of the groove structure. After etching the second isolation layer, the process also includes: Remove the protective layer.

2. The preparation method according to claim 1, characterized in that, Etching the second isolation layer to remove the protrusion structure includes: The second isolation layer is etched using a wet etching process, wherein the wet etching agent in the wet etching process includes phosphoric acid.

3. The preparation method according to claim 2, characterized in that, The temperature of the wet etching process is controlled between 155 and 165 degrees Celsius.

4. The preparation method according to claim 1, characterized in that, Etching the third isolation layer includes: The third isolation layer is etched using a gas etching process, wherein the gas includes hydrogen and oxygen.

5. The preparation method according to claim 1, characterized in that, Etching the third isolation layer further includes: This makes the upper surface of the third isolation layer flush with the upper surface of the first isolation layer.

6. The preparation method according to claim 1, characterized in that, include: The protective layer was removed using a hydrofluoric acid solution.

7. The preparation method according to claim 1, characterized in that, After removing the protective layer, it also includes: A high-k dielectric layer is deposited on top of the substrate; A first gate stack is formed on a high-k dielectric layer on one side of the groove structure where the silicon-germanium layer is formed, and a second gate stack is formed on a high-k dielectric layer on the other side of the groove structure. The first gate stack and the second gate stack are made of different materials.

8. The preparation method according to claim 7, characterized in that, include: The first gate stack includes a stacked structure of titanium nitride, aluminum oxide and titanium nitride, and the second gate stack includes a stacked structure of lanthanum oxide and titanium nitride.

9. The preparation method according to claim 7, characterized in that, Before depositing a high-k dielectric layer over the substrate, the method further includes: An interface layer is formed on the surface of the silicon-germanium layer and on the surface of the substrate located on the other side of the groove structure.

10. The preparation method according to claim 1, characterized in that, A PMOS is formed on one side of the groove structure where the silicon-germanium layer is formed, and an NMOS is formed on the other side of the groove structure.

11. A semiconductor structure formed by the preparation method according to any one of claims 1-10, characterized in that, include: Substrate, the substrate including a groove structure; An insulating dielectric material is provided, which fills the groove structure. The insulating dielectric material includes a first insulating layer, a second insulating layer, and a third insulating layer sequentially covering the bottom surface and sidewalls of the groove structure. The upper surface of the isolation dielectric is lower than the upper surface of the substrate, and the upper surfaces of the first isolation layer and the second isolation layer are flush.

12. The semiconductor structure according to claim 11, characterized in that, The upper surfaces of the first isolation layer, the second isolation layer, and the third isolation layer are flush.

13. The semiconductor structure according to claim 11, characterized in that, Also includes: A silicon-germanium layer, the silicon-germanium layer being located on the surface of the substrate on one side of the groove structure.

14. The semiconductor structure according to claim 13, characterized in that, Also includes: PMOS, wherein the PMOS is located on one side of the groove structure, and the channel of the PMOS includes a silicon-germanium layer; The NMOS is located on the other side of the groove structure.

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