Redundancy method for multi-chip stacked device

Abstract

Some examples described herein relate to redundancy in a multi-chip stacked device. Examples described herein are multi-chip devices. The multi-chip devices include a chip stack, including vertically stacked chips. Adjacent pairs of chips are directly connected together. Each of the two or more chips includes a processing integrated circuit. The chip stack is configurable to run a functional subset of the processing integrated circuits of the two or more chips when any portion of the processing integrated circuits is defective.

Description

Technical Field

[0001] Examples of the present invention generally relate to redundancy in multi-chip stacking devices that include stacked chips. Background Technology

[0002] In some multi-chip devices, the chips of a Field Programmable Gate Array (FPGA) can be packaged to form a package in which the chips are disposed on a common substrate or interposer. The chips can be bonded side-by-side to the same surface of the interposer. The interposer is typically passive (e.g., does not include active components such as transistors) and includes data paths for connecting the chips to each other.

[0003] Due to manufacturing defects, one or more chips to be incorporated into a multi-chip device may malfunction. In the aforementioned example of the multi-chip device, defective chips can be identified and discarded before being connected to the interposer. In the development techniques of multi-chip stacked devices, in some cases, even if defective chips are identified, they may still be incorporated into the multi-chip stacked device. This leads to a decrease in the yield of the manufactured multi-chip stacked device because any defective chip in the multi-chip stacked device renders the entire multi-chip stacked device defective. Summary of the Invention

[0004] The examples described herein relate to redundancy in multi-chip stacked devices. A multi-chip device can be manufactured according to included device specifications, for example, each chip in the multi-chip device can operate to meet said device specifications. The multi-chip device can be configurable such that it is operable according to another device specification, such as a device specification with fewer but common operable chips (or portions thereof). In such an example, a defective multi-chip device manufactured according to one specification can be restored to operation according to a different specification. Further examples describe techniques for implementing multi-chip devices based on the ability to restore defective devices.

[0005] The example described in this article is a multi-chip device. A multi-chip device includes a chip stack comprising multiple chips stacked vertically. Adjacent chip pairs are directly connected together. Each of two or more chips includes a processing integrated circuit. The chip stack can be configured to operate a functional subset of the processing integrated circuits of two or more chips when any part of the processing integrated circuit is defective.

[0006] Another example described here is a method for implementing the device. The chip stack is configured to operate a functional subset of multiple processing integrated circuits in the event of a defect in any part of the processing integrated circuit. The chip stack comprises vertically stacked chips. Adjacent chip pairs are directly connected together. Each of two or more chips includes a corresponding processing integrated circuit.

[0007] Another example described herein is a multi-chip device. A multi-chip device includes a chip stack comprising chips. Each chip includes an integrated circuit. At least one chip includes an integrated circuit containing a programmable logic region. The chip stack can be configured to operate all of the individual chips in the chip stack, and can also be configured to operate fewer than all of the chips in the chip stack. When the chip stack is configured to operate fewer than all of the chips in the chip stack, at least a portion of the programmable logic region of the programmable logic region of at least one chip having the integrated circuit including the programmable logic region is operable. The chip stack can operate to load and run configuration data, and the configuration data is operable on one or more programmable logic regions of the chip stack. The chip stack can be configured to run the configuration data regardless of which parts of the chips the chip stack is configured to operate.

[0008] Another example described herein is a method for implementing a device. Testing includes a multi-chip device comprising a stack of chips. Each chip includes a processing integrated circuit. The multi-chip device is manufactured according to a first device specification. Based on testing the multi-chip device, it is determined whether the multi-chip device operates according to the first device specification or according to a second device specification different from the first device specification. Based on this determination, the multi-chip device is programmed to operate according to one of the first and second device specifications.

[0009] Another example described herein is a method for implementing a device. A multi-chip stacked device is manufactured according to a first specification. The first specification includes a first number of chips. The first number of chips includes at least one chip that includes an integrated circuit having a programmable logic region. The multi-chip stacked device is tested. The multi-chip stacked device is configured to operate according to either the first specification or a second specification. The second specification includes a second number of chips, fewer than the first number. The second number of chips includes at least one chip that includes an integrated circuit having a programmable logic region.

[0010] A further example described herein is a method for manufacturing devices. A first target number of multi-chip devices to be achieved according to a first specification and a second target number of multi-chip devices to be achieved according to a second specification are obtained. A first manufacturing quantity of multi-chip devices to be manufactured according to the first specification is determined based on the first target quantity and a first expected manufacturing yield according to the first specification. A recovery quantity of expectedly defective multi-chip devices manufactured according to the first specification is determined, these devices being recoverable to at least partially achieve the second target quantity. A second manufacturing quantity of multi-chip devices to be manufactured according to the second specification is determined based on the second target quantity minus the recovery quantity and based on a second expected manufacturing yield according to the second specification. The first manufacturing quantity of multi-chip devices is manufactured according to the first specification. The second manufacturing quantity of multi-chip devices is manufactured according to the second specification.

[0011] A further example described herein is a method for manufacturing devices. Target quantities of multi-chip devices to be realized according to different specifications are determined. This is done iteratively until each target quantity is met: (i) determining the number of multi-chip devices to be manufactured according to a specification having the highest manufacturing cost and a remaining unmet target quantity, and (ii) determining the corresponding expected recoverable quantity of defective multi-chip devices manufactured according to the specification, recoverable to at least partially realize and meet the corresponding target quantities of multi-chip devices for other specifications. The manufacturing quantity is determined based on the unfinished, remaining target quantities manufactured according to the specifications and the expected manufacturing yield. The various manufacturing quantities of multi-chip devices are manufactured according to these specifications. Attached Figure Description

[0012] To gain a more detailed understanding of the features listed above, a more specific description of the invention can be obtained by referring to the example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical exemplary embodiments and should not be considered as limiting the scope of the invention.

[0013] Figure 1 It is based on the structure of some example multi-chip devices; Figure 2 It is formed based on some examples Figure 1 A flowchart of a method for a multi-chip device; Figure 3 This is a schematic diagram illustrating the deactivation of programmable logic regions of chips in a multi-chip device, based on some examples. Figure 4 It is a representation of a multi-chip device specification for multiple examples, which can allow for recovery schemes based on some examples; Figure 5 This is a schematic diagram of a sub-region of the programmable logic region of a multi-chip device, based on some examples of disabling the programmable logic region. Figure 6 This is a schematic diagram of a sub-region of the programmable logic region of a multi-chip device, based on some examples of disabling the programmable logic region. Figure 7 The diagram shows circuit schematics of inter-chip bridges on and between thin strips, based on some examples; Figure 8 This is a flowchart based on some examples of methods for implementing multi-chip devices; Figure 9 This is a flowchart based on some examples of methods for implementing multi-chip devices.

[0014] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is anticipated that a unit in one example can be beneficially incorporated into other examples. Detailed Implementation

[0015] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description or as a limitation on the scope of the claims. Furthermore, the illustrated examples do not need to have all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described.

[0016] The examples described herein relate to redundancy in a multi-chip stacked device. A multi-chip device may include stacked chips. A multi-chip device can be manufactured according to a device specification that includes, for example, each chip in the multi-chip device being operable to meet the device specification. However, as a result of manufacturing, one or more chips in the multi-chip device may be wholly or partially defective. A multi-chip device may be configurable such that it can operate according to another device specification, for example, a device specification with fewer but more common operable chips (or portions thereof). In some examples described herein, an entire chip with defective portions can be deactivated by configuring the multi-chip device. In some examples, the defective portions can be deactivated while other functional portions of the chip are configured to operate by configuring the multi-chip device. In such examples, a defective multi-chip device manufactured according to one specification can be restored to operate according to a different specification.

[0017] Some examples describe techniques for implementing multi-chip devices based on the ability to recover defective devices. As noted, since some multi-chip devices manufactured according to one device specification can be recovered to operate according to another device specification, the number of multi-chip devices that can be recovered to operate according to another device specification can be reduced. Therefore, manufacturing costs can be reduced by reducing the number of multi-chip devices that need to be manufactured according to other device specifications.

[0018] The various examples described herein are described in the context of chips in multi-chip devices having programmable logic regions, such as those used in field-programmable gate arrays (FPGAs). The concepts described herein can be extended to chips in multi-chip devices having any integrated circuits. For example, when multiple chips have processors, memory, or any other circuitry, even if this circuitry can be application-specific integrated circuits (ASICs), redundancy can be implemented. As used herein, a “processing integrated circuit” refers to an integrated circuit that includes circuitry capable of, configured to, and / or configurable to process or operate data, as opposed to memory that merely stores data and any auxiliary memory (e.g., memory controllers, address decoders, etc.). In addition to circuitry capable of, configured to, and / or configurable to process or operate data, a processing integrated circuit may also include memory. Examples of processing integrated circuits include integrated circuits that include programmable logic regions (e.g., FPGAs), processors (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), ASICs, etc., or combinations thereof.

[0019] Figure 1 It is based on the structure of some example multi-chip devices. Figure 1 The multi-chip devices shown are for the purpose of facilitating the description and understanding of the various examples described herein. Various other multi-chip devices may have different structures, different numbers of chips, other components, etc.

[0020] The multi-chip device includes a first chip 102, a second chip 104, a third chip 106, and a fourth chip 108. Typically, chips 102-108 are stacked to form a chip stack in the multi-chip device. In some examples, chips 102-108 are stacked to form an active-on-a-chip (AoA) device. In some examples, such as those described below, more or fewer chips may be included in the chip stack. For example, one or more of the second chip 104 and / or the third chip 106 may be removed or added to the chip stack.

[0021] Each of chips 102-108 includes a semiconductor substrate 112 and a front dielectric layer 114 on the front side of the respective semiconductor substrate 112. The front dielectric layer 114 includes metallization (e.g., metal lines and / or vias) formed therein (shown but not specifically numbered), which can electrically connect various components in an integrated circuit. Each of chips 102-106 includes a back dielectric layer 116 on the back side of the respective semiconductor substrate 112. The back dielectric layer 116 includes metallization structures (e.g., metal lines and / or vias) formed therein (shown but not specifically numbered), which can electrically connect various components in an integrated circuit. Each semiconductor substrate 112 of chips 102-108 includes, for example, a transistor 118 formed on and / or in the front surface of the respective semiconductor substrate 112. The transistor 118 and any other components can be connected to the metallization layer in the front dielectric layer 114. Each semiconductor substrate 112 of each chip 102-106 has a through back substrate via (TSV) 120 that can electrically connect the metallization layer in the front dielectric layer 114 to the metallization layer in the back dielectric layer 116 of the corresponding chip 102-106.

[0022] Front pads 122 are formed in the corresponding front dielectric layers 114 of chips 102-108, at the outer surface remote from the corresponding semiconductor substrate 112. The front pads 122 are connected to the metallization layer of the corresponding front dielectric layer 114. Back pads 124 are formed in the corresponding back dielectric layers 116 of chips 104, 106, at the outer surface remote from the corresponding semiconductor substrate 112. The back pads 124 are connected to the metallization layer in the corresponding back dielectric layer 116.

[0023] Chips 102-108 are bonded together (e.g., using a hybrid bonding method of metal-to-metal and oxide-to-oxide bonding). First chip 102 is bonded to second chip 104 front-to-front, such that the outer surfaces of the front pads 122 and front dielectric layer 114 of first chip 102 are bonded to the outer surfaces of the front pads 122 and front dielectric layer 114 of second chip 104. Second chip 104 is bonded to third chip 106 back-to-front, such that the outer surfaces of the back pads 124 and back dielectric layer 116 of second chip 104 are bonded to the outer surfaces of the front pads 122 and front dielectric layer 114 of third chip 106. Third chip 106 is bonded to fourth chip 108 back-to-front, such that the outer surfaces of the back pads 124 and back dielectric layer 116 of third chip 106 are bonded to the outer surfaces of the front pads 122 and front dielectric layer 114 of fourth chip 108.

[0024] Other bonding methods can be implemented. In other examples, chips 102-108 can be bonded together using external connectors (e.g., microbumps, solder, etc.). In some examples, some of chips 102-108 can be bonded together using external connectors, while others can be bonded together without using external connectors. Any combination of bonding and use of external connectors can be achieved.

[0025] External connector pads 126 (e.g., aluminum pads) are formed in the back dielectric layer 116 of chip 102, on the outer surface of the semiconductor substrate 112 away from chip 102. External connector bonding pads 126 are connected to a metallization layer in the back dielectric layer 116 of chip 102. A passivation layer 128 is formed on the outer surface of the semiconductor substrate 112 away from chip 102, having corresponding openings through which the external connector pads 126 are exposed. External connectors 130 (e.g., controlled collapse chip connections (C4), microbumps, etc.) are formed on the respective external connector pads 126 through the openings in the passivation layer 128.

[0026] External connector 130 can be coupled to a package substrate. The package substrate can be further coupled to, for example, a printed circuit board (PCB) to bond the package substrate (and therefore the multi-chip device) to the PCB. Various other components may be included in the multi-chip device. For example, interposers, sealants (e.g., molding compounds, MUFs, etc.) may be included in the multi-chip device. Various modifications that can be made to the multi-chip device will be readily apparent to those skilled in the art.

[0027] Figure 2 It is formed Figure 1 The flowchart of the method for multi-chip devices 200. Figure 2 The method described herein is general in nature, and those skilled in the art will readily understand the more specific processes that can be performed. More specific processes may include dicing the substrate into chips, depending on any semiconductor processing used to form an integrated circuit on the substrate.

[0028] In block 202, front-side processing is performed on the chips on each substrate (e.g., a wafer). For example, front-side processing of each semiconductor substrate 112 (e.g., a wafer) may include forming devices (e.g., transistors 118) in and / or on the front side of the semiconductor substrate 112, and forming a front-side dielectric layer 114 having a metallization layer and front-side pads 122 on the front surface of the semiconductor substrate 112. A plurality of first chips 102 may be formed on a first substrate. A plurality of second chips 104 may be formed on a second substrate. A plurality of third chips 106 may be formed on a third substrate. A plurality of fourth chips 108 may be formed on a fourth substrate.

[0029] In block 204, the corresponding substrates of the first chip and the second chip (e.g., the first substrate and the second substrate) are bonded, for example, as shown below. Figure 1 The front-to-front bonding is shown. The bonding can be at the substrate (e.g., wafer) layer. The bonding can be a hybrid bonding, such as bonding the front pad 122 of the first substrate to the front pad 122 of the second substrate, and bonding the outer surface of the front dielectric layer 114 of the first substrate to the outer surface of the front dielectric layer 114 of the second substrate.

[0030] In block 206, the semiconductor substrate 112 of the second chip (e.g., the semiconductor substrate 112 of the second substrate) is thinned from the back side. Thinning can be performed by chemical mechanical polishing (CMP) or other suitable processes. In block 208, the second chip on the second substrate undergoes back-side processing. Back-side processing may include forming a back-side TSV 120 through the semiconductor substrate 112 of the second substrate, and a metallization layer connected to the front-side dielectric layer 114 of the second substrate. Back-side processing may also include forming a back-side dielectric layer 116 having a metallization layer and back-side pads 124 on the back side of the semiconductor substrate 112. The metallization layer in the back-side dielectric layer 116 may be connected through the back-side TSV 120 to the metallization layer in the front-side dielectric layer 114 of the second substrate.

[0031] In block 210, the corresponding substrates of the second and third chips are joined (e.g., the second substrate and the third substrate), for example, by joining the back side (of the second substrate) to the front side (of the third substrate), as shown. Figure 1 As shown. The bonding can be at the substrate (e.g., wafer) level. The bonding can be a hybrid bonding, such as bonding the back pad 124 of the second substrate to the front pad 122 of the third substrate, and bonding the outer surface of the back dielectric layer 116 of the second substrate to the outer surface of the front dielectric layer 114 of the third substrate.

[0032] In block 212, the semiconductor substrate 112 of the third chip (e.g., the semiconductor substrate 112 of the third substrate) is thinned from the back side, as in block 206. In block 214, the third chip on the third substrate is back-side processed, as in block 208. In block 216, the corresponding substrates of the third chip and the fourth chip (e.g., the third substrate and the fourth substrate) are bonded, for example, as in... Figure 1 The back side (of the third base) is joined to the front side (of the fourth base), as shown in block 210.

[0033] In block 218, the semiconductor substrate 112 of the first chip (e.g., the semiconductor substrate 112 of the first substrate) is thinned from the back side, as in block 206. In block 220, the first chip on the first substrate is back-side processed, as in block 208. The back-side processing of the first chip may further include forming external connector pads 126, passivation layer 128, and external connector 130. In block 222, the bonded substrate is cut (e.g., by sawing) to separate the individual formed multi-chip devices. Each multi-chip device may be as follows: Figure 1 As shown.

[0034] According to some examples, multiple chips 102-108 have the same integrated circuits (ICs) (e.g., the same processing ICs) formed on the respective chips 102-108. Therefore, in some cases, these multiple chips 102-108 can form a larger set of ICs than each individual chip, and / or in some cases, one or more chips 102-108 can be redundant for device recovery. For example, if the second chip 104, the third chip 106, and the fourth chip 108 have the same ICs, then any one or more of these chips can allow redundancy within a multi-chip device. For example, if one of the multiple chips 102-108 fails, a redundant chip among the multiple chips 102-108 can be used or activated to replace the failed chip, for example, through power gating, switching, and / or configuration data. Furthermore, even if the multiple chips 102-108 do not have the same ICs, the multi-chip device can be configured to operate a subset of the functions of the ICs of the chips 102-108 when any part of those ICs is defective.

[0035] For example, the first chip 102 may have an interconnect IC, and each of chips 104-108 may have the same programmable IC. Each of chips 102-106 includes a TSV (Transient Voltage Supplier) passing through the corresponding semiconductor substrate 112 of chips 102-106 to vertically accommodate boot signals and power supplies in the chip stack. The interconnect IC on the first chip 102 may route and boot signals and power supplies horizontally and then vertically in the chip stack. The interconnect IC may also include various subsystems and may be a system-on-a-chip (SoC). For example, the interconnect IC may include a processing system that can control the configuration or programming of the programmable ICs of chips 104-108 (e.g., through a controller of the processing system, which may include any control logic). In addition, the interconnected ICs can have on-chip networks (NoC), input / output blocks (such as Extreme Performance Input / Output (XPIO), Multi-Gigabit Transceiver (MGT), High Bandwidth Memory (HBM) interfaces, peripheral devices (Fast Component Interconnect (PCIe) interfaces, Cache Coherent Interconnect (CCIX) interfaces for accelerators, Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), etc.) and / or any IP hard cores (such as memory controllers (such as Double Data Rate (DDR) memory controllers, High Bandwidth Memory (HBM) memory controllers, etc.), PCIe blocks, CCIX blocks, Ethernet cores, Forward Error Correction (FEC) blocks, etc.).

[0036] The programmable IC of chips 104-108 may include a programmable logic region. The programmable logic region may include programmable logic elements, including configurable logic blocks (CLBs), lookup tables (LUTs), blocks of random access memory (BRAM), ultra-RAM (URAM), input / output blocks (IOBs), digital signal processing blocks (DSPs), clock managers, and / or delay-locked loops (DLLs). In some architectures, the programmable logic region may include columns of programmable logic elements, where each column includes a single type of programmable logic element (e.g., a CLB column, a BRAM column, etc.). Programmable logic elements may have one or more associated programmable interconnect elements. For example, in some architectures, the programmable logic region includes each column of programmable logic elements associated with it and adjacent columns of programmable interconnect elements. In such examples, each programmable interconnect element is connected to a related programmable logic element in an adjacent column and to an adjacent programmable interconnect element in the same column. The interconnect columns of programmable interconnect elements can form a global routing network within the programmable logic region. In some examples, the programmable IC may include a controller (with boot read-only memory (ROM)) and a NoC. The controller can read the ROM to configure the corresponding programmable IC to a basic configuration that allows the programmable IC to receive configuration data, such as from the interconnect IC of the first chip 102 used for system-level configuration.

[0037] According to some examples, if one or more chips or a portion thereof are defective, a multi-chip device can still be operational by disabling any defective chip or portion thereof and operating the remaining chips or portions. For example, when multiple chips in a multi-chip device each have a programmable logic region, and when any one programmable logic region is defective or faulty, that entire programmable logic region of that chip can be disabled, while the programmable logic region of another chip can operate. In some examples, when multiple chips in a multi-chip device each have a programmable logic region, and when a portion of any programmable logic region is defective or faulty, that portion of that chip's programmable logic region can be disabled, while the programmable logic regions of other chips and the remaining portion of that chip's programmable logic region are operational.

[0038] Figure 3 This is a schematic diagram illustrating the programmable logic regions of chips in a multi-chip device, based on some examples. A first chip 102 includes interconnect 302. A second chip 104, a third chip 106, and a fourth chip 108 each include programmable logic regions 304-1, 304-2, and 304-3 (programmable logic region 304 individually or collectively). Interconnect 302 includes a controller 303 (e.g., a controller for a processing system) and is communicatively connected to each programmable logic region 304 via a programmable interconnect 306 (e.g., a configuration frame (CFRAME) interconnect). For example, controller 303 can transmit configuration data to each of the programmable logic regions 304 via programmable interconnect 306. In some examples, each of chips 102-108, or any subset thereof, may include a controller, such that control communication configuration data can be distributed across the multi-chip device. Each of chips 102-108 is communicatively connected to an adjacent chip via connection 308.

[0039] exist Figure 3 In this example, the programmable logic region 304-2 of the third chip 106 is shown as defective or faulty. In other examples, any programmable logic region 304 may be defective or faulty. In forming multi-chip devices (e.g., Figure 2Following the processing in the first chip 102, the functionality of the multi-chip device can be tested to identify, for example, whether any programmable logic region 304 is defective or faulty. If a sufficient number of programmable logic regions 304 are functional (e.g., without defects or faults), the multi-chip device can operate to include a number of functional programmable logic regions 304. The controller 303 in the first chip 102 may include a memory (e.g., eFuse) that can be programmed to indicate which programmable logic regions 304 are functioning correctly and / or faulty or defective. The controller 303 can responsively distribute configuration data to the functional programmable logic regions 304 via programmable interconnects 306 based on the programmed memory. Furthermore, the controller 303 can be used to implement power gating to reduce or eliminate power to the programmable logic regions 304 and / or the corresponding faulty or defective chips. In this example, the entire defective chip or the entire defective programmable logic region 304 of the chip is deactivated, while the entire functional programmable logic region 304 remains operational.

[0040] In the context of a programmable logic device (e.g., an FPGA) implemented as a multi-chip device, as described, the user design can be implemented in programmable logic region 304. Which programmable logic regions 304 are functional, faulty, or defective is transparent to the user design. For example, in Figure 3 In this context, the multi-chip device can implement a user design in two programmable logic regions 304 (e.g., programmable logic regions 304-1 and 304-3) as if these two programmable logic regions 304 were adjacent in the chip stack of the multi-chip device (e.g., as if the programmable logic regions 304 were in the second chip 104 and the third chip 106, respectively). The controller 303 of the first chip 102 is configured to allocate configuration data for the programmable logic regions 304 to accommodate the intermediate defective programmable logic region 304-2, without the user design needing to know about the intermediate defective programmable logic region 304-2.

[0041] Figure 4 This is a representation of multiple example multi-chip device specifications that allow for recovery schemes based on some examples 400. Figure 4 The illustration shows four device specifications 402, 404, 406, and 408 for a multi-chip device. For ease of description, device specifications 402-408 are shown in a single plane, but can be configured in... Figure 1 In a multi-chip device as generally shown (although there may be different numbers of chips).

[0042] As shown in the figure, device specifications 402-408 include the same base chip 410 in different specifications. For example, the base chip 410 could be... Figure 1The first chip 102, and may include, for example, about Figure 3 The interconnect 302 and controller 303 are described. Device specification 402 includes a single structure chip 412. Structure chip 412 can be... Figure 1 Any one of the second chip 104, the third chip 106, and the fourth chip 108, and may include, for example, regarding Figure 3 The programmable logic region 304 is described. Device specification 404 includes two structure chips 414 and 416. Structure chips 414 and 416 can be... Figure 1 Any one of the second chip 104, the third chip 106, and the fourth chip 108, and each may include, for example, regarding Figure 3 The described programmable logic region 304. Device specification 406 includes three structure chips 418, 420, and 422. Structure chips 418, 420, and 422 can be... Figure 1 Any one of the second chip 104, the third chip 106, and the fourth chip 108, and each may include, for example, regarding Figure 3 The programmable logic region 304 is described. Device specification 408 includes a structure chip 424 and an acceleration chip 426 (e.g., different from structure chip 424). Structure chip 424 may be... Figure 1 Either the second chip 104 or the third chip 106, and may include, for example, regarding Figure 3 The programmable logic region 304 is described. The acceleration chip 426 is physically located above the structural chip 424 in the multi-chip device, and can be... Figure 1 The third chip 106 or the fourth chip 108. Each of the structure chips 412-424 has the same integrated circuit.

[0043] A multi-chip device manufactured according to a given device specification comprises chips of that specification stacked sequentially. For example, a multi-chip device manufactured according to device specification 402 has a first chip (e.g., base chip 410) and a second chip stacked on the first chip (e.g., structural chip 412), with no other chips. For example, a multi-chip device manufactured according to device specification 404 has a first chip (e.g., base chip 410), a second chip stacked on the first chip (e.g., structural chip 414), and a third chip stacked on the second chip (e.g., structural chip 414), with no other chips. As another example, a multi-chip device manufactured according to device specification 406 has a first chip (e.g., base chip 410), a second chip stacked on the first chip (e.g., structural chip 418), a third chip stacked on the second chip (e.g., structural chip 420), and a fourth chip stacked on the third chip (e.g., structural chip 422), with no other chips.

[0044] Assuming a multi-chip device is manufactured according to device specification 408 (e.g., in... Figure 1 In the context of this, the first chip 102 is the base chip 410, the second chip 104 is the structure chip 424, and the third chip 106 is the accelerator chip 426. If the accelerator chip 426 is defective or faulty and cannot function, and the base chip 410 and the structure chip 424 are operable, then the multi-chip device can implement a device specification 402 (e.g., a single-layer programmable logic region or structure) with the base chip 410 and a single structure chip 412.

[0045] Assuming a multi-chip device is manufactured according to device specification 406 (e.g., in... Figure 1 In the context of the above, the first chip 102 is the base chip 410, and the second chip 104, the third chip 106, and the fourth chip 108 are the structure chips 418, 420, and 422, respectively. If one of the structure chips 418, 420, and 422 is defective or faulty and inoperable, and two of the base chip 410 and the structure chips 418, 420, and 422 are operable, then the multi-chip device can implement device specification 404, having a base chip 410 and two structure chips 414 and 416 (e.g., two layers of programmable logic regions or structures). If two of the structure chips 418, 420, and 422 are defective or faulty and inoperable, and one of the base chip 410 and the structure chips 418, 420, and 422 is operable, then the multi-chip device can implement device specification 402, having a base chip 410 and a single structure chip 412 (e.g., a single-layer programmable logic region or structure).

[0046] Assuming a multi-chip device is manufactured according to device specification 404 (e.g., in... Figure 1 In the context of this, the first chip 102 is the base chip 410, while the second chip 104 and the third chip 106 are structural chips 414 and 416, respectively, and there is no fourth chip 108. If one of the structural chips 414 and 416 is defective or faulty and inoperable, and the other of the base chip 410 and structural chips 414 and 416 is operable, then the multi-chip device can implement device specification 402, having a base chip 410 and a single structural chip 412 (e.g., a single-layer programmable logic region or structure).

[0047] The example above illustrates how a multi-chip device manufactured according to one device specification can be implemented or operated according to another device specification when one chip is faulty or defective. A multi-chip device can be configured to logically implement the device specifications that the multi-chip device can satisfy, and this logical configuration is transparent to the user and the user design. For example, if a user design is to be implemented on a multi-chip device that satisfies device specification 404, whether the multi-chip device is manufactured according to device specification 404 or device specification 406 (using one of the fabrication chips 418, 420, 422 being faulty or defective) is unknown and transparent to the user design, and the user design is functionally identical in either case. The logical implementation can be based on configuration data stored in memory in the base chip 410, which determines how the controller in the base chip 410 allocates the configuration data to the corresponding fabrication chips.

[0048] In some examples, the architectures of different multi-chip devices are very similar in terms of connectivity, latency, and power, resulting in nearly identical parameters. This may allow multi-chip devices to have different physical components (e.g., different numbers of chips) to meet the same device specifications. In some examples, multi-chip devices include chip-to-chip connections that allow signals to optionally pass through the chips when not activated, with only minor latency overhead, such as via TSVs. In some examples, multi-chip devices include configuration schemes to optionally send configuration data to different layers. In some examples, multi-chip devices include timing methods to accommodate worst-case latency across any possible inter-chip paths.

[0049] Figure 5 This is a schematic diagram of sub-regions of programmable logic regions in a multi-chip device, based on some examples. A first chip 102 includes an interconnect 502. A second chip 104, a third chip 106, and a fourth chip 108 each include programmable logic regions 504-1, 504-2, and 504-3 (programmable logic region 504, individually or collectively). Interconnect 502 includes a controller 503 (e.g., for a processing system) and is communicatively connected to each programmable logic region 504 via a programmable interconnect 506. For example, controller 503 can transmit configuration data to each programmable logic region 504 via programmable interconnect 506. In some examples, each of chips 102-108, or any subset thereof, may include a controller, such that control of communicating configuration data can be distributed throughout the multi-chip device. Each of chips 102-108 is communicatively connected to an adjacent chip via connection 508.

[0050] Each programmable logic region 504 includes subregions. Programmable logic region 504-1 includes subregions 504-11, 504-12, 504-13, and 504-14. Programmable logic region 504-2 includes subregions 504-21, 504-22, 504-23, and 504-24. Programmable logic region 504-3 includes subregions 504-31, 504-32, 504-33, and 504-34. Subregions can be physically and / or logically partitioned. The partitioning between subregions can be based on any number of logical and / or physical boundaries, such as boundaries between different clock domains, boundaries between different voltage domains, boundaries between different types of circuits or logic blocks, etc. In this example, each subregion can be deactivated when the subregion is faulty and / or when the subregion is selected as not an active subregion in a multi-chip device.

[0051] Each subregion can communicate with other adjacent subregions in adjacent chips via connection 508. Connection 508 can be a passive connection, including, for example, TSVs and metal lines, as well as vias in the front and / or back dielectric layers. Therefore, disabling an intermediate subregion does not affect communication between other subregions via connection 508. In some examples, a subregion may include separate receiving and driving circuitry for relaying signals via connection 508 when a given subregion is disabled. Therefore, in some examples, not all circuitry in a disabled subregion is unusable.

[0052] exist Figure 5 In this example, sub-regions 504-13 and 504-14 of the second chip 104 and sub-region 504-34 of the fourth chip 108 are shown as defective or faulty. In other examples, any sub-region may be defective or faulty. In forming multi-chip devices (e.g., Figure 2 Following the processing in the first chip 102, the functionality of the multi-chip device can be tested to identify, for example, whether any sub-region of the programmable logic region 504 is defective or faulty. If a sufficient number of sub-regions of the programmable logic region 504 are functional (e.g., without defects or faults), the multi-chip device can be operated to include multiple functional sub-regions of the programmable logic region 504. The controller 503 in the first chip 102 may include a memory (e.g., eFuse) that can be programmed to indicate which sub-regions of the programmable logic region 504 are functioning correctly and / or faulty or defective. The controller 503 can responsively distribute configuration data to the functional programmable logic region 304 via a programmable interconnect 506 based on the programmed memory. Additionally, the controller 503 can be used to implement power gating to reduce or eliminate power to faulty or defective sub-regions of the programmable logic region 504.

[0053] exist Figure 5In the example shown, the multi-chip device can be operated to include, for example, two programmable logic regions 504, which can be distributed across chips 104-108. Any number of sub-regions can be operational on any of chips 104-108 to allow the multi-chip device to meet device specifications, such as those mentioned above. Figure 4 The description refers to a finer granularity at the sub-region level. Other granularity levels will be readily understood by those skilled in the art.

[0054] In the context of a programmable logic device (e.g., an FPGA) implemented as a multi-chip device, as described, the user design can be implemented in programmable logic region 504. Which subregions of programmable logic region 504 are functional, faulty, or defective is transparent to the user design. For example, in Figure 5 In this context, a multi-chip device can implement a user design (e.g., using sub-regions 504-11, 504-12, 504-21, 504-22, 504-23, 504-24, 504-31, 504-32) in eight sub-regions (e.g., equivalent to two fully programmable logic regions 504), as if those sub-regions of programmable logic region 504 were adjacent in the chip stack of the multi-chip device. In the example shown, each half of programmable logic regions 504-1 and 504-3, regardless of how the operable sub-regions are aligned (logically or physically), can be implemented to form a logic layer of programmable logic regions. As described, half of programmable logic region 504-1 includes sub-regions 504-11 and 504-12, and half of programmable logic region 504-3 can include any two of sub-regions 504-31 and 504-32. Different numbers of sub-regions of each programmable logic region 504 can be combined to form a layer of programmable logic regions. The controller 503 of the first chip 102 is configured to allocate configuration data for sub-regions of the programmable logic region 504 to accommodate any intermediate defective sub-regions of the programmable logic region 504, while the user design is unaware of the intermediate defective sub-regions of the programmable logic region 504.

[0055] In the above Figure 5 In the description, sub-regions can be implemented to form an integer number of logic units, a complete programmable logic region 504. In other examples, a multi-chip device can implement any combination of partial programmable logic regions 504; for example, implementing an integer number of logic units, a complete programmable logic region 504, is not considered. For example, in Figure 5 In the example shown, the first layer can be implemented as a half-layer including sub-regions 504-11 and 504-12; the second layer can be implemented as a complete layer of programmable logic region 504-2; and the third layer can be implemented as a three-quarter layer including sub-regions 504-31, 504-32, and 504-33.

[0056] Figure 6 This is a schematic diagram of sub-regions of a programmable logic region in a multi-chip device, based on some examples. A first chip 102 includes an interconnect 602. A second chip 104, a third chip 106, and a fourth chip 108 each include programmable logic regions 604-1, 604-2, and 604-3 (programmable logic region 604 individually or collectively). Interconnect 602 includes a controller 603 (e.g., for a processing system) and is communicatively connected to each programmable logic region 604 via a programmable interconnect 606. For example, controller 603 can transmit configuration data to each programmable logic region 604 via programmable interconnect 606. In some examples, each of chips 102-108, or any subset thereof, may include a controller, such that control of communicating configuration data can be distributed throughout the multi-chip device. Each of chips 102-108 is communicatively connected to an adjacent chip via connection 608.

[0057] Each programmable logic region 604 includes sub-regions. Programmable logic region 604-1 includes sub-regions 604-11, 604-12, 604-13, and 604-14. Programmable logic region 604-2 includes sub-regions 604-21, 604-22, 604-23, and 604-24. Programmable logic region 604-3 includes sub-regions 604-31, 604-32, 604-33, and 604-34. Sub-regions can be physically and / or logically partitioned. The partitioning between sub-regions can be based on any number of logical and / or physical boundaries, such as boundaries between different clock domains, boundaries between different voltage domains, boundaries between different types of circuits or logic blocks, etc.

[0058] In this example, individual sub-regions can be deactivated when a sub-region fails and / or when a sub-region is selected as an active sub-region in a multi-chip device. Logically and / or physically aligned sub-regions in chips 104-108 can form stripes. Each sub-region in a strip is identical and / or functionally equivalent to the other sub-regions in that strip. Sub-regions in different strips can have different circuitry and / or functions. During operation, one or more sub-regions of a strip can be deactivated. For example, if a sub-region in a strip fails, that sub-region is deactivated, while the other sub-regions in the strip are activated and operable. Furthermore, for example, if no sub-region in a strip fails, any sub-region in that strip can be selected to be deactivated, while the other sub-regions in the strip are activated and operable.

[0059] In the context of the example shown, the multi-chip device has four stripes. The first stripe includes sub-regions 604-11, 604-21, and 604-31. The second stripe includes sub-regions 604-12, 604-22, and 604-32. The third stripe includes sub-regions 604-13, 604-23, and 604-33. The fourth stripe includes sub-regions 604-14, 604-24, and 604-34. In some examples, the multi-chip device can logically include up to three programmable logic chips (e.g., structure chips) to operate, provided that a sufficient number of sub-regions in each stripe are fault-free. For example, if sub-regions 604-31, 604-13, and 604-14 malfunction and / or become unusable, then sub-regions 604-11 and 604-21 can operate in the first thin strip; sub-regions 604-12 and 604-22 can operate in the second thin strip; sub-regions 604-23 and 604-33 can operate in the third thin strip; and sub-regions 604-24 and 604-34 can operate in the fourth thin strip.

[0060] Each sub-region within the elongated strip can communicate with other sub-regions within the same strip via connection 608. Connection 608 can be a passive connection, including, for example, TSVs and metal lines, as well as vias in the front and / or back dielectric layers. Therefore, deactivating an intermediate sub-region in the elongated strip may not affect communication between other sub-regions in the elongated strip via connection 608. In some examples, sub-regions in the elongated strip may include relay signals via connection 608, which is unaffected when a given sub-region in the elongated strip is deactivated. For example, if sub-region 604-13 is deactivated, the driver and receiver circuitry for connection 608 via sub-region 604-13 remains operational, allowing sub-regions 604-23 and 604-33 to communicate via connection 608. Therefore, in some examples, not all circuitry in deactivated sub-regions is unusable.

[0061] Inter-chip bridges 610 are positioned at the boundaries between sub-regions, enabling each sub-region to selectively communicate with sub-regions in adjacent strips. Via inter-chip bridges 610, each sub-region can communicate with another sub-region located in a strip adjacent to the corresponding sub-region and in the same chip as the corresponding sub-region, or in a chip adjacent to the chip in which the corresponding sub-region is located. For example, via inter-chip bridges 610, sub-region 604-22 in the second strip can communicate with one or more of sub-regions 604-11, 604-21, and 604-31 in the first strip, and via other inter-chip bridges 610, sub-region 604-22 in the second strip can communicate with one or more of sub-regions 604-13, 604-23, and 604-33 in the third strip. In some examples, where a multi-chip device includes multiple redundant physical chips, inter-chip bridges can allow selective communication between sub-regions on a chip and one or more other chips located between the sub-regions.

[0062] As an example, assume that sub-regions 604-31, 604-13, and 604-14 are faulty and / or disabled. Sub-regions 604-11, 604-12, 604-23, and 604-24 can communicate via their respective inter-chip bridges 610 and can operate as first logic chips. Sub-regions 604-21, 604-22, 604-33, and 604-34 can communicate via their respective inter-chip bridges 610 and can operate as second logic chips. In this case, chips 104-108 operate as a multi-chip device with a logic-two structure. These functionalities can be extended to multi-chip devices with different numbers of physical chips and logic chips.

[0063] The inter-chip bridge 610 includes active devices (e.g., transistors) on a corresponding semiconductor substrate of the chip, a TSV in the semiconductor substrate, and a metallization layer in the chip. Those skilled in the art will readily understand the components that can be implemented in the inter-chip bridge 610.

[0064] In some examples, like Figure 6 Inter-chip bridges like the 610 can be used for inter-chip bridges. Figure 5 The above examples are implemented to provide additional connectivity and / or flexibility. Inter-chip bridges can be implemented in, for example... Figure 6 The sub-regions of the programmable logic region 604 in the diagram are shown and described. Figure 5 It is implemented between subregions of the programmable logic region 504 in the programmable logic region.

[0065] Figure 7Circuit diagrams are shown, according to some examples, of inter-chip bridges 610-2, 610-4, 610-6 on chips 104, 106, 108 and between the first and second elongated stripes, respectively. Figure 7 The inter-chip bridge 610 shown is unidirectional (e.g., from the first strip to the second strip). A similar circuit schematic can also be implemented to allow bidirectional communication between the strips (e.g., adding another unidirectional circuit from the second strip to the first strip). Those skilled in the art will readily understand such additions, and any number of circuits can be implemented as the inter-chip bridge 610 to enable communication.

[0066] Each inter-chip bridge 610-2, 610-4, 610-6 (individually or collectively, inter-chip bridge 610) includes a driver 702, tri-state drivers 704, 706, a multiplexer 708, and a driver 710. The input nodes of driver 702 are connected to the output nodes of corresponding sub-regions 604-11, 604-21, 604-31 in the first elongated strip, and serve as inter-chip bridge 610 on the same chips 104-108. The output nodes of driver 702 are connected to the corresponding input nodes of tri-state drivers 704, 706, and multiplexer 708. The respective output nodes of tri-state drivers 704, 706 are connected to a first node 712 and a second node 714, which in turn are connected to the respective input nodes of multiplexer 708. The output node of multiplexer 708 is connected to the input node of driver 710, and the output node of driver 710 is connected to the input nodes of corresponding sub-regions 604-12, 604-22, and 604-32 in the second elongated strip, and also to chips 104-108, which are the same as inter-chip bridge 610. Additionally, a first node 712 in inter-chip bridge 610 is connected, for example, via a TSV of one or two chips to a second node 714 in inter-chip bridge 610 of an adjacent upper chip. For example, a first node 712 in chip 104 is connected to a second node 714 in chip 106, and a first node 712 in chip 106 is connected to a second node 714 in chip 108.

[0067] The tri-state drivers 704 and 706 are controlled by their respective enable signals EN1 and EN2. For example, when enable signals EN1 and EN2 are asserted, the signals at the output nodes of the corresponding tri-state drivers 704 and 706 follow or correspond to the signals at the input nodes of the tri-state drivers 704 and 706, and when the enable signals are deasserted, the impedance at the output nodes of the corresponding tri-state drivers 704 and 706 is in a high-impedance output state. The multiplexer 708 is controlled by the selection signal SEL to output the signal input to the multiplexer 708 at one of its input nodes.

[0068] Different examples illustrating communication with sub-regions 604-22 are described to illustrate different configurations of inter-chip bridge 610. Those skilled in the art will readily understand how these configurations can be applied to other inter-chip bridges 610 and / or for communication between other sub-regions.

[0069] In the first example, sub-region 604-11 communicates with sub-region 604-22. In such an example, sub-region 604-12 can be disabled. Sub-region 604-11 outputs signals (e.g., data) to driver 702 in inter-chip bridge 610-2, and driver 702 outputs signals to tri-state drivers 704 and 706 and multiplexer 708 in inter-chip bridge 610-2. Enable signal EN1 in inter-chip bridge 610-2 causes tri-state driver 704 in inter-chip bridge 610-2 to output a signal at the first node 712 of inter-chip bridge 610-2, thereby to the second node 714 of inter-chip bridge 610-4. Enable signal EN2 in inter-chip bridge 610-2 causes tri-state driver 706 in inter-chip bridge 610-2 to be in a high-impedance output state. The selection signal SEL in the inter-chip bridge 610-2 causes the multiplexer 708 in the inter-chip bridge 610-2 to output a signal at the second node 714 in the inter-chip bridge 610-2. Because the tri-state driver 706 in the inter-chip bridge 610-2 has a high-impedance output state, no signal or signal from the underlying chip can be transmitted to the second node 714 in the inter-chip bridge 610-2, and it can propagate to the sub-region 604-12.

[0070] The enable signal EN2 in inter-chip bridge 610-4 puts the tri-state driver 706 in inter-chip bridge 610-4 into a high-impedance output state. The select signal SEL in inter-chip bridge 610-4 causes the multiplexer 708 in inter-chip bridge 610-4 to output a signal at the second node 714 in inter-chip bridge 610-4. This signal is the signal output from sub-region 604-11 via driver 702 and tri-state driver 704 in inter-chip bridge 610-2. Therefore, the signal output from sub-region 604-11 can propagate to sub-region 604-22.

[0071] In the second example, sub-region 604-21 communicates with sub-region 604-22. Sub-region 604-21 outputs signals (e.g., data) to driver 702 in inter-chip bridge 610-4, and driver 702 outputs signals to tri-state drivers 704 and 706 and multiplexer 708 in inter-chip bridge 610-4. The select signal SEL in inter-chip bridge 610-4 causes multiplexer 708 in inter-chip bridge 610-4 to output the signal from driver 702 in inter-chip bridge 610-4. Therefore, the signal output from sub-region 604-21 can propagate to sub-region 604-22. Enable signals EN1 and EN2 in inter-chip bridge 610-4 can put tri-state drivers 704 and 706 in inter-chip bridge 610-4 into a high-impedance output state. Enable signal EN1 in inter-chip bridge 610-2 can put tri-state driver 704 in inter-chip bridge 610-2 into a high-impedance output state. The enable signal EN2 in the inter-chip bridge 610-6 can put the tri-state driver 706 in the inter-chip bridge 610-6 into a high-impedance output state.

[0072] In the third example, sub-region 604-31 communicates with sub-region 604-22. In such an example, sub-region 604-32 can be disabled. Sub-region 604-31 outputs signals (e.g., data) to driver 702 in inter-chip bridge 610-6, and driver 702 outputs signals to tri-state drivers 704 and 706 and multiplexer 708 in inter-chip bridge 610-6. Enable signal EN1 in inter-chip bridge 610-6 puts tri-state driver 704 in a high-impedance output state. Enable signal EN2 in inter-chip bridge 610-6 causes tri-state driver 706 in inter-chip bridge 610-6 to output a signal at the second node 714 of inter-chip bridge 610-6, thereby reaching the first node 712 of inter-chip bridge 610-4. The selection signal SEL in the inter-chip bridge 610-6 causes the multiplexer 708 in the inter-chip bridge 610-6 to output a signal at the first node 712 in the inter-chip bridge 610-6. Because the tri-state driver 704 in the inter-chip bridge 610-6 has a high-impedance output, no signal or signal from an upper-layer chip can be transmitted at the first node 712 in the inter-chip bridge 610-6; this can propagate to sub-regions 604-32.

[0073] The enable signal EN1 in inter-chip bridge 610-4 puts the tri-state driver 704 in inter-chip bridge 610-4 into a high-impedance output state. The select signal SEL in inter-chip bridge 610-4 causes the multiplexer 708 in inter-chip bridge 610-4 to output a signal at the first node 712 in inter-chip bridge 610-4. This signal is output from sub-region 604-31 via driver 702 and tri-state driver 706 in inter-chip bridge 610-6. Therefore, the signal output from sub-region 604-31 can propagate to sub-region 604-22.

[0074] Data used for enable signals EN1, EN2, and select signal SEL can be stored, for example, in one or more configuration registers, eFuse, and / or other memories on the respective chips 104-108. The inter-chip bridge 610 of each chip 104-108 is configured with the data stored for these signals. Data can be stored after the multi-chip device has been manufactured and tested. Tests can indicate any faulty sub-regions. If sufficient operable sub-regions are preserved in each stripe based on the test results, data can be stored in, for example, configuration registers, eFuse, and / or other memories to appropriately configure the inter-chip bridge 610 to allow communication between operable sub-regions. For example, the eFuse can be cleared to allow data to be written to the eFuse.

[0075] Figure 8 This is a flowchart of a method 800 for implementing a multi-chip device, based on some examples. In block 802, the multi-chip device is manufactured according to device specifications. For example, the multi-chip device can be as described above regarding... Figure 2 It was manufactured as described.

[0076] In block 804, chips in the multi-chip device are tested to identify non-functional programmable logic regions or sub-regions. In block 806, method 800 determines whether sufficient programmable logic regions or sub-regions are operable to meet device specifications. In some examples, block 806 determines to first attempt to determine whether the multi-chip device is operable to meet the most stringent device specifications, and then continues to determine whether the multi-chip device is operable to meet the next less stringent device specifications. For example, refer to... Figure 4 If the multi-chip device is manufactured according to device specification 406, the determination of block 806 first determines whether the multi-chip device is operable to meet device specification 406; if not, the determination of block 806 then determines whether the multi-chip device is operable to meet device specification 404; if not, the determination of block 806 then determines whether the multi-chip device is operable to meet device specification 402. This determination can be performed using programmable logic region-level analysis or sub-region-level analysis as described above.

[0077] If it is determined at block 806 that the multi-chip device is operable to meet device specifications, then at block 808, the multi-chip device is configured to meet the corresponding device specifications. More generally, a multi-chip device (e.g., a chip stack) can be configured to operate a subset of the IC's functionality when any part of the IC is defective. A multi-chip device can also be configured to operate the full functionality of the IC when no part of the IC is defective. The multi-chip device can be configured by programming memory (e.g., eFuse) on any chip. For example, the memory can be programmed in the controller of a processing system (e.g., of the first chip 102) to responsively control the distribution of configuration data within the multi-chip device to configure operable programmable logic regions and / or sub-regions. In some examples, the memory in chips 104-108 can be programmed to configure inter-chip bridges to interconnect sub-regions of programmable logic regions in appropriate layers. The configuration at block 808 can disable any defective or faulty chip (e.g., the entire chip and / or the entire programmable logic region of the chip) or a portion thereof. The configuration of Block 808 can activate the entire functional chip and / or activate the functional parts of the chip.

[0078] If it is determined at block 806 that the multi-chip device cannot operate to meet device specifications, then at block 810, the multi-chip device is discarded or reworked.

[0079] Redundancy in the multi-chip device architecture described herein allows for recovery. Typically, the more chips included in a chip stack of a multi-chip device manufactured to a specific device specification, the lower the yield of such a multi-chip device that can operate according to that device specification. Additional chips often contribute to other defective instances, further reducing yield. The recovery scheme is based on the premise that some multi-chip devices, which may have a certain number of chips in their stack that are defective due to manufacturing processes, can be configured to operate using a smaller number of chips in the stack.

[0080] For example, many multi-chip devices (e.g., having three structure chips 418, 420, 422) can be manufactured according to device specification 406. According to device specification 406, some multi-chip devices in a batch may be defective and inoperable. However, these multi-chip devices may be able to be configured to operate according to device specification 404 (e.g., having two structure chips 414, 416). Furthermore, some defective multi-chip devices manufactured according to device specification 406 may be able to be configured to operate according to device specification 402 (e.g., having one structure chip 412). Therefore, multi-chip devices manufactured according to device specification 406 that are defective and inoperable according to that specification can be recovered and configured to operate according to another device specification 402, 404. By taking into account the ability to recover some defective multi-chip devices in planned manufacturing, fewer multi-chip devices can be manufactured, and / or costs can be reduced.

[0081] Suppose we want to implement 1000 multi-chip devices that operate according to device specification 402, and 1000 multi-chip devices that operate according to device specification 404. Further assume a 90% yield rate for manufacturing device specification 402 and a 50% yield rate for manufacturing device specification 404. Even further assume that each chip has a cost of 1 arbitrary unit (AU), such that a multi-chip device manufactured according to device specification 402 has a cost of 2 AU, and a multi-chip device manufactured according to device specification 404 has a cost of 3 AU.

[0082] If a multi-chip device operable according to device specification 402 is implemented independently of a multi-chip device operable according to device specification 404, then the number of such devices to be manufactured based on yield is a direct calculation result. 1111 multi-chip devices manufactured according to device specification 402 will be manufactured to achieve 1000 multi-chip devices operable according to device specification 402 (e.g., 1111 x 0.9 = 1000), and 2000 multi-chip devices manufactured according to device specification 404 will be manufactured to achieve 1000 multi-chip devices operable according to device specification 404 (e.g., 2000 x 0.5 = 1000). This results in a cost of 8222 AU (e.g., 1111 x 2 + 2000 x 3).

[0083] Costs can be reduced if a larger chip quantity specification, such as device specification 404, is considered separately, while a smaller chip quantity specification, such as device specification 402 in this example, is considered dependent on the larger chip quantity specification. As described above, 2000 multi-chip devices manufactured according to device specification 404 will be produced to achieve 1000 multi-chip devices operable according to device specification 404 (e.g., 2000 x 0.5 = 1000). Clearly, multi-chip devices manufactured according to the smaller chip quantity specification do not affect the number of multi-chip devices usable according to the larger chip quantity specification. Assume that 40% of the defective multi-chip devices manufactured according to device specification 404 can be reconstructed to be operable according to device specification 402. A defective multi-chip device 400 manufactured according to device specification 404 is reconstructed to be operable according to device specification 402 (e.g., 1000 x 0.4 = 400). This results in another 600 multi-chip devices being operable as required by device specification 402. Based on yield, 667 multi-chip devices will be manufactured according to device specification 402 to achieve 600 multi-chip devices that can operate according to device specification 402 (e.g., 667 x 0.9 = 600). In these cases, this results in a cost of 7334 AU (e.g., 2000 x 3 + 667 x 2), a 10.8% reduction from the aforementioned 8222 AU.

[0084] Figure 9 This is a flowchart illustrating a method 900 for implementing a multi-chip device, based on several examples. Example methods 900 are described within the context of device specifications 402, 404, 406, and 408 to provide an illustration of various aspects of method 900. Other example implementations of method 900 may use different device specifications. Furthermore, method 900 may be described below in the context of causing chip defects, and other implementations may be applied to situations where defects may cause a portion or sub-region of the chip to be defective while the rest of the chip remains operational.

[0085] Before describing method 900, we define various variables to simplify the following description: T A It is the target number of multi-chip devices implemented and operated according to device specification A.

[0086] C A It is the cost of a multi-chip device manufactured according to device specification A.

[0087] Y A It is the expected manufacturing yield based on device specification A.

[0088] D AIt is the expected number of defective multi-chip devices manufactured according to device specification A (e.g., D). A = M A x (1- Y A )).

[0089] B|A It is the expected yield of multi-chip devices that can be recovered and operated according to device specification B, which are defective devices manufactured according to device specification A.

[0090] R B|A This refers to the number of multi-chip devices that are expected to be recoverable and operational according to device specification B, which are defective devices manufactured according to device specification A (e.g., R...). B|A = D A x B|A ).

[0091] U B Is it to reach T B The estimated number of remaining multi-chip devices, i.e., U B =T B – (M B x Y B ) – .

[0092] M B The number of multi-chip devices to be manufactured is determined based on device specification B (e.g., M). B = U B / Y B ).

[0093] Each M A All are initialized to zero.

[0094] In block 902, identify the target number of different multi-chip devices to be implemented corresponding to the device specifications. For example, the target numbers are listed below, where the subscript indicates which of device specifications 402, 404, 406, and 408 corresponds to the target number. Initially, U A Set to equal T A .

[0095] T 402 = U 402 = 1000 T 404 = U 404 = 1000 T 406 = U 406 = 1000 T 408= U 408 = 1000 It is obvious that these target quantities can be achieved by manufacturing multi-chip devices according to one device specification and by manufacturing multi-chip devices according to another device specification, which can be restored to operation according to the corresponding device specification.

[0096] In block 904, the expected yield rate is determined based on the device specifications. For example, the expected yield rate is listed below: Y 402 = 90% Y 404 = 50% Y 406 = 30% Y 408 = 40% In block 906, based on the corresponding expected yield, determine the number of multi-chip devices to be manufactured according to the remaining highest-cost device specification to achieve the target quantity required for that device specification. For illustrative purposes, the cost of manufacturing the multi-chip device is listed below: C 402 = 2 AU C 404 = 3 AU C 406 = 4 AU C 408 = 3.2 AU In the described method 900, it is assumed that increasing the number of chips typically leads to increased costs and reduced yield. In other example implementations, alternative costs or other considerations besides cost may be considered to determine the order in which device specifications are analyzed in block 906 and subsequent steps to determine the number of multi-chip devices to be manufactured for the corresponding device specifications.

[0097] Under these assumptions, the highest remaining cost device specification in the first instance of block 906 is device specification 406. According to device specification 406 (e.g., denoted as M...), 406 The number of devices to be manufactured is 3333 (e.g., M). 406 x Y 406 = U 406 == 3333 x 0.3 = 1000). Therefore, the target number of multi-chip devices implemented and operated according to device specification 406 can be achieved by manufacturing 3333 multi-chip devices according to device specification 406.

[0098] In block 908, based on the remaining highest-cost device specifications, several manufactured multi-chip devices are identified as expected to be defective and can be reverted to multi-chip devices that can operate according to another device specification to at least partially meet the target quantity of other device specifications to be achieved. Continuing the example, the expected yield of multi-chip devices reverted and operated according to device specifications that are defective devices manufactured according to another specification is listed below.

[0099] 402|406 = 20% 404|406 = 10% 408|406 = 0% Please note that in this example, defective multi-chip devices manufactured according to device specification 406 cannot be restored to operate according to device specification 408 because such defective multi-chip devices were not manufactured to include accelerator chip 426.

[0100] Under the above assumptions and conditions, the various determined quantities are summarized as follows by passing through blocks 906 and 908 for the first time.

[0101] M 406 = U 406 / Y 406 = 1000 / 0.3 = 3333 D 406 = M 406 x (1 - Y 406 = 3333 x (1 – 0.3) = 2333 R 402|406 = D 406 x 402|406 = 2333 x 0.2 = 466 R 404|406 = D 406 x 404|406 = 2333 x 0.1 = 233 R 408|406 = D 406 x 408|406 = 2333 x 0 = 0 U 402 =T 402 – (M 402 x Y 402 ) – = 1000 – (0 x 0.9) – 466 = 534 U 404 =T 404 – (M 404 x Y 404 ) – = 1000 – (0 x 0.5) – 233 = 767 U 406 =T 406 – (M 406 x Y 406 ) – = 1000 – (3333 x 0.3) – 0 = 0 U 408 =T 408 – (M 408 x Y 408 ) – = 1000 – (0 x 0.4) – 0 = 1000 In block 910, it is determined whether the target number of different multi-chip devices has been met. If not, method 900 loops back to block 906 and iteratively executes blocks 906 and 908 until the target number of different multi-chip devices has been met. In the example shown, method 900 loops back to block 906 through the execution of block 910 until U 402 = U 404 = U 406 =U 408 = 0. If the determination in block 910 already satisfies the target number of different multi-chip devices, then in block 912, different multi-chip devices are manufactured based on the determined number of multi-chip devices to be manufactured. In the example shown, the determined M 402 M 404 M 406 and M 408 They are manufactured according to their respective device specifications 402, 404, 406, and 408. Manufacturing according to device specifications can, for example, be achieved through... Figure 2 Method 200 is used. Any defective multi-chip device is configured to operate according to another device specification, such as regarding Figure 8 The method described in 800.

[0102] In the described example, the target number is still not achieved after the first passage of blocks 906 and 908 (e.g., U). 402 U 404 and U 408(Not zero). Therefore, the second iteration of blocks 906 and 908 is performed, and the resulting determinations and assumptions are as follows. The remaining highest cost specification is device specification 408.

[0103] 402|408 = 10% 404|408 = 0% Please note that in this example, defective multi-chip devices manufactured according to device specification 408 cannot be restored to operate according to device specification 404 because such defective multi-chip devices were not manufactured to include two structural chips 414, 416.

[0104] M 408 = U 408 / Y 408 = 1000 / 0.4 = 250 D 408 = M 408 x (1 - Y 408 = 2500 x (1 – 0.4) = 150 R 402|408 = D 408 x 402|408 = 1500 x 0.1 = 150 R 404|408 = D 408 x 404|408 = 1500 x 0 = 0 U 402 =T 402 – (M 402 x Y 402 ) – = 1000 – (0 x 0.9) – (466 + 150) =384 U 404 =T 404 – (M 404 x Y 404 ) – = 1000 – (0 x 0.5) – (233 + 0) = 767 U 406 =T 406 – (M 406 x Y 406 ) – = 1000 – (3333 x 0.3) – 0 = 0 U 408 =T 408 – (M 408 x Y 408 ) – = 1000 – (2500 x 0.4) – 0 = 0 In the described example, the target number is still not achieved after the second pass of blocks 906 and 908 (e.g., U402 and U404 are not zero). Therefore, a third iteration of blocks 906 and 908 is performed, and the resulting determinations and assumptions are as follows. The remaining highest cost specification is device specification 404.

[0105] 402|404 = 10% M 404 = U 404 / Y 404 = 767 / 0.5 = 1534 D 404 = M 404 x (1 - Y 404 = 1534 x (1 – 0.5) = 767 R 402|404 = D 404 x 402|404 = 767 x 0.1 = 76 U 402 =T 402 – (M 402 x Y 402 ) – = 1000 – (0 x 0.9) – (466 + 150 + 76) = 308 U 404 =T 404 – (M 404 x Y 404 ) – = 1000 – (1534 x 0.5) – (233 + 0) = 0 U 406 =T 406 – (M 406 x Y 406 ) – = 1000 – (3333 x 0.3) – 0 = 0 U408 =T 408 – (M 408 x Y 408 ) – = 1000 – (2500 x 0.4) – 0 = 0 In the described example, the target number was still not achieved after the third pass of blocks 906 and 908 (e.g., U402 is not zero). Therefore, a fourth iteration of blocks 906 and 908 was performed, and the resulting determinations and assumptions are explained below. The remaining highest cost specification is device specification 404.

[0106] M 402 = U 402 / Y 402 = 308 / 0.9 = 342 U 402 =T 402 – (M 402 x Y 402 ) – = 1000 – (342 x 0.9) – (466 + 150 +76) = 0 U 404 =T 404 – (M 404 x Y 404 ) – = 1000 – (1534 x 0.5) – (233 + 0) = 0 U 406 =T 406 – (M 406 x Y 406 ) – = 1000 – (3333 x 0.3) – 0 = 0 U 408 =T 408 – (M 408 x Y 408 ) – = 1000 – (2500 x 0.4) – 0 = 0 In the described example, after the fourth pass of blocks 906 and 908, the target quantity was met, and the corresponding number of multi-chip devices to be manufactured were produced according to the device specifications. These numbers are listed below: M 402 = 342 M 404 = 1534 M406 = 3333 M 408 = 2500 Therefore, in the described example, for device specification 408, the target number of multi-chip devices to be implemented and operational according to the device specification (e.g., 1000) can be achieved by manufacturing the number of multi-chip devices determined to be manufactured (e.g., 2500) given an expected manufacturing yield (e.g., 40%). For device specification 406, the target number of multi-chip devices to be implemented and operational according to the device specification (e.g., 1000) can be achieved by manufacturing the number of multi-chip devices determined to be manufactured (e.g., 3333) given an expected manufacturing yield (e.g., 30%). For device specification 404, the target number of multi-chip devices to be realized and operational according to the device specification (e.g., 1000) can be determined by manufacturing the number of multi-chip devices to be manufactured (e.g., 1534) under a given manufacturing expected yield (e.g., 50%), and can be achieved by recovering multiple defective multi-chip devices manufactured according to device specification 408 (e.g., 150), multiple defective multi-chip devices manufactured according to device specification 406 (e.g., 466), and multiple defective multi-chip devices manufactured according to device specification 404 (e.g., 76). For device specification 402, the target number of multi-chip devices to be manufactured (e.g., 1000) based on the specification and the number of operable multi-chip devices, under a given manufacturing expected yield (e.g., 90%), can be determined by manufacturing (e.g., 342), and this is achieved by recovering the number of defective multi-chip devices manufactured according to device specification 408 (e.g., 150), the number of defective multi-chip devices manufactured according to device specification 406 (e.g., 466), and the number of defective multi-chip devices manufactured according to device specification 404 (e.g., 76).

[0107] By using the disclosed recovery scheme, many manufactured multi-chip devices can be recovered. Other examples can have any number of device specifications, can use any recovery mechanism, and can have any number of devices to be implemented. The foregoing examples are described to illustrate the described method more clearly.

[0108] Examples include multi-chip devices comprising a chip stack comprising a plurality of chips stacked vertically. Adjacent chip pairs are directly connected together. Each chip includes a first chip that includes a controller and memory. The plurality of chips includes two or more second chips located above the first chip in the chip stack, and each of the two or more second chips includes a processing integrated circuit. The chip stack is configurable to operate a functional subset of the processing integrated circuit of the two or more second chips when any part of the processing integrated circuit is defective. The memory is operable to store configuration information relating to the operability of the processing integrated circuit. The controller is communicatively connected to the processing integrated circuit and operable to assign configuration data to the processing integrated circuit based on the configuration information to enable operation of at least a functional subset.

[0109] In the example multi-chip device above, each processing integrated circuit may include a programmable logic region, and the chip stack may be configured to operate the corresponding whole of the programmable logic regions of fewer than two or more second chips, and to deactivate the corresponding whole of the programmable logic regions of at least one of the two or more second chips.

[0110] In the example multi-chip device above, each processing integrated circuit may include a programmable logic region, and the chip stack may be configured to operate and deactivate any sub-region of the programmable logic region of two or more second chips. Further, in the example multi-chip device above, the sub-regions of the programmable logic region of two or more second chips may be arranged in elongated strips, and each elongated strip may include a sub-region of the programmable logic region of each of the two or more second chips. Two or more second chips may each include an inter-chip bridge, and each inter-chip bridge may connect (i) sub-regions of the programmable logic region in adjacent elongated strips and (ii) adjacent chips, or sub-regions of the programmable logic region in the same chip.

[0111] In the example multi-chip device above, the controller is operable to load configuration data, and the configuration data is operable on one or more processing integrated circuits. The chip stack can be configured to run the configuration data, regardless of which parts of the processing integrated circuits on the chip stack are configured to operate.

[0112] In the multi-chip device of the above example, at least one of the two or more second chip processing integrated circuits may be different from at least one of the two or more second chip processing integrated circuits.

[0113] In the above example of a multi-chip device, two or more processing integrated circuits of two or more second chips are the same processing integrated circuit.

[0114] Another example includes a method for implementing the apparatus. A controller configures a chip stack to run a functional subset of multiple processing integrated circuits. The chip stack comprises multiple chips stacked vertically. Adjacent chip pairs are directly connected together. The chip includes a first chip and two or more second chips located above the first chip. The first chip includes a controller and memory. Each of the two or more second chips includes a corresponding one of the multiple processing integrated circuits. The controller configures which or those portions of the multiple processing integrated circuits to run the functional subset based on configuration information stored in the memory.

[0115] In the example method above, configuring the chip stack may include a corresponding overall configuration of the chip stack to operate programmable logic regions of fewer than two or more second chips, and a corresponding overall deactivation of programmable logic regions of at least one of the two or more second chips. Each processing integrated circuit includes a programmable logic region.

[0116] In the example method above, configuring the chip stack may include any sub-regions of configuring the chip stack to operate programmable logic regions of two or more second chips, and any sub-regions of deactivating programmable logic regions of two or more second chips, each processing integrated circuit including a programmable logic region. Further, in the example method above, the sub-regions of the programmable logic regions of two or more second chips may be arranged in elongated strips, and each elongated strip may include a sub-region of the programmable logic region of each of the two or more second chips. The two or more second chips may each include an inter-chip bridge, and each inter-chip bridge may connect (i) sub-regions of programmable logic regions in adjacent elongated strips and (ii) sub-regions of programmable logic regions in adjacent chips or the same chip. Configuring the chip stack may include configuring inter-chip bridges.

[0117] In the above example method, at least one of the multiple processing integrated circuits of two or more second chips may be different from at least one of the other multiple processing integrated circuits of two or more second chips.

[0118] In the example method described above, the two or more processing integrated circuits of the two or more second chips can be the same processing integrated circuit.

[0119] Another example includes a multi-chip device comprising a chip stack having stacked chips having adjacent pairs of chips bonded together. The chip stack includes a first chip and two or more second chips stacked on the first chip. The first chip includes a controller and a memory. Each of the two or more second chips includes a processing integrated circuit. The memory is operable to store configuration information indicating any defective portions of the processing integrated circuit. The controller is communicatively connected to the processing integrated circuit and operable to allocate configuration data to non-defective portions of the processing integrated circuit based on the configuration information, thereby enabling operation of at least a functional subset of the processing integrated circuits of the two or more chips. The chip stack is configurable to operate a functional subset of the processing integrated circuits of the two or more second chips when any portion of the processing integrated circuit is defective.

[0120] In the example multi-chip device above, each processing integrated circuit includes a programmable logic region.

[0121] Another example is a method for implementing a device. Testing involves a multi-chip device comprising a stack of chips. Each chip includes a processing integrated circuit. The multi-chip device is manufactured according to a first device specification. Based on testing the multi-chip device, it is determined whether the multi-chip device can operate according to the first device specification or a second device specification different from the first device specification. Based on this determination, the multi-chip device is programmed to operate according to one of the first and second device specifications.

[0122] In the example method described above, programming a multi-chip device may include disabling at least a portion of at least one chip.

[0123] In the above example method, two or more chips may include the same processing integrated circuit, which includes programmable logic regions, and programming the multi-chip device may include configuring the multi-chip device to be operable by using at least one complete programmable logic region and deactivating at least a portion of at least one programmable logic region.

[0124] In the above example method, two or more chips may include the same processing integrated circuit, which includes a programmable logic region, and programming the multi-chip device may include configuring the multi-chip device to be operable by using the entire programmable logic region of at least one chip and deactivating the entire programmable logic region of at least one chip.

[0125] In the above example method, two or more chips may include the same integrated circuit, which includes programmable logic regions, and programming the multi-chip device may include configuring the multi-chip device to operate using at least a portion of the programmable logic regions in the chips, and deactivating at least a portion of the programmable logic regions of at least one chip including the same integrated circuit.

[0126] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of the systems and methods according to various examples. In other embodiments, the functions marked in the blocks may not appear in the order indicated in the figures. For example, two blocks displayed consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. Although the foregoing is directed to specific examples, other further examples can be designed without departing from its basic scope, the scope of which is determined by the appended claims.

Claims

1. A multi-chip device, characterized in that, The multi-chip device includes: A chip stack comprising multiple vertically stacked chips, wherein: Adjacent chip pairs are directly connected together; The plurality of chips includes a first chip, which includes a controller and a memory; The plurality of chips includes two or more second chips above the first chip in the chip stack, each of the two or more second chips including a processing integrated circuit, each of the processing integrated circuits including a programmable logic region, wherein sub-regions of the programmable logic regions of the two or more second chips are arranged in elongated strips, each elongated strip including a sub-region of the programmable logic region of each of the two or more second chips, and each sub-region of a corresponding elongated strip in the plurality of elongated strips is identical and / or functionally equivalent to each other; The chip stack is configurable based on configuration data to operate a subset of the functionality of the processing integrated circuit of the two or more second chips when any part of the processing integrated circuit is defective. A memory, operable to store configuration information relating to the operability of the processing integrated circuit; and A controller, communicatively connected to the processing integrated circuit and operable to allocate configuration data to the processing integrated circuit based on the configuration information, thereby enabling operation of at least the subset of functions.

2. The multi-chip device according to claim 1, characterized in that, Each of the processing integrated circuits includes a programmable logic region; and The chip stack can be configured to operate a corresponding whole of programmable logic regions of fewer than the two or more second chips, and a corresponding whole of programmable logic regions of at least one of the two or more second chips being disabled.

3. The multi-chip device according to claim 1, characterized in that, The chip stack can be configured to operate any sub-region of the programmable logic region of the two or more second chips, and to disable any sub-region of the programmable logic region of the two or more second chips.

4. The multi-chip device according to claim 3, characterized in that, Each of the two or more second chips includes an inter-chip bridge, each of the inter-chip bridges connecting (i) sub-regions of a programmable logic region in an adjacent strip and (ii) in an adjacent chip, or between sub-regions of a programmable logic region in the same chip.

5. The multi-chip device according to claim 1, characterized in that, The controller is operable to load configuration data, which is operable on one or more of the processing integrated circuits; and The chip stack can be configured to run configuration data, regardless of which parts of the processing integrated circuits in the chip stack are configured to run.

6. The multi-chip device according to claim 1, characterized in that, At least one of the processing integrated circuits of the two or more second chips is different from at least one of the processing integrated circuits of the two or more second chips.

7. The multi-chip device according to claim 1, characterized in that, The two or more processing integrated circuits of the two or more second chips are the same processing integrated circuits.

8. A method for implementing the apparatus, characterized in that, The method includes: When any part of the plurality of processing integrated circuits is defective, the controller uses configuration data to configure a chip stack to operate a functional subset of the plurality of processing integrated circuits. Configuring the chip stack includes configuring the chip stack to operate any sub-region of the programmable logic region of two or more second chips, and deactivating any sub-region of the programmable logic region of the two or more second chips. The chip stack comprises a plurality of vertically stacked chips, with adjacent chip pairs directly connected together. The chip stack includes a first chip and two or more second chips located above the first chip. The first chip includes a controller and a memory. Each of the two or more second chips includes a corresponding one of the plurality of processing integrated circuits. The memory stores configuration information relating to the operability of the processing integrated circuits. Configuring the chip stack includes allocating configuration data from the controller to the plurality of processing integrated circuits based on the configuration information stored in the memory. The sub-regions of the programmable logic region of the two or more second chips are arranged in strips, each strip including a sub-region of the programmable logic region of each of the two or more second chips, and each sub-region of a corresponding strip in the plurality of strips is identical and / or functionally equivalent to each other.

9. The method according to claim 8, characterized in that, Configuring the chip stack includes configuring the chip stack to operate a corresponding overall programmable logic region of fewer than the two or more second chips, and disabling a corresponding overall programmable logic region of at least one of the two or more second chips, each of the processing integrated circuits including a programmable logic region.

10. The method according to claim 8, characterized in that, Each of the processing integrated circuits includes a programmable logic region.

11. The method according to claim 10, characterized in that, Each of the two or more second chips includes an inter-chip bridge, each of the inter-chip bridges connecting (i) a sub-region of a programmable logic region in an adjacent strip and (ii) a sub-region of a programmable logic region in an adjacent chip, or connecting a sub-region of a programmable logic region in the same chip, wherein configuring the chip stack includes configuring the inter-chip bridges.

12. The method according to claim 8, characterized in that, At least one of the plurality of processing integrated circuits of the two or more second chips is different from at least one other of the plurality of processing integrated circuits of the two or more second chips.

13. The method according to claim 8, characterized in that, The two or more processing integrated circuits of the two or more second chips are the same processing integrated circuits.

14. A multi-chip device, characterized in that, The multi-chip device includes: A chip stack comprising a plurality of stacked chips, the plurality of stacked chips including adjacent chip pairs joined together, wherein: The plurality of chips includes a first chip and two or more second chips stacked on the first chip; The first chip includes a controller and a memory; Each of the two or more second chips includes a processing integrated circuit, each processing integrated circuit including a programmable logic region, wherein sub-regions of the programmable logic regions of the two or more second chips are arranged in an elongated strip, each elongated strip including a sub-region of the programmable logic region of each of the two or more second chips, and each sub-region of a corresponding elongated strip in the plurality of elongated strips is identical and / or functionally equivalent to each other. A memory operable to store configuration information indicating any defective portions of the processing integrated circuit; A controller, communicatively connected to the processing integrated circuit and operable to allocate configuration data to a defect-free portion of the processing integrated circuit based on the configuration information, thereby enabling the operation of at least a functional subset of the processing integrated circuit of the two or more second chips; and The chip stack can be configured based on the configuration data to operate a functional subset of the processing integrated circuit of the two or more second chips when any part of the processing integrated circuit is defective.

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