Two-stage cache interconnection structure based on flexible conversion of multi-bus protocol

Abstract

The application relates to a two-stage cache interconnection structure based on flexible conversion of a multi-bus protocol, which is composed of a reset management unit, a bus protocol conversion unit, a read request processing unit, a write request processing unit, a listening request processing unit and a programmable arbitration unit. Each processor core has a separate interconnection unit to realize interconnection communication with a two-stage cache, and can simultaneously receive requests sent by each core. The reset management unit can realize automatic refreshing of the two-stage cache after reset. The bus protocol conversion unit can realize conversion between different protocols of a processor core interface and a two-stage cache interface. The read request processing unit and the write request processing unit respectively classify and process read operation and write operation, and the listening request processing unit realizes processing of listening request information between the two-stage caches. The programmable arbitration unit realizes transmission of read-write and listening information between each processor core and the two-stage cache according to different arbitration configurations.

Description

Technical Field

[0001] This invention relates to the field of multi-core processor design technology, and to a two-level cache interconnect structure, particularly a connection method suitable for multiple processor cores to share a two-level cache with different bus interfaces. Background Technology

[0002] Currently, multi-core processors have replaced single-core processors as the main research direction for improving overall system performance, and the methods for improving processor performance have also shifted from instruction-level parallelism to thread-level parallelism. In processor architectures that apply thread-level parallelism, shared memory has significant advantages and is widely used.

[0003] Compared to traditional private storage structures, a secondary storage system shared by multiple processor cores can significantly reduce the cost of L1 cache misses, provide an effective low-latency, high-bandwidth communication mechanism, and provide the operating system with a global address space so that multi-process applications can run in parallel in the shared storage space.

[0004] In current multi-core processor architectures with shared memory, the L2 cache interface must conform to the same bus protocol as the processor core bus interface. In particular, when processors with a bus interface conforming to the serial bus protocol design multi-core shared L2 cache structures, they often use a method of connecting the L2 cache with the same protocol interface through the slave interface of the serial bus connected to the processor master. This connection method is similar to connecting the L2 cache module as an external device. Due to the sequential execution characteristics of the serial bus and the fact that multiple processor cores share the same L2 cache device interface on a single bus, when multiple cores access the shared L2 memory space at the same time, bus arbitration is required. The processor core that does not obtain the right to use the bus has to wait for a long clock cycle before it can access the L2 cache. This connection method cannot fully utilize the parallel operation characteristics of multi-core processors, thus limiting the improvement of the overall system speed. Summary of the Invention

[0005] The technical problem solved by this invention is to overcome the above-mentioned defects of existing connection methods and provide a two-level cache interconnect structure based on flexible conversion of multiple bus protocols. Through the flexible conversion design between the processor bus interface and the secondary cache bus interface, this interconnect structure can not only realize the connection between two-level caches with different interfaces, but also support multiple serial interface processor cores to access the shared secondary cache space simultaneously, thereby improving the response speed of processor core read and write access and improving the memory access performance of multi-core processor systems.

[0006] The technical solution of this invention is: a two-level cache interconnection structure based on flexible conversion of multiple bus protocols, the interconnection structure including a programmable arbitration unit and N interconnection units; N is greater than or equal to 1;

[0007] Each processor core has its own L1 cache and bus interface. The L1 cache communicates with the outside world through the bus interface. N processor cores share a L2 cache. The L2 cache includes at least one interface module that communicates with a programmable arbitration unit. There is a one-to-one correspondence between processor cores and interconnect units.

[0008] The interconnect unit is used to implement protocol conversion between the processor core bus interface and the L2 cache interface. It receives read and write request information from the processor core, generates L2 read request signals and L2 write request signals for the L2 cache, and sends them to the programmable arbitration unit; it receives listen requests from the programmable arbitration unit, generates listen request signals and sends them to the processor core; and it receives response signals from the L2 cache and feeds them back to the processor core.

[0009] The programmable arbitration unit arbitrates the L2 read request signals or L2 write request signals sent by each interconnect unit according to the number of L2 cache ports, ensuring that only one processor core accesses each L2 cache port at any given time; it feeds back the response signals sent by the L2 cache ports to the corresponding interconnect unit; and it receives the listen requests sent by the L2 cache and sends them to the interconnect unit.

[0010] The aforementioned two-level cache interconnect structure based on flexible switching of multiple bus protocols also includes a reset management unit;

[0011] The reset management unit receives an externally input reset signal. After the reset signal is released, it sends a refresh command to the L2 cache, causing all remaining data in the L2 cache to be marked as invalid after the reset.

[0012] Preferably, the interconnection unit includes a bus protocol conversion unit, a read request processing unit, and a write request processing unit;

[0013] The bus protocol conversion unit parses the processor core bus interface signals according to the processor core's interface protocol, decomposes them into read request information or write request information, and generates secondary read request information and secondary write request information according to the secondary cache's interface protocol. The secondary read request information is sent to the read request processing unit, and the secondary write request information is sent to the write request processing unit. The secondary read request information includes the read operation request type, request address, and data size; the secondary write request information includes the write operation request type, request address, data size, data to be written, and valid bytes.

[0014] The read request processing unit identifies the request type of the read operation in the secondary read request information, generates corresponding attribute values ​​for different request types, assigns a unique read request ID to the secondary read request information, and sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol.

[0015] The write request processing unit extracts the address, data to be written, data size, and valid bytes from the secondary write request information; identifies the request type of the write operation, generates corresponding attribute values ​​for different request types, and represents them using attribute signals; assigns a unique write request ID to the secondary write request information; stores the write request ID, address, type, attribute, and data size in the address buffer; writes the write request ID, data to be written, and valid bytes in the data buffer; and sends the secondary write request information, its attribute signals, and the write request ID signal to the programmable arbitration unit according to the secondary cache interface protocol.

[0016] Preferably, the read request processing unit includes a read request type identification module, a read request signal generation module, an ID management module, and a read response signal processing module;

[0017] The read request type identification module parses the secondary read request information, identifies the request type of the read operation issued by the processor core, generates corresponding attribute values ​​for different request types, and sends them to the read request signal generation module.

[0018] The read request signal generation module sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol;

[0019] The ID management module assigns different read request IDs to the secondary read request information and sends them to the read request signal generation module. It receives the read response identification number from the read response information returned by the secondary cache, determines whether the read request ID in the read request information matches the read response identification number, and sends a matching success signal to the read response signal processing module.

[0020] The read response signal processing module receives read response information returned by the secondary cache; the read response information includes a read response identification number, returned data, a data return completion signal, and a read response type; it receives a matching success signal from the ID management module; and it returns the returned data and response type to the bus protocol conversion unit.

[0021] Preferably, the write request processing unit includes a write request type identification module, a write request signal generation module, an ID management module, a write request buffer, and a write response signal processing module;

[0022] The write request type identification module extracts the request type, address, data to be written, data size, and valid bytes from the secondary write request information. Then, it sends an ID request message to the ID management module and sends the write request information to the write request signal generation module.

[0023] The write request signal generation module receives the secondary write request information and generates corresponding attributes for different request types. Based on the address of the data to be written, it sets the secondary write request information to match the bit width of the secondary cache data interface. It then sends the secondary write request information, attributes, and the request ID generated by the ID management module to the write request buffer. Afterward, it sends a write request arrival identifier signal to the write response signal processing module. Finally, it extracts the address, type, attributes, data size, data to be written, and valid bytes corresponding to the same write request ID from the write request buffer and sends them to the programmable arbitration module according to the secondary cache interface protocol.

[0024] After receiving the ID request message, the ID management module assigns a unique write request ID to the secondary write request information and sends the write request ID to the write request buffer and the write request signal generation module; it receives the write response identification number from the write response information returned by the secondary cache, determines whether the write request ID in the write request information matches the write response identification number, and sends the matching success information to the write response signal processing module and the write request buffer.

[0025] The write request buffer stores the write request ID, address, type, attributes, and data size in the address buffer; it writes the write request ID, data to be written, and valid bytes in the data buffer; the data bit width in the data buffer and the address bit width in the address buffer are the same as the corresponding interface bit width of the secondary cache; it receives the matching success information sent by the ID management module and clears the matching write request information from the write request buffer;

[0026] Upon receiving a write request arrival identifier signal, the write response signal processing module returns a write response signal to the bus protocol conversion unit according to the interface protocol of the L2 cache. At the same time, the write response signal processing module also receives the write response information returned by the L2 cache, which includes a write response identification number and a write response type, and sends the error signal fed back by the L2 cache to the processor core for processing.

[0027] Preferably, the write request buffer can cache up to four sets of write operation request information.

[0028] Preferably, the interconnection unit further includes a listening request processing unit;

[0029] The listener request processing unit processes and transmits listener request information from the processor core. It uses a programmable arbitration unit to transmit read / write and listener information with the L2 cache, ensuring the consistency of cached data.

[0030] Preferably, the listening request processing unit includes a listening request signal generation module and a listening response signal generation module;

[0031] The programmable arbitration module simultaneously listens for listener request information from the L2 cache and L2 write operation request information from each processor core. When it receives a listener request from the L2 cache or a write operation request from a processor core, it sends a L2 listener request to the listener request signal generation module through the programmable arbitration module. The L2 listener request includes a listener address and a listener type.

[0032] After receiving the secondary listening request from the programmable arbitration module, the listening request signal generation module adjusts the listening address in the secondary listening request according to the cache line size of the primary and secondary caches. It converts the address of the secondary cache in the listening request into the primary cache address corresponding to each processing core, and uses it as the adjusted listening address. The adjusted listening address and listening type are combined to form the processor core-side listening request information and sent to each processor core.

[0033] After receiving the core-side listen response information from each processor core, the listen response signal generation module adjusts the listen return data according to the cache line size of the L1 and L2 caches. It converts the data bit width in the core-side listen response information that matches the processor core bus interface into the data bit width that matches the L2 cache interface, and uses this as the adjusted listen response data. The adjusted listen response data and the listen response type are combined to form the listen response information, which is then sent to the L2 cache through the programmable arbitration module.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] (1) The two-level cache interconnection structure proposed in this invention has scalability. Each processor core has a separate read / write and listen channel as well as a corresponding secondary cache interface, which can be applied to different processor core architectures.

[0036] (2) Through the flexible conversion design of bus protocol, the present invention enables the interconnection structure to support the interconnection between two-level caches with different bus interfaces, giving multi-core processor architects more options when choosing the type of secondary cache.

[0037] (3) The present invention enables the interconnect structure to support simultaneous access to the shared L2 cache space by multiple serial interface processor cores through configurable bus protocol conversion and arbitration selection functions, thereby avoiding long waiting cycles caused by bus arbitration and improving the memory access performance of multi-core processor systems.

[0038] (4) The present invention adds a write buffer through the write request processing unit, which can cache up to four sets of write operation request information, reducing the blockage of processor memory access operations caused by the inability of the secondary cache to receive write requests in a timely manner, and improving the execution speed of processor memory access instructions.

[0039] (5) The present invention automatically sends a refresh instruction to the secondary cache after the reset signal is released by the reset management unit, so that the software programmer does not need to refresh the invalid data in the secondary cache through the software after the system is reset.

[0040] (6) This invention ensures cache data consistency by monitoring write operations and transmitting secondary cache listening information, and adjusts the listening address according to the cache line size of the primary and secondary caches, which can be applied to processor architectures with different cache line sizes in the two-level cache.

[0041] (7) After receiving a write request, the write response signal processing module of the present invention automatically returns a write response signal to the bus protocol conversion unit in accordance with the requirements of the bus protocol, without waiting for the response of the L2 cache, which reduces the time for the processor core to wait for the L2 cache to return the write response signal and improves the response speed to the processor core's write request. Attached Figure Description

[0042] Figure 1 This is a schematic diagram illustrating the application of the two-level cache interconnection structure of the present invention;

[0043] Figure 2 This is a schematic diagram of the read request processing unit structure in the interconnection structure of the present invention;

[0044] Figure 3 This is a schematic diagram of the write request processing unit structure in the interconnection structure of the present invention;

[0045] Figure 4 This is a schematic diagram of the internal structure of the write request buffer in the interconnect structure of the present invention;

[0046] Figure 5 This is a schematic diagram of the listening request address processing method in the interconnection structure of the present invention. Detailed Implementation

[0047] The present invention will now be further described with reference to the accompanying drawings:

[0048] This invention provides a two-level cache interconnection structure based on flexible switching of multiple bus protocols. The two-level cache interconnection structure includes a reset management unit; a programmable arbitration unit; and N interconnection units; where N is greater than or equal to 1.

[0049] Each processor core has its own L1 cache and bus interface. The L1 cache communicates with the outside world through the bus interface. N processor cores share a L2 cache. The L2 cache includes at least one interface module that communicates with a programmable arbitration unit. There is a one-to-one correspondence between processor cores and interconnect units. The L2 cache can communicate with multiple processor cores simultaneously.

[0050] The interconnect unit is used to implement protocol conversion between the processor core's L1 cache interface and L2 cache interface. It receives read and write request information from the processor core, generates L2 read request signals and L2 write request signals for the L2 cache, and sends them to the programmable arbitration unit; it receives listen requests from the programmable arbitration unit, generates listen request signals, and sends them to the processor core; it receives response signals from the L2 cache and feeds them back to the processor core.

[0051] The programmable arbitration unit enables the transmission of read, write, and listening information between each processor core and the L2 cache according to different arbitration configurations. It maintains data consistency between L1 caches by listening to processor core write operations. Specifically, it arbitrates L2 read request signals or L2 write request signals issued by each interconnect unit according to the number of L2 cache ports, ensuring that only one processor core accesses each L2 cache port at any given time; it feeds back the response signals sent by the L2 cache ports to the corresponding interconnect unit; and it receives listening requests issued by the L2 cache and sends them to the interconnect unit.

[0052] The reset management unit receives an external reset signal and sends a refresh command to the secondary cache after the reset signal is released, so that all residual data in the secondary cache is marked as invalid after the reset, thus realizing the automatic refresh function of the secondary cache after the reset.

[0053] Preferably, the interconnection unit includes a bus protocol conversion unit, a read request processing unit, and a write request processing unit;

[0054] The bus protocol conversion unit is used to convert between different protocols of the processor core interface and the L2 cache interface. Specifically, it parses the processor core bus interface signals according to the processor core's interface protocol, decomposes them into read request information or write request information, and generates L2 read request information and L2 write request information according to the L2 cache's interface protocol. The L2 read request information is sent to the read request processing unit, and the L2 write request information is sent to the write request processing unit. The L2 read request information includes the read operation request type, request address, and data size; the L2 write request information includes the write operation request type, request address, data size, data being written, and valid bytes. The bus protocol conversion unit can flexibly convert between multiple bus protocols, enabling interconnection and communication between processor cores and L2 caches with different bus interfaces.

[0055] The read request processing unit identifies the request type of the read operation in the secondary read request information, generates corresponding attribute values ​​for different request types, assigns a unique read request ID to the secondary read request information, and sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol.

[0056] The write request processing unit extracts the address, data to be written, data size, and valid bytes from the secondary write request information; identifies the request type of the write operation, generates corresponding attribute values ​​for different request types, and represents them using attribute signals; assigns a unique write request ID to the secondary write request information; stores the write request ID, address, type, attribute, and data size in the address buffer; writes the write request ID, data to be written, and valid bytes in the data buffer; and sends the secondary write request information, its attribute signals, and the write request ID signal to the programmable arbitration unit according to the secondary cache interface protocol.

[0057] The read request processing unit is used to implement handshake communication between read operation requests and responses between the two-level caches; preferably, the read request processing unit includes a read request type identification module, a read request signal generation module, an ID management module, and a read response signal processing module;

[0058] The read request type identification module parses the secondary read request information, identifies the request type of the read operation issued by the processor core, generates corresponding attribute values ​​for different request types, and sends them to the read request signal generation module.

[0059] The read request signal generation module sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol;

[0060] The ID management module assigns different read request IDs to the secondary read request information and sends them to the read request signal generation module. It receives the read response identification number from the read response information returned by the secondary cache, determines whether the read request ID in the read request information matches the read response identification number, and sends a matching success signal to the read response signal processing module.

[0061] The read response signal processing module receives read response information returned by the secondary cache; the read response information includes a read response identification number, returned data, a data return completion signal, and a read response type; it receives a matching success signal from the ID management module; and it returns the returned data and response type to the bus protocol conversion unit.

[0062] The specific steps to determine whether the ID number in the secondary read request information matches the read response identification number are as follows:

[0063] When the ID number in the read request information is the same as the read response identification number, it is considered that the read request ID number in the read request information matches the read response identification number.

[0064] If the ID number in the read request information is different from the read response identification number, it is considered that the ID number in the read request information and the read response identification number do not match.

[0065] Depending on the type and size of the read request, a read request may return data multiple times in succession. The data return completion signal is used to indicate that all data has been returned.

[0066] The write request processing unit is used to implement the caching of write requests to the processor core and the handshake communication between the two levels of cache for write operation requests and responses.

[0067] Preferably, the write request processing unit includes a write request type identification module, a write request signal generation module, an ID management module, a write request buffer, and a write response signal processing module;

[0068] The write request type identification module extracts the request type, address, data to be written, data size, and valid bytes from the secondary write request information. Then, it sends an ID request message to the ID management module and sends the write request information to the write request signal generation module.

[0069] The write request signal generation module receives the secondary write request information and generates corresponding attributes for different request types. Based on the address of the data to be written, it sets the secondary write request information to match the bit width of the secondary cache data interface. It then sends the secondary write request information, attributes, and the request ID generated by the ID management module to the write request buffer. Afterward, it sends a write request arrival identifier signal to the write response signal processing module. Finally, it extracts the address, type, attributes, data size, data to be written, and valid bytes corresponding to the same write request ID from the write request buffer and sends them to the programmable arbitration module according to the secondary cache interface protocol.

[0070] After receiving the ID request message, the ID management module assigns a unique write request ID to the secondary write request information and sends the write request ID to the write request buffer and the write request signal generation module; it receives the write response identification number from the write response information returned by the secondary cache, determines whether the write request ID in the write request information matches the write response identification number, and sends the matching success information to the write response signal processing module and the write request buffer.

[0071] The write request buffer stores the write request ID, address, type, attributes, and data size in the address buffer; it writes the write request ID, data to be written, and valid bytes in the data buffer; the data bit width in the data buffer and the address bit width in the address buffer are the same as the corresponding interface bit width of the secondary cache; it receives the matching success information sent by the ID management module and clears the matching write request information from the write request buffer;

[0072] The write response signal processing module, upon receiving a write request arrival identifier signal, returns a write response signal to the bus protocol conversion unit according to the L2 cache interface protocol. Simultaneously, the write response signal processing module also receives write response information returned by the L2 cache, including a write response identifier and a write response type, and sends the error signal fed back by the L2 cache to the processor core for processing. Here, the write response module returns a write response to the bus protocol conversion unit in advance after the write request arrives; if the write response type returned by the L2 cache is an error, then an error is fed back separately. This is to reduce the time the processor core waits for write feedback.

[0073] Preferably, the write request buffer can cache up to four sets of write operation request information.

[0074] Preferably, the interconnection unit further includes a listening request processing unit;

[0075] The listener request processing unit processes and transmits listener request information from the processor core. It uses a programmable arbitration unit to transmit read / write and listener information with the L2 cache, ensuring the consistency of cached data.

[0076] Preferably, the listening request processing unit includes a listening request signal generation module and a listening response signal generation module;

[0077] The programmable arbitration module simultaneously listens for listener request information from the L2 cache and L2 write operation request information from each processor core. When it receives a listener request from the L2 cache or a write operation request from a processor core, it sends a L2 listener request to the listener request signal generation module through the programmable arbitration module. The L2 listener request includes a listener address and a listener type.

[0078] After receiving the secondary listening request from the programmable arbitration module, the listening request signal generation module adjusts the listening address in the secondary listening request according to the cache line size of the primary and secondary caches. It converts the address of the secondary cache in the listening request into the primary cache address corresponding to each processing core, and uses it as the adjusted listening address. The adjusted listening address and listening type are combined to form the processor core-side listening request information and sent to each processor core.

[0079] After receiving the core-side listen response information from each processor core, the listen response signal generation module adjusts the listen return data according to the cache line size of the L1 and L2 caches. It converts the data bit width in the core-side listen response information that matches the processor core bus interface into the data bit width that matches the L2 cache interface, and uses this as the adjusted listen response data. The adjusted listen response data and the listen response type are combined to form the listen response information, which is then sent to the L2 cache through the programmable arbitration module.

[0080] Example:

[0081] like Figure 1 As shown, the two-level cache interconnect structure based on flexible conversion of multiple bus protocols of the present invention mainly consists of a reset management unit, a programmable arbitration unit, and N interconnect units, where N is greater than or equal to 1. Each interconnect unit includes a bus protocol conversion unit, a read request processing unit, a write request processing unit, and a listen request processing unit.

[0082] Each processor core has a dedicated interconnect unit to communicate with the L2 cache. Different bus protocols define different signals. For example, a request type from the processor core bus interface might use a single 4-bit signal line to represent N attributes, while a different bus protocol for the L2 cache interface would require two sets of signal lines—one for type and one for attribute, each representing a subset of attributes. Therefore, the interconnect unit uses a bus protocol conversion unit to switch between the different protocols of the processor core interface and the L2 cache interface. It also uses separate read and write request processing units to handle read and write operations, a listener request processing unit to process and transmit L2 cache listener request information, and a programmable arbitration unit to transmit read, write, and listener information between the processor core and the L2 cache, as well as to listen for write operations from other masters, ensuring cache data consistency.

[0083] The reset management unit is used to implement the function of automatically refreshing the L2 cache after a reset. After the reset signal is released, the reset management unit sends a refresh command to the L2 cache, enabling all residual data in the L2 cache to be automatically refreshed after a reset.

[0084] The bus protocol conversion unit converts interface protocol signals and can be configured according to different two-level cache interfaces. When the processor core is a serial bus interface, it can convert the processor core interface signals from serial to parallel to achieve the separation of read and write channels, which makes it easier for the two-level cache interconnect structure to process read and write operations between the two caches separately.

[0085] like Figure 2The diagram shows the structure of the read request processing unit. This unit implements the handshake communication between the two-level cache for read operation requests and responses. It includes a read request type identification module, a read request signal generation module, an ID management module, and a read response signal processing module. After receiving read request information from the processor core, the unit uses the read request type identification module to identify the request type, classifying it into instruction read requests, data read requests, cacheable read requests, and non-cacheable read requests. This allows the second-level cache module to process different types of requests separately. For example, the second-level cache stores instructions and data in different storage areas. When a data read request is received, data is retrieved from the data storage area; when an instruction read request is received, it is read from the instruction storage area. The read request signal generation module sets corresponding attribute values ​​for different request types and sends them, along with the request ID generated by the ID management module, as the identification information for the request to the second-level cache. The ID management module is responsible for assigning different identification numbers (IDs) to each read request based on its request type and matching these IDs with the read response identification numbers returned by the second-level cache. The read response signal processing module is used to receive the read response signal returned by the L2 cache, and return the returned read request data and information on whether the read request was successful to the bus protocol conversion unit in accordance with the requirements of the bus protocol.

[0086] like Figure 3 The diagram shows the internal structure of the write request processing unit. This unit implements the caching of write requests to the processor cores and the handshake communication between the two levels of cache for write operation requests and responses. It includes a write request type identification module, a write request signal generation module, an ID management module, a write request buffer, and a write response signal processing module.

[0087] The write request type identification module identifies the type of write operation request issued by the processor core. The write request signal generation module sets corresponding write request types and attribute values ​​based on the identified cacheable write request types, non-cacheable write request types, and cache consistency maintenance operation request types. It also sets write request information matching the bit width of the L2 cache data interface based on the address of the written data, and sends this information, along with the request ID generated by the ID management module, to the write request buffer. The ID management module assigns a different identification number (ID) to each write request based on different request types and matches it with the ID of the write response returned by the L2 cache. Upon receiving a write request, the write response signal processing module returns a write response signal to the bus protocol conversion unit according to the bus protocol requirements, without waiting for a response from the L2 cache, thus improving the response speed to processor core write requests. Simultaneously, the write response signal processing module is also responsible for sending error signals fed back by the L2 cache to the processor core for processing.

[0088] The write request buffer contains four write request buffers, which can cache four sets of write operation request information, such as... Figure 4 The diagram illustrates the information cached by the write request buffer, which includes an address information buffer and a data information buffer. The address buffer stores the ID, address, type, attributes, and size information of the address request, while the data buffer stores the ID, data, and valid bytes information of the data request. The ID information ensures the matching relationship between address and data requests. The write request buffer caches write request information issued by the processor core and sends the write request out when the L2 cache is ready, reducing processor core memory access blockage caused by the L2 cache's inability to receive write requests in a timely manner.

[0089] The listen request processing unit includes a listen request signal generation module and a listen response signal generation module. These modules process the listen information and feed the listen request back to the processor core, enabling the processor core to perform data consistency maintenance operations. Upon receiving a listen request from the L2 cache, the listen request signal generation module adjusts the listen request based on the cache line sizes of the L1 and L2 caches, and sends the adjusted listen address and listen request signal to the processor core. The listen response signal generation module receives the listen response information from the processor core and sends response information to the L2 cache based on the adjustments made to the listen request by the listen request signal generation module. The listen request information includes the listen address and listen type. The type includes options such as invalidating an address, i.e., reading out or invalidating a specific address.

[0090] like Figure 5 For example, when the L2 cache line size is 64 bytes, its listen address is 64-byte aligned. That is, regardless of whether the write operation address is 0x40 or 0x70, the L2 cache will always send a listen address of 0x40. At this time, when the L1 cache line size is 32 bytes, i.e., the address is 32-byte aligned, the listen request signal generation module will continuously send two listen requests with addresses of 0x40 and 0x60 to the processor core to ensure that the data consistency between the two caches can be guaranteed, whether the write operation is performed to the high-order address or the low-order address of the L2 cache line.

[0091] The programmable arbitration module receives read / write request information from each processor core in the interconnect unit and can configure arbitration according to the number of L2 cache interfaces. If the L2 cache has multiple interfaces that can receive requests from each processor core, the read / write request information from each processor core can be sent to the L2 cache in parallel, reducing the waiting cycle required for bus arbitration. If the L2 cache has only one interface, the programmable arbitration module can be configured to arbitration mode, and the requests from each processor core are sent to the L2 cache after arbitration.

[0092] To enable the processor core to listen for write operations to shared addresses, the programmable arbitration module simultaneously listens for listening requests from the L2 cache and write operation requests from each processor core. The listened information is sent to the listening request processing unit for processing. After receiving the listening request, the processor core matches the listening address with its own L1 cache. If a cache line is hit, the cache line is invalidated to ensure cache data consistency.

[0093] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A two-level cache interconnection structure based on flexible switching of multiple bus protocols, characterized in that... Programmable arbitration unit, N interconnection units; N is greater than or equal to 1; Each processor core has its own L1 cache and bus interface. The L1 cache communicates with the outside world through the bus interface. N processor cores share a L2 cache. The L2 cache includes at least one interface module that communicates with a programmable arbitration unit. There is a one-to-one correspondence between processor cores and interconnect units. The interconnect unit is used to implement protocol conversion between the processor core bus interface and the L2 cache interface. It receives read and write request information from the processor core, generates L2 read request signals and L2 write request signals for the L2 cache, and sends them to the programmable arbitration unit. It also receives listen requests from the programmable arbitration unit and generates listen request signals to send to the processor core. It receives the response signal from the L2 cache and feeds it back to the processor core; The programmable arbitration unit arbitrates the L2 cache read or write request signals from each interconnect unit based on the number of L2 cache ports, ensuring that only one processor core accesses each L2 cache port at any given time; it feeds back the response signals sent by the L2 cache ports to the corresponding interconnect unit; and it receives listen requests from the L2 cache and sends them to the interconnect unit. The interconnection unit includes a bus protocol conversion unit, a read request processing unit, and a write request processing unit; The bus protocol conversion unit parses the processor core bus interface signals according to the processor core's interface protocol, decomposes them into read request information or write request information, and generates secondary read request information and secondary write request information according to the secondary cache's interface protocol. The secondary read request information is sent to the read request processing unit, and the secondary write request information is sent to the write request processing unit. The secondary read request information includes the read operation request type, request address, and data size; the secondary write request information includes the write operation request type, request address, data size, data to be written, and valid bytes. The read request processing unit identifies the request type of the read operation in the secondary read request information, generates corresponding attribute values ​​for different request types, assigns a unique read request ID to the secondary read request information, and sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol. The write request processing unit extracts the address, data to be written, data size, and valid bytes from the secondary write request information; identifies the request type of the write operation, generates corresponding attribute values ​​for different request types, and represents them using attribute signals; assigns a unique write request ID to the secondary write request information; stores the write request ID, address, type, attribute, and data size in the address buffer; writes the write request ID, data to be written, and valid bytes in the data buffer; and sends the secondary write request information, its attribute signals, and the write request ID signal to the programmable arbitration unit according to the secondary cache interface protocol.

2. The two-level cache interconnection structure based on flexible switching of multiple bus protocols according to claim 1, characterized in that... It also includes a reset management unit; The reset management unit receives an externally input reset signal. After the reset signal is released, it sends a refresh command to the L2 cache, causing all remaining data in the L2 cache to be marked as invalid after the reset.

3. A two-level cache interconnection structure based on flexible switching of multiple bus protocols as described in claim 1, characterized in that... The read request processing unit includes a read request type identification module, a read request signal generation module, an ID management module, and a read response signal processing module; The read request type identification module parses the secondary read request information, identifies the request type of the read operation issued by the processor core, generates corresponding attribute values ​​for different request types, and sends them to the read request signal generation module. The read request signal generation module sends the secondary read request information, attributes, and read request ID to the programmable arbitration unit according to the timing requirements of the secondary cache interface protocol; The ID management module assigns different read request IDs to the secondary read request information and sends them to the read request signal generation module. It receives the read response identification number from the read response information returned by the secondary cache, determines whether the read request ID in the read request information matches the read response identification number, and sends a matching success signal to the read response signal processing module. The read response signal processing module receives read response information returned by the secondary cache; the read response information includes a read response identification number, returned data, data return completion signal, and read response type. Receive the matching success signal from the ID management module; return the returned data and response type to the bus protocol conversion unit.

4. A two-level cache interconnection structure based on flexible switching of multiple bus protocols as described in claim 1, characterized in that... The write request processing unit includes a write request type identification module, a write request signal generation module, an ID management module, a write request buffer, and a write response signal processing module. The write request type identification module extracts the request type, address, data to be written, data size, and valid bytes from the secondary write request information. Then, it sends an ID request message to the ID management module and sends the write request information to the write request signal generation module. The write request signal generation module receives the secondary write request information and generates corresponding attributes for different request types. Based on the address of the data to be written, it sets the secondary write request information to match the bit width of the secondary cache data interface. It then sends the secondary write request information, attributes, and the request ID generated by the ID management module to the write request buffer. Afterward, it sends a write request arrival identifier signal to the write response signal processing module. Finally, it extracts the address, type, attributes, data size, data to be written, and valid bytes corresponding to the same write request ID from the write request buffer and sends them to the programmable arbitration module according to the secondary cache interface protocol. After receiving the ID request message, the ID management module assigns a unique write request ID to the secondary write request information and sends the write request ID to the write request buffer and the write request signal generation module. Receive the write response identification number from the write response information returned by the second-level cache, determine whether the write request ID in the write request information matches the write response identification number, and send the matching success information to the write response signal processing module and the write request buffer. The write request buffer stores the write request ID, address, type, attributes, and data size in the address buffer; it writes the write request ID, data to be written, and valid bytes in the data buffer; the data bit width in the data buffer and the address bit width in the address buffer are the same as the corresponding interface bit width of the secondary cache; it receives the matching success information sent by the ID management module and clears the matching write request information from the write request buffer; Upon receiving a write request arrival identifier signal, the write response signal processing module returns a write response signal to the bus protocol conversion unit according to the interface protocol of the L2 cache. At the same time, the write response signal processing module also receives the write response information returned by the L2 cache, which includes a write response identification number and a write response type, and sends the error signal fed back by the L2 cache to the processor core for processing.

5. A two-level cache interconnection structure based on flexible switching of multiple bus protocols as described in claim 4, characterized in that... The write request buffer can cache up to four sets of write operation request information.

6. A two-level cache interconnection structure based on flexible switching of multiple bus protocols as described in claim 1, characterized in that... The interconnection unit also includes a listening request processing unit; The listener request processing unit processes and transmits listener request information from the processor core. It uses a programmable arbitration unit to transmit read / write and listener information with the L2 cache, ensuring the consistency of cached data.

7. A two-level cache interconnection structure based on flexible switching of multiple bus protocols as described in claim 6, characterized in that... The listening request processing unit includes a listening request signal generation module and a listening response signal generation module; The programmable arbitration module simultaneously listens for listener request information from the L2 cache and L2 write operation request information from each processor core. When it receives a listener request from the L2 cache or a write operation request from a processor core, it sends a L2 listener request to the listener request signal generation module through the programmable arbitration module. The L2 listener request includes a listener address and a listener type. After receiving the secondary listening request from the programmable arbitration module, the listening request signal generation module adjusts the listening address in the secondary listening request according to the cache line size of the primary and secondary caches. It converts the address of the secondary cache in the listening request into the primary cache address corresponding to each processing core, and uses it as the adjusted listening address. The adjusted listening address and listening type are combined to form the processor core-side listening request information and sent to each processor core. After receiving the core-side listen response information from each processor core, the listen response signal generation module adjusts the listen return data according to the cache line size of the L1 and L2 caches. It converts the data bit width in the core-side listen response information that matches the processor core bus interface into the data bit width that matches the L2 cache interface, and uses this as the adjusted listen response data. The adjusted listen response data and the listen response type are combined to form the listen response information, which is then sent to the L2 cache through the programmable arbitration module.

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