Driving circuit for driving a light emitting unit and electronic device

Abstract

A driving circuit for driving a light emitting unit and an electronic device are provided. The driving circuit includes a driving transistor, a switching transistor, a lighting transistor, a first capacitor and a first compensation transistor. The switching transistor is coupled to the driving transistor. The lighting transistor is coupled between the light emitting unit and the driving transistor. The first capacitor is coupled to the driving transistor. The first compensation transistor is coupled to the first capacitor. A first end of the first compensation transistor receives a same signal as a first end of the lighting transistor.

Description

Technical Field

[0001] This disclosure relates to a driving circuit, and more particularly to a driving circuit and electronic device for driving a light emitting unit. Background Technology

[0002] For current display panels, such as light-emitting diode (LED) display panels, organic light-emitting diode (OLED) display panels, mini LED display panels, or micro LED display panels, their driving circuits are mostly manufactured using process technologies such as low-temperature polysilicon (LTPS), amorphous silicon (a-Si), or oxide thin-film transistors (TFTs). Therefore, the characteristics of the circuit components themselves in the driving circuit will vary due to the aforementioned process, resulting in errors in the output voltage. For example, when the critical voltage of the TFT varies, the output voltage of the TFT will have an error. Furthermore, the more TFTs included in the driving circuit, the more the switching action of these TFTs will have a non-ideal bias effect on the gate voltage level of the TFTs due to parasitic capacitive coupling effects. Summary of the Invention

[0003] This disclosure provides a special circuit design architecture for a driving circuit and electronic device used to drive an optical emitting unit, which can effectively compensate for the driving transistors in the driving circuit.

[0004] According to embodiments of this disclosure, the driving circuit for driving a light-emitting unit includes a driving transistor, a switching transistor, a lighting transistor, a first capacitor, and a first compensation transistor. The switching transistor is coupled to the driving transistor. The lighting transistor is coupled between the light-emitting unit and the driving transistor. The first capacitor is coupled to the driving transistor. The first compensation transistor is coupled to the first capacitor. A first terminal of the first compensation transistor receives the same signal as a first terminal of the lighting transistor.

[0005] According to embodiments of this disclosure, the electronic device includes a substrate, a light-emitting unit, and a driving circuit. The light-emitting unit is disposed on the substrate. The driving circuit is disposed on the substrate. The driving circuit drives the light-emitting unit and includes a driving transistor, a switching transistor, a lighting transistor, a first capacitor, and a first compensation transistor. The switching transistor is coupled to the driving transistor. The lighting transistor is coupled between the light-emitting unit and the driving transistor. The first capacitor is coupled to the driving transistor. The first compensation transistor is coupled to the first capacitor. A first terminal of the first compensation transistor and a first terminal of the lighting transistor receive the same signal.

[0006] Based on the above, the driving circuit and electronic device disclosed herein for driving the light emitting unit can effectively compensate the voltage of the driving transistor in the driving circuit by designing a compensation transistor in the driving circuit.

[0007] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 2 This is a schematic diagram of the driving circuit of the first embodiment disclosed herein;

[0010] Figure 3 This is a signal timing diagram of one embodiment of the present disclosure;

[0011] Figure 4 This is a schematic diagram of the driving circuit of the second embodiment disclosed herein;

[0012] Figure 5 This is a schematic diagram of the driving circuit of the third embodiment disclosed herein;

[0013] Figure 6 This is a schematic diagram of the driving circuit of the fourth embodiment disclosed herein;

[0014] Figure 7 This is a schematic diagram of the current-voltage curve of one embodiment of the present disclosure;

[0015] Figure 8 This is a schematic diagram of the current-voltage curve of another embodiment disclosed herein.

[0016] Explanation of reference numerals in the attached figures

[0017] 100, 200, 400, 500, 600: Electronic devices;

[0018] 110, 210, 410, 510, 610: substrate;

[0019] 120, 220, 420, 520, 620: Drive circuit;

[0020] 121: Driving transistor;

[0021] 122: Turn on the transistor;

[0022] 123: Data writing circuit;

[0023] 124: Storage circuit;

[0024] 125, 225-1, 225-2, 425, 525, 625: Compensation circuits;

[0025] 130, 230, 430, 530, 630: Optical emitting units;

[0026] 701, 801, 802: Current-voltage curves;

[0027] VDD: Operating voltage;

[0028] VSS: Grounding voltage;

[0029] T1~T12: Transistors;

[0030] C1~C3, Cst: Capacitors;

[0031] EM: Transmit signal;

[0032] DA: Data signal;

[0033] Sn: Write signal;

[0034] RST: Reset signal;

[0035] Vrst: Reset voltage;

[0036] Vref: Reference voltage;

[0037] AN: Anode;

[0038] t0~t4: Time. Detailed Implementation

[0039] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0040] In some embodiments disclosed herein, the term "coupled" may include any direct and indirect electrical connection means. An indirect electrical connection means that other components may exist between the coupled parties, and these other components may include circuit components such as capacitors, resistors, or inductors, general components, or combinations thereof. In some embodiments disclosed herein, the term "coupled between" means that any direct and indirect electrical connection means that there may be other components between the coupled objects, and these other components may include circuit components such as capacitors, resistors, or inductors, general components, or combinations thereof. Furthermore, in some embodiments disclosed herein, the term "coupled to a voltage" may refer to directly or indirectly coupling to a voltage line, a voltage terminal, or a voltage source, or receiving a voltage.

[0041] In some embodiments disclosed herein, the term “setup” may include any direct and indirect means of setting, configuring or forming, wherein an indirect means of setting refers to a situation where other components, objects or other material layers may be set, configured or formed between the two sets.

[0042] It should be understood that the features described below can be combined, modified, substituted, or transferred from several different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0043] The ordinal numbers used in the specification and claims, such as "first," "second," "third," etc., to modify components, do not in themselves imply or represent any prior ordinal number for that component, nor do they represent the order of one component with another, or the order of manufacture. The use of these ordinal numbers is solely to clearly distinguish one component with a given name from another component with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0044] The electronic device disclosed herein may include, for example, a display device, an antenna device, a sensing device, a touch display, a curved display, or a free-shape display, and may also be a bendable or flexible splicing electronic device, but is not limited thereto. The light emitting unit of the electronic device may include, for example, a light-emitting diode (LED), liquid crystal, fluorescence, phosphorescence, quantum dot (QD), other suitable display media, or combinations thereof, but is not limited thereto. The LED may include, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode, a mini LED, a micro LED, or a quantum dot light-emitting diode (e.g., QLED, QDLED), or other suitable materials or any arrangement and combination thereof, but is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. It should be noted that the electronic device disclosed herein can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, light source systems, and shelving systems to support display devices or antenna devices.

[0045] Throughout this specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0046] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of this disclosure. (See reference) Figure 1The electronic device 100 includes a substrate 110, a driving circuit 120, and a light-emitting unit 130. The driving circuit 120 and the light-emitting unit 130 are disposed on the substrate 110. The driving circuit 120 includes a driving transistor 121, an emitting transistor 122, a data writing circuit 123, a storage circuit 124, and a compensation circuit 125. In this embodiment, the first terminal of the driving transistor 121 is coupled to the storage circuit 124 and the compensation circuit 125. The second terminal of the driving transistor 121 is coupled to the operating voltage VDD. The third terminal of the driving transistor 121 is coupled to the second terminal of the emitting transistor 122. The third terminal of the emitting transistor 122 is coupled to one end of the light-emitting unit 130, and the first terminal of the emitting transistor 122 can receive a signal (not shown) to determine whether to illuminate the light-emitting unit 130. The other end of the light-emitting unit 130 is coupled to the ground voltage VSS. The storage circuit 124 is also coupled to the data writing circuit 123. In this embodiment, the operating voltage VDD, driving transistor 121, lighting transistor 122, light emitting unit 130, and ground voltage VSS form the pixel driving current path. The transistors disclosed herein (e.g., the driving transistor 121 or lighting transistor 122 described above) may contain semiconductor materials, such as amorphous silicon, low-temperature polysilicon (LTPS), or metal oxide. The transistor may be a thin-film transistor containing a top gate, a bottom gate, or a dual gate or double gate, or a combination of the above materials; this disclosure is not limited thereto. In some embodiments, the thin-film transistor may have the different semiconductor materials described above. The first, second, and third terminals of the transistors disclosed herein (e.g., driving transistor 121 or lighting transistor 122) may be the gate, source, and drain, respectively, but this disclosure is not limited thereto. Furthermore, the gate of the transistor can be considered as the control terminal of the transistor. Additionally, the gate of the transistor disclosed herein may contain polysilicon, metal, or other conductive materials, and is not limited thereto. The aforementioned metals include, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), or titanium (Ti). The source and drain materials of the transistor disclosed herein may include metals such as copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), or titanium (Ti), but are not limited to these.

[0047] The substrate 110 disclosed herein can be a rigid substrate or a flexible substrate. The material of the substrate 110 may include, for example, glass, quartz, ceramic, sapphire, or plastic, but this disclosure is not limited thereto. In another embodiment, the material of the substrate 110 may include a suitable opaque material. In some embodiments, when the substrate 110 is a flexible substrate, it may contain a suitable flexible material, such as polycarbonate (PC), polyimide (PI), polypropylene (PP), or polyethylene terephthalate (PET), other suitable materials, or combinations of the foregoing materials, but is not limited thereto. Furthermore, the light transmittance of the substrate 110 is not limited; that is, the substrate 110 may be a transparent substrate, a semi-transparent substrate, or an opaque substrate.

[0048] In this embodiment, the data writing circuit 123 and the compensation circuit 125 may each include circuits composed of one or more transistors, and the storage circuit 124 may include a capacitor. The data writing circuit 123 can provide a data signal to the storage circuit 124, and the storage circuit 124 can store the data signal. The storage circuit 124 can provide the data signal to the driving transistor 121, so that the driving transistor 121 can provide a corresponding driving current from the operating voltage VDD to the lighting transistor 122 according to the voltage magnitude of the data signal. When the lighting transistor 122 is turned on (or conducted), the lighting transistor 122 can provide the driving current to the light emitting unit 130. It is worth noting that the compensation circuit 125 is also coupled to any node on the pixel driving current path to provide a compensation bias to the first terminal of the driving transistor 121 according to the voltage of the node. The driving circuit 120 in this embodiment can be a circuit architecture composed of multiple transistors, such as a circuit architecture composed of two transistors and one capacitor (2T1C), or a circuit architecture composed of seven transistors and two capacitors (7T2C), or a circuit architecture composed of eight transistors and two capacitors (8T2C). This disclosure is not limited to this, and the following embodiments will be illustrated with a circuit architecture composed of eight transistors, but this disclosure is not limited to this.

[0049] Figure 2 This is a schematic diagram of the driving circuit of the first embodiment disclosed herein. (See reference) Figure 2The electronic device 200 includes a substrate 210, a driving circuit 220, and a light emitting unit 230. Examples of the materials used for the substrate 210 can be found in the previously described examples of the materials used for the substrate 110, and will not be repeated here. The driving circuit 220 is disposed on the substrate 210 and includes transistors T1-T12, capacitors C1-C3, and a storage capacitor Cst. Transistors T1-T12 may be P-type transistors, but this disclosure is not limited thereto. In one embodiment, transistors T1-T12 may also be designed as N-type transistors. Alternatively, a portion of transistors T1-T12 may be P-type transistors, while another portion may be N-type transistors. Furthermore, it should be understood that, for better understanding, some components will... Figure 2 The characters are omitted and / or simplified.

[0050] In this embodiment, transistor T1 can be a driving transistor, and can correspond to, for example... Figure 1 The driving transistor 121, and transistor T11 can be a compensation transistor. The first terminal of transistor T1 (e.g., gate G) is coupled to one end of storage capacitor Cst, and the other end of storage capacitor Cst is coupled to the third terminal of transistor T2 and the third terminal of transistor T4 through node N. Transistor T2 can be a switch transistor, and can correspond to... Figure 1 The data writing circuit 123. The first terminal of transistor T2 receives the write signal Sn, and the second terminal of transistor T2 receives the data signal DA. The first terminal of transistor T4 can receive the transmit signal EM. The second terminal of transistor T4 is coupled to the reference voltage Vref. The second terminal of transistor T1 is coupled to the operating voltage VDD, and capacitor C1 is coupled between the first and second terminals (e.g., the source S) of transistor T1. The third terminal (e.g., the drain D) of transistor T1 is coupled to the second terminal of transistor T5. Transistor T5 can be a lighting transistor and can correspond to... Figure 1 The light-up transistor 122. The first terminal of transistor T5 can receive the emitting signal EM. The third terminal of transistor T5 is coupled to the anode AN of the light-emitting unit 230. The cathode of the light-emitting unit 230 is coupled to ground voltage VSS. The light-emitting unit 230 can be configured as follows: Figure 1 The light emitting unit 130. Furthermore, it should be noted that transistors T5, T10, and T11 in this embodiment can, for example, receive the same signal, such as the transmitted signal EM, but this disclosure is not limited thereto. More specifically, the first terminal of transistor T11 and the first terminal of transistor T5 can receive the same transmitted signal EM. Similarly, the first terminal of transistor T10 and the first terminal of transistor T5 can receive the same transmitted signal EM.

[0051] In this embodiment, the operating voltage VDD, transistor T1, transistor T5, light emitting unit 230, and ground voltage VSS form the pixel driving current path. When transistor T2 is turned on, the data signal DA can be written from transistor T2 to the storage capacitor Cst, and capacitor Cst can provide a corresponding voltage to transistor T1, causing transistor T1 to operate in the saturation region, and providing a corresponding driving current from the operating voltage VDD to transistor T5. When transistor T5 is turned on, the light emitting unit 230 can be driven by the driving current provided by transistor T5.

[0052] In this embodiment, transistor T3 can be a compensating transistor. The first terminal of transistor T3 receives the write signal Sn, and the second and third terminals of transistor T3 are coupled to the first and third terminals of transistor T1, respectively. Transistor T3 can compensate for the voltage at the first terminal of transistor T1.

[0053] In this embodiment, transistor T6 can be a reset transistor. The first terminal of transistor T6 can receive a reset signal RST. The second terminal of transistor T6 is coupled to a reset voltage Vrst. The third terminal of transistor T6 is coupled to capacitor C1 and the first terminal of transistor T1. In this embodiment, transistor T6 can be used to reset the potential of the first terminal of transistor T1.

[0054] In this embodiment, transistor T7 can be a reset transistor. The first terminal of transistor T7 can receive a reset signal RST. The second terminal of transistor T7 is coupled to a reference voltage Vref. The third terminal of transistor T7 is coupled to node N. Transistor T7 can be used to reset the potential of node N (i.e., the potential of one end of the storage capacitor Cst). In one embodiment, the voltage of the reference voltage Vref can be less than the voltage of the ground voltage VSS, but this disclosure is not limited thereto. Furthermore, the reference voltage Vref and the reset voltage Vrst are independent voltages. That is, the reference voltage Vref and the reset voltage Vrst can be given different voltage values ​​according to design requirements, and their voltage values ​​are not interfered with each other. In one embodiment, the voltage of the reference voltage Vref can be equal to the voltage of the reset voltage Vrst, but this disclosure is not limited thereto. In another embodiment, the reference voltage Vref and the reset voltage Vrst can be dependent voltages, that is, the voltage values ​​of the reference voltage Vref and the reset voltage Vrst will affect each other, but this disclosure is not limited thereto.

[0055] In this embodiment, transistor T8 can be a reset transistor. The first terminal of transistor T8 can receive a reset signal RST or a write signal Sn. The second terminal of transistor T8 is coupled to the anode AN of the light emitting unit 230. The third terminal of transistor T8 is coupled to the reset voltage Vrst. In this embodiment, transistor T8 can be used to reset the potential of the anode AN of the light emitting unit 230.

[0056] In this embodiment, transistors T9 and T10, along with capacitor C2, constitute compensation circuit 225-1. Transistor T9 can be a compensation transistor. Transistor T10 can be a reset transistor. One end of capacitor C2 is coupled to the first terminal of transistor T1, and the other end of capacitor C2 is coupled to the second terminals of transistors T9 and T10. The first terminal of transistor T9 can receive a write signal Sn. The third terminal of transistor T9 is coupled to the anode AN of the light emitting unit 230 or the ground voltage VSS. The first terminal of transistor T10 can receive a transmit signal EM. The third terminal of transistor T10 is coupled to the reset voltage Vrst. In this embodiment, compensation circuit 225-1 can compensate transistor T1 based on the voltage of the anode AN of the light emitting unit 230 or the ground voltage VSS.

[0057] In this embodiment, transistors T11 and T12, along with capacitor C3, constitute compensation circuit 225-2. According to some embodiments, transistor T12 may be a rechargeable transistor. One end of capacitor C3 is coupled to the first terminal of transistor T1, and the other end of capacitor C3 is coupled to the third terminals of both transistor T11 and T12. The first terminal of transistor T11 receives the transmit signal EM. The second terminal of transistor T11 is coupled to the operating voltage VDD. The first terminal of transistor T12 receives the write signal Sn. The third terminal of transistor T12 is coupled to the reset voltage Vrst. In this embodiment, compensation circuit 225-2 compensates transistor T1 based on the operating voltage VDD.

[0058] Figure 3 This is a signal timing diagram of one embodiment of the present disclosure. (See reference...) Figure 2 as well as Figure 3 , Figure 3 Signal timing can be applied to Figure 2The driving circuit 220 is described. Please refer to Table 1 below. In this embodiment, before time t0, the reset signal RST and the write signal Sn (for example, using a P-type transistor) are at high voltage potentials. During the reset period from time t0 to time t1, the reset signal RST switches to a low voltage potential, while the write signal Sn and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1, T6, T7, and T8 are turned on, and transistors T2-T5 and T9-T12 are turned off (or not conducting). When the first terminal of transistor T8 receives the write signal Sn, transistors T1, T6, and T7 are turned on, and transistors T2-T5 and T8-T12 are turned off. During the reset period, the voltage of node N is reset according to the reference voltage Vref, and the reference voltage Vref is reset according to the reset voltage Vrst. Therefore, during the reset period, the voltage of node N is the reference voltage Vef. The voltage at the first terminal of transistor T1 is approximately equal to the reset voltage Vrst. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is also the operating voltage VDD. It is worth noting that... Figure 3 Taking a P-type transistor as an example, but this disclosure is not limited to this.

[0059] During time t1 to time t2, the reset signal RST returns to a high voltage potential, and the write signal Sn and the transmit signal EM are also at high voltage potentials. During the compensation period from time t2 to time t3, the write signal Sn switches to a low voltage potential, while the reset signal RST and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1-T3, T9, and T12 are turned on, and transistors T4-T8, T10, and T11 are turned off. When the first terminal of transistor T8 receives the write signal Sn, transistors T1-T3, T8, T9, and T12 are turned on, and transistors T4-T7, T10, and T11 are turned off. During the compensation period, the data signal DA is written to the storage capacitor Cst, and transistor T3 compensates the first terminal of transistor T1 according to the operating voltage VDD. Therefore, during the compensation period, the voltage at node N is "Vda", where "Vda" is the voltage of the data signal DA. The voltage at the first terminal of transistor T1 is "VDD - |Vth|", where "|Vth|" is the threshold voltage of transistor T1. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "VDD - Vx", where "Vx" is a constant voltage value that can be used to offset the voltage effects caused by one or more transistor effects, such as the voltage effects caused by the kinke effect.

[0060] During time t3 to time t4, the write signal Sn returns to a high voltage potential, and the reset signal RST and the transmit signal EM are also at high voltage potentials. During the transmit period after time t4, the transmit signal EM switches to a low voltage potential, while the write signal Sn and the reset signal RST remain at high voltage potentials. Therefore, transistors T1, T4, T5, T10, and T11 are turned on, and transistors T2, T3, T6 to T9, and T12 are turned off. During the transmit period, the storage capacitor Cst and capacitor C1 provide corresponding voltages to the first terminal of transistor T1, so that transistor T1 drives the light emitting unit 230 using the corresponding drive current provided by the operating voltage VDD. During the transmit period, the voltage at node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is "(Vrst-Van)+(VDD-Vrst)+VDD-|Vth|+(Vref-Vda)", where "Van" is the voltage of the cathode of the light emitting unit 230. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "Van - VDD + Vx". Finally, the voltage difference between the second and first terminals of transistor T1, plus the compensation result Vsg + Vth of the threshold voltage of transistor T1, can be "Vx + (Vda - Vref)". Accordingly, the compensation result Vsg + Vth can reduce non-ideal bias, mitigate the effect of junction effect, or reduce the effect of voltage deviation of operating voltage VDD and ground voltage VSS.

[0061]

[0062] Table 1

[0063] Figure 4 This is a schematic diagram of the driving circuit of the second embodiment disclosed herein. (See reference) Figure 4 The electronic device 400 includes a substrate 410, a driving circuit 420, and a light emitting unit 430. Examples of the materials used in the substrate 410 can be found in the previously described examples of the materials used in the substrate 110, and will not be repeated here. The driving circuit 420 is disposed on the substrate 410 and includes transistors T1 to T10, capacitors C1 to C2, and a storage capacitor Cst. In this embodiment, the circuit coupling relationship between transistors T1 to T10 and the storage capacitor Cst is as follows: Figure 2 As described in the embodiments, the above can be referred to. Figure 2 The embodiments will not be described in detail here. Furthermore, it should be noted that transistors T5 and T10 in this embodiment can, for example, receive the same signal, such as the transmitted signal EM. More specifically, the first terminal of transistor T10 and the first terminal of transistor T5 can receive the same transmitted signal EM, but this disclosure is not limited thereto. Additionally, according to some embodiments, transistor T10 can be a compensation transistor. It should be understood that, for better understanding, some components will... Figure 4 The characters are omitted and / or simplified.

[0064] In this embodiment, transistors T9 and T10, along with capacitor C2, form compensation circuit 425. One end of capacitor C2 is coupled to the first terminal of transistor T1, and the other end of capacitor C2 is coupled to the second terminals of transistors T9 and T10. The first terminal of transistor T9 can receive a write signal Sn. The third terminal of transistor T9 is coupled to the anode AN of the light emitting unit 430 or receives the ground voltage VSS. The first terminal of transistor T10 can receive a transmit signal EM. The third terminal of transistor T10 can receive the operating voltage VDD. In this embodiment, compensation circuit 425 can compensate transistor T1 based on the operating voltage VDD and the voltage of the anode AN of the light emitting unit 430 or the ground voltage VSS.

[0065] refer to Figure 4 as well as Figure 3 , Figure 3 Signal timing can also be applied Figure 4 The driving circuit 420 is described. Please refer to Table 2 below. In this embodiment, before time t0, the reset signal RST and the write signal Sn (for example, a P-type transistor) are at high voltage potentials. During the reset period from time t0 to time t1, the reset signal RST switches to a low voltage potential, while the write signal Sn and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1, T6, T7, and T8 are turned on, and transistors T2-T5, T9, and T10 are turned off (or not conducting). When the first terminal of transistor T8 receives the write signal Sn, transistors T1, T6, and T7 are turned on, and transistors T2-T5 and T8-T12 are turned off. During the reset period, the voltage of node N is reset according to the reference voltage Vref, and the reference voltage Vref is reset according to the reset voltage Vrst. Therefore, during the reset period, the voltage of node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is the reset voltage Vrst. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is the operating voltage VDD.

[0066] During time t1 to time t2, the reset signal RST returns to a high voltage potential, and the write signal Sn and the transmit signal EM are also at high voltage potentials. During the compensation period from time t2 to time t3, the write signal Sn switches to a low voltage potential, while the reset signal RST and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1-T3 and T9 are turned on, and transistors T4-T8 and T10 are turned off. When the first terminal of transistor T8 receives the write signal Sn, transistors T1-T3 and T8-T9 are turned on, and transistors T4-T7 and T10 are turned off. During the compensation period, the data signal DA is written to the storage capacitor Cst, and transistor T3 compensates the first terminal of transistor T1 according to the operating voltage VDD. Therefore, during the compensation period, the voltage at node N is, for example, "Vda". The voltage at the first terminal of transistor T1 is "VDD-|Vth|". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "VDD-Vx".

[0067] During time t3 to time t4, the write signal Sn returns to a high voltage potential, and the reset signal RST and the transmit signal EM are also at high voltage potentials. During the transmit period after time t4, the transmit signal EM switches to a low voltage potential, while the write signal Sn and the reset signal RST remain at high voltage potentials. Therefore, transistors T1, T4, T5, and T10 are turned on, and transistors T2, T3, and T6 to T9 are turned off. During the transmit period, the storage capacitor Cst and capacitor C1 provide corresponding voltages to the first terminal of transistor T1, so that transistor T1 drives the optical emitting unit 430 using the corresponding drive current provided by the operating voltage VDD. During the transmit period, the voltage at node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is "(VDD-Van)+VDD-|Vth|+(Vref-Vda)". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "Van-VDD+Vx". Finally, the voltage Vsg+Vth, the compensation result of the voltage difference between the second and first terminals of transistor T1 plus the threshold voltage of transistor T1, can be "Vx+(Vda-Vref)". Accordingly, the compensation result Vsg+Vth can reduce the non-ideal bias voltage, or mitigate the effect of the junction effect, or reduce the effect of the operating voltage VDD and the ground voltage VSS voltage offset.

[0068]

[0069] Table 2

[0070] Figure 5 This is a schematic diagram of the driving circuit of the third embodiment disclosed herein. (See reference...) Figure 5 The electronic device 500 includes a substrate 510, a driving circuit 520, and a light emitting unit 530. Examples of the materials used in the substrate 510 can be found in the previously described examples of the materials used in the substrate 110, and will not be repeated here. The driving circuit 520 is disposed on the substrate 510 and includes transistors T1-T10, capacitors C1-C2, and a storage capacitor Cst. In this embodiment, the circuit coupling relationship between transistors T1-T8, capacitor C1, and storage capacitor Cst is as follows: Figure 2 As described in the embodiments, the above can be referred to. Figure 2 The embodiments will not be described in detail here. Furthermore, it should be noted that transistors T4, T5, and T10 in this embodiment can, for example, receive the same signal, such as the transmitted signal EM. More specifically, the first terminal of transistor T10, the first terminal of transistor T5, and the first terminal of transistor T4 can receive the same transmitted signal EM, but this disclosure is not limited thereto. Additionally, according to some embodiments, transistor T10 can be a compensation transistor. It should be understood that, for better understanding, some components will... Figure 5 The characters are omitted and / or simplified.

[0071] In this embodiment, transistors T9 and T10, along with capacitor C2, constitute a compensation circuit 525. One end of capacitor C2 is coupled to the first terminal of transistor T1, and the other end of capacitor C2 is coupled to the second terminals of transistors T9 and T10. The first terminal of transistor T9 can receive a write signal Sn. The third terminal of transistor T9 is coupled to the anode AN of the light emitting unit 530 or the ground voltage VSS. The first terminal of transistor T10 can receive a transmit signal EM. The third terminal of transistor T10 is coupled to a reset voltage Vrst. In this embodiment, the compensation circuit 525 can compensate transistor T1 based on the voltage of the anode AN of the light emitting unit 530 or the ground voltage VSS.

[0072] refer to Figure 5 as well as Figure 3 , Figure 3 Signal timing can also be applied Figure 5The driving circuit 520 is described. Please refer to Table 3 below. In this embodiment, before time t0, the reset signal RST and the write signal Sn (for example, using a P-type transistor) are at high voltage potentials. During the reset period from time t0 to time t1, the reset signal RST switches to a low voltage potential, while the write signal Sn and the transmit signal EM remain at high voltage potentials. Therefore, when the reset signal RST is received at the first terminal of transistor T8, transistors T1, T6, T7, and T8 are turned on, and transistors T2 to T5, T9, and T10 are turned off (or not conducting). When the write signal Sn is received at the first terminal of transistor T8, transistors T1, T6, and T7 are turned on, and transistors T2 to T5, T8, T9, and T10 are turned off. During the reset period, the voltage of node N is reset according to the reference voltage Vref, and the reference voltage Vref is reset according to the reset voltage Vrst. Therefore, during the reset period, the voltage of node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is the reset voltage Vrst. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is the operating voltage VDD.

[0073] During time t1 to time t2, the reset signal RST returns to a high voltage potential, and the write signal Sn and the transmit signal EM are also at high voltage potentials. During the compensation period from time t2 to time t3, the write signal Sn switches to a low voltage potential, while the reset signal RST and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1-T3 and T9 are turned on, and transistors T4-T8 and T10 are turned off. When the first terminal of transistor T8 receives the write signal Sn, transistors T1-T3, T8, and T9 are turned on, and transistors T4-T7 and T10 are turned off. During the compensation period, the data signal DA is written to the storage capacitor Cst, and transistor T3 compensates the first terminal of transistor T1 according to the operating voltage VDD. Therefore, during the compensation period, the voltage at node N is, for example, "Vda". The voltage at the first terminal of transistor T1 is "VDD-|Vth|". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "VDD-Vx".

[0074] During time t3 to time t4, the write signal Sn returns to a high voltage potential, and the reset signal RST and the transmit signal EM are also at high voltage potentials. During the transmit period after time t4, the transmit signal EM switches to a low voltage potential, while the write signal Sn and the reset signal RST remain at high voltage potentials. Therefore, transistors T1, T4, T5, and T10 are turned on, and transistors T2, T3, and T6 to T9 are turned off. During the transmit period, the storage capacitor Cst and capacitor C1 provide corresponding voltages to the first terminal of transistor T1, so that transistor T1 drives the optical emitting unit 530 using the corresponding drive current provided by the operating voltage VDD. During the transmit period, the voltage at node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is "(Vrst-Van)+VDD-|Vth|+(Vref-Vda)". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "Van-VDD+Vx". Finally, the voltage Vsg+Vth, the compensation result of the voltage difference between the second and first terminals of transistor T1 plus the threshold voltage of transistor T1, can be expressed as "VDD-Vrst+(Vda-Vref)+Vx". Accordingly, the compensation result Vsg+Vth can reduce the non-ideal bias voltage, mitigate the effect of the junction effect, or reduce the influence of the operating voltage VDD and the ground voltage VSS voltage offset.

[0075]

[0076] Table 3

[0077] Figure 6 This is a schematic diagram of the driving circuit of the fourth embodiment disclosed herein. (See reference...) Figure 6 The electronic device 600 includes a substrate 610, a driving circuit 620, and a light emitting unit 630. Examples of the materials used in the substrate 610 can be found in the previously described examples of the materials used in the substrate 110, and will not be repeated here. The driving circuit 620 is disposed on the substrate 610 and includes transistors T1-T8, T11, and T12, capacitors C1 and C3, and a storage capacitor Cst. In this embodiment, the circuit coupling relationships of transistors T1-T8, capacitor C1, and storage capacitor Cst are as follows: Figure 2 As described in the embodiments, the above can be referred to. Figure 2 The embodiments will not be described in detail here. Furthermore, it should be noted that transistors T5 and T11 in this embodiment can, for example, receive the same signal, such as the transmitted signal EM. More specifically, the first terminal of transistor T11 and the first terminal of transistor T5 can receive the same transmitted signal EM, but this disclosure is not limited thereto. Additionally, it should be understood that, according to some embodiments, transistor T11 can be a compensation transistor. For better understanding, some components will... Figure 6 The characters are omitted and / or simplified.

[0078] In this embodiment, transistors T11 and T12, along with capacitor C3, form a compensation circuit 625. One end of capacitor C3 is coupled to the first terminal of transistor T1, and the other end of capacitor C3 is coupled to the third terminals of both transistors T11 and T12. The first terminal of transistor T11 receives the transmit signal EM. The second terminal of transistor T11 is coupled to the operating voltage VDD. The first terminal of transistor T12 receives the write signal Sn. The second terminal of transistor T12 is coupled to the reset voltage Vrst. In this embodiment, the compensation circuit 625 compensates for transistor T1 based on the operating voltage VDD.

[0079] refer to Figure 6 as well as Figure 3 , Figure 3 Signal timing can also be applied Figure 6 The driving circuit 620 is described. Please refer to Table 4 below. In this embodiment, before time t0, the reset signal RST and the write signal Sn (for example, using a P-type transistor) are at high voltage potentials. During the reset period from time t0 to time t1, the reset signal RST switches to a low voltage potential, while the write signal Sn and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1, T6, T7, and T8 are turned on, and transistors T2-T5, T11, and T12 are turned off (or not conducting). When the first terminal of transistor T8 receives the write signal Sn, transistors T1, T6, and T7 are turned on, and transistors T2-T5, T8, T11, and T12 are turned off. During the reset period, the voltage of node N is reset according to the reference voltage Vref, and the reference voltage Vref is reset according to the reset voltage Vrst. Therefore, during the reset period, the voltage of node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is the reset voltage Vrst. The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is the operating voltage VDD.

[0080] During time t1 to time t2, the reset signal RST returns to a high voltage potential, and the write signal Sn and the transmit signal EM are also at high voltage potentials. During the compensation period from time t2 to time t3, the write signal Sn switches to a low voltage potential, while the reset signal RST and the transmit signal EM remain at high voltage potentials. Therefore, when the first terminal of transistor T8 receives the reset signal RST, transistors T1-T3 and T12 are turned on, and transistors T4-T8 and T11 are turned off. When the first terminal of transistor T8 receives the write signal Sn, transistors T1-T3, T8, and T12 are turned on, and transistors T4-T7 and T11 are turned off. During the compensation period, the data signal DA is written to the storage capacitor Cst, and transistor T3 compensates the first terminal of transistor T1 according to the operating voltage VDD. Therefore, during the compensation period, the voltage at node N is, for example, "Vda". The voltage at the first terminal of transistor T1 is "VDD-|Vth|". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "VDD-Vx".

[0081] During time t3 to time t4, the write signal Sn returns to a high voltage potential, and the reset signal RST and the transmit signal EM are also at high voltage potentials. During the transmit period after time t4, the transmit signal EM switches to a low voltage potential, while the write signal Sn and the reset signal RST remain at high voltage potentials. Therefore, transistors T1, T4, T5, and T10 are turned on, and transistors T2, T3, and T6 to T9 are turned off. During the transmit period, the storage capacitor Cst and capacitor C1 provide corresponding voltages to the first terminal of transistor T1, so that transistor T1 drives the optical emitting unit 630 using the corresponding drive current provided by the operating voltage VDD. During the transmit period, the voltage at node N is the reference voltage Vref. The voltage at the first terminal of transistor T1 is "(VDD-Vrst)+VDD-|Vth|+(Vref-Vda)". The voltage at the second terminal of transistor T1 is the operating voltage VDD. The voltage at the third terminal of transistor T1 is "Van-VDD+Vx". Finally, the voltage Vsg+Vth, the compensation result of the potential difference between the second and first terminals of transistor T1 plus the threshold voltage of transistor T1, can be expressed as "Vrst+(Vda-Vref)+Van+Vx". Accordingly, the compensation result Vsg+Vth can reduce the non-ideal bias voltage, or mitigate the effect of the junction effect, or reduce the effect of the operating voltage VDD and the ground voltage VSS voltage offset.

[0082]

[0083] Table 4

[0084] Figure 7This is a schematic diagram of the current-voltage curves of one embodiment of this disclosure. (Reference) Figure 7 , Figure 7 The current-voltage curve 701 can correspond to Figure 2 The driving circuit 220 compensates the transistor T1 according to the working voltage VDD through the compensation circuit 225-1, or it can correspond to... Figure 4 The driving circuit 420 compensates the transistor T1 according to the operating voltage VDD through the compensation circuit 425, or may correspond to Figure 6 The driving circuit 620 compensates the transistor T1 based on the operating voltage VDD through the compensation circuit 625. For example... Figure 7 As shown, when transistor T1 enters the saturation region, the current-voltage curve 701 of transistor T1 can still maintain a stable current value even when the operating voltage VDD drifts (for example, between 7V and 9V).

[0085] Figure 8 This is a schematic diagram of the current-voltage curves of another embodiment of this disclosure. (Reference) Figure 8 , Figure 8 The current-voltage curve 801 can correspond to Figure 2 The driving circuit 220 compensates the transistor T1 based on the voltage of the anode AN of the light emitting unit 230 through the compensation circuit 225-2, or it can correspond to... Figure 4 The driving circuit 420 compensates the transistor T1 based on the voltage of the anode AN of the light emitting unit 430 through the compensation circuit 425, or may correspond to Figure 5 The driving circuit 520 compensates the transistor T1 based on the voltage of the anode AN of the light emitting unit 530 via the compensation circuit 525. For example... Figure 8 As shown in the current-voltage curve 801, when transistor T1 enters the saturation region, the current-voltage curve 801 of transistor T1 can still maintain a stable current value even when the ground voltage VSS drifts (for example, between -2V and 0V).

[0086] Figure 8 The current-voltage curve 802 can correspond to Figure 2 The driving circuit 220 compensates the transistor T1 based on the ground voltage VSS through the compensation circuit 225-2, or it can correspond to... Figure 4 The driving circuit 420 compensates the transistor T1 based on the ground voltage VSS through the compensation circuit 425, or may correspond to Figure 5 The driving circuit 520 compensates the transistor T1 based on the ground voltage VSS through the compensation circuit 525. For example... Figure 8As shown in the current-voltage curve 802, when transistor T1 enters the saturation region, the current-voltage curve 801 of transistor T1 can still maintain a stable current value even when the ground voltage VSS drifts (for example, between -2V and 0V).

[0087] Furthermore, when analyzing or providing evidence regarding electronic products, if the driving circuit of the electronic product contains a transistor that includes a compensation circuit as described in the above embodiments, or has such... Figure 7 , Figure 8 The current-voltage curve characteristics can be regarded as the circuit design architecture for implementing the present disclosure of this electronic product.

[0088] In summary, the driving circuit and electronic device disclosed herein for driving optical emitting units can effectively compensate the driving transistor by designing a compensation circuit to couple any node on the driving current path to the first terminal of the driving transistor, such as the gate, and by using a transistor switching timing with a compensation period. This compensation result can reduce non-ideal bias voltage, mitigate the effects of junction effects, or reduce the effects of operating voltage and ground voltage offset.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. A driving circuit for driving an optical emitting unit, characterized in that, Include: Drive transistors; Switching transistors; A light-up transistor is coupled between the light-emitting unit and the driving transistor; A first capacitor, wherein a first terminal of the first capacitor is coupled to the gate of the driving transistor; A first reset transistor, wherein a first terminal of the first reset transistor is coupled to a second terminal of the first capacitor, and a second terminal of the first reset transistor is coupled to a reset voltage; A first compensation transistor, wherein a first terminal of the first compensation transistor is coupled to a second terminal of the first capacitor, and a second terminal of the first compensation transistor is coupled to an operating voltage, wherein the reset voltage coupled to the second terminal of the first reset transistor is different from the operating voltage coupled to the second terminal of the first compensation transistor, wherein the gate of the first compensation transistor and the gate of the lighting transistor receive the same signal. A storage capacitor, wherein a first terminal of the storage capacitor is coupled to the gate of the driving transistor and a first terminal of the first capacitor; A second reset transistor, wherein a first terminal of the second reset transistor is coupled to a second terminal of the storage capacitor to perform a reset operation on the second terminal of the storage capacitor, and the second terminal of the second reset transistor is coupled to a reference voltage; as well as A first transistor, wherein a first terminal of the first transistor is coupled to a second terminal of the storage capacitor and a first terminal of the switching transistor, and a second terminal of the first transistor is coupled to the reference voltage.

2. The driving circuit according to claim 1, characterized in that, Also includes: Second capacitor; as well as The second compensation transistor has one end coupled to the anode of the light emitting unit and the other end coupled to the second capacitor.

3. The driving circuit according to claim 2, characterized in that, Also includes: The third reset transistor has one end coupled to the second capacitor and the other end coupled to the reset voltage.

4. The driving circuit according to claim 1, characterized in that, Also includes: Second capacitor; as well as The second compensation transistor has one end coupled to the cathode of the light emitting unit and the other end coupled to the second capacitor.

5. The driving circuit according to claim 4, characterized in that, Also includes: The third reset transistor has one end coupled to the second capacitor and the other end coupled to the reset voltage.

6. The driving circuit according to claim 1, characterized in that, Also includes: The second compensation transistor has one end coupled to the anode of the light emitting unit and the other end coupled to the first capacitor.

7. The driving circuit according to claim 1, characterized in that, Also includes: The second compensation transistor has one end coupled to the cathode of the light emitting unit and the other end coupled to the first capacitor.

8. The driving circuit according to claim 1, characterized in that, Also includes: The fourth reset transistor has one end coupled to the anode of the light emitting unit and the other end coupled to the reset voltage.

9. An electronic device, characterized in that, Include: substrate; A light emitting unit is disposed on the substrate; and A driving circuit is disposed on the substrate, wherein the driving circuit drives the light emitting unit, and the driving circuit includes: Drive transistors; Switching transistors; A light-up transistor is coupled between the light-emitting unit and the driving transistor; A first capacitor, wherein a first terminal of the first capacitor is coupled to the driving transistor; A first reset transistor, wherein a first terminal of the first reset transistor is coupled to a second terminal of the first capacitor, and a second terminal of the first reset transistor is coupled to a reset voltage; A first compensation transistor, wherein a first terminal of the first compensation transistor is coupled to a second terminal of the first capacitor, and a second terminal of the first compensation transistor is coupled to an operating voltage, wherein the reset voltage coupled to the second terminal of the first reset transistor is different from the operating voltage coupled to the second terminal of the first compensation transistor, wherein the gate of the first compensation transistor and the gate of the lighting transistor receive the same signal. A storage capacitor, wherein a first terminal of the storage capacitor is coupled to the gate of the driving transistor and a first terminal of the first capacitor; A second reset transistor, wherein a first terminal of the second reset transistor is coupled to a second terminal of the storage capacitor to perform a reset operation on the second terminal of the storage capacitor, and the second terminal of the second reset transistor is coupled to a reference voltage; as well as A first transistor, wherein a first terminal of the first transistor is coupled to a second terminal of the storage capacitor and a first terminal of the switching transistor, and a second terminal of the first transistor is coupled to the reference voltage.

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