Charge pump circuit, memory and storage system

Abstract

The application provides a charge pump circuit, a memory and a storage system, and belongs to the technical field of storage. In the scheme provided by the application, the charge pump circuit comprises a first charge pump and a first voltage clamping circuit connected in parallel with the first charge pump. When the voltage difference between the output end and the input end of the first charge pump is greater than or equal to the threshold voltage of the first voltage clamping circuit, the first voltage clamping circuit can be turned on, so as to clamp the voltage difference between the output end and the input end of the first charge pump to the threshold voltage. Therefore, the risk of damage of a low-voltage transistor in the first charge pump can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a charge pump circuit, a memory, and a storage system. Background Technology

[0002] A memory typically consists of a memory array and peripheral circuitry. The peripheral circuitry is used to apply a programming voltage to the memory array to write data into it, and to apply a read voltage to the memory array to read data from it.

[0003] The peripheral circuit typically includes a charge pump composed of transistors and capacitors. The input of this charge pump is connected to the power supply, and its output is connected to the memory array. The charge pump can boost the lower power supply voltage received at its input and output it, thereby providing a higher programming, erasing, or reading voltage for the memory array. Furthermore, when the voltage to be applied to the memory array needs to be lowered, the charge pump can also discharge at both its input and output terminals to reduce the output voltage.

[0004] However, if the discharge rates at the input and output terminals of the charge pump are different, an excessively large voltage difference may occur between them. This excessive voltage difference can cause the voltage applied to the transistor in the charge pump to exceed the transistor's withstand voltage, leading to transistor failure. Summary of the Invention

[0005] This application provides a charge pump circuit, a memory, and a storage system, which can solve the technical problem in related technologies where transistors may fail during discharge in charge pumps. The technical solution is as follows:

[0006] On one hand, a charge pump circuit is provided, the charge pump circuit comprising: a first charge pump and a first voltage clamping circuit;

[0007] The first charge pump has a first input terminal and a first output terminal. The first charge pump is used to boost the input voltage at the first input terminal and then transmit it to the first output terminal.

[0008] The first voltage clamping circuit has a first connection terminal and a second connection terminal, the first connection terminal being connected to the first input terminal and the second connection terminal being connected to the first output terminal;

[0009] The first voltage clamping circuit is used to form a current path between the first connection terminal and the second connection terminal if the first voltage difference obtained by subtracting the voltage of the first connection terminal from the voltage of the second connection terminal is greater than or equal to the threshold voltage of the first voltage clamping circuit.

[0010] Optionally, the first voltage clamping circuit is further configured to disconnect the first connection terminal from the second connection terminal if the first voltage difference is less than the threshold voltage of the first voltage clamping circuit.

[0011] Optionally, the first voltage clamping circuit further has at least one control terminal, which is used to connect to the threshold control circuit;

[0012] The first voltage clamping circuit is further configured to adjust the magnitude of the threshold voltage of the first voltage clamping circuit based on the control signal output by the threshold control circuit to the at least one control terminal.

[0013] Optionally, the first voltage clamping circuit includes: a switching sub-circuit, and at least two clamping sub-circuits connected in series between the first connection terminal and the second connection terminal;

[0014] The switching sub-circuit is connected to the at least one control terminal, the target connection terminal, and the series node between each of the two adjacent clamping sub-circuits, respectively. The target connection terminal is either the first connection terminal or the second connection terminal.

[0015] The switching sub-circuit is used to form a current path between the target connection terminal and one of the series nodes based on the control signal received by the at least one control terminal.

[0016] Optionally, the switching sub-circuit includes at least one switching transistor corresponding to each of the at least one control terminal;

[0017] The gate of each of the at least one switching transistors is connected to a corresponding control terminal, the first terminal of each switching transistor is connected to a series node, and the second terminal of each switching transistor is connected to the target connection terminal.

[0018] Optionally, the first voltage clamping circuit includes: one first transistor or multiple first transistors; wherein the gate of each first transistor is connected to a first terminal or a second terminal;

[0019] Furthermore, in the plurality of first transistors, the first terminal of one of every two adjacent first transistors is connected to the second terminal of the other first transistor.

[0020] Optionally, the charge pump circuit further includes: a second charge pump and a second voltage clamping circuit;

[0021] The second charge pump is connected in series or in parallel with the first charge pump, and the second charge pump has a second input terminal and a second output terminal. The second charge pump is used to boost the input voltage at the second input terminal and then transmit it to the second output terminal.

[0022] The second voltage clamping circuit has a third connection terminal and a fourth connection terminal, the third connection terminal being connected to the second input terminal and the fourth connection terminal being connected to the second output terminal;

[0023] The second voltage clamping circuit is used to form a current path between the third connection terminal and the fourth connection terminal if the second voltage difference obtained by subtracting the voltage of the third connection terminal from the voltage of the fourth connection terminal is greater than or equal to the threshold voltage of the second voltage clamping circuit.

[0024] Optionally, the second voltage clamping circuit is further configured to disconnect the third connection terminal from the fourth connection terminal if the second voltage difference is less than the threshold voltage of the second voltage clamping circuit.

[0025] Optionally, the charge pump circuit further includes: a cascaded switch circuit;

[0026] The cascaded switch circuit is connected to the first input terminal, the first output terminal, the second input terminal, and the second output terminal respectively. The cascaded switch circuit is used to control the connection state between the first input terminal, the first output terminal, the second input terminal, and the second output terminal.

[0027] Optionally, the first charge pump includes a plurality of transistors, among which at least one target transistor is included; the charge pump circuit further includes at least one third voltage clamping circuit corresponding one-to-one with the at least one target transistor;

[0028] Each of the at least one third voltage clamping circuits has a fifth connection terminal and a sixth connection terminal, the fifth connection terminal being connected to the first terminal of a corresponding target transistor, and the sixth connection terminal being connected to the second terminal of a corresponding target transistor.

[0029] Each of the at least one third voltage clamping circuits is configured to form a current path between the fifth connection terminal and the sixth connection terminal if the third voltage difference obtained by subtracting the voltage of the sixth connection terminal from the voltage of the fifth connection terminal is greater than or equal to the threshold voltage of the third voltage clamping circuit.

[0030] Optionally, each of the at least one third voltage clamping circuits is further configured to disconnect the fifth connection terminal from the sixth connection terminal if the third voltage difference is less than the threshold voltage of the third voltage clamping circuit.

[0031] Optionally, each of the at least one third voltage clamping circuits includes: a second transistor;

[0032] The first terminal of the second transistor is connected to the fifth connection terminal, and the gate and second terminal of the second transistor are both connected to the sixth connection terminal.

[0033] Optionally, the first charge pump is a cross-coupled charge pump, and the at least one target transistor is a P-type transistor in the cross-coupled charge pump, with the second terminal of the P-type transistor connected to the first output terminal.

[0034] On the other hand, a charge pump circuit is provided, the charge pump circuit comprising: a charge pump and at least one voltage clamping circuit;

[0035] The charge pump has an input terminal and an output terminal, and the charge pump is used to boost the input voltage at the input terminal and then transmit it to the output terminal;

[0036] The at least one voltage clamping circuit corresponds one-to-one with at least one target transistor in the charge pump, and each voltage clamping circuit has a first clamping terminal and a second clamping terminal. The first clamping terminal is connected to the first electrode of the corresponding target transistor, and the second clamping terminal is connected to the second electrode of the corresponding target transistor.

[0037] Each of the at least one voltage clamping circuits is configured to form a current path between the first clamping terminal and the second clamping terminal if the voltage difference obtained by subtracting the voltage of the second clamping terminal from the voltage of the first clamping terminal is greater than or equal to the threshold voltage of the voltage clamping circuit.

[0038] Optionally, the voltage clamping circuit is further configured to disconnect the first clamping terminal from the second clamping terminal if the voltage difference is less than the threshold voltage of the voltage clamping circuit.

[0039] Optionally, each voltage clamping circuit in the at least one voltage clamping circuit includes: a transistor; the first terminal of the transistor is connected to the first clamping terminal, and the gate and second terminal of the transistor are both connected to the second clamping terminal.

[0040] Optionally, the charge pump is a cross-coupled charge pump, and the at least one target transistor is a P-type transistor in the cross-coupled charge pump, with the second terminal of the P-type transistor connected to the output terminal.

[0041] In another aspect, a memory is provided, the memory comprising: a memory array and peripheral circuitry, the peripheral circuitry comprising a charge pump circuitry as provided in the above aspects.

[0042] Optionally, the peripheral circuit further includes: a threshold control circuit;

[0043] The threshold control circuit is connected to at least one control terminal of the first voltage clamping circuit in the charge pump circuit, and the threshold control circuit is used for:

[0044] If the first charge pump in the charge pump circuit is in a charging state, a first control signal is provided to at least one control terminal of the first voltage clamping circuit. The first control signal is used to control the threshold voltage of the first voltage clamping circuit to be a first voltage.

[0045] If the first charge pump is in the target state, a second control signal is provided to at least one control terminal of the first voltage clamping circuit. The second control signal is used to control the threshold voltage of the first voltage clamping circuit to be a second voltage, which is less than the first voltage.

[0046] The target states include: a discharge state, a non-operating state, or a state that switches to a cascade relationship with other charge pumps.

[0047] In another aspect, a storage system is provided, the storage system comprising: a memory controller, and at least one memory as provided above.

[0048] The technical solution provided in this application may include the following beneficial effects:

[0049] This application provides a charge pump circuit, a memory, and a storage system. In this charge pump circuit, a first voltage clamping circuit is connected in parallel with a first charge pump. When the voltage difference between the output and input terminals of the first charge pump is greater than or equal to a threshold voltage of the first voltage clamping circuit, the first voltage clamping circuit is activated, thereby clamping the voltage difference between the output and input terminals of the first charge pump to the threshold voltage. This effectively reduces the risk of damage to the low-voltage transistors in the first charge pump. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0052] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0053] Figure 3This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of the structure of a charge pump provided in an embodiment of this application;

[0055] Figure 5 This is a schematic diagram of a parallel charge pump structure provided in an embodiment of this application;

[0056] Figure 6 This is a schematic diagram of a charge pump connected in series according to an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of a charge pump circuit provided in an embodiment of this application;

[0058] Figure 8 This is a schematic diagram of another charge pump circuit provided in an embodiment of this application;

[0059] Figure 9 This is a schematic diagram of the structure of a first voltage clamping circuit provided in an embodiment of this application;

[0060] Figure 10 This is a schematic diagram of another first voltage clamping circuit provided in the embodiments of this application;

[0061] Figure 11 This is a schematic diagram of another first voltage clamping circuit provided in the embodiments of this application;

[0062] Figure 12 This is a schematic diagram of another first voltage clamping circuit provided in the embodiments of this application;

[0063] Figure 13 This is a schematic diagram of the current flowing between a first connection terminal and a second connection terminal provided in an embodiment of this application;

[0064] Figure 14 This is a schematic diagram of another current flowing between the first connection terminal and the second connection terminal provided in an embodiment of this application;

[0065] Figure 15 This is a schematic diagram of another charge pump circuit provided in the embodiments of this application;

[0066] Figure 16 This is a schematic diagram of another charge pump circuit provided in the embodiments of this application;

[0067] Figure 17 This is a schematic diagram of another charge pump circuit provided in the embodiments of this application;

[0068] Figure 18This is a schematic diagram showing the change of voltage difference between nodes in a charge pump circuit over time, as provided in an embodiment of this application.

[0069] Figure 19 This is a schematic diagram showing the voltage difference between nodes over time in another charge pump circuit provided in this application embodiment. Detailed Implementation

[0070] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0071] The solutions provided in this application can be applied to electronic devices. These electronic devices can be mobile terminals, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality devices, augmented reality devices, or any other suitable electronic device having memory.

[0072] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1 As shown, the electronic device includes a storage system 1000 and a host 2000. The host 2000 can be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 2000 is used to send data to the storage system 1000 for storage, or to read data from the storage system 1000.

[0073] refer to Figure 1 The storage system 1000 includes a memory controller 000 and at least one memory 100 for storing data, for example... Figure 1 Multiple memories 100 are shown. Each memory 100 can be a three-dimensional (3D) memory, such as a 3D NAND flash memory. A memory controller 000 is connected to both the memory 100 and the host 2000. The memory controller 000 is used to manage the data stored in the memory 100 and to communicate with the host 2000.

[0074] In this embodiment, the memory controller 000 and at least one memory 100 can be integrated, meaning the storage system 1000 can be integrated into a single storage device. As a possible example, the memory controller 000 and a single memory 100 can be integrated into a memory card. This memory card may include PCMCIA cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, multi-media cards (MMC), secure digital (SD) cards, and universal flash storage (UFS), etc. As another possible example, the memory controller 000 and multiple memories 100 can be integrated into a solid-state disk (SSD).

[0075] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 2 As shown, the memory 100 includes peripheral circuitry 110 and a memory array 120. The peripheral circuitry 110 is used to write data into the memory array 120 and to read data from the memory array 120. Figure 3 This is a schematic diagram of a storage array structure provided in an embodiment of this application, with reference to... Figure 3 The memory array 120 may include a plurality of memory strings 121, which are arranged along a bearing surface parallel to the substrate (i.e., Figure 3 The memory cells are arranged in the XY plane of the substrate. Each memory string 121 includes multiple memory cells connected in series, which are arranged in a direction perpendicular to the bearing surface of the substrate (i.e., the XY plane of the substrate). Figure 3 The memory cells are arranged in the Z-direction. Each memory cell can be a floating-gate field-effect transistor or a charge-trap field-effect transistor.

[0076] like Figure 3 As shown, each memory string 121 also includes at least one upper select transistor connected to the first pole of the first memory cell, and at least one lower select transistor connected to the second pole of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor, and the lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0077] Each TSG's gate is connected to the drain select line (DSL), and the second terminal of each TSG is connected to the first terminal of the first memory cell in its memory string. The first terminal of each TSG is also connected to the bit line (BL). Each BSG's gate is connected to the source select line (SSL), and the first terminal of each BSG is connected to the second terminal of the last memory cell in its memory string. The second terminal of each BSG is also connected to the source line (SL). It is understood that the first terminal mentioned above can refer to either the source or the drain, and the second terminal can refer to the other. For example, the first terminal could refer to the drain, and the second terminal could refer to the source.

[0078] from Figure 3 As can be seen, the memory array 120 includes n BLs (BL1 to BLn) arranged along the X direction, x DSLs (DSL1 to DSLx) arranged along the Y direction, and x SSLs (SSL1 to SSLx) arranged along the Y direction. Here, n and x are both integers greater than 1. Each DSL is connected to the gate of the n TSGs arranged along the X direction, each BL is connected to the first electrode of the x TSGs arranged along the Y direction, and each SSL is connected to the gate of the n BSGs arranged along the X direction. Furthermore, the second electrode of each BSG is connected to the same SL.

[0079] Continue to refer to Figure 3 Each memory cell in a memory string 121 shares a set of memory lines (WLs) with memory cells in other memory strings 121. Assuming each memory string 121 includes m memory cells, the memory array 120 can include m WLs arranged along the Z direction: WL1 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., having the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell located on the same layer, and the gate connection lines between the control gates, constitute a WL.

[0080] Peripheral circuitry 110 can be connected to storage array 120 via BL, WL, DSL, SSL, and SL. For example... Figure 2 As shown, the peripheral circuit 110 may include a charge pump circuit 111, a page buffer (also known as a sense amplifier) ​​112, a column decoder (also known as a bit line driver) 113, a row decoder (also known as a word line driver) 114, and a control logic circuit 115.

[0081] The charge pump circuit 111 is connected to the control logic circuit 115 and is used to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, and verification voltage), bit line voltages, and source line voltages for loading onto the memory array 120 under the control of the control logic circuit 115.

[0082] Page buffer 112 is used to read data from memory array 120 under the control of control logic circuitry 115. In one example, page buffer 112 may store data to be programmed into memory array 120. In another example, page buffer 112 may perform a programming verification operation to ensure that data has been correctly programmed into the memory cell connected to the selected word line. In yet another example, page buffer 112 may also sense voltage signals from bit lines representing data bits stored in the memory cell and amplify the sensed voltage signals to a recognizable logic level.

[0083] The column decoder 113 is connected to each bit line of the memory array 120 and is used to apply bit line voltage from the charge pump circuit 111 to each bit line of the memory array 120 under the control of the control logic circuit 115.

[0084] The row decoder 114 is connected to each row line of the memory array 120 and, under the control of the control logic circuit 115, applies row line voltages from the charge pump circuit 111 to each row line of the memory array 120. Each row line of the memory array 120 includes a word line, a drain select line, a source select line, and a source line. For example, during the programming phase, the row decoder 114, under the control of the control logic circuit 115, can apply a programming voltage to selected word lines and a pass voltage to non-selected word lines.

[0085] The working principle of charge pump circuit 111 is described below. Charge pump circuit 111 may include multiple charge pumps, each of which may be a cross-coupled charge pump, also known as a Pelliconi charge pump. Figure 4 This is a schematic diagram of a cross-coupled charge pump provided in an embodiment of this application. Figure 4 As shown, the cross-coupled charge pump has an input terminal VIN and an output terminal VOUT, and includes two N-type transistors MN1 and MN2, two P-type transistors MP1 and MP2, and two capacitors C1 and C2. Both the two N-type transistors and the two P-type transistors can be MOSFETs.

[0086] In this configuration, the gate of MN1 is connected to the first node P1, the first electrode is connected to the second node P2, and the second electrode is connected to the input terminal VIN; the gate of MN2 is connected to the second node P2, the first electrode is connected to the first node P1, and the second electrode is connected to the input terminal VIN.

[0087] MP1's gate is connected to the second node P2, its first terminal is connected to the first node P1, and its second terminal is connected to the output terminal VOUT; MP2's gate is connected to the first node P1, its first terminal is connected to the second node P2, and its second terminal is connected to the output terminal VOUT.

[0088] One end of capacitor C1 is connected to the first clock signal terminal CLK1, and the other end is connected to the first node P1. One end of capacitor C2 is connected to the second clock signal terminal CLK2, and the other end is connected to the second node P2. The first clock signal terminal CLK1 is used to provide the first clock signal, and the second clock signal terminal CLK2 is used to provide the second clock signal. The first clock signal and the second clock signal have the same frequency but opposite phase. That is, when the first clock signal is high, the second clock signal is low; when the first clock signal is low, the second clock signal is high.

[0089] Assuming the input voltage received at input terminal VIN is VDD, and the amplitudes of the first clock signal and the second clock signal are both V... CK That is, the voltage when the clock signal is high is V. CK If, in the initial transient, the first clock signal is low and the second clock signal is high (i.e., CLK1 = 0, CLK2 = V), then... CK If the voltage at node P1 is pulled low, the voltage at node P2 is pulled high. At this time, MN1 and MP1 are turned off, and MN2 and MP2 are turned on. The input terminal VIN sets the voltage at node P1 to VDD through MN2, and the voltage at the output terminal VOUT is equal to the voltage at node P2.

[0090] Subsequently, during the first clock cycle, the first clock signal is high and the second clock signal is low (i.e., CLK1 = V). CK (CLK2 = 0). Since the voltage across the capacitor cannot change abruptly, the voltage at the first node P1 will be pulled up to VDD + V by capacitor C1. CK The voltage at the second node P2 will be pulled low by capacitor C2. At this time, MN1 and MP1 are turned on, while MN2 and MP2 are turned off. The input terminal VIN sets the voltage at the second node P2 to VDD through MN1, and the voltage at the output terminal VOUT is equal to the voltage at the first node P1, VDD + V. CK .

[0091] In the second clock cycle, the level of the first clock signal transitions to low, and the level of the second clock signal transitions to high (i.e., CLK1 = 0, CLK2 = V). CK Since the voltage across a capacitor cannot change abruptly, the voltage at the second node P2 will be pulled up to VDD+V by capacitor C2. CKThe voltage at the first node P1 will be pulled low by capacitor C1. At this time, MN2 and MP2 are turned on, while MN1 and MP1 are turned off. The input terminal VIN sets the voltage at the first node P1 to VDD through MN2, and the voltage at the output terminal VOUT is equal to the voltage at the second node P2, VDD + V. CK .

[0092] As the levels of the first and second clock signals change from high to low, the cross-coupled charge pump alternately repeats the states of the first and second clock cycles to ensure that the voltage at the output terminal VOUT remains constant at VDD+V. CK That is, the boost voltage of this cross-coupled charge pump to its input voltage can be Vck, where V... CK It can be equal to VDD.

[0093] Figure 5 This is a schematic diagram of a parallel charge pump structure provided in an embodiment of this application, as shown below. Figure 5 As shown, the charge pump circuit can include N charge pumps connected in parallel, from CP1 to CPN. N is an integer greater than 1. The input terminals VIN of these N charge pumps are connected together to form the input terminal of the charge pump circuit, and the output terminals VOUT of these N charge pumps are connected together to form the input terminal of the charge pump circuit. By connecting multiple charge pumps in parallel, the output current of the charge pump circuit can be effectively increased while boosting the power supply voltage.

[0094] Figure 6 This is a schematic diagram of a charge pump connected in series according to an embodiment of this application, as shown below. Figure 6 Therefore, the charge pump circuit can include N charge pumps connected in series, from CP1 to CPN. The input terminal VIN of the first charge pump is the input terminal of the charge pump circuit. The input terminals of the second to Nth charge pumps are all connected to the output terminal of the preceding charge pump. The output terminal VOUT of the last charge pump is the output terminal of the charge pump circuit. By connecting multiple charge pumps in series, the power supply voltage can be amplified step-by-step, thereby effectively increasing the voltage boost. For example, assuming that the voltage boost of each charge pump is Vck, then after connecting N charge pumps in series, the final output voltage of the charge pump circuit can achieve a voltage boost of N×Vck compared to the power supply voltage.

[0095] Understandably, during the various operations (such as programming, reading, and erasing) performed on the memory array 120 by the peripheral circuit 110, the voltage to be applied to the memory array 120 will continuously change, and therefore the output voltage required by the charge pump circuit 111 will also continuously change. The charge pump circuit 111 can typically adjust its output voltage in the following ways:

[0096] As a first possible implementation, the charge pump circuit 111 may also include a cascaded switching circuit. This cascaded switching circuit can be connected to the input and output terminals of each charge pump separately, and the number of charge pumps connected in series (or in parallel) in the charge pump circuit can be adjusted by changing the connection relationship between the input and output terminals of each charge pump, thereby adjusting the output voltage of the charge pump circuit. For example, when it is necessary to increase the output voltage of the charge pump circuit, the number of charge pumps connected in series in the charge pump circuit can be increased; when it is necessary to decrease the output voltage of the charge pump circuit, the number of charge pumps connected in series in the charge pump circuit can be decreased.

[0097] As a second possible implementation, the charge pump circuit 111 may further include multiple discharge switches. At least one input and output terminal of the charge pump may also be connected to a low-voltage discharge terminal via a discharge switch. When it is necessary to reduce the output voltage of the charge pump circuit, the discharge switch can be closed, allowing the input and output terminals of the charge pump to discharge to the discharge terminal respectively, thereby reducing the output voltage of the charge pump circuit.

[0098] As a third possible implementation, the output of the charge pump circuit 111 can also be connected to a power supply circuit via a charging switch, which can provide a higher voltage. When it is necessary to increase the output voltage of the charge pump circuit, the charging switch can be closed, and the power supply circuit can then directly pull up the output voltage of the charge pump circuit.

[0099] Understandably, when the charge pump circuit 111 is operating normally, the voltage difference between the output voltage at the output terminal VOUT and the input voltage at the input terminal VIN of each charge pump is generally less than or equal to the amplitude Vck of the clock signal. However, the following situations can cause the voltage difference between the output voltage and the input voltage to be too large:

[0100] 1. When the charge pump discharges, if the discharge rates at the input terminal VIN and the output terminal VOUT are different, it may result in an excessive voltage difference between the output voltage and the input voltage.

[0101] 2. When the number of charge pumps connected in series in a charge pump circuit changes, it may cause a sudden change in the input or output voltage of a certain charge pump, which in turn leads to an excessive voltage difference between the output voltage and the input voltage of that charge pump.

[0102] 3. When the charge pump is not working, that is, when the clock signal terminal connected to the charge pump does not provide a clock signal, if the voltage of the output terminal VOUT of the charge pump is pulled high by other circuits (such as power supply circuits), and the input voltage of the input terminal VIN remains unchanged, it will cause the voltage difference between the output voltage and the input voltage of the charge pump to be too large.

[0103] Because charge pumps contain some low-voltage transistors (such as P-type transistors MP1 and MP2), a large voltage difference between the output and input voltages can cause excessive voltage to be applied to these low-voltage transistors, leading them to operate outside their safe operating area (SOA). In other words, when the voltage difference between the output and input voltages is too large, the low-voltage transistors in the charge pump are at risk of burning out.

[0104] This application provides a charge pump circuit in which a voltage clamping circuit can clamp the voltage difference between the output and input terminals of the charge pump, thereby effectively reducing the risk of damage to the low-voltage transistors in the charge pump. Figure 7 As shown, the charge pump circuit 111 provided in this application embodiment includes: a first charge pump 10 and a first voltage clamping circuit 20.

[0105] The first charge pump 10 has a first input terminal VIN1 and a first output terminal VOUT1. The first charge pump 10 is used to boost the input voltage of the first input terminal VIN1 and then transmit it to the first output terminal VOUT1.

[0106] The first voltage clamping circuit 20 has a first connection terminal L1 and a second connection terminal L2. The first connection terminal L1 is connected to the first input terminal VIN1, and the second connection terminal L2 is connected to the first output terminal VOUT1, that is, the first voltage clamping circuit 20 is connected in parallel with the first charge pump 10. The first voltage clamping circuit 20 is used for:

[0107] If the first voltage difference obtained by subtracting the voltage of the first connection terminal L1 from the voltage of the second connection terminal L2 is greater than or equal to the threshold voltage of the first voltage clamping circuit 20, a current path is formed between the first connection terminal L1 and the second connection terminal L2, that is, the first voltage clamping circuit 20 can be turned on.

[0108] The threshold voltage of the first voltage clamping circuit 20 can be the lowest voltage required to turn on the first voltage clamping circuit 20. Accordingly, after the first voltage clamping circuit 20 is turned on and forms a current path, the voltage drop of the current path is equal to the threshold voltage of the first voltage clamping circuit 20.

[0109] It is understandable that, since the first voltage clamping circuit 20 is connected in parallel with the first charge pump 10, when a current path is formed between the first connection terminal L1 and the second connection terminal L2, the voltage difference between the first output terminal VOUT1 and the first input terminal VIN1 can be clamped to the threshold voltage of the first voltage clamping circuit 20. The voltage difference between the first output terminal VOUT1 and the first input terminal VIN1 refers to the difference between the voltage at the first output terminal VOUT1 and the voltage at the first input terminal VIN1.

[0110] Based on the above analysis, it can be seen that when the voltage difference between the first output terminal VOUT1 and the first input terminal VIN1 of the first charge pump 10 is greater than or equal to the threshold voltage of the first voltage clamping circuit 20, the two connection terminals of the first voltage clamping circuit 20 are turned on, thereby clamping the voltage difference between the first output terminal VOUT1 and the first input terminal VIN1 to the threshold voltage. This ensures that the voltage applied to the low-voltage transistor in the first charge pump 10 will not be too high, effectively reducing the risk of damage to the low-voltage transistor.

[0111] For example, during the discharge process of the first charge pump 10, the clamping effect of the first voltage clamping circuit 20 ensures that the first output terminal VOUT1, the first input terminal VIN1, and the internal nodes of the first charge pump 20 (such as the first node P1 and the second node P2) all discharge at similar rates. This ensures that the voltages of the first output terminal VOUT1, the first input terminal VIN1, and the internal nodes do not experience large voltage drops, thereby ensuring a relatively stable voltage applied to the low-voltage transistors in the first charge pump 10.

[0112] Alternatively, when the first charge pump 10 is not operating, if the voltage at the first output terminal VOUT1 is pulled high by other circuits (e.g., a power supply circuit), the clamping effect of the first voltage clamping circuit 20 can ensure that the voltages of the internal nodes (e.g., the first node P1 and the second node P2) of the first charge pump 10 are pulled high synchronously. This ensures that the voltage applied to the low-voltage transistors in the first charge pump 10 is not excessive.

[0113] In this embodiment, the threshold voltage of the first voltage clamping circuit 20 can be greater than the boost amplitude when the first charge pump 10 boosts the input voltage of the first input terminal VIN1. Therefore, it can be ensured that when the first charge pump 10 boosts the input voltage, i.e., when the first charge pump 10 charges the first output terminal VOUT1, the two connection terminals of the first voltage clamping circuit 20 will not erroneously conduct, thereby avoiding affecting the normal charging of the first charge pump 10.

[0114] Furthermore, the threshold voltage of the first voltage clamping circuit 20 can be determined based on the upper limit of the withstand voltage of the low-voltage transistor in the first charge pump 10, so as to ensure that after clamping the voltage difference across the first charge pump 10 to the threshold voltage, the voltage applied to the low-voltage transistor will not exceed the upper limit of the withstand voltage, thereby ensuring that the low-voltage transistor can always operate in SOA.

[0115] In summary, this application provides a charge pump circuit in which a first voltage clamping circuit is connected in parallel with a first charge pump. When the voltage difference between the output and input terminals of the first charge pump is greater than or equal to the threshold voltage of the first voltage clamping circuit, the first voltage clamping circuit can conduct, thereby clamping the voltage difference between the output and input terminals of the first charge pump to the threshold voltage. This effectively reduces the risk of damage to the low-voltage transistors in the first charge pump.

[0116] Optionally, the first voltage clamping circuit 20 is further configured to: if the first voltage difference is less than the threshold voltage of the first voltage clamping circuit 20, then the first connection terminal L1 and the second connection terminal L2 are disconnected.

[0117] Understandably, when the first connection terminal L1 is disconnected from the second connection terminal L2, the first voltage clamping circuit 20 will not affect the voltage at the first input terminal VIN1 and the first output terminal VOUT1 of the first charge pump 10. Therefore, the normal operation of the first charge pump 10 can be avoided.

[0118] Optionally, such as Figure 8 As shown, the first charge pump 10 can be as follows: Figure 4 The cross-coupled charge pump shown. Alternatively, the first charge pump 10 can also be other types of charge pumps containing low-voltage transistors.

[0119] Figure 9 This is a schematic diagram of a first voltage clamping circuit provided in an embodiment of this application. Figure 9 As shown, the first voltage clamping circuit 20 also has at least one control terminal CT. Figure 9 A control terminal CT is schematically shown. The at least one control terminal CT is used to connect to the threshold control circuit 116 in the peripheral circuit 110. The first voltage clamping circuit 20 is also used to adjust the magnitude of the threshold voltage of the first voltage clamping circuit 20 based on the control signal output by the threshold control circuit 116 to the at least one control terminal CT.

[0120] For example, assuming the first voltage clamping circuit 20 has a control terminal CT, during the process of the first charge pump 10 boosting the input voltage of the first input terminal VIN1, the threshold control circuit 116 can provide a first control signal to the control terminal CT of the first voltage clamping circuit 20. Based on this first control signal, the first voltage clamping circuit 20 can control its threshold voltage to a first voltage. This first voltage is greater than the boosting amplitude of the input voltage by the first charge pump 10, ensuring that the first charge pump 10 can normally charge the first output terminal VOUT1.

[0121] When the first charge pump 10 is in the target state, the threshold control circuit 116 can provide a second control signal to the control terminal CT of the first voltage clamping circuit 20. Based on the second control signal, the first voltage clamping circuit 20 can adjust its threshold voltage to the second voltage.

[0122] The second voltage can be less than the first voltage; the target state can include: a discharge state, a non-operating state, or a state of switching the cascade relationship with other charge pumps. Switching the cascade relationship with other charge pumps can refer to: the cascade switching circuit adjusting the series and parallel connection relationship between the first charge pump and other charge pumps, and the cascade switching circuit adjusting the number of other charge pumps cascaded with the first charge pump.

[0123] Since the stability of the input voltage at the first input terminal VIN1 and the output voltage at the first output terminal VOUT is poor when the first charge pump 10 is in the aforementioned target state, the threshold voltage of the first voltage clamping circuit 20 can be lowered. This allows for reliable protection of low-voltage transistors.

[0124] Furthermore, when the first charge pump 10 discharges, by lowering the threshold voltage of the first voltage clamping circuit 20, the voltage difference across the first charge pump 10 can be clamped to a lower voltage value. This ensures that the two ends of the first charge pump 10 can discharge at similar discharge rates, thereby ensuring that the discharge rate of the first charge pump 10 can be relatively high.

[0125] Optionally, such as Figure 9 and Figure 10 As shown, the first voltage clamping circuit 20 may include: a switching sub-circuit 201, and at least two clamping sub-circuits 202 connected in series between the first connection terminal L1 and the second connection terminal L2. Figure 9 and Figure 10 The diagram schematically illustrates two clamping sub-circuits 202.

[0126] The switching sub-circuit 201 is connected to at least one control terminal CT, the target connection terminal, and the series node P0 between every two adjacent clamping sub-circuits 202. (Reference) Figure 9The target connection can be the first connection L1, or, refer to... Figure 10 The target connection can be the second connection L2.

[0127] The switch sub-circuit 201 is used to form a current path between the target connection terminal and a series node P0 based on the control signal sent to the at least one control terminal CT by the threshold control circuit 116, thereby short-circuiting the clamping sub-circuit 202 between the target connection terminal and the series node P0.

[0128] For example, refer to Figure 9 and Figure 10 Assuming the first voltage clamping circuit 20 has a control terminal CT and includes two clamping sub-circuits 202, the switching sub-circuit 201 can remain in the off state based on the first control signal sent by the threshold control circuit 116, and can form a current path between the target connection terminal and the series node P0 based on the second control signal sent by the threshold control circuit 116, that is, the switching sub-circuit 201 can be turned on.

[0129] Specifically, when the switching sub-circuit 201 is in the off state, the threshold voltage of the first voltage clamping circuit 20 is equal to the sum of the threshold voltages of the two clamping sub-circuits 202, meaning the threshold voltage of the first voltage clamping circuit 20 is relatively large. When the switching sub-circuit 201 is on, one clamping sub-circuit 202 between the target connection terminal and the series node P0 is short-circuited, and the threshold voltage of the first voltage clamping circuit 20 is equal to the threshold voltage of the other clamping sub-circuit 202, meaning the threshold voltage of the first voltage clamping circuit 20 is relatively small. Therefore, by adjusting the on / off state between the target connection terminal and the series node P0 through the switching sub-circuit 201, the threshold voltage of the first voltage clamping circuit 20 can be flexibly adjusted.

[0130] It is understood that the threshold voltages of the at least two clamping sub-circuits 202 may be equal or unequal, and this application embodiment does not limit this.

[0131] It is also understandable that if the number of clamping sub-circuits 20 connected in series in the first voltage clamping circuit 20 is greater than 2, then the number of series nodes P0 in the first voltage clamping circuit 20 will be greater than 1. Correspondingly, the number of control terminals CT in the first voltage clamping circuit 20 is also greater than 1, and the multiple control terminals CT of the first voltage clamping circuit 20 correspond one-to-one with the multiple series nodes P0.

[0132] In this circuit, the control signal received by each control terminal CT is used to control the switching sub-circuit 201 to form a current path between the target connection terminal and a corresponding series node P0. Based on this, the switching sub-circuit 201 can flexibly form a current path between the target connection terminal and one of the series nodes P0 based on the control signals received by the multiple control terminals CT. Therefore, the number of short-circuited clamping sub-circuits 202 in the first voltage clamping circuit 20 can be flexibly adjusted, thereby achieving fine adjustment of the threshold voltage of the first voltage clamping circuit 20 to meet the needs of different scenarios.

[0133] For example, refer to Figure 11 Assuming the first voltage clamping circuit 20 includes three series-connected clamping sub-circuits 202, then the first voltage clamping circuit 20 has two series-connected nodes P01 and P02, and the first voltage clamping circuit 20 has a control terminal CT1 corresponding to the series node P01 and a control terminal CT2 corresponding to the series node P02. The switching sub-circuits 201 are respectively connected to the target terminal ( Figure 11 Taking the first connection terminal L1 as an example, the serial nodes P01 and P02, as well as the control terminals CT1 and CT2 are connected.

[0134] When the switch sub-circuit 201 remains in the off state based on the control signals received from the control terminals CT1 and CT2, that is, when no current path is formed between the first connection terminal L1 and any series node, the threshold voltage of the first voltage clamping circuit 20 is equal to the sum of the threshold voltages of the three clamping sub-circuits 202.

[0135] Based on the control signal received from the control terminal CT1, when a current path is formed between the first connection terminal L1 and the series node P01, a clamping sub-circuit 202 between the first connection terminal L1 and the series node P01 is short-circuited. At this time, the threshold voltage of the first voltage clamping circuit 20 is equal to the sum of the threshold voltages of the two clamping sub-circuits 202 between the series node P01 and the second connection terminal L2.

[0136] Based on the control signal received from the control terminal CT2, when a current path is formed between the first connection terminal L1 and the series node P02, the two clamping sub-circuits 202 between the first connection terminal L1 and the series node P02 are short-circuited. At this time, the threshold voltage of the first voltage clamping circuit 20 is equal to the threshold voltage of one of the clamping sub-circuits 202 between the series node P02 and the second connection terminal L2.

[0137] Based on the above analysis, it can be seen that the switch sub-circuit 201 can control the threshold voltage of the first voltage clamping circuit 20 to flexibly switch between three different voltage levels based on the control signals received by the control terminals CT1 and CT2.

[0138] As a possible example, such as Figure 12 As shown, each clamping sub-circuit 202 may include: one diode D0, or multiple diodes D0 connected in series. Furthermore, among the multiple diodes D0 connected in series in the first voltage clamping circuit 20, the cathode of the first diode D0 is connected to the first connection terminal L1, the cathode of each of the remaining diodes D0 is connected to the anode of the preceding diode D0, and the anode of the last diode D0 is connected to the second connection terminal L2. In this example, the threshold voltage of each clamping sub-circuit 202 may be equal to the sum of the threshold voltages of its individual diodes D0.

[0139] As another possible example, Figures 9 to 11 As shown, each clamping sub-circuit 202 in the first voltage clamping circuit 20 may include one or more first transistors M10. Among these multiple first transistors M10, the first terminal of one of every two adjacent first transistors M10 is connected to the second terminal of the other first transistor M10. Furthermore, each first transistor M10 in each clamping sub-circuit 202 is connected using a diode connection. In this example, the threshold voltage of each clamping sub-circuit 202 may be equal to the sum of the threshold voltages of its individual first transistors M10.

[0140] In this context, the diode connection method refers to shorting the gate of the first transistor M10 to either its first or second terminal, causing the first transistor M10 to operate like a diode. That is, when the first transistor M10 is connected in a diode connection manner, it can be considered equivalent to a diode. The following explanation uses a P-type transistor as an example to illustrate the principle of a P-type transistor operating in a diode-like manner:

[0141] The condition for a P-type transistor to operate in the saturation region is: |Vds|≥|Vgs|-|Vth|. Here, Vds is the source-drain voltage difference of the P-type transistor, i.e., the voltage difference between the drain and source; Vgs is the gate-source voltage difference of the P-type transistor, i.e., the voltage difference between the gate and source; and Vth is the threshold voltage of the P-type transistor. After connecting the gate and source of the P-type transistor, since Vgs = 0, the above condition can be updated to: |Vds|≥-|Vth|. That is, when the voltage difference |Vds| between the drain and source of the P-type transistor is greater than or equal to Vth, the P-type transistor can conduct and operate in the saturation region, meaning the current flowing through the P-type transistor will not change. At this time, the operating characteristics of the P-type transistor are the same as those of a diode, and therefore it can be considered equivalent to a diode. The principle of N-type transistors operating in the same way as diodes can be found in the P-type transistor diagram, and will not be elaborated here.

[0142] In this embodiment, the first transistor M10 in each clamping sub-circuit 202 can be either a P-type transistor or an N-type transistor. If all the first transistors M10 in the clamping sub-circuit 202 are P-type transistors, then... Figure 9 and Figure 11 As shown, the gate of each first transistor M10 is connected to the first terminal. Furthermore, among the plurality of first transistors M10 included in the first voltage clamping circuit 20, the first terminal of the first first transistor M10 is connected to the first connection terminal L1, the first terminal of each of the remaining first transistors M10 is connected to the second terminal of the previous first transistor M10, and the second terminal of the last first transistor M10 is connected to the second connection terminal L2.

[0143] If each first transistor M10 is an N-type transistor, then as Figure 10 As shown, the gate of each first transistor M10 is connected to its second terminal. Furthermore, among the multiple first transistors M10 included in the first voltage clamping circuit 20, the second terminal of the first first transistor M10 is connected to the first connection terminal L1, the second terminal of each of the remaining first transistors M10 is connected to the first terminal of the preceding first transistor M10, and the first terminal of the last first transistor M10 is connected to the second connection terminal L2.

[0144] Since the first charge pump 10 typically includes multiple transistors, using transistors to construct the clamping sub-circuit allows the clamping sub-circuit and the first charge pump to be fabricated using the same process. This avoids increasing the complexity of the manufacturing process for the charge pump circuit.

[0145] Optionally, refer to Figures 9 to 11 The switching sub-circuit 201 may include at least one switching transistor M20 corresponding one-to-one with at least one control terminal CT. Wherein, Figure 9 and Figure 10 The diagram schematically shows a switching transistor M20. Figure 11 Two switching transistors M20 are shown in the figure.

[0146] like Figures 9 to 11 As shown, the gate of each of the at least one switching transistor M20 is connected to a corresponding control terminal CT, the first electrode of each switching transistor M20 is connected to a series node P0, and the second electrode of each switching transistor M20 is connected to a target connection terminal. The series node P0 connected to the first electrode of different switching transistors M20 is different. Each switching transistor M20 can be turned on or off under the control of its connected control terminal CT.

[0147] In the embodiments of this application, such as Figure 9 and Figure 12As shown, the switching transistor M20 can be an N-type transistor. Alternatively, as... Figure 10 As shown, the switching transistor M20 can be a P-type transistor. If the switching transistor M20 is an N-type transistor, then when the switching transistor M20 receives a low-level first control signal at its gate, it can turn off its first and second terminals. Furthermore, when the switching transistor M20 receives a high-level second control signal at its gate, it can turn on its first and second terminals to form a current path between the target connection terminal and a series node P0.

[0148] If the switching transistor M20 is a P-type transistor, then when the switching transistor M20 receives a high-level control signal at its gate, it can turn off its first and second terminals. Furthermore, when the switching transistor M20 receives a low-level control signal at its gate, it can turn on its first and second terminals to form a current path between the target connection terminal and a series node P0.

[0149] In scenarios where the number of clamping sub-circuits 202 connected in series in the first voltage clamping circuit 20 is greater than 2, such as Figure 11 As shown, the switching sub-circuit 201 may include multiple switching transistors M20, each corresponding to a multiple control terminal CT. For example, Figure 11 The switch sub-circuit 201 shown includes two switch transistors M20. The first terminal of one switch transistor M20 is connected to the series node P01, and its gate is connected to the control terminal CT1. The first terminal of the other switch transistor M20 is connected to the series node P02, and its gate is connected to the control terminal CT2.

[0150] The threshold control circuit 116 in the peripheral circuit 110 can control the conduction of different switching transistors M20 by adjusting the level of the control signal transmitted to each control terminal CT. As a result, the switching sub-circuit 201 can form a current path between the target connection terminal and different series nodes, thereby realizing flexible and precise adjustment of the threshold voltage of the first voltage clamping circuit 20.

[0151] The embodiments of this application are as follows: Figure 9 Taking the first voltage clamping circuit 20 shown as an example, the current flowing between the first connection terminal L1 and the second connection terminal L2 was simulated when the switching transistor M20 was turned off and on, respectively. During the simulation, the input voltage applied to the first input terminal VIN1 was 0V. Figure 13As shown, when the switching transistor M20 is turned off, and the output voltage Vout of the first output terminal VOUT1 is greater than approximately 4.231V, the current I flowing between the first connection terminal L1 and the second connection terminal L2 is ≥ 1 microamp (µA), meaning that the first connection terminal L1 and the second connection terminal L2 are connected. In other words, when the switching transistor M20 is turned off, the threshold voltage of the first voltage clamping circuit 20 is approximately 4.231V.

[0152] like Figure 14 As shown, when the switching transistor M20 is turned on, and the output voltage Vout of the first output terminal VOUT1 is greater than approximately 1.67V, the current I flowing between the first connection terminal L1 and the second connection terminal L2 is ≥1uA, meaning that the first connection terminal L1 and the second connection terminal L2 are connected. In other words, when the switching transistor M20 is turned on, the threshold voltage of the first voltage clamping circuit 20 is approximately 1.67V.

[0153] Furthermore, this embodiment of the application also tested the threshold voltage of the first voltage clamping circuit 20 of the first transistor M10 using different process corners under different ambient temperatures. The test results can be found in Table 1. In Table 1, TT indicates that the driving current of the first transistor M10 is its average value, that is, the carrier mobility is typical; SS indicates that the driving current of the first transistor M10 is its minimum value, that is, the carrier mobility is slow; and FF indicates that the driving current of the first transistor M10 is its maximum value, that is, the carrier mobility is fast.

[0154] As shown in Table 1, if the process corner of the first transistor M10 used in the first voltage clamping circuit 20 is SS and the ambient temperature is -40℃, then when the switching transistor M20 is turned off, the threshold voltage of the first voltage clamping circuit 20 is 4.893V; when the switching transistor M20 is turned on, the threshold voltage of the first voltage clamping circuit 20 is 1.956V.

[0155] Table 1

[0156] Experimental parameters TT / 25℃ SS / -40℃ FF / 125℃ M20 shutdown 4.231V 4.893V 3.440V M20 conduction 1.670V 1.956V 1.339V

[0157] It is understood that the first voltage clamping circuit 20 provided in this application embodiment may also not include the control terminal CT, that is, the threshold voltage of the first voltage clamping circuit 20 can be a fixed value. Accordingly, refer to Figure 8As an optional implementation, the first voltage clamping circuit 20 may include one transistor M10 or multiple first transistors M10, wherein the first terminal of one of every two adjacent first transistors M10 is connected to the second terminal of the other first transistor M10. Furthermore, each first transistor M10 in the first voltage clamping circuit 20 is connected using a diode connection. In this implementation, the threshold voltage of the first voltage clamping circuit 20 may be equal to the sum of the threshold voltages of its individual transistors M10.

[0158] As an alternative implementation, the first voltage clamping circuit 20 may include a diode D0, or multiple diodes D0 connected in series. In this implementation, the threshold voltage of the first voltage clamping circuit 20 may be equal to the sum of the threshold voltages of its individual diodes D0.

[0159] Figure 15 This is a schematic diagram of another charge pump circuit provided in an embodiment of this application. For example... Figure 15 As shown, the charge pump circuit may further include: a second charge pump 30 and a second voltage clamping circuit 40.

[0160] The second charge pump 30 is connected in series or in parallel with the first charge pump 10, and the second charge pump 30 has a second input terminal VIN2 and a second output terminal VOUT2. The second charge pump 30 is used to boost the input voltage at the second input terminal VIN2 and then transmit it to the second output terminal VOUT2.

[0161] The second voltage clamping circuit 40 has a third connection terminal L3 and a fourth connection terminal L4. The third connection terminal L3 is connected to the second input terminal VIN2, and the fourth connection terminal L4 is connected to the second output terminal VOUT2. That is, the second voltage clamping circuit 40 is connected in parallel with the second charge pump 30. The second voltage clamping circuit 40 is used for:

[0162] If the second voltage difference obtained by subtracting the voltage of the third connection terminal L3 from the voltage of the fourth connection terminal L4 is greater than or equal to the threshold voltage of the second voltage clamping circuit 40, a current path is formed between the third connection terminal L3 and the fourth connection terminal L4, that is, the second voltage clamping circuit 40 can be turned on.

[0163] The threshold voltage of the second voltage clamping circuit 40 can be defined as the lowest voltage required to turn on the second voltage clamping circuit 40. Accordingly, after the second voltage clamping circuit 40 is turned on and forms a current path, the voltage drop of this current path is equal to the threshold voltage of the second voltage clamping circuit 40.

[0164] Optionally, the second voltage clamping circuit 40 is further configured to disconnect the third connection terminal L3 from the fourth connection terminal L4 if the second voltage difference is less than the threshold voltage of the second voltage clamping circuit 40.

[0165] It is understood that the structure and working principle of the second charge pump 30 are the same as those of the first charge pump 10; the structure and working principle of the second voltage clamping circuit 40 can be referred to the relevant description of the first voltage clamping circuit 20, and will not be repeated here.

[0166] Continue to refer to Figure 15 The charge pump circuit may further include a cascaded switch circuit 50. The cascaded switch circuit 50 is connected to the first input terminal VIN1, the first output terminal VOUT1, the second input terminal VIN2, and the second output terminal VOUT2, respectively.

[0167] The cascaded switch circuit 50 is used to control the connection state between the first input terminal VIN1, the first output terminal VOUT1, the second input terminal VIN2, and the second output terminal VOUT2, thereby realizing flexible adjustment of the series-parallel relationship between the first charge pump 10 and the second charge pump 30.

[0168] For example, when the cascade switch circuit 50 controls the second input terminal VIN2 to be connected to the first output terminal VOUT1, the first charge pump 10 and the second charge pump 30 can be connected in series. When the cascade switch circuit 50 controls the second input terminal VIN2 to be connected to the first input terminal VIN1 and controls the second output terminal VOUT2 to be connected to the first output terminal VOUT1, the first charge pump 10 and the second charge pump 30 can be connected in parallel.

[0169] Optionally, the cascaded switch circuit 50 may include multiple cascaded switches and a control sub-circuit for controlling the on / off states of the multiple cascaded switches. Each cascaded switch has one end connected to a first input terminal VIN1 or a first output terminal VOUT1, and the other end connected to a second input terminal VIN2 or a second output terminal VOUT2.

[0170] In this embodiment, the charge pump circuit may include more than two charge pumps, and each charge pump may be connected in parallel with a voltage clamping circuit. The cascaded switch circuit 50 may be connected to the input and output terminals of each charge pump, and the charge pumps may be connected in series or in parallel by controlling the connection state between their input and output terminals. Furthermore, the cascaded switch circuit 50 can flexibly adjust the number of charge pumps connected in series or in parallel in the charge pump circuit according to the needs of different application scenarios.

[0171] Optionally, the first charge pump 10 may include a plurality of transistors, among which at least one target transistor may be a low-voltage transistor in the first charge pump 10. Figure 16 As shown, the charge pump circuit may further include at least one third voltage clamping circuit 60 corresponding one-to-one with the at least one target transistor. For example, Figure 16 The diagram shows two target transistors, MP1 and MP2, and two third voltage clamping circuits 60 corresponding to these two target transistors.

[0172] Each of the at least one third voltage clamping circuit 60 has a fifth connection terminal L5 and a sixth connection terminal L6, wherein the fifth connection terminal L5 is connected to the first terminal of a corresponding target transistor, and the sixth connection terminal L6 is connected to the second terminal of a corresponding target transistor. Each of the at least one third voltage clamping circuit 60 can be used for:

[0173] If the voltage difference between the fifth terminal L5 and the sixth terminal L6 is greater than or equal to the threshold voltage of the third voltage clamping circuit 60, a current path is formed between the fifth terminal L5 and the sixth terminal L6, meaning the third voltage clamping circuit 60 can be turned on. The threshold voltage of the third voltage clamping circuit 60 can be defined as the minimum voltage required for it to turn on. Correspondingly, after the third voltage clamping circuit 60 is turned on and a current path is formed, the voltage drop across this current path is equal to the threshold voltage of the third voltage clamping circuit 60.

[0174] It is understood that the threshold voltage of each third voltage clamping circuit 60 can be greater than the voltage difference between the two terminals of its corresponding target transistor when it is operating normally (i.e., the voltage difference between the first terminal and the second terminal). Furthermore, the threshold voltage of each third voltage clamping circuit 60 can be less than or equal to the upper voltage limit of its corresponding target transistor.

[0175] Optionally, each of the at least one third voltage clamping circuit 60 can also be used to: if the third voltage difference is less than the threshold voltage of the third voltage clamping circuit 60, then the fifth connection terminal L5 and the sixth connection terminal L6 are disconnected.

[0176] Therefore, when the voltage difference between the two terminals of any target transistor is less than the threshold voltage of its corresponding third voltage clamping circuit 60, the two terminals of the third voltage clamping circuit 60 are disconnected, and the normal operation of the target transistor is not affected. When the voltage difference between the two terminals of any target transistor is greater than or equal to the threshold voltage of its corresponding third voltage clamping circuit 60, the two terminals of the third voltage clamping circuit 60 are turned on, thereby clamping the voltage difference between the two terminals of the target transistor to the threshold voltage of the third voltage clamping circuit 60, so as to prevent the target transistor from operating outside the SOA.

[0177] As one possible example, each third voltage clamping circuit 60 may include a diode, the anode of which is connected to the fifth connection terminal L5 and the cathode of which is connected to the sixth connection terminal L6. Alternatively, each third voltage clamping circuit 60 may include multiple diodes connected in series, wherein the anode of the first diode is connected to the fifth connection terminal L5, the anode of each of the remaining diodes is connected to the cathode of the preceding diode, and the cathode of the last diode is connected to the sixth connection terminal L6.

[0178] As another possible example, Figure 16 As shown, each third voltage clamping circuit 60 may include a second transistor M30. The first terminal of the second transistor M30 is connected to the fifth connection terminal L5, and the gate and second terminal of the second transistor M30 are both connected to the sixth connection terminal L6. That is, the second transistor M30 is also connected in a diode configuration and can be equivalent to a diode.

[0179] The second transistor M30 can be either a P-type transistor or an N-type transistor; this embodiment does not limit the type. Furthermore, using a transistor to construct the third voltage clamping circuit 60 allows it to be formed using the same process as the first charge pump 10. This avoids increasing the complexity of the charge pump circuit's manufacturing process.

[0180] It is understood that if the first charge pump circuit 10 includes multiple low-voltage transistors (i.e., multiple target transistors exist), then multiple third voltage clamping circuits 60, each corresponding to one of the multiple target transistors, can be configured in the charge pump circuit. For example, refer to... Figure 16 If transistors MP1 and MP2 in the first charge pump 10 are both low-voltage target transistors, then the charge pump circuit may include two third voltage clamping circuits 60. This allows for reliable protection of each low-voltage transistor.

[0181] Optionally, the first charge pump 10 can be a cross-coupled charge pump. For example... Figure 16As shown, this cross-coupled charge pump may include two N-type transistors MN1 and MN2, and two P-type transistors MP1 and MP2. Since the P-type transistors in a cross-coupled charge pump are generally low-voltage transistors, at least one target transistor in this cross-coupled charge pump may include the P-type transistors MP1 and MP2. (Reference) Figure 16 It can be seen that the second terminal of each P-type transistor is connected to the first output terminal VOUT1.

[0182] Based on the working principle of the cross-coupled charge pump, it is known that during normal charging of the first charge pump 10, the voltage of the first terminal of the P-type transistor (i.e., the voltage of the first node P1 or the second node P2) is less than or equal to the voltage of the first output terminal VOUT1. If, during charging, the voltage of the first node P1 or the second node P2 exceeds the voltage of the first output terminal VOUT1 due to glitches, or if, during discharging, the voltage exceeds the voltage of the first output terminal VOUT1 due to the different discharge rates of the first output terminal VOUT1 and the first output terminal VIN1, the P-type transistor may fail to operate in SOA mode.

[0183] In this embodiment, since a third voltage clamping circuit 60 is used to clamp the voltage difference between the first and second terminals of the P-type transistor, it can be effectively ensured that the P-type transistor can always operate in SOA.

[0184] It is understandable that if the two N-type transistors MN1 and MN2 in the first charge pump 10 are also low-voltage transistors, then as... Figure 17 As shown, the charge pump circuit may further include two third voltage clamping circuits 60, each connected to one of the two N-type transistors. That is, refer to... Figure 17 The first charge pump 10 includes four target transistors, MP1, MP2, MN1 and MN2, and the charge pump circuit includes four third voltage clamping circuits 60 corresponding to the four target transistors.

[0185] Specifically, a third voltage clamping circuit 60 corresponding to each N-type transistor can clamp the voltage difference between the first and second terminals of the N-type transistor when the voltage difference between the first and second terminals of the transistor exceeds its threshold voltage. In other words, the third voltage clamping circuit 60 can clamp the voltage difference between the first output terminal VIN1 and the voltage of either the first node P1 or the second node P2 to its threshold voltage, ensuring that the N-type transistor always operates at SOA.

[0186] This application embodiment also simulates the voltage difference Vout-Vin between the first output terminal VOUT1 and the first input terminal VIN1, the source-drain voltage difference Vds of the P-type transistor, and the gate-source voltage difference Vgs of the P-type transistor. For example... Figure 18 As shown, when no voltage clamping circuit is set in the charge pump circuit, the voltage difference Vout-Vin fluctuates within a large range, which in turn leads to a large fluctuation range in the source-drain voltage difference Vds and the gate-source voltage difference Vgs of the P-type transistor. Figure 18 As can be seen, the voltage difference Vout-Vin can reach a maximum of 6.39V, the source-drain voltage difference Vds of the P-type transistor can reach a minimum of -6.48V, and the gate-source voltage difference Vgs of the P-type transistor can reach a minimum of -4.88V.

[0187] When the charge pump circuit provided in the embodiments of this application is adopted, such as Figure 19 As shown, the fluctuation range of the voltage difference Vout-Vin is small, which ensures that the fluctuation ranges of the source-drain voltage difference Vds and the gate-source voltage difference Vgs of the P-type transistor are also small. From Figure 19 As can be seen, the upper limit of the voltage difference Vout-Vin is 4.36V, the highest source-drain voltage difference Vds of the P-type transistor is 2.21V, and the lowest is -4.48V. The highest gate-source voltage difference Vgs of the P-type transistor is 1.89V, and the lowest is -4.18V. From... Figure 19 It can also be seen that the solution provided in this application embodiment can basically control the source-drain voltage difference |Vds| and gate-source voltage difference |Vgs| of the P-type transistor within 4V, and the peak value does not exceed 5V. This effectively ensures the stability of the P-type transistor during operation.

[0188] In summary, this application provides a charge pump circuit in which a first voltage clamping circuit is connected in parallel with a first charge pump. When the voltage difference between the output and input terminals of the first charge pump is greater than or equal to the threshold voltage of the first voltage clamping circuit, the first voltage clamping circuit can conduct, thereby clamping the voltage difference between the output and input terminals of the first charge pump to the threshold voltage. This effectively reduces the risk of damage to the low-voltage transistors in the first charge pump.

[0189] This application also provides another charge pump circuit, such as... Figure 16 As shown, the charge pump circuit includes a charge pump 10 and at least one voltage clamping circuit 60.

[0190] The charge pump 10 has an input terminal VIN1 and an output terminal VOUT1. The charge pump 10 is used to boost the input voltage at the input terminal VIN1 and then transmit it to the output terminal VOUT1.

[0191] The at least one voltage clamping circuit 60 corresponds one-to-one with at least one target transistor in the charge pump 10, and each of the at least one voltage clamping circuit 60 has a first clamping terminal L5 and a second clamping terminal L6. The first clamping terminal L5 is connected to the first terminal of the corresponding target transistor, and the second clamping terminal L6 is connected to the second terminal of the corresponding target transistor. For example, Figure 16 At least one target transistor in the charge pump 10 shown includes MP1 and MP2.

[0192] Each of the at least one voltage clamping circuit 60 is configured to: form a current path between the first clamping terminal L5 and the second clamping terminal L6 if the voltage difference obtained by subtracting the voltage of the second clamping terminal L6 from the voltage of the first clamping terminal L5 is greater than or equal to the threshold voltage of the voltage clamping circuit 60, that is, the voltage clamping circuit 60 can be turned on.

[0193] The threshold voltage of the voltage clamping circuit 60 can be defined as the lowest voltage required to turn on the voltage clamping circuit 60. Correspondingly, after the voltage clamping circuit 60 is turned on and forms a current path, the voltage drop across this current path is equal to the threshold voltage.

[0194] Optionally, each of the at least one voltage clamping circuit 60 is further configured to disconnect the first clamping terminal L5 from the second clamping terminal L6 if the voltage difference is less than the threshold voltage of the voltage clamping circuit 60.

[0195] Optionally, continue to refer to Figure 16 Each voltage clamping circuit 60 may include: a transistor M30; the first terminal of the transistor M30 is connected to the first clamping terminal L5, and the gate and the second terminal of the transistor M30 are both connected to the second clamping terminal L6.

[0196] Optionally, such as Figure 16 As shown, the charge pump 10 can be a cross-coupled charge pump, and the at least one target transistor can be a P-type transistor in the cross-coupled charge pump. The second terminal of the P-type transistor is connected to the output terminal VOUT1.

[0197] The structure and working principle of the voltage clamping circuit 60 can be referred to the relevant descriptions in the above embodiments, and will not be repeated here.

[0198] It is understood that each transistor (including transistors and switching transistors, etc.) in the charge pump circuit provided in the embodiments of this application can be a MOSFET.

[0199] In summary, this application provides a charge pump circuit in which a voltage clamping circuit is connected to a target transistor. When the voltage difference between the two terminals of the target transistor exceeds the threshold voltage of the voltage clamping circuit, the voltage clamping circuit can conduct, thereby clamping the voltage difference between the two terminals of the target transistor to the threshold voltage. This effectively reduces the risk of damage to the target transistor.

[0200] This application provides a memory, such as... Figure 2 As shown, the memory includes a storage array 120 and peripheral circuitry 110. The peripheral circuitry 110 may include the charge pump circuitry 111 provided in the above embodiments.

[0201] Optionally, continue to refer to Figure 2 The peripheral circuit 110 may further include a threshold control circuit 116. For example... Figure 9 and Figure 10 As shown, the threshold control circuit 116 is connected to at least one control terminal CT of the first voltage clamping circuit 20 in the charge pump circuit 111. The threshold control circuit 116 can be used for:

[0202] If the first charge pump 10 in the charge pump circuit 111 is in a charging state, a first control signal is provided to at least one control terminal CT of the first voltage clamping circuit 20. The first control signal is used to control the threshold voltage of the first voltage clamping circuit 20 to be a first voltage.

[0203] If the first charge pump 10 is in the target state, a second control signal is provided to at least one control terminal CT of the first voltage clamping circuit 20. The second control signal is used to control the threshold voltage of the first voltage clamping circuit 20 to be a second voltage, which is less than the first voltage.

[0204] The target state may include: a discharge state, a non-operating state, or a state that switches to a cascade relationship with other charge pumps (e.g., a second charge pump).

[0205] In this embodiment, when the first charge pump 10 is in a charging state, the threshold control circuit 116 can set the threshold voltage of the first voltage clamping circuit 20 to a higher value to avoid affecting the normal charging of the first charge pump 10. When the first charge pump 10 is in a target state, the threshold control circuit 116 can lower the threshold voltage of the first voltage clamping circuit 20 to reliably protect the low-voltage transistors in the first charge pump 10.

[0206] Optionally, the threshold control circuit 116 can be integrated with the control logic circuit 115, meaning the threshold control circuit 116 can reuse a circuit module from the control logic circuit 115. Alternatively, the threshold control circuit 116 can be independent of the control logic circuit 115. For example, the threshold control circuit 116 can be a separate integrated circuit (IC).

[0207] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0208] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charge pump circuit (111), characterized in that, The charge pump circuit (111) includes: a first charge pump (10) and a first voltage clamping circuit (20); The first charge pump (10) has a first input terminal (VIN1) and a first output terminal (VOUT1). The first charge pump (10) is used to boost the input voltage of the first input terminal (VIN1) and transmit it to the first output terminal (VOUT1). The first voltage clamping circuit (20) has a first connection terminal (L1) and a second connection terminal (L2), the first connection terminal (L1) is connected to the first input terminal (VIN1), and the second connection terminal (L2) is connected to the first output terminal (VOUT1); The first voltage clamping circuit (20) is used to form a current path between the first connection terminal (L1) and the second connection terminal (L2) if the first voltage difference obtained by subtracting the voltage of the first connection terminal (L1) from the voltage of the second connection terminal (L2) is greater than or equal to the threshold voltage of the first voltage clamping circuit (20). The first voltage clamping circuit (20) also has at least one control terminal (CT) for connection to the threshold control circuit (116); The first voltage clamping circuit (20) is also used to adjust the magnitude of the threshold voltage of the first voltage clamping circuit (20) based on the control signal output by the threshold control circuit (116) to the at least one control terminal (CT).

2. The charge pump circuit (111) according to claim 1, characterized in that, The first voltage clamping circuit (20) is also used to disconnect the first connection terminal (L1) from the second connection terminal (L2) if the first voltage difference is less than the threshold voltage of the first voltage clamping circuit (20).

3. The charge pump circuit (111) according to claim 1, characterized in that, The first voltage clamping circuit (20) includes: a switching sub-circuit (201), and at least two clamping sub-circuits (202) connected in series between the first connection terminal (L1) and the second connection terminal (L2). The switching sub-circuit (201) is connected to at least one control terminal (CT), a target connection terminal, and a series node (P0) between each two adjacent clamping sub-circuits (202), wherein the target connection terminal is either the first connection terminal (L1) or the second connection terminal (L2). The switching sub-circuit (201) is used to form a current path between the target connection terminal and one of the series nodes (P0) based on the control signal received by the at least one control terminal (CT).

4. The charge pump circuit (111) according to claim 3, characterized in that, The switching sub-circuit (201) includes at least one switching transistor (M20) corresponding one-to-one with the at least one control terminal (CT). The gate of each of the at least one switching transistor (M20) is connected to a corresponding control terminal (CT), the first terminal of each switching transistor (M20) is connected to a series node (P0), and the second terminal of each switching transistor (M20) is connected to the target connection terminal.

5. The charge pump circuit (111) according to claim 1, characterized in that, The first voltage clamping circuit (20) includes: a first transistor (M10) or a plurality of first transistors (M10), wherein the gate of each first transistor (M10) is connected to a first pole or a second pole; In the plurality of first transistors (M10), the first terminal of one of the two adjacent first transistors (M10) is connected to the second terminal of the other first transistor (M10).

6. The charge pump circuit (111) according to any one of claims 1 to 5, characterized in that, The charge pump circuit (111) further includes: a second charge pump (30) and a second voltage clamping circuit (40); The second charge pump (30) is connected in series or in parallel with the first charge pump (10), and the second charge pump (30) has a second input terminal (VIN2) and a second output terminal (VOUT2). The second charge pump (30) is used to boost the input voltage of the second input terminal (VIN2) and transmit it to the second output terminal (VOUT2). The second voltage clamping circuit (40) has a third connection terminal (L3) and a fourth connection terminal (L4), the third connection terminal (L3) being connected to the second input terminal (VIN2) and the fourth connection terminal (L4) being connected to the second output terminal (VOUT2); The second voltage clamping circuit (40) is used to form a current path between the third connection terminal (L3) and the fourth connection terminal (L4) if the second voltage difference obtained by subtracting the voltage of the third connection terminal (L3) from the voltage of the fourth connection terminal (L4) is greater than or equal to the threshold voltage of the second voltage clamping circuit (40).

7. The charge pump circuit (111) according to claim 6, characterized in that, The charge pump circuit (111) also includes: a cascaded switch circuit (50); The cascaded switch circuit (50) is connected to the first input terminal (VIN1), the first output terminal (VOUT1), the second input terminal (VIN2), and the second output terminal (VOUT2) respectively. The cascaded switch circuit (50) is used to control the connection status between the first input terminal (VIN1), the first output terminal (VOUT1), the second input terminal (VIN2), and the second output terminal (VOUT2).

8. The charge pump circuit (111) according to any one of claims 1 to 5, characterized in that, The first charge pump (10) includes a plurality of transistors, among which at least one target transistor is included; the charge pump circuit (111) further includes at least one third voltage clamping circuit (60) corresponding to the at least one target transistor. Each of the at least one third voltage clamping circuit (60) has a fifth connection terminal (L5) and a sixth connection terminal (L6), the fifth connection terminal (L5) being connected to the first terminal of a corresponding target transistor, and the sixth connection terminal (L6) being connected to the second terminal of a corresponding target transistor; Each of the at least one third voltage clamping circuit (60) is configured to form a current path between the fifth connection terminal (L5) and the sixth connection terminal (L6) if the third voltage difference obtained by subtracting the voltage of the sixth connection terminal (L6) from the voltage of the fifth connection terminal (L5) is greater than or equal to the threshold voltage of the third voltage clamping circuit (60).

9. The charge pump circuit (111) according to claim 8, characterized in that, Each of the at least one third voltage clamping circuit (60) includes: a second transistor (M30); The first terminal of the second transistor (M30) is connected to the fifth connection terminal (L5), and the gate and the second terminal of the second transistor (M30) are both connected to the sixth connection terminal (L6).

10. The charge pump circuit (111) according to claim 8, characterized in that, The first charge pump (10) is a cross-coupled charge pump, and the at least one target transistor is a P-type transistor (MP1, MP2) in the cross-coupled charge pump. The second terminal of the P-type transistor (MP1, MP2) is connected to the first output terminal (VOUT1).

11. A charge pump circuit (111), characterized in that, The charge pump circuit (111) includes: a charge pump (10) and at least one voltage clamping circuit (60). The charge pump (10) has an input terminal (VIN1) and an output terminal (VOUT1). The charge pump (10) is used to boost the input voltage at the input terminal (VIN1) and then transmit it to the output terminal (VOUT1). The at least one voltage clamping circuit (60) corresponds one-to-one with at least one target transistor in the charge pump (10), and each voltage clamping circuit (60) has a first clamping terminal (L5) and a second clamping terminal (L6), the first clamping terminal (L5) is connected to the first electrode of the corresponding target transistor, and the second clamping terminal (L6) is connected to the second electrode of the corresponding target transistor; Each of the at least one voltage clamping circuit (60) is configured to form a current path between the first clamping terminal (L5) and the second clamping terminal (L6) if the voltage difference obtained by subtracting the voltage of the second clamping terminal (L6) from the voltage of the first clamping terminal (L5) is greater than or equal to the threshold voltage of the voltage clamping circuit (60).

12. The charge pump circuit (111) according to claim 11, characterized in that, Each of the at least one voltage clamping circuit (60) is further configured to disconnect the first clamping terminal (L5) from the second clamping terminal (L6) if the voltage difference is less than the threshold voltage.

13. The charge pump circuit (111) according to claim 11, characterized in that, Each of the at least one voltage clamping circuit (60) includes a transistor (M30). The first terminal of the transistor (M30) is connected to the first clamping terminal (L5), and the gate and the second terminal of the transistor (M30) are both connected to the second clamping terminal (L6).

14. The charge pump circuit (111) according to any one of claims 11 to 13, characterized in that, The charge pump (10) is a cross-coupled charge pump, and the at least one target transistor is a P-type transistor (MP1, MP2) in the cross-coupled charge pump. The second terminal of the P-type transistor (MP1, MP2) is connected to the output terminal (VOUT1).

15. A memory (100), characterized in that, The memory (100) includes a memory array (120) and peripheral circuitry (110), the peripheral circuitry (110) including a charge pump circuit (111) as described in any one of claims 1 to 14.

16. The memory (100) according to claim 15, characterized in that, The peripheral circuit (110) further includes: a threshold control circuit (116); The threshold control circuit (116) is connected to at least one control terminal (CT) of the first voltage clamping circuit (20) in the charge pump circuit (111), and the threshold control circuit (116) is used for: If the first charge pump (10) in the charge pump circuit (111) is in a charging state, a first control signal is provided to at least one control terminal (CT) of the first voltage clamping circuit (20), and the first control signal is used to control the threshold voltage of the first voltage clamping circuit (20) to be a first voltage; If the first charge pump (10) is in the target state, a second control signal is provided to at least one control terminal (CT) of the first voltage clamping circuit (20), the second control signal being used to control the threshold voltage of the first voltage clamping circuit (20) to be a second voltage, the second voltage being less than the first voltage; The target states include: a discharge state, a non-operating state, or a state that switches to a cascade relationship with other charge pumps.

17. A storage system (1000), characterized in that, The storage system (1000) includes: a memory controller (000), and at least one memory (100) as described in claim 15 or 16.

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