Semiconductor structure fabrication methods and semiconductor structures

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes providing a substrate, the substrate including a first region and a second region; forming a first device on the first region, the first device including a first gate structure, the first gate structure including a first work function layer; forming a second device on the second region, the second device including a second gate structure, the second gate structure including a second work function layer; the top surface of the first gate structure and the top surface of the second gate structure are flush. In this disclosure, the first gate structure of the first device and the second gate structure of the second device are formed in the same etching process, and the process heights of the first gate structure and the second gate structure are equal, which reduces the process difficulty of forming the first gate structure and the second gate structure, and improves the yield and reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the development of integrated circuits, the structural size of Dynamic Random Access Memory (DRAM) has shrunk, and the size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has become smaller and smaller. In order to improve the leakage current of transistors and improve the reliability of devices, High-K Metal Gate (HKMG) technology has been widely used in semiconductor manufacturing processes.

[0003] In semiconductor manufacturing, transistors with different conductivity types are often formed in the same process. However, the process heights of transistors with different conductivity types are different, which often results in some parts of the structure being under-etched while others are over-etched, reducing the electrical performance and reliability of the transistors. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a first region and a second region;

[0007] A first device is formed on the first region, the first device including a first gate structure, the first gate structure including a first work function layer;

[0008] A second device is formed on the second region, the second device including a second gate structure, the second gate structure including a second work function layer;

[0009] The top surface of the first gate structure is flush with the top surface of the second gate structure.

[0010] According to some embodiments of this disclosure, the manufacturing method includes:

[0011] A stacked structure is formed on the substrate, the stacked structure including a first stacked portion located in the first region and a second stacked portion located in the second region;

[0012] The first stacked portion and the second stacked portion are of the same height.

[0013] According to some embodiments of this disclosure, forming a stacked structure on the substrate includes:

[0014] An initial gate dielectric layer is formed on the first region and the second region of the substrate, respectively. The initial gate dielectric layer includes an initial oxide layer and an initial high-k dielectric layer, and the initial high-k dielectric layer is formed on the top surface of the initial oxide layer.

[0015] According to some embodiments of this disclosure, forming a stacked structure on the substrate further includes:

[0016] An initial first barrier layer, an initial first work function layer, and an initial second barrier layer are sequentially stacked on the top surface of the initial high-k dielectric layer.

[0017] Remove the initial first barrier layer, the initial first work function layer, and the initial second barrier layer formed above the second region, and retain the initial first barrier layer, the initial first work function layer, and the initial second barrier layer formed above the first region.

[0018] According to some embodiments of this disclosure, forming a stacked structure on the substrate further includes:

[0019] An etching barrier layer is formed on the top surface of the initial second barrier layer above the first region and on the top surface of the initial high-k dielectric layer above the second region; the etching barrier layer includes an oxide layer and a nitride layer;

[0020] Remove the etching barrier layer formed above the second region, and retain the etching barrier layer formed above the first region.

[0021] According to some embodiments of this disclosure, forming a stacked structure on the substrate further includes:

[0022] An initial second work function layer is formed, which covers the top surface of the initial high-k dielectric layer located above the second region and the top surface of the etching barrier layer;

[0023] An initial third barrier layer is formed, which covers the second work function layer;

[0024] Remove the initial second work function layer, the initial third barrier layer, and the etching barrier layer formed above the first region, and retain the initial second work function layer and the initial third barrier layer formed above the second region.

[0025] According to some embodiments of this disclosure, the top surface of the initial second barrier layer and the top surface of the initial third barrier layer are flush.

[0026] According to some embodiments of this disclosure, forming a stacked structure on the substrate further includes:

[0027] An initial metal layer and an initial isolation layer are formed by stacking them sequentially on the top surfaces of the initial second barrier layer and the initial third barrier layer.

[0028] According to some embodiments of this disclosure, forming a stacked structure on the substrate further includes:

[0029] An initial semiconductor layer and an initial fourth barrier layer are formed, wherein the semiconductor layer and the initial fourth barrier layer are sequentially stacked between the initial second barrier layer and the initial metal layer above the first region, and between the initial third barrier layer and the initial metal layer sequentially stacked above the second region.

[0030] According to some embodiments of this disclosure, the manufacturing method further includes:

[0031] A mask layer is formed on the surface of the isolation layer, and the stacked structure is etched through the mask layer to form the first gate structure and the second gate structure.

[0032] According to some embodiments of this disclosure, the manufacturing method further includes:

[0033] Ion implantation is performed on the first regions on both sides of the first gate structure to form a first source region and a first drain region, respectively;

[0034] Ion implantation is performed on the second regions on both sides of the second gate structure to form a second source region and a second drain region.

[0035] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0036] A substrate, the substrate comprising a first region and a second region;

[0037] At least one first device is disposed in the first region, the first device includes a first gate structure, and the first gate structure includes a first work function layer;

[0038] At least one second device is disposed in the second region, the second device includes a second gate structure, the second gate structure includes a second work function layer;

[0039] The top surfaces of the first gate structure and the second gate structure are flush.

[0040] According to some embodiments of the present disclosure, the first gate structure includes a first gate dielectric layer, a first barrier layer, a first work function layer, a second barrier layer, a first metal layer, and a first isolation layer stacked sequentially on the first region.

[0041] The second gate structure includes a second gate dielectric layer, a second work function layer, a third barrier layer, a second metal layer, and a second isolation layer stacked sequentially on the second region.

[0042] The top surface of the second barrier layer is flush with the top surface of the third barrier layer.

[0043] According to some embodiments of this disclosure, the first gate structure further includes: a first semiconductor layer and a first fourth barrier layer sequentially stacked between the second barrier layer and the first metal layer.

[0044] According to some embodiments of this disclosure, the second gate structure further includes: a second semiconductor layer and a second fourth barrier layer sequentially stacked between the third barrier layer and the second metal layer.

[0045] According to some embodiments of the present disclosure, the first device further includes: a first source region, a first drain region, and a first channel region, wherein the first source region and the first drain region are respectively located on both sides of the first gate structure, and the first channel region is disposed below the first gate structure;

[0046] The second device further includes a second source region, a second drain region, and a second channel region, wherein the second source region and the second drain region are located on opposite sides of the second gate structure, and the second channel region is disposed below the second gate structure.

[0047] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the first gate structure of the first device and the second gate structure of the second device are formed in the same etching process. The process heights of the first gate structure and the second gate structure are equal, which reduces the process difficulty of forming the first gate structure and the second gate structure and improves the yield and reliability of the semiconductor structure.

[0048] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0050] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0051] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 3 This is a schematic diagram of a substrate according to an exemplary embodiment.

[0053] Figure 4 This is a schematic diagram of forming a gate dielectric layer according to an exemplary embodiment.

[0054] Figure 5 This is a schematic diagram of a first barrier layer, a first work function layer, and a second barrier layer stacked sequentially on a high-K dielectric layer, according to an exemplary embodiment.

[0055] Figure 6 This is a schematic diagram of forming a first photoresist mask according to an exemplary embodiment.

[0056] Figure 7 This is a schematic diagram of removing the first blocking layer, the first work function layer, and the second blocking layer above the second region according to an exemplary embodiment.

[0057] Figure 8 This is a schematic diagram of forming an etch barrier layer according to an exemplary embodiment.

[0058] Figure 9 This is a schematic diagram of forming a second photoresist mask on an etch barrier layer above a first region according to an exemplary embodiment.

[0059] Figure 10 This is a schematic diagram of removing an etch barrier layer above a second region according to an exemplary embodiment.

[0060] Figure 11 This is a schematic diagram illustrating the formation of a second work function layer and a third work function layer according to an exemplary embodiment.

[0061] Figure 12 This is a schematic diagram of forming a third photoresist mask according to an exemplary embodiment.

[0062] Figure 13 This is a schematic diagram of a second work function layer and a third work function layer formed above a second region according to an exemplary embodiment.

[0063] Figure 14 This is a schematic diagram of removing an etch barrier layer above a first region according to an exemplary embodiment.

[0064] Figure 15 This is a schematic diagram of forming a metal layer according to an exemplary embodiment.

[0065] Figure 16 This is a schematic diagram of a stacked structure formed according to an exemplary embodiment.

[0066] Figure 17 This is a schematic diagram of forming a mask layer on a stacked structure according to an exemplary embodiment.

[0067] Figure 18 This is a schematic diagram of forming a fourth photoresist mask according to an exemplary embodiment.

[0068] Figure 19 This is a schematic diagram of forming a first gate structure and a second gate structure according to an exemplary embodiment.

[0069] Figure 20 This is a schematic diagram of forming a first device and a second device according to an exemplary embodiment.

[0070] Figure 21 This is a schematic diagram of a stacked structure formed according to an exemplary embodiment.

[0071] Figure 22 This is a schematic diagram of forming a mask layer on a stacked structure according to an exemplary embodiment.

[0072] Figure 23 This is a schematic diagram of a first gate structure and a second gate structure formed according to an exemplary embodiment.

[0073] Figure 24 This is a schematic diagram of a first device and a second device formed according to an exemplary embodiment.

[0074] Figure label:

[0075] 10. First photoresist mask; 20. Etch barrier layer; 21. Oxide layer; 22. Nitride layer; 30. Second photoresist mask; 40. Third photoresist mask; 50. Fourth photoresist mask; 100. Substrate; 110. First region; 120. Second region; 200. First device; 210. First gate structure; 211. First gate dielectric layer; 2111. First oxide layer; 2112. First high-k dielectric layer 212. First barrier layer; 213. First work function layer; 214. Second barrier layer; 215. First metal layer; 216. First isolation layer; 217. First semiconductor layer; 218. First fourth barrier layer; 220. First source region; 230. First drain region; 240. First channel region; 300. Second device; 310. Second gate structure; 311. Second gate dielectric layer; 3111. Second oxide layer; 311 2. Second high-k dielectric layer; 312. Second work function layer; 313. Third barrier layer; 314. Second metal layer; 315. Second isolation layer; 316. Second semiconductor layer; 317. Second and fourth barrier layers; 320. Second source region; 330. Second drain region; 340. Second channel region; 400. Stacked structure; 401. First stacked portion; 402. Second stacked portion; 410. Initial gate dielectric layer; 411. Initial oxide layer; 412. Initial high-k dielectric layer; 420. Initial first barrier layer; 430. Initial first work function layer; 440. Initial second barrier layer; 450. Initial second work function layer; 460. Initial third barrier layer; 470. Initial metal layer; 480. Initial isolation layer; 491. Initial semiconductor layer; 492. Initial fourth barrier layer; 500. Mask layer; 510. Silicon nitride layer; 520. Amorphous carbon layer. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0077] This disclosure provides a method for fabricating a semiconductor structure in an exemplary embodiment. When forming a device on two regions, a stacked structure is formed above the two regions. The stacked portions of the two regions in the stacked structure have the same height, and the stacked portions of the two regions in the stacked structure include work function layers corresponding to their respective regions. The stacked structure is etched to form gate structures on the two regions. The etching height of the two gate structures is the same, and the top surfaces of the two gate structures are flush. This reduces the process difficulty of forming the first gate structure and the second gate structure, and improves the yield and reliability of the semiconductor structure.

[0078] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment. Figures 3-24 The diagram below illustrates the structures formed at each stage of the semiconductor fabrication process. Figures 3-24 The method for fabricating the semiconductor structure in this embodiment will be described.

[0079] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0080] Step S110: Provide a substrate, the substrate including a first region and a second region.

[0081] like Figure 3 As shown, substrate 100 can be a semiconductor substrate, which may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The semiconductor substrate may be doped with ions; for example, it can be a P-type doped substrate or an N-type doped substrate. In this embodiment, substrate 100 is a silicon substrate.

[0082] like Figure 3 As shown, at least one first region 110 is provided in the substrate 100, which is a P-type conductive doped region, and at least one second region 120 is provided in the substrate 100, which is an N-type conductive doped region. When the substrate 100 is a P-type doped substrate or an N-type doped substrate, the doping concentration of doped ions in the first region 110 and the second region 120 is greater than the doping concentration of doped ions in the other regions of the substrate 100. In this embodiment, the substrate 100 is provided with a plurality of first regions 110 and a plurality of second regions 120, wherein the number of first regions 110 and second regions 120 may be equal or unequal.

[0083] Step S120: A first device is formed on a first region, and a second device is formed on a second region. The first device includes a first gate structure, and the second device includes a second gate structure. The top surface of the first gate structure is flush with the top surface of the second gate structure.

[0084] like Figure 20 As shown, refer to Figure 16 , Figure 17 The first gate structure 210 of the first device 200 and the second gate structure 310 of the second device 300 are formed by etching a stacked structure 400 located on the substrate 100. The heights of the first stacked portion 401 on the first region 110 and the second stacked portion 402 on the second region 120 of the stacked structure 400 are equal. The stacked structure 400 is etched once, simultaneously forming the first gate structure 210 and the second gate structure 310. In this etching process, the height of the first gate structure 210 formed by etching the first stacked portion 401 is equal to the height of the second gate structure 310 formed by etching the second stacked portion 402. That is, in the etching process, the etching rates of the first gate structure 210 and the second gate structure 310 are equal, and the first gate structure 210 and the second gate structure 310 are formed simultaneously, with the first gate structure 210 and the second gate structure 310 having the same height.

[0085] like Figure 20 As shown, refer to Figure 19 In this embodiment, the first gate structure 210 includes a first work function layer 213, and the second gate structure 310 includes a second work function layer 312. In this embodiment, the first device 200 is a PMOS, and the first work function layer 213 is a P-type work function layer formed according to the conductivity type of the first region 110. The second device 300 is an NMOS, and the second work function layer 312 is an N-type work function layer formed according to the conductivity type of the second region 120.

[0086] It should be noted that different methods can be used to keep the top surfaces of the first gate structure 210 and the second gate structure 310 flush. In one example, the first gate structure 210 includes a first work function layer 213 but not a second work function layer 312, and the second gate structure 310 includes a second work function layer 312 but not a first work function layer 213. By adjusting the number of layers and the thickness of each layer in the first gate structure 210, and by adjusting the number of layers and the thickness of each layer in the second gate structure 310, the top surfaces of the first gate structure 210 and the second gate structure 310 are made flush. In another example, the first gate structure 210 includes a first work function layer 213 and a second work function layer 312, and the second gate structure 310 also includes a first work function layer 213 and a second work function layer 312, so that the first gate structure 210 and the second gate structure 310 have the same number of layers and the same thickness of each layer, ensuring that the top surfaces of the first gate structure 210 and the second gate structure 310 are flush.

[0087] In this embodiment of the semiconductor structure formation method, the first gate structure and the second gate structure can be formed in the same etching process. The etching height for forming the first gate structure and the etching height for forming the second gate structure are equal. The first gate structure and the second gate structure are formed simultaneously and have the same morphology. This embodiment avoids the problem of different etching heights for the first or second gate structure, which could lead to one being etched while the other is still being etched, making etching time difficult to control and resulting in insufficient or over-etching of the first and / or second gate structures. This embodiment reduces the process difficulty of forming the first and second gate structures, improves the control precision of etching the first and second gate structures, and improves the yield and reliability of the formed semiconductor structure.

[0088] According to an exemplary embodiment, this disclosure provides a method for fabricating a semiconductor structure. For example... Figure 2 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0089] Step S210: Provide a substrate, the substrate including a first region and a second region.

[0090] The implementation method of step S210 in this embodiment is the same as that of step S110 in the above embodiment, and will not be repeated here.

[0091] Step S220: A stacked structure is formed on the substrate. The stacked structure includes a first stacked portion located in a first region and a second stacked portion located in a second region. The first stacked portion and the second stacked portion are of equal height.

[0092] When implementing this step, there is no specific time limit for forming the first stacked part and the second stacked part. The first stacked part can be formed first, or the second stacked part can be formed first, or a part of the first stacked part can be formed first, and then a part of the second stacked part can be formed, and then the remaining structure of the first stacked part can be formed, and then the remaining structure of the second stacked part can be formed.

[0093] In one possible implementation, step S220 may include the following steps during implementation:

[0094] Step S221: An initial gate dielectric layer is formed on a first region and a second region of the substrate, respectively. The initial gate dielectric layer includes an initial oxide layer and an initial high-k dielectric layer. The initial high-k dielectric layer is formed on the top surface of the initial oxide layer.

[0095] like Figure 4 As shown, refer to Figure 3 An initial oxide layer 411 is formed on the surface of substrate 100 using an in-situ steam generation (ISSG) process. The material of the initial oxide layer 411 may include silicon oxide or silicon oxynitride. In this embodiment, the material of the initial oxide layer 411 is silicon oxide.

[0096] An initial high-k dielectric layer 412 is formed on the top surface of the initial oxide layer 411 by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering. The initial high-k dielectric layer 412 covers the initial oxide layer 411. The material of the initial high-k dielectric layer 412 is selected as a dielectric material with a high dielectric constant. In this embodiment, the material of the initial high-k dielectric layer 412 includes hafnium or hafnium compounds. For example, the material of the initial high-k dielectric layer 412 may include one or more of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO).

[0097] like Figure 4As shown, the initial oxide layer 411 and the initial high-k dielectric layer 412 together constitute the initial gate dielectric layer 410. When the material of the initial oxide layer 411 is silicon oxide, its dielectric constant is 3.9. When the material of the initial high-k dielectric layer 412 is hafnium, its dielectric constant is approximately 25. Since the dielectric constant of the initial high-k dielectric layer 412 is greater than that of the initial oxide layer 411, under the same conditions, the thickness of the initial high-k dielectric layer formed in the semiconductor structure is thicker, increasing the thickness of the initial gate dielectric layer 410, reducing the tunneling problem of the subsequently formed first gate structure 210 and second gate structure 310, and reducing the leakage current of the first gate structure 210 and second gate structure 310.

[0098] Step S222: An initial first barrier layer, an initial first work function layer, and an initial second barrier layer are formed in sequence above the first region.

[0099] like Figure 5 As shown, an initial first barrier layer 420, an initial first work function layer 430, and an initial second barrier layer 440 are sequentially stacked on the top surface of the initial high-k dielectric layer 412 using any of the above deposition processes. The initial first barrier layer 420 may be made of titanium nitride, and the initial second barrier layer 440 may also be made of titanium nitride. In this embodiment, since the first region 110 is a P-type doped region and the first device 200 is a PMOS, the initial first work function layer 430 is a P-type work function layer corresponding to the first region 110. The material of the initial first work function layer 430 includes aluminum or an aluminum compound, wherein the aluminum compound may be, for example, aluminum nitride. Since the material of the initial first work function layer 430 is soluble in the material of the initial high-K dielectric layer 412, and the material of the initial first work function layer 430 is also soluble in the metal material of the subsequently formed initial metal layer 470, in this embodiment, an initial first barrier layer 420 is formed on the bottom surface of the initial first work function layer 430 to prevent the material in the initial first work function layer 430 from diffusing into the initial high-K dielectric layer 412, and a second barrier layer 440 is formed on the top surface of the initial first work function layer 430 to prevent the material in the initial first work function layer 430 from diffusing into the subsequently formed initial metal layer 470.

[0100] like Figure 6 As shown, refer to Figure 5 A first photoresist mask 10 is formed on the top surface of the initial second barrier layer 440. The first photoresist mask 10 covers the initial second barrier layer 440 located above the first region 110, and exposes the initial second barrier layer 440 located above the second region 120. Figure 7As shown, according to the pattern defined by the first photoresist mask 10, the initial second barrier layer 440, the initial first work function layer 430, and the initial second barrier layer 440 are etched layer by layer. The initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 formed above the second region 120 are removed, while the initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 formed above the first region 110 are retained. That is, only the initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 above the first region 110 are retained, and the initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 at other locations are all etched away.

[0101] Step S223: Form an initial second work function layer and an initial third blocking layer sequentially above the second region.

[0102] In this step, before forming the initial second work function layer, an etch barrier layer 20 needs to be formed above the first region 110. For example... Figure 8 As shown, refer to Figure 7 During implementation, an etch stop layer 20 is simultaneously formed on the top surface of the initial second barrier layer 440 above the first region 110 and on the top surface of the initial high-k dielectric layer 412 above the second region 120. The etch stop layer 20 includes an oxide layer 21 and a nitride layer 22. Figure 10 As shown, the etching barrier layer 20 formed above the second region 120 is removed, while the etching barrier layer 20 formed above the first region 110 is retained.

[0103] like Figure 8 As shown, refer to Figure 7 When forming the etch barrier layer 20, an oxide layer 21 can first be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD). The oxide layer 21 covers the top surface of the initial second barrier layer 440 and the exposed top surface of the initial high-k dielectric layer 412. The material of the oxide layer 21 includes silicon oxide or silicon oxynitride. The material of the oxide layer 21 has a high etch selectivity relative to the material of the initial second barrier layer 440, so that the oxide layer 21 can be subsequently etched away from the initial second barrier layer 440, preventing the initial second barrier layer 440 from being removed by the etching process and retaining the initial second barrier layer 440 to block the diffusion of material from the initial first work function layer 430. After forming the oxide layer 21, a nitride layer 22 can be formed on the top surface of the oxide layer 21 using CVD or PVD. The material of the nitride layer 22 includes silicon nitride.

[0104] like Figure 9As shown, a second photoresist mask 30 is formed on the top surface of the nitride layer 22 located above the first region 110. Figure 10 As shown, the nitride layer 22 and oxide layer 21 exposed outside the second photoresist mask 30 are removed sequentially by dry etching or wet etching process, while the nitride layer 22 and oxide layer 21 above the first region 110 are retained, and the etching barrier layer 20 above the first region 110 is retained.

[0105] like Figure 11 As shown, refer to Figure 10 After forming an etch stop layer 20 above the first region 110, an initial second work function layer 450 is then formed above the second region. The initial second work function layer 450 covers the top surface of the initial high-k dielectric layer 412 located above the second region 120, as well as the top surface of the etch stop layer 20. Next, an initial third barrier layer 460 is formed on the top surface of the initial second work function layer 450, covering the entire initial second work function layer 450. In this embodiment, the initial second work function layer 450 and the initial third barrier layer 460 can be formed by chemical vapor deposition or atomic layer deposition.

[0106] like Figure 12 As shown, refer to Figure 11 Next, a third photoresist mask 430 is formed on the top surface of the initial third barrier layer 460 located above the second region 120. For example... Figure 13 As shown, the initial third barrier layer 460 and the initial second work function layer 450 formed above the first region 110 are removed layer by layer by dry etching or wet etching, while the initial second work function layer 450 and the initial third barrier layer 460 formed above the second region 120 are retained.

[0107] Then, as Figure 14 As shown, refer to Figure 13 The entire etching barrier layer 20 is removed using a dry etching process or a wet etching process, exposing the top surface of the initial second barrier layer 440. At this time, the initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 are stacked above the first region 110, and the initial second work function layer 450 and the initial third barrier layer 460 are stacked sequentially above the second region 120. In this embodiment, the deposition time of the initial second work function layer 450 and the initial third barrier layer 460 can be adjusted so that the top surface of the initial third barrier layer 460 is flush with the top surface of the initial second barrier layer 440. That is, in this embodiment, the total thickness of the initial second work function layer 450 and the initial third barrier layer 460 formed on the second region 120 is equal to the total thickness of the initial first barrier layer 420, the initial first work function layer 430, and the initial second barrier layer 440 formed on the first region 110.

[0108] In this embodiment, the second region 120 is an N-type conductive doped region, the second device 300 is an NMOS, and the initial second work function layer 450 is an N-type work function layer corresponding to the second region 120. The material of the initial second work function layer 450 includes lanthanum or a lanthanum compound. For example, the lanthanum compound can be lanthanum boride.

[0109] When the material of the initial high-K dielectric layer 412 is hafnium, lanthanum or lanthanum compounds are insoluble in the initial high-K dielectric layer 412, but will dissolve in the metal material of the initial metal layer 470 formed in the subsequent fabrication. Therefore, in this embodiment, an initial third barrier layer 460 is formed on the top surface of the initial second work function layer 450. The initial third barrier layer 460 can prevent the material of the initial second work function layer 450 from dissolving into the initial metal layer 470 formed in the subsequent fabrication, so as to prevent the material in the initial second work function layer 450 from diffusing into the initial metal layer 470 in the subsequent process and causing the initial metal layer 470 to be contaminated.

[0110] Step S224: The initial metal layer and the initial isolation layer are sequentially stacked on the top surface of the initial second barrier layer and the top surface of the initial third barrier layer to form an initial metal layer and an initial isolation layer.

[0111] like Figure 15 As shown, refer to Figure 14 In step S224, an initial metal layer 470 can be formed using chemical vapor deposition or atomic layer deposition. The initial metal layer 470 covers the top surfaces of the initial second barrier layer 440 and the initial third barrier layer 460. The initial metal layer 470 is made of tungsten or a tungsten compound. The top surface of the initial first work function layer 430 is separated from the initial metal layer 470 by the initial second barrier layer 440, and the top surface of the initial second work function layer 450 is separated from the initial metal layer 470 by the initial third barrier layer 460. This prevents interpenetration between the materials of the initial metal layer 470 and the initial first work function layer 430, and also prevents interpenetration between the materials of the initial metal layer 470 and the initial second work function layer 450. This avoids cross-contamination between adjacent layers due to material penetration, ensuring high reliability of the formed semiconductor structure.

[0112] like Figure 16 As shown, in this step, an initial isolation layer 480 can be formed using chemical vapor deposition or atomic layer deposition. The initial isolation layer 480 covers the top surface of the initial metal layer 470, and the material of the initial isolation layer 480 may include silicon oxide or silicon oxynitride. By setting the initial isolation layer 480, the material of the initial metal layer 470 can be prevented from being exposed to the process environment and reacting with the gases in the process environment.

[0113] In this embodiment, as Figure 16 As shown, refer to Figure 17 The first stack portion 401 includes an initial oxide layer 411, an initial high-k dielectric layer 412, an initial first barrier layer 420, an initial first work function layer 430, an initial second barrier layer 440, an initial metal layer 470, and an initial isolation layer 480 formed over the first region 110. The second stack portion 402 includes an initial oxide layer 411, an initial high-k dielectric layer 412, an initial second work function layer 450, an initial third barrier layer 460, an initial metal layer 470, and an initial isolation layer 480 formed over the second region 120.

[0114] On one hand, the top surfaces of the initial second barrier layer 440 of the first stacked portion 401 and the initial third barrier layer 460 of the second stacked portion 402 are flush. On the other hand, the initial metal layer 470 and the initial isolation layer 480 formed above the first region 110 are formed in the same deposition process as the initial metal layer 470 and the initial isolation layer 480 formed on the second region 120. Therefore, the thickness of the initial metal layer 470 and the initial isolation layer 480 formed above the first region 110 is equal to the thickness of the initial metal layer 470 and the initial isolation layer 480 formed on the second region 120. For these two reasons, the heights of the first stacked portion 401 and the second stacked portion 402 are equal. This ensures that the etching height required to etch the first stacked portion 401 to form the first gate structure 210 is equal to the etching height required to etch the second stacked portion 402 to form the second gate structure 310. In other words, the etching time for the first stacked portion 401 and the second stacked portion 402 to form the first gate structure 210 and the second gate structure 310 is equal in the same etching process. The first gate structure 210 and the second gate structure 310 are formed simultaneously, preventing the problem of inconsistent etching progress that could lead to one forming first and the other forming later, resulting in etched portions or over-etching. This reduces the difficulty of subsequently forming the first gate structure 210 and the second gate structure 310 and improves the yield rate of the formed first gate structure 210 and the second gate structure 310.

[0115] In some embodiments, prior to forming the initial metal layer 470 and the initial isolation layer 480, the following steps are further included:

[0116] Reference Figure 21First, an initial semiconductor layer 491 is formed, covering the top surface of the initial second barrier layer 440 and the top surface of the initial third barrier layer 460. Then, an initial fourth barrier layer 492 is formed, covering the initial semiconductor layer 491. The initial semiconductor layer 491 and the initial fourth barrier layer 492 are sequentially stacked between the initial second barrier layer 440 and the initial metal layer 470 above the first region 110, and between the initial third barrier layer 460 and the initial metal layer 470 above the second region 120.

[0117] Reference Figure 14 , Figure 21 The initial semiconductor layer 491 can be formed using chemical vapor deposition or atomic layer deposition. The initial semiconductor layer 491 simultaneously covers the top surfaces of the initial second barrier layer 440 and the initial third barrier layer 460. Additionally, the initial semiconductor layer 491 also covers the exposed top surface of the initial high-k dielectric layer 412. The material of the initial semiconductor layer 491 can be one or more of single-crystal silicon or polycrystalline silicon. The material comprising the initial semiconductor layer 491 can be an intrinsic semiconductor material or a doped semiconductor material. In this embodiment, the material of the initial semiconductor layer 491 includes polycrystalline silicon.

[0118] Reference Figure 14 , Figure 21 An initial fourth barrier layer 492 is formed using chemical vapor deposition or atomic layer deposition, covering the initial semiconductor layer 491. By setting the initial fourth barrier layer 492, it isolates the initial semiconductor layer 491 from the initial semiconductor layer 491, preventing the material of the initial metal layer 470 from diffusing into the initial semiconductor layer 491. In this embodiment, the material of the initial fourth barrier layer 492 can be titanium nitride, and the titanium nitride in the initial fourth barrier layer 492 may be doped with a small amount of sulfur (S).

[0119] like Figure 21 As shown, refer to Figure 22In this embodiment, a stacked structure 400 is formed. The first stacked portion 401 includes, in addition to, an initial oxide layer 411, an initial high-k dielectric layer 412, an initial first barrier layer 420, an initial first work function layer 430, an initial second barrier layer 440, an initial metal layer 470, and an initial isolation layer 480, an initial semiconductor layer 491 and an initial fourth barrier layer 492 formed between the initial second barrier layer 440 and the initial metal layer 470. The second stacked portion 402 includes, in addition to, an initial oxide layer 411, an initial high-k dielectric layer 412, an initial second work function layer 450, an initial third barrier layer 460, an initial metal layer 470, and an initial isolation layer 480, an initial semiconductor layer 491 and an initial fourth barrier layer 492 formed between the initial third barrier layer 460 and the initial metal layer 470. Since the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the first stacked portion 401 are formed simultaneously with the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the second stacked portion 402, the thicknesses of the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the first stacked portion 401 are equal to the thicknesses of the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the second stacked portion 402. This ensures that the heights of the first stacked portion 401 and the second stacked portion 402 formed in this embodiment are equal. This ensures that the process heights of the first gate structure 210 and the second gate structure 310 are equal in subsequent processes.

[0120] Step S230: A mask layer is formed on the surface of the initial isolation layer, and the first gate structure and the second gate structure are formed by etching the stacked structure through the mask layer.

[0121] like Figure 17 As shown, during this step, a mask layer 500 can be formed using chemical vapor deposition or physical vapor deposition, covering the initial isolation layer 480. The mask layer 500 can be a single-layer or multi-layer structure. In this embodiment, the mask layer 500 is a multi-layer structure, including a silicon nitride layer 510 covering the initial isolation layer 480 and an amorphous carbon layer 520 covering the silicon nitride layer 510. The material of the silicon nitride layer 510 has a high etch selectivity relative to the material of the initial isolation layer 480 to prevent the initial isolation layer 480 from being removed during the etching process of the silicon nitride layer 510, ensuring that the initial isolation layer 480 covers the top surface of the initial metal layer 470.

[0122] like Figure 18 As shown, a fourth photoresist mask 50 is formed on the mask layer 500, as follows: Figure 19 As shown, refer to Figure 18 , Figure 20The mask layer 500 is etched according to the pattern defined by the fourth photoresist mask 50, extending the pattern of the fourth photoresist mask 50 into the mask layer 500. The retained mask layer 500 exposes a portion of the initial isolation layer 480. Based on the retained mask layer 500, a portion of the stacked structure 400 is etched away, that is, a portion of the first stacked portion 401 and a portion of the second stacked portion 402 are removed. The retained first stacked portion 401 forms the first gate structure 210, and the retained second stacked portion 402 forms the second gate structure 310. The first gate structure 210 and the second gate structure 310 formed in this step are of the same height.

[0123] In this embodiment, the projection of the first gate structure 210 onto the substrate 100 falls in the first region 110. That is, after the first gate structure 210 is formed, the first region 110 still retains a processable portion on the outer periphery of the first gate structure 210. Similarly, the projection of the second gate structure 310 formed in this embodiment onto the substrate 100 falls in the second region 120, and the exposed portion of the second region 120 is the processable portion.

[0124] Step S240: Ion implantation is performed on the first regions on both sides of the first gate structure to form the first source region and the first drain region, respectively.

[0125] like Figure 20 As shown, the exposed portion of the first region 110 on both sides of the first gate structure 210 can be ion-implanted using an ion implantation process to form a first source region 220 and a first drain region 230 on both sides of the first gate structure 210, respectively. In one example, using... Figure 20 Based on the orientation shown in the figure, boron ions (B) are injected into the left side region of the exposed first region 110. + ), forming the first source region 220; boron ions (B) are injected into the right region of the exposed first region 110. + This forms the first leak zone 230.

[0126] Continue to refer to Figure 20 After the first source region 220 and the first drain region 230 are formed, a first channel region 240 is formed in the region between the first source region 220 and the first drain region 230 below the first gate structure 210. The first gate structure 210, the first source region 220, the first drain region 230 and the first channel region 240 form the first device 200.

[0127] Step S250: Ion implantation is performed on the second regions on both sides of the second gate structure to form the second source region and the second drain region.

[0128] like Figure 20As shown, the exposed portion of the second region 120 on both sides of the second gate structure 310 can be ion-implanted using an ion implantation process to form a second source region 320 and a second drain region 330 on both sides of the second gate structure 310, respectively. In one example, using... Figure 20 Based on the orientation shown in the figure, phosphorus ions (P) are injected into the left side region of the exposed second region 120. 5+ This forms a second source region 320; phosphorus ions (P ions) are injected into the right side of the exposed second region 120. 5+ This forms the second leak zone 330.

[0129] like Figure 20 As shown, after the second source region 320 and the second drain region 330 are formed, a second channel region 340 is formed in the region between the second source region 320 and the second drain region 330 below the second gate structure 310. The second gate structure 310, the second source region 320, the second drain region 330, and the second channel region 340 form the second device 300.

[0130] In the fabrication method of this embodiment, the heights of the first stacked portion and the second stacked portion are consistent. The time for etching the first stacked portion to form the first gate structure is basically equal to the time for etching the second stacked portion to form the second gate structure. This avoids the problem of insufficient or excessive etching of the first gate structure and / or the second gate structure. It not only reduces the etching difficulty of forming the first gate structure and the second gate structure, but also improves the yield of the formed semiconductor structure.

[0131] According to an exemplary embodiment, this disclosure provides a semiconductor structure, such as... Figure 20 , Figure 24 As shown, refer to Figure 19 , Figure 23 The semiconductor structure includes a substrate 100, and at least one first device 200 and at least one second device 300 disposed on the substrate 100. The substrate 100 includes a first region 110 and a second region 120. The first device 200 is disposed on the first region 110 and includes a first gate structure 210, which includes a first work function layer 213. The second device 300 is disposed on the second region 120 and includes a second gate structure 310, which includes a second work function layer 312. The top surfaces of the first gate structure 210 and the second gate structure 310 are flush.

[0132] The first region 110 includes doped ions of a first conductivity type, and the second region 120 includes doped ions of a second conductivity type. The first and second conductivity types are different. In this embodiment, the first region 110 is a P-type conductive doped region, the first device 200 is a PMOS, and the first work function layer 213 of the first gate structure 210 is a P-type work function layer. The second region 120 is an N-type conductive doped region, the second device 300 is an NMOS, and the second work function layer 312 of the second gate structure 310 is an N-type work function layer.

[0133] In some embodiments, such as Figure 19 As shown, the first gate structure 210 includes a first gate dielectric layer 211, a first barrier layer 212, a first work function layer 213, a second barrier layer 214, a first metal layer 215, and a first isolation layer 216 stacked sequentially above the first region 110. The first gate dielectric layer 211 of the first gate structure 210 includes a first oxide layer 2111 and a first high-k dielectric layer 2112 sequentially disposed on the first region 110, with the first oxide layer 2111 located below the first high-k dielectric layer 2112.

[0134] In some embodiments, such as Figure 23 As shown, the first gate structure 210 also includes a first semiconductor layer 217 and a first fourth barrier layer 218 stacked sequentially between the second barrier layer 214 and the first metal layer 215.

[0135] like Figure 19 As shown, the second gate structure 310 includes a second gate dielectric layer 311, a second work function layer 312, a third barrier layer 313, a second metal layer 314, and a second isolation layer 315, stacked sequentially from bottom to top on the second region 120. The second gate dielectric layer 311 of the second gate structure 310 includes a second oxide layer 3111 and a second high-k dielectric layer 3112 sequentially disposed on the first region 110. The top surface of the second barrier layer 214 is flush with the top surface of the third barrier layer 313.

[0136] like Figure 23 As shown, the second gate structure 310 further includes a second semiconductor layer 316 and a second fourth barrier layer 317 stacked sequentially between the third barrier layer 313 and the second metal layer 314.

[0137] In some embodiments, such as Figure 20 , Figure 24 As shown, the first device 200 further includes a first source region 220, a first drain region 230 and a first channel region 240. The first source region 220 and the first drain region 230 are located on both sides of the first gate structure 210, and the first channel region 240 is disposed below the first gate structure 210.

[0138] In some embodiments, such as Figure 20 , Figure 24 As shown, the second device 300 also includes a second source region 320, a second drain region 330, and a second channel region 340. The second source region 320 and the second drain region 330 are located on both sides of the second gate structure 310, and the second channel region 340 is disposed below the second gate structure 310.

[0139] In this embodiment, the semiconductor structure has multiple first devices and multiple second devices disposed on the same substrate, and the heights of the first devices and second devices are equal. Both the first devices and second devices of the semiconductor structure have good electrical performance, and the yield and reliability of the semiconductor structure are higher.

[0140] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0141] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0142] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0143] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0144] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0145] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The manufacturing method includes: A substrate is provided, the substrate comprising a first region and a second region; A first device is formed on the first region, the first device including a first gate structure, the first gate structure including a first work function layer; A second device is formed on the second region, the second device including a second gate structure, the second gate structure including a second work function layer; The top surface of the first gate structure is flush with the top surface of the second gate structure; The manufacturing method includes: A stacked structure is formed on the substrate, the stacked structure including a first stacked portion located in the first region and a second stacked portion located in the second region; The first stacked portion and the second stacked portion are of the same height; The stacked structure formed on the substrate includes: An initial gate dielectric layer is formed on the first region and the second region of the substrate, respectively. The initial gate dielectric layer includes an initial oxide layer and an initial high-k dielectric layer, and the initial high-k dielectric layer is formed on the top surface of the initial oxide layer. An initial first barrier layer, an initial first work function layer, and an initial second barrier layer are sequentially stacked on the top surface of the initial high-k dielectric layer. Remove the initial first barrier layer, the initial first work function layer, and the initial second barrier layer formed above the second region, and retain the initial first barrier layer, the initial first work function layer, and the initial second barrier layer formed above the first region; An etching barrier layer is formed on the top surface of the initial second barrier layer above the first region and on the top surface of the initial high-k dielectric layer above the second region; the etching barrier layer includes an oxide layer and a nitride layer; Remove the etching barrier layer formed above the second region, and retain the etching barrier layer formed above the first region; An initial second work function layer is formed, which covers the top surface of the initial high-k dielectric layer located above the second region and the top surface of the etching barrier layer; An initial third barrier layer is formed, which covers the second work function layer; Remove the initial second work function layer, the initial third barrier layer, and the etching barrier layer formed above the first region, and retain the initial second work function layer and the initial third barrier layer formed above the second region; The top surface of the initial second barrier layer is flush with the top surface of the initial third barrier layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method of forming a stacked structure on the substrate further includes: An initial metal layer and an initial isolation layer are formed by stacking them sequentially on the top surfaces of the initial second barrier layer and the initial third barrier layer.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The method of forming a stacked structure on the substrate further includes: An initial semiconductor layer and an initial fourth barrier layer are formed, wherein the semiconductor layer and the initial fourth barrier layer are sequentially stacked between the initial second barrier layer and the initial metal layer above the first region, and between the initial third barrier layer and the initial metal layer sequentially stacked above the second region.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The manufacturing method further includes: A mask layer is formed on the surface of the isolation layer, and the stacked structure is etched through the mask layer to form the first gate structure and the second gate structure.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The manufacturing method further includes: Ion implantation is performed on the first regions on both sides of the first gate structure to form a first source region and a first drain region, respectively; Ion implantation is performed on the second regions on both sides of the second gate structure to form a second source region and a second drain region.

6. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the fabrication method according to any one of claims 1-5, and the semiconductor structure comprises: A substrate, the substrate comprising a first region and a second region; At least one first device is disposed in the first region, the first device includes a first gate structure, and the first gate structure includes a first work function layer; At least one second device is disposed in the second region, the second device includes a second gate structure, the second gate structure includes a second work function layer; The top surfaces of the first gate structure and the second gate structure are flush.

7. The semiconductor structure according to claim 6, characterized in that, The first gate structure includes a first gate dielectric layer, a first barrier layer, a first work function layer, a second barrier layer, a first metal layer, and a first isolation layer stacked sequentially on the first region. The second gate structure includes a second gate dielectric layer, a second work function layer, a third barrier layer, a second metal layer, and a second isolation layer stacked sequentially on the second region. The top surface of the second barrier layer is flush with the top surface of the third barrier layer.

8. The semiconductor structure according to claim 7, characterized in that, The first gate structure further includes a first semiconductor layer and a first fourth barrier layer stacked sequentially between the second barrier layer and the first metal layer.

9. The semiconductor structure according to claim 7, characterized in that, The second gate structure further includes a second semiconductor layer and a second fourth barrier layer stacked sequentially between the third barrier layer and the second metal layer.

10. The semiconductor structure according to claim 6, characterized in that, The first device further includes: a first source region, a first drain region, and a first channel region, wherein the first source region and the first drain region are respectively located on both sides of the first gate structure, and the first channel region is disposed below the first gate structure; The second device further includes a second source region, a second drain region, and a second channel region, wherein the second source region and the second drain region are located on opposite sides of the second gate structure, and the second channel region is disposed below the second gate structure.

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