Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and a method for manufacturing the same. The method includes: providing a substrate; forming a plurality of first trenches extending along a first direction within the substrate, the first trenches forming spaced semiconductor layers on the substrate, and filling the first trenches with a first isolation layer; forming a plurality of second trenches extending along a second direction within the semiconductor layers and the first isolation layer, the depth of the second trenches being less than the depth of the first trenches, to form a plurality of discrete semiconductor pillars and initial bit lines located below the semiconductor pillars; forming a third trench parallel to the first trenches at a position below the second trenches, the width of the third trench being greater than the width of the second trenches in a direction perpendicular to the sidewalls of the semiconductor pillars; and filling the second trenches and the third trenches with a second isolation layer, wherein the second isolation layer within the third trench has voids. This disclosure can at least improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical gate-all-around (GAA) transistor structure as a dynamic memory access transistor, its area can reach 4F² (F: the minimum pattern size achievable under given process conditions), which in principle can achieve higher density efficiency. However, due to the reduction in the spacing between adjacent bit lines, the size of the isolation layer between adjacent bit lines is also reduced, and the coupling capacitance between adjacent bit lines has an increased impact on the electrical performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the electrical performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of first trenches extending along a first direction within the substrate, the first trenches forming spaced semiconductor layers on the substrate, and filling the first trenches with a first isolation layer; forming a plurality of second trenches extending along a second direction within the semiconductor layers and the first isolation layer, the depth of the second trenches being less than the depth of the first trenches, so as to form the semiconductor layers into a plurality of discrete semiconductor pillars and initial bit lines located below the semiconductor pillars; forming a third trench parallel to the first trenches at a position below the second trenches, the width of the third trench being greater than the width of the second trenches in a direction perpendicular to the sidewalls of the semiconductor pillars; filling the second trenches and the third trenches with a second isolation layer, wherein the second isolation layer within the third trench has voids.

[0006] In some embodiments, the width of the first trench is greater than or equal to the width of the second trench in a direction perpendicular to the sidewall of the semiconductor pillar.

[0007] In some embodiments, the step of forming the third trench parallel to the first trench at a position lower than the second trench includes: forming a protective layer located on the sidewall of the second trench and exposing the top surface of the initial bit line and the top surface of the first isolation layer between adjacent initial bit lines; removing a portion of the thickness of the first isolation layer located on the sidewall of the initial bit line using the protective layer as a mask to form the third trench; and removing the protective layer.

[0008] In some embodiments, prior to forming the protective layer, the method further includes forming a third isolation layer located only on the exposed sidewall surface of the trench.

[0009] In some embodiments, under the same etching process, the etching selectivity ratio between the first isolation layer and the protective layer is greater than or equal to 50.

[0010] In some embodiments, after forming the third trench and before forming the second isolation layer, the method further includes forming a fourth isolation layer on the surface of the initial bit line exposed by the third trench, wherein the fourth isolation layer does not change the overall morphology of the third trench.

[0011] In some embodiments, after forming the fourth isolation layer and before forming the second isolation layer, the method further includes: removing the fourth isolation layer located on the top surface of the initial bit line; and performing metallization on the exposed initial bit line to form a bit line, wherein the material of the bit line includes a metal semiconductor compound.

[0012] In some embodiments, in the direction in which the semiconductor pillar points to the bit line, the depth of the third trench is greater than the depth of the metal semiconductor compound.

[0013] In some embodiments, the manufacturing method further includes: removing a portion of the thickness of the second isolation layer within the second trench to form a groove, the groove extending along the second direction; forming an insulating layer that fills the groove; removing a portion of the thickness of the first isolation layer and the second isolation layer from the sidewall of the semiconductor pillar using the insulating layer as a mask to form a gap between the semiconductor pillar and the insulating layer; and sequentially stacking a gate dielectric layer and a word line in the gap in a direction perpendicular to the sidewall of the second trench.

[0014] In some embodiments, along the direction from the initial bit line to the semiconductor pillar, the semiconductor pillar includes a first doped region, a channel region, and a second doped region arranged sequentially; the method of forming the groove includes patterning, and the sidewalls of the groove are formed by the remaining second isolation layer, and in the direction from the first doped region to the channel region, the depth of the groove is greater than or equal to the sum of the height of the channel region and the height of the second doped region.

[0015] In some embodiments, the step of forming the gap includes: removing the first isolation layer and the second isolation layer corresponding to the second doped region using the insulating layer as a mask; forming a dielectric layer, the dielectric layer surrounding the sidewall of the second doped region and located on the sidewall of the insulating layer, the sidewall of the dielectric layer forming a through hole, the bottom of the through hole exposing the first isolation layer, and the materials of the dielectric layer and the insulating layer are different from the materials of the first isolation layer; removing the second isolation layer and the first isolation layer exposed by the through hole corresponding to the channel region to form the gap, the remaining second isolation layer and the first isolation layer together surrounding the sidewall of the first doped region.

[0016] In some embodiments, the step of forming the gap includes: using the insulating layer as a mask to remove the first isolation layer and the second isolation layer corresponding to the second doped region and the channel region to form the gap, wherein the remaining second isolation layer and the first isolation layer together surround the sidewall of the first doped region.

[0017] In some embodiments, the gate dielectric layer is located at least on the sidewall of the exposed channel region, and a second gap exists between the gate dielectric layer and the insulating layer.

[0018] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate, the substrate including a plurality of spaced semiconductor layers and a first isolation layer located between adjacent semiconductor layers, the semiconductor layers including bit lines extending along a first direction and semiconductor pillars located on the top surface of the bit lines, the first isolation layer being located on the sidewall of the semiconductor pillar near the bit line and between adjacent bit lines, and a third trench being formed between the first isolation layer between adjacent bit lines and the first isolation layer located on the sidewall of the semiconductor pillar, and the third trench being spaced apart along a second direction, the second direction being different from the first direction; and a second isolation layer being located on the sidewall of the semiconductor pillar near the bit line and on the surface of the bit line exposed by the third trench, and a gap being formed within the second isolation layer located in the third trench.

[0019] In some embodiments, the semiconductor structure further includes: a gate dielectric layer surrounding at least a portion of the thickness of the remaining semiconductor pillars near the second isolation layer; word lines surrounding the sidewall surface of the gate dielectric layer away from the semiconductor pillars, the word lines extending along the second direction and spaced apart from adjacent word lines; and an insulating layer that at least fills the space.

[0020] The technical solution provided in this disclosure has at least the following advantages:

[0021] In the above technical solution, a portion of the thickness of the first isolation layer on the sidewall of the initial bit line is removed to form a third trench between adjacent initial bit lines. This results in the width of the third trench being greater than the width of the second trench in the direction perpendicular to the sidewall of the semiconductor pillar. Therefore, when the second isolation layer is subsequently formed, the region within the second isolation layer corresponding to the third trench has a gap. Thus, the adjacent initial bit lines are insulated by an isolation structure including the second isolation layer and the gap. Since the relative permittivity of air in the gap is much smaller than that of the second isolation layer, i.e., the insulation of air is better than that of the second isolation layer, it is beneficial to reduce the parasitic capacitance between adjacent initial bit lines and reduce the influence between semiconductor pillars electrically connected to different initial bit lines, thereby improving the overall electrical performance of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figures 1 to 24 This is a schematic diagram of the structure corresponding to each step of the manufacturing method of a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0024] This disclosure provides a semiconductor structure and its manufacturing method. In the manufacturing method, a third trench is formed in advance between adjacent initial bit lines, so that when a second isolation layer is formed subsequently, the region in the second isolation layer corresponding to the third trench has a gap. Since the relative permittivity of the air in the gap is much smaller than the relative permittivity of the second isolation layer, it is beneficial to reduce the parasitic capacitance between adjacent initial bit lines and reduce the influence between semiconductor pillars electrically connected to different initial bit lines, thereby improving the overall electrical performance of the semiconductor structure.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] This disclosure provides a method for manufacturing a semiconductor structure according to an embodiment. The method for manufacturing a semiconductor structure according to an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 24 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure manufacturing method provided in an embodiment of this disclosure. It should be noted that, for ease of description and clear illustration of the steps of the semiconductor structure fabrication method, the following diagrams are provided in this embodiment. Figures 1 to 24These are partial structural diagrams of semiconductor structures.

[0027] in, Figure 4 for Figure 3 Top view of the structure shown. Figure 5 for Figure 4 The diagram shows a cross-sectional view of the structure along the first section direction AA1. Figure 6 and Figure 7 This is a schematic cross-sectional view of the intermediate structure formed subsequently along the direction AA1 of the first section. Figure 8 This is a schematic cross-sectional view of the intermediate structure formed subsequently along the second section direction BB1. Figure 9 This is a cross-sectional view of the intermediate structure to be formed later along the third section direction CC1. It should be noted that, depending on the description, one, two, or three of the following will be set: a cross-sectional view along the first section direction AA1, a cross-sectional view along the second section direction BB1, and a cross-sectional view along the third section direction CC1.

[0028] refer to Figure 1 and Figure 2 A substrate 100 is provided; a plurality of first trenches 113 extending along a first direction X are formed in the substrate 100, the first trenches 113 forming spaced semiconductor layers 101 in the substrate 100; and a first isolation layer 102 is filled in the first trenches 113.

[0029] In some embodiments, providing the substrate 100 includes the following steps:

[0030] An initial substrate is provided; specifically, the material type of the initial substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium dihydrogen phosphate, etc.

[0031] The initial substrate is doped and annealed to incorporate N-type or P-type ions, which are then used to form initial bit lines and semiconductor pillars on the substrate. Specifically, the N-type ions can be at least one of arsenic, phosphorus, or antimony ions; the P-type ions can be at least one of boron, indium, or gallium ions.

[0032] refer to Figure 1 A first mask layer (not shown in the figure) is formed on the initial substrate. The first mask layer has a plurality of mutually independent first openings. The first openings extend along the first direction X, and the length of the first openings is consistent with the length of the subsequently formed initial bit line 104.

[0033] The initial substrate is etched using the first mask layer as a mask to form multiple first trenches 113.

[0034] refer to Figure 2 The first mask layer is removed and a deposition process is performed to form a first isolation membrane covering the top surface of the initial substrate and filling the first trench 113; the first isolation membrane is chemically and mechanically planarized until the top surface of the initial substrate is exposed to form the first isolation layer 102.

[0035] refer to Figures 3 to 5 Multiple second trenches 123 extending along the second direction Y are formed in the semiconductor layer 101 and the first isolation layer 102. The depth of the second trenches 123 is less than the depth of the first trenches 113, so as to form multiple discrete semiconductor pillars 105 and initial bit lines 104 located below the semiconductor pillars 105 in the semiconductor layer 101.

[0036] Continue to refer to Figures 3 to 5 In some embodiments, forming the semiconductor pillar 105 and the initial bit line 104 includes the following steps:

[0037] A second mask layer (not shown in the figure) is formed on the top surface formed by the first isolation layer 102 and the remaining initial substrate. The second mask layer has a plurality of mutually independent second openings. The second openings extend along the second direction Y, and the length of the second openings is consistent with the length of the word lines subsequently formed.

[0038] Then, the initial substrate and the first isolation layer 102 are etched using the second mask layer as a mask. It should be noted that after the semiconductor pillars 105 and the initial bit lines 104 are formed, the first isolation layer 102 is located not only in the interval between adjacent initial bit lines 104, but also in the interval between adjacent semiconductor pillars 105.

[0039] In the Z direction, the depth of the second trench 123 is less than that of the first trench 113 (reference). Figure 1 The depth of the initial bit line 104 is conducive to forming multiple discrete semiconductor pillars 105 on one side of the initial bit line 104 while forming the initial bit line 104, and the initial bit line 104 is in contact with the first doped region I of the semiconductor pillar 105; and the second mask layer is removed.

[0040] In the X direction, the width of the first groove 113 is greater than or equal to that of the second groove 123 (reference). Figure 4 The width of the trench is such that it helps to ensure the subsequent formation of the third trench 133 (reference). Figure 8 During the formation of the second trench 123, the opening of the second trench 123 is always smaller than the opening of the third trench 133, thereby ensuring the formation of the second isolation layer 132 (see reference). Figure 14 When the first trench 113 is formed, a second isolation layer 132 with gaps is formed in the corresponding region of the third trench 133. In some examples, the ratio of the width of the first trench 113 to the width of the second trench 123 can be 1.5 to 2.

[0041] The methods for forming the initial bit line 104, semiconductor pillar 105 and first isolation layer 102 include self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0042] refer to Figure 3 and Figure 5 The second trench 123 is spaced apart along the first direction X. Along the direction Z from the bottom to the top of the second trench 123, the semiconductor layer 101 includes sequentially arranged initial bit lines 104 and semiconductor pillars 105, and the semiconductor pillars 105 include sequentially arranged first doped region I, channel region II, and second doped region III. It should be noted that both the first doped region I and the second doped region III can serve as the source or drain of the subsequently formed GAA transistor with the semiconductor layer 101, and the channel region II corresponds to the gate dielectric layer and word line of the GAA transistor. In some embodiments, the initial bit lines 104 are prepared for subsequent metal silicide processing to form the bit lines.

[0043] refer to Figure 3 and Figure 4 In some embodiments, the first direction X is perpendicular to the second direction Y, such that the formed semiconductor layer 101 exhibits a 4F shape. 2 The arrangement of (F: the minimum pattern size achievable under given process conditions) is beneficial for increasing the integration density of semiconductor structures. In other embodiments, the first direction intersects the second direction, and the included angle between them can be, for example, 80°, 85°, 100°, or 120°.

[0044] It should be noted that the semiconductor layer 101 has a plurality of initial bit lines 104 arranged at intervals, and each initial bit line 104 can contact at least one first doped region I. Figure 1 The example uses four mutually spaced initial bit lines 104 and each initial bit line 104 in contact with four first doped regions I. In practical applications, the number of initial bit lines 104 and the number of first doped regions I in contact with each initial bit line 104 can be reasonably set according to actual electrical requirements.

[0045] Furthermore, the device constructed from semiconductor pillars 105 can be a junctionless transistor, meaning that the types of dopant ions in the first doped region I, channel region II, and second doped region III are the same. Here, "junctionless" refers to the absence of a PN junction, meaning the doping concentration of the dopant ions in the first doped region I, channel region II, and second doped region III is the same. This has several advantages: firstly, it eliminates the need for additional doping of the first doped region I and second doped region III, thus avoiding the difficulty in controlling the doping process of these regions, especially as transistor sizes shrink further; secondly, since the device is a junctionless transistor, it avoids the phenomenon of fabricating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. This avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, thus contributing to further improvements in the integration density and electrical performance of the semiconductor structure. It is understood that "additional doping" here refers to doping performed to differentiate the types of dopant ions in the first doped region I and second doped region III from those in the channel region II.

[0046] Please return to the reference. Figures 1 to 5 In this embodiment, the initial bit line 104 and the semiconductor layer 101 are both formed by etching the initial substrate. That is, the initial bit line 104 and the semiconductor layer 101 are formed using the same film structure, making the initial bit line 104 and the semiconductor layer 101 an integral structure, thereby improving the interface state defects between the initial bit line 104 and the semiconductor layer 101 and improving the performance of the semiconductor structure.

[0047] refer to Figures 1 to 5 In some embodiments, the top surface of the semiconductor pillar 105 away from the initial bit line 104 also has a polysilicon layer 115; in other embodiments, the top surface of the semiconductor pillar 105 may not have a polysilicon layer, that is, the top surface of the semiconductor pillar 105 may also be exposed.

[0048] refer to Figure 3 , Figures 6 to 9 A parallel groove to the first groove 113 is formed at a position lower than the second groove 123 (reference). Figure 1 The third trench 133, in the X direction, has a width greater than the width of the second trench 123. This facilitates the subsequent formation of the second isolation layer 132 (see reference). Figure 14 When the second isolation layer 132 is in place, a gap is formed in the area corresponding to the third trench 133.

[0049] In some embodiments, forming a third trench 133 parallel to the first trench 113 at a position below the second trench 123 includes the following steps:

[0050] refer to Figure 6 A protective layer 125 is formed, which is located on the sidewall of the second trench 123 and exposes the top surface of the initial bit line 104 and the top surface of the first isolation layer 102 between adjacent initial bit lines 104. It should be noted that when the top surface of the semiconductor pillar 105 is covered by a polysilicon layer 115, the protective layer 125 can also be located on the sidewall of the polysilicon layer 115.

[0051] It should be noted that, in some embodiments, references Figure 6 The protective layer 125 is located on the sidewall surface of the second trench 123. The protective layer 125 can be formed using the following process steps: performing a deposition process to form a protective film covering the sidewalls and bottom of the second trench 123 and the top surface of the semiconductor pillar 105; etching the protective film, for example, using vertical dry etching, to expose a portion of the bottom surface of the second trench 123, i.e., exposing a portion of the top surface of the initial bit line 104, with the remaining protective film serving as the protective layer 125. The material of the protective film includes silicon nitride.

[0052] In other embodiments, reference is made to Figure 7 Before forming the protective layer 125, the process may further include forming a third isolation layer 112, which is located only on the exposed sidewall surface of the second trench 123. The third isolation layer 112 and the protective layer 125 can be formed using the following process steps: first, the third isolation layer 112 is formed on the sidewall surface of the semiconductor pillar 105; then, a deposition process is performed to form a protective film covering the surface of the third isolation layer 112, the bottom surface of the second trench 123, and the top surface of the semiconductor pillar 105; the protective film is then etched, for example, using vertical dry etching, to expose a portion of the bottom surface of the second trench 123, i.e., exposing a portion of the top surface of the initial bit line 104 and the first isolation layer 102; the remaining protective film serves as the protective layer 125. The material of the protective film includes silicon nitride, and the material of the third isolation layer 112 includes silicon oxide. When the initial bit line 104 requires subsequent metallization, the third isolation layer 112 can be used to protect the semiconductor pillar 105, preventing it from being metallized.

[0053] In the two embodiments described above, in conjunction with the reference Figure 6 and Figures 8 to 9 or in conjunction with references Figures 7 to 9Using the protective layer 125 as a mask, a portion of the thickness of the first isolation layer 102 located on the sidewall of the initial bit line 104 is removed to form a third trench 133 between adjacent initial bit lines 104, preparing for the subsequent formation of a gap between adjacent initial bit lines 104. Since the material of the protective layer 125 is different from that of the first isolation layer 102, a wet etching process can be used, starting from the exposed top surface of the first isolation layer 102 exposed by the protective layer 125, to remove a portion of the thickness of the first isolation layer 102 located on the sidewall of the initial bit line 104.

[0054] In the same etching process, the etching selectivity ratio between the first isolation layer 102 and the protective layer 125 can be greater than or equal to 50, such as 60, 70, or 100, or no etching may occur. This is beneficial because when removing a portion of the thickness of the first isolation layer 102 located on the sidewall of the initial bit line 104, the protective layer 125 and the structure covered by the protective layer 125 are etched less or not at all.

[0055] Then, for example, the protective layer 125 can be removed. It should be noted that the polysilicon layer 115 can also be removed during the step of removing the protective layer 125. When there is a third isolation layer 112 between the sidewall of the semiconductor pillar 105 and the protective layer 125, in some embodiments, the third isolation layer 112 can be removed together with the protective layer 125; in other embodiments, it can be removed after the subsequent metallization process of the initial bit line 104, so that the semiconductor pillar 105 is protected by the third isolation layer 112 during the metallization process of the initial bit line.

[0056] In the direction perpendicular to the sidewall of the semiconductor pillar 105, the width of the third trench 133 is greater than the width of the second trench 123. When the width of the third trench 133 is greater than the width of the second trench 123, the width of the second trench 123 is narrower, which is beneficial for the subsequent formation of the second isolation layer 132 (see reference). Figure 14 In the step of ), the second isolation layer 132 is sealed before the third groove 133 is completely filled, so that there is a gap in the area of ​​the second isolation layer 132 corresponding to the third groove 133. The ratio of the width of the formed third groove 133 to the width of the second groove 123 can be 1.1 to 4, for example 1.5, 2, 3.5, 4.

[0057] In some embodiments, after forming the third trench 133 and before subsequently forming the second isolation layer 132, the manufacturing method may further include the following steps:

[0058] refer to Figures 10 to 12After the third trench 133 is formed, a fourth isolation layer 122 is formed on the surface of the semiconductor layer 101 exposed by the third trench 133, and the fourth isolation layer 122 does not change the overall appearance of the third trench 133.

[0059] It should be noted that after the third trench 133 is formed, the protective layer 125 and the polysilicon layer 115 are removed. In some embodiments, in Figures 12 to 14 In the step of forming the fourth isolation layer 122 shown, the third isolation layer 112 has also been removed, that is, the fourth isolation layer 122 not only surrounds the sidewall surface exposed by the initial bit line 104, but also is located on the top surface and part of the exposed sidewall of the semiconductor pillar 105; in other embodiments, when the third isolation layer is not removed, the fourth isolation layer surrounds the sidewall surface exposed by the initial bit line and is located on the top surface of the semiconductor pillar.

[0060] In both embodiments described above, the fourth isolation layer 122 can be formed by thermally oxidizing the exposed surface of the semiconductor layer 101. The fourth isolation layer 122 is used to protect other parts of the semiconductor layer 101 from the effects of metal silicide treatment during the metal silicide treatment of the top surface of the initial bit line 104. For example, firstly, it prevents other parts of the semiconductor layer 101 from being metal silicided; secondly, it prevents the presence of metallic materials between subsequent adjacent semiconductor layers 101 in addition to insulating materials, thus preventing excessive parasitic capacitance between adjacent semiconductor layers 101 and reducing the electrical performance of the semiconductor structure. Wherein, the material of the semiconductor layer 101 can be silicon, and the material of the fourth isolation layer 122 can be silicon oxide.

[0061] Then, after the fourth isolation layer 122 is formed and before the second isolation layer 132 is subsequently formed, the manufacturing method may further include the following steps:

[0062] refer to Figure 13 Remove the bit line located at initial bit line 104 (reference). Figure 10 The fourth isolation layer 122 on the top surface. It should be noted that in some embodiments, the fourth isolation layer 122 on the top surface of the semiconductor pillar 105 is also removed in the step of removing the fourth isolation layer 122 on the top surface of the initial bit line 104; in other embodiments, the fourth isolation layer 122 on the top surface of the semiconductor pillar may be retained.

[0063] Continue to refer to Figure 10 as well as Figure 13 The exposed initial bit line 104 is subjected to metallization to form bit line 114, the material of bit line 114 including metal semiconductor compound 124.

[0064] In some embodiments, the metal silicide process includes: forming a metal layer (not shown) on a fourth isolation layer 122, a portion of the top surface of the initial bit line 104, and a portion of the top surface of the first isolation layer 102; performing an annealing process to cause the metal layer to react with the initial bit line 104 to form a bit line 114; and removing any unreacted remaining metal layer.

[0065] In other embodiments, the metal silicide process includes: directionally doping the top surface of the initial bit line 104 exposed with metal elements, followed by annealing, which helps to avoid the formation of metal semiconductor compounds elsewhere that would need to be removed.

[0066] In some embodiments, in the direction of the semiconductor pillar 105 pointing to the bit line 114, the depth of the third trench 133 is greater than the depth of the metal semiconductor compound 124.

[0067] It should be noted that in some embodiments, the material of the initial bit line 104 located directly below the first doped region I is a semiconductor material, and the material of a portion of the initial bit line 104 not covered by the first doped region I is a metal semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, while the material of a portion of the initial bit line 104 located directly below the first doped region I may be a semiconductor material, the material of the remaining portions of the initial bit line 104 located directly below the first doped region I may also be a metal semiconductor compound. Here, the "remaining portions" are located outside the "partial portions."

[0068] For example, refer to Figure 13 In semiconductor layer 101, multiple metal-semiconductor compounds 124 are interconnected to form part of bit line 114; in other embodiments, multiple metal-semiconductor compounds in the same bit line may also be spaced apart from each other. It should be noted that... Figure 13 The region of semiconductor layer 101 defined by the dashed box resembling an ellipse is a metal semiconductor compound, and in practical applications, the size of the contact area between adjacent metal semiconductor compounds is not limited. In other embodiments, the initial bit line of full thickness can be converted into a metal semiconductor compound.

[0069] In other embodiments, when the top surface of the second doped region II is exposed and not protected by a polishing layer, the manufacturing method may further include: metallizing the top surface of the second doped region II. This facilitates the formation of an ohmic contact between the second doped region II and the lower electrode when a capacitor structure is subsequently formed on the top surface of the second doped region II, avoiding direct contact between the lower electrode and the semiconductor material to form a Schottky barrier contact. The ohmic contact helps reduce the contact resistance between the second doped region III and the lower electrode, thereby reducing the energy consumption of the semiconductor structure during operation and improving the RC delay effect, thus enhancing the electrical performance of the semiconductor structure. The metallization of the top surface of the initial bit line 104 and the top surface of the second doped region II can be performed in the same process step, simplifying the process. In other embodiments, the metallization of the top surface of the initial bit line 104 and the top surface of the second doped region II can also be performed step-by-step.

[0070] In the above embodiments, taking silicon as the material of semiconductor layer 101 as an example, the material of the metal layer or the directionally doped metal element may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum. The metal semiconductor compound includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide. Compared to unmetallized semiconductor materials, the metal semiconductor compound has a relatively lower resistivity. Therefore, compared to the initial unmetallized bit line 104, the bit line 114 has a lower resistivity, which helps to reduce the resistance of the bit line 114 itself and the contact resistance between the bit line 114 and the first doped region I, further improving the electrical performance of the semiconductor structure.

[0071] refer to Figures 14 to 16 In the second trench 123 (reference) Figure 3 ) and the third trench 133 (reference) Figure 8 The second isolation layer 132 is filled within the third trench 133, wherein the second isolation layer 132 within the third trench 133 has a void 143. The method for forming the second isolation layer 132 with the void 143 includes a deposition process. Since the width of the third trench 133 is greater than the width of the second trench 123 in the direction perpendicular to the sidewall of the semiconductor pillar 105 (direction X), during the deposition process of forming the second isolation layer 132, the deposition material used to form the second isolation layer 132 forms a seal above the void 143 before completely filling the third trench 133, thus forming the void 143 within the second isolation layer 132. Because the relative permittivity of air in the void 143 is much smaller than that of the second isolation layer 132, i.e., the insulating properties of air are superior to those of the second isolation layer 132, this helps to reduce the parasitic capacitance between adjacent bit lines 114 and reduce the influence between semiconductor pillars 105 electrically connected to different bit lines 114, thereby improving the overall electrical performance of the semiconductor structure.

[0072] In some embodiments, reference Figures 17 to 20 The manufacturing method may further include: removing the second groove 123 (see reference). Figure 3 A second isolation layer 132 with a certain thickness is formed to form a groove, the groove extending along the second direction Y; an insulating layer 117 is formed to fill the groove; a first isolation layer 102 and a second isolation layer 132 with a certain thickness of the semiconductor pillar 105 sidewall are removed using the insulating layer 117 as a mask to form a gap 153 between the semiconductor pillar 105 and the insulating layer 117.

[0073] Subsequently, a gate dielectric layer and word lines are formed on the basis of gap 153. The gate dielectric layer and word lines with precise dimensions can be formed in the gap 143 by self-alignment. High-precision gate dielectric layer and word lines can be formed without etching process, which helps to simplify the formation steps of gate dielectric layer and word lines. Furthermore, by adjusting the size of gap 143, small-sized gate dielectric layer and word lines can be obtained.

[0074] The method for forming the groove includes patterning, and the sidewalls of the groove are formed by the remaining second isolation layer 132. In the direction from the first doped region I to the channel region II, the depth of the groove is greater than or equal to the sum of the height of the channel region II and the height of the second doped region III, that is, the bottom surface of the insulating layer 117 near the bit line 114 is not higher than the top surface of the first doped region I away from the bit line 114. It should be noted that in practical applications, the depth of the insulating layer 117 can be at most equal to the depth of the semiconductor pillar 105. The material of the insulating layer 117 includes silicon nitride.

[0075] In addition, in other embodiments, when a third isolation layer is also present between the sidewall of the semiconductor pillar and the second isolation layer, when the second isolation layer is patterned to form a groove, the portion of the second isolation layer with a thickness corresponding to the depth of the groove is removed, and the sidewall of the groove can also be formed by the remaining third isolation layer.

[0076] In some embodiments, forming the gap 153 may include the following steps:

[0077] refer to Figures 17 to 20 Using the insulating layer 117 as a mask, the first isolation layer 102 and the second isolation layer 132 corresponding to the second doped region III are removed; a dielectric layer 127 is formed, which surrounds the sidewall of the second doped region III and is located on the sidewall of the insulating layer 117. The sidewall of the dielectric layer 127 forms a through hole 163, and the bottom of the through hole 163 exposes the first isolation layer 102. The materials of the dielectric layer 127 and the insulating layer 117 are different from the materials of the first isolation layer 102.

[0078] The insulating layer 117 and the dielectric layer 127 can both be made of silicon nitride, and the first isolation layer 102 and the second isolation layer 132 can both be made of silicon oxide. Since silicon nitride and silicon oxide have a high etching selectivity relative to the same etching process, the structure formed by the insulating layer 117 and the dielectric layer 127 can be used as a mask to etch the first isolation layer 102 and the second isolation layer 132 to form the gap 153.

[0079] refer to Figure 19 and Figure 20 Remove through hole 163 (reference) Figure 18 The exposed second isolation layer 132 and first isolation layer 102, corresponding to the channel region II, form a gap 153, and the remaining second isolation layer 132 and first isolation layer 102 together surround the sidewall of the first doped region I.

[0080] It should be noted that in some embodiments, a fourth isolation layer 122 is also provided between the sidewall of the semiconductor pillar 105 and the second isolation layer 132. When the second isolation layer 132 and the first isolation layer 102 corresponding to the channel region II are removed, the fourth isolation layer 122 corresponding to the channel region II is also removed.

[0081] Since the via 163 exposes part of the top surface of the second isolation layer 132, and the materials of the second isolation layer 132, the first isolation layer 102, and the fourth isolation layer 122 are the same, but different from the materials of the insulating layer 117 and the dielectric layer 127, etching solution can be injected into the via 163 to remove the second isolation layer 132, the first isolation layer 102, and the fourth isolation layer 122 surrounding the sidewall of the channel region II by wet etching process, while retaining the second isolation layer 132, the first isolation layer 102, and the fourth isolation layer 122 surrounding the sidewall of the first doped region I.

[0082] Furthermore, the insulating layer 117 and the dielectric layer 127 together form a support framework, which is in contact with the second doped region III, and a portion of the support framework is embedded in the second isolation layer 132. During the wet etching process, on the one hand, the support framework provides support and fixation for the semiconductor pillar 105. When the etching solution flows, it generates a squeezing force on the semiconductor pillar 105, which helps prevent the semiconductor pillar 105 from tilting or shifting due to squeezing, thereby improving the stability of the semiconductor structure. On the other hand, the support framework wraps around the sidewalls of the second doped region III, which helps prevent the etching solution from damaging the second doped region III.

[0083] In other embodiments, forming the gap may include the following steps: using an insulating layer as a mask, removing the first and second isolation layers corresponding to the second doped region and the channel region to form the gap, with the remaining second and first isolation layers together surrounding the sidewall of the first doped region. It should be noted that in some embodiments, a fourth isolation layer is also present between the sidewall of the semiconductor pillar and the second isolation layer; when removing the second and first isolation layers corresponding to the channel region, the fourth isolation layer corresponding to the channel region is also removed.

[0084] refer to Figures 21 to 22 In forming gap 153 (reference) Figure 20 After that, perpendicular to the second groove 123 (reference) Figure 3 In the direction of the sidewall, i.e. in direction X, a gate dielectric layer 118 and a word line 128 are sequentially stacked in the gap 153. The gate dielectric layer 118 is located at least on the sidewall of the exposed channel region II, and a second gap exists between the gate dielectric layer 118 and the insulating layer 117.

[0085] The method for forming the gate dielectric layer 118 includes thermal oxidation of the exposed semiconductor pillars 105. It should be noted that in some embodiments, when only the first isolation layer 102 and the second isolation layer 132 corresponding to the channel region II are removed using the insulating layer 117 as a mask, the gate dielectric layer 118 only surrounds the exposed sidewalls of the channel region II. In other embodiments, when the first isolation layer and the second isolation layer corresponding to the second doped region and the channel region are removed using the insulating layer as a mask, the gate dielectric layer is located on the sidewalls of the second doped region and the channel region, and may also be located on the top surface of the second doped region. Where the top surface of the second doped region is exposed and no mask protection is formed on the top surface of the second doped region, during the thermal oxidation process, a portion of the second doped region near the top surface is also converted to silicon oxide, which can be subsequently removed by an etching process.

[0086] In some embodiments, since the semiconductor pillar 105 is made of silicon, the step of forming the gate dielectric layer 118 includes: thermally oxidizing the exposed sidewalls of the channel region II to form the gate dielectric layer 118, and the gate dielectric layer 118 covers the remaining sidewall surfaces of the channel region II. The gate dielectric layer 118 is made of silicon oxide. In other embodiments, the gate dielectric layer covering the sidewall surfaces of the channel region can also be formed by a deposition process.

[0087] Because the exposed sidewalls of the channel region II are thermally oxidized, a portion of the channel region II is transformed into the gate dielectric layer 118. This results in the orthogonal projection of the channel region II onto the bit line 114 being smaller than the orthogonal projection of the second doped region III onto the bit line 114, and also smaller than the orthogonal projection of the first doped region I onto the bit line 114. This facilitates the formation of a channel region II with a smaller cross-sectional area in the direction Z perpendicular to the bit line 114 and pointing to the semiconductor pillar 105 without the use of an etching process. This is beneficial for improving the control capability of the subsequently formed word line over the channel region II, thereby making it easier to control the turn-on or turn-off of the GAA transistor.

[0088] Furthermore, the orthographic projection of the periphery of the gate dielectric layer 118 onto the bit line 114 is smaller than the orthographic projection of the periphery of the dielectric layer 127 onto the bit line 114. That is, the outer wall of the gate dielectric layer 118 away from the semiconductor pillar 105 is closer to the semiconductor pillar 105 than the outer wall of the dielectric layer 127 away from the semiconductor pillar 105. This ensures a second gap between the gate dielectric layer 118 and the dielectric layer 127, allowing subsequent word lines to surround the gate dielectric layer 118 located on the sidewall of the channel region II. Additionally, the outer wall of the gate dielectric layer 118 away from the semiconductor pillar 105 can also be closer to the semiconductor pillar 105 than the outer wall of the first isolation layer 102 away from the semiconductor pillar 105. The word line 128 fills the second gap, and the word line 128 is only located on the sidewall surface of the gate dielectric layer 118 corresponding to the channel region II.

[0089] It should be noted that in some embodiments, the word line 128 can be a single-layer structure; in other embodiments, the word line can be a multi-layer structure.

[0090] In some embodiments, a first word line is formed on a portion of the gate dielectric layer 118, and the first word line is also located on the top surface of the remaining isolation layer; a second word line is formed on the remaining gate dielectric layer 118, the work function value of the second word line is different from the work function value of the first word line, and the first word line and the second word line are stacked in the Z direction. The step of forming the first word line may include: forming an initial word line that fills the gap between the gate dielectric layer 118 and the insulating layer 117; removing a portion of the initial word line thickness, leaving the remaining initial word line as the first word line. The initial word line can be formed by a deposition process, and the material of the initial word line includes at least one selected from polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, cobalt, aluminum, lanthanum, copper, or tungsten.

[0091] The initial word line self-aligns and fills the gap formed by the gate dielectric layer 118 and the insulating layer 117, which facilitates the self-alignment and precise formation of the first word line. This eliminates the need for etching to design the size of the first word line, simplifying the formation process. Furthermore, by adjusting the gap size, a small-sized first word line can be obtained. The steps for forming the second word line are the same as those for forming the first word line, and will not be described in detail here. The second and first word lines together constitute word line 128.

[0092] Since the work function value of the second word line is different from that of the first word line, the work function value of word line 128 can be reduced by adjusting the work function values ​​of the second and first word lines, as well as the size ratio of the first word line to the second word line. This reduces the difference between the work function value of word line 128 and the work function value of semiconductor layer 101. On the one hand, this helps to reduce the lateral electric field at the corresponding location of word line 128 and semiconductor layer 101, reducing GIDL, which in turn helps to increase the on / off ratio of channel region II, thereby improving the sensitivity of controlling the on / off state of channel region II. On the other hand, it helps to reduce the threshold voltage of the transistor while adjusting the relevant parameters of the first and second word lines so that word line 128 can be used for different types of transistors, thereby reducing the number of semiconductor structure fabrication steps and reducing fabrication costs.

[0093] It should be noted that the above description is only an example of word line 128 containing two conductive layers with different work function values. In actual applications, there is no limit to the number of conductive layers with different work function values ​​contained in the word line.

[0094] refer to Figure 23 and Figure 24 After the word line 128 is formed, a barrier layer 109 is also formed. The barrier layer 109 fills the gaps formed by the dielectric layer 127 and is located on the top surface formed by the semiconductor pillar 105, the insulating layer 117, and the dielectric layer 127. The material of the barrier layer 109 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0095] In summary, by removing a portion of the thickness of the first isolation layer 102 from the sidewalls of the initial bit lines 104 to form a third trench 133 between adjacent initial bit lines 104, the width of the third trench 133 is greater than the width of the second trench 123 in the direction perpendicular to the sidewalls of the semiconductor pillars 105. Therefore, when the second isolation layer 132 is subsequently formed, the region within the second isolation layer 132 corresponding to the third trench 133 has a gap 143. Thus, the adjacent initial bit lines 104 are insulated from each other by the isolation structure including the second isolation layer 132 and the gap 143. Since the relative permittivity of air in the gap 143 is much smaller than that of the second isolation layer 132, i.e., the insulation of air is better than that of the second isolation layer 132, it is beneficial to reduce the parasitic capacitance between adjacent initial bit lines 104 and reduce the influence between semiconductor pillars 105 electrically connected to different initial bit lines 104, thereby improving the overall electrical performance of the semiconductor structure.

[0096] Another embodiment of this disclosure provides a semiconductor structure formed by the manufacturing method provided in the above embodiments. The semiconductor structure provided in another embodiment of this disclosure will now be described in detail with reference to the accompanying drawings.

[0097] refer to Figure 23 and Figure 24 The semiconductor structure includes: a substrate 100, which includes a plurality of spaced semiconductor layers 101 and a first isolation layer 102 located between adjacent semiconductor layers 101. Each semiconductor layer 101 includes a bit line 114 extending along a first direction X and a semiconductor pillar 105 located on the top surface of the bit line 114. The first isolation layer 102 is located on the sidewall of the semiconductor pillar 105 near the bit line 114 and between adjacent bit lines 114. A third trench is formed between the first isolation layer 102 between adjacent bit lines 114 and the first isolation layer 102 located on the sidewall of the semiconductor pillar 105. The third trench is spaced along a second direction Y, which is different from the first direction X. A second isolation layer 132 is located on the sidewall of the semiconductor pillar 105 near the bit line 114 and on the surface of the bit line 114 exposed by the third trench. A gap 143 is formed within the second isolation layer 132 located in the third trench.

[0098] In some embodiments, the semiconductor structure may further include a fourth isolation layer 122 located between the sidewall of the first doped region I and the second isolation layer 132.

[0099] In some embodiments, the semiconductor structure may further include: a dielectric layer 127 surrounding the sidewall of the second doped region III and located on the sidewall of the insulating layer 117. Furthermore, the semiconductor structure may also include: a barrier layer 109 filling the voids formed by the dielectric layer 127 and located on the top surface formed by the semiconductor pillar 105, the insulating layer 117, and the dielectric layer 127. It should be noted that in some embodiments, the dielectric layer and the barrier layer are formed in different steps, and the materials of the dielectric layer and the barrier layer are different; in other embodiments, the dielectric layer and the barrier layer can be formed in the same process step, in which case the materials of the dielectric layer and the barrier layer are the same.

[0100] The material of bit line 114 may include metal semiconductor compound 124. Metal semiconductor compound 124 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide. Compared to unmetallized semiconductor materials, metal semiconductor compound 124 has a relatively lower resistivity. Therefore, compared to unmetallized bit lines, bit line 114 including metal semiconductor compound 124 has a lower resistivity, which helps to reduce the resistance of bit line 114 itself and the contact resistance between bit line 114 and the first doped region I, further improving the electrical performance of the semiconductor structure.

[0101] In some embodiments, the semiconductor structure may further include: a gate dielectric layer 118 that surrounds at least a portion of the thickness of the remaining semiconductor pillar 105 near the second isolation layer 132; word lines 128 that surround the sidewall surface of the gate dielectric layer 118 away from the semiconductor pillar 105 and extend along a second direction Y, with a gap between adjacent word lines 128; and an insulating layer 117 that at least fills the gap.

[0102] In summary, the second isolation layer 132 has a void 143 in the region corresponding to the third trench. Since the relative permittivity of air in the void 143 is much smaller than that of the second isolation layer 132, i.e., the insulating properties of air are better than those of the second isolation layer 132, it is beneficial to reduce the parasitic capacitance between adjacent bit lines 114 and reduce the influence between semiconductor pillars 105 electrically connected to different bit lines 114, thereby improving the overall electrical performance of the semiconductor structure.

[0103] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; Multiple first trenches extending along a first direction are formed in the substrate, the first trenches form spaced semiconductor layers in the substrate, and a first isolation layer is filled in the first trenches; Multiple second trenches extending along a second direction are formed within the semiconductor layer and the first isolation layer. The depth of the second trenches is less than the depth of the first trenches, so as to form multiple discrete semiconductor pillars and an initial bit line located below the semiconductor pillars in the semiconductor layer. A third trench is formed at a position lower than the second trench, parallel to the first trench, and the width of the third trench is greater than the width of the second trench in a direction perpendicular to the sidewall of the semiconductor pillar. A second isolation layer is filled in the second trench and the third trench, wherein the second isolation layer in the third trench has voids.

2. The manufacturing method as described in claim 1, characterized in that, In a direction perpendicular to the sidewall of the semiconductor pillar, the width of the first trench is greater than or equal to the width of the second trench.

3. The manufacturing method as described in claim 1, characterized in that, The step of forming the third trench parallel to the first trench at a position lower than the second trench includes: A protective layer is formed on the sidewall of the second trench, and the top surface of the initial bit line and the top surface of the first isolation layer between adjacent initial bit lines are exposed. Using the protective layer as a mask, a portion of the thickness of the first isolation layer located on the sidewall of the initial bit line is removed to form the third trench; Remove the protective layer.

4. The manufacturing method as described in claim 3, characterized in that, Before forming the protective layer, the method further includes forming a third isolation layer, which is located only on the exposed sidewall surface of the trench.

5. The manufacturing method as described in claim 3, characterized in that, Under the same etching process, the etching selectivity ratio between the first isolation layer and the protective layer is greater than or equal to 50.

6. The manufacturing method as described in claim 3, characterized in that, After the formation of the third trench and before the formation of the second isolation layer, the method further includes: A fourth isolation layer is formed on the surface of the initial bit line exposed by the third trench, and the fourth isolation layer does not change the overall morphology of the third trench.

7. The manufacturing method as described in claim 6, characterized in that, After the formation of the fourth isolation layer and before the formation of the second isolation layer, the method further includes: Remove the fourth isolation layer located on the top surface of the initial bit line; The exposed initial bit lines are subjected to metallization to form bit lines, the material of which includes a metal semiconductor compound.

8. The manufacturing method as described in claim 7, characterized in that, In the direction from the semiconductor pillar to the bit line, the depth of the third trench is greater than the depth of the metal-semiconductor compound.

9. The manufacturing method as described in claim 1, characterized in that, Also includes: The second insulating layer, representing a portion of the thickness of the second trench, is removed to form a groove extending along the second direction; An insulating layer is formed that fills the groove; Using the insulating layer as a mask, a portion of the thickness of the first and second isolation layers of the semiconductor pillar sidewall is removed to form a gap between the semiconductor pillar and the insulating layer; In a direction perpendicular to the sidewall of the second trench, a gate dielectric layer and word lines are sequentially stacked in the gap.

10. The manufacturing method as described in claim 9, characterized in that, Along the direction from the initial bit line to the semiconductor pillar, the semiconductor pillar includes a first doped region, a channel region, and a second doped region arranged sequentially; the method of forming the groove includes patterning, and the sidewalls of the groove are formed by the remaining second isolation layer, and in the direction from the first doped region to the channel region, the depth of the groove is greater than or equal to the sum of the height of the channel region and the height of the second doped region.

11. The manufacturing method as described in claim 10, characterized in that, The steps for forming the gap include: The first isolation layer and the second isolation layer corresponding to the second doped region are removed using the insulating layer as a mask; A dielectric layer is formed, which surrounds the sidewall of the second doped region and is located on the sidewall of the insulating layer. The sidewall of the dielectric layer forms a through hole, the bottom of which exposes the first isolation layer. The materials of the dielectric layer and the insulating layer are different from the material of the first isolation layer. Remove the second isolation layer and the first isolation layer that are exposed in the via corresponding to the channel region to form the gap, and the remaining second isolation layer and the first isolation layer together surround the sidewall of the first doped region.

12. The manufacturing method as described in claim 10, characterized in that, The steps for forming the gap include: Using the insulating layer as a mask, the first isolation layer and the second isolation layer corresponding to the second doped region and the channel region are removed to form the gap, and the remaining second isolation layer and the first isolation layer together surround the sidewall of the first doped region.

13. The manufacturing method as described in claim 11 or 12, characterized in that, The gate dielectric layer is located at least on the sidewall of the exposed channel region, and a second gap exists between the gate dielectric layer and the insulating layer.

14. A semiconductor structure, characterized in that, include: The substrate includes a plurality of spaced semiconductor layers formed by a plurality of first trenches extending along a first direction formed internally, and a first isolation layer located between adjacent semiconductor layers. The semiconductor layers include bit lines extending along the first direction and semiconductor pillars located on the top surface of the bit lines. The first isolation layer is located on the sidewall of the semiconductor pillar near the bit line and between adjacent bit lines. A second trench extending along a second direction and separating adjacent semiconductor pillars, the second direction being different from the first direction; A third trench, parallel to the first trench, is formed at a position below the bottom surface of the semiconductor pillar and between adjacent bit lines. The width of the third trench is greater than the width of the second trench in a direction perpendicular to the sidewall of the semiconductor pillar. The third trench is spaced apart along the second direction and is offset from the semiconductor pillar along the second direction. A second isolation layer fills the second trench and covers the sidewall of the semiconductor pillar near the bit line end and the bit line surface exposed by the third trench. Since the width of the second trench is smaller than the width of the third trench, during the deposition of the second isolation layer, it is sealed above the third trench near the bottom of the second trench before filling it, resulting in gaps within the second isolation layer in the third trench. These gaps are segmented along the second direction between adjacent bit lines. The bit line material includes a metal semiconductor compound, and the depth of the third trench is greater than the depth of the metal semiconductor compound in the direction from the semiconductor pillar to the bit line.

15. The semiconductor structure as described in claim 14, characterized in that, Also includes: A gate dielectric layer, at least surrounding the sidewalls of the remaining semiconductor pillars with a portion of their thickness near the second isolation layer; Word lines surround the sidewall surface of the gate dielectric layer away from the semiconductor pillar, and the word lines extend along the second direction, with a gap between adjacent word lines; An insulating layer that at least fills the space.

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