Semiconductor package structure

Abstract

The semiconductor package structure provided by the present disclosure routes the power supply lines from the side of the substrate to the metal layer (such as the electromagnetic shielding layer or the circuit layer in the metal core printed circuit board (MCPCB)) outside the electronic component, and then transmits the power supply lines to the electronic component through the electrical connectors on the back of the electronic component (or the through silicon via (TSV) in the electronic component) to provide the power required for the operation of the electronic component. The signals are still transmitted from the electrical connectors on the active surface of the electronic component, so that the power supply does not interfere with the signals and affect the signal quality. At the same time, the heat generated by the operation of the power supply can be directly conducted through the metal layer and dissipated to the air, avoiding the heat generated by the operation of the power supply from affecting the performance of the electronic component in the semiconductor package structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures. Background Technology

[0002] like Figure 1 As shown, the power 7 required for the operation of the current semiconductor packaging structure is provided by the printed circuit board 1 below the chip 5. The power 7 enters the printed circuit board 1 through solder balls 2, and then enters the chip 5 through the microbumps 4 between the chip 5 and the printed circuit board 1 to provide the electrical energy required for the chip 5 to operate. The signal 8 generated by the operation of the chip 5 enters the printed circuit board 1 through the microbumps 4, and then forms electrical connections and transmits signals with other electronic components 6 disposed on the printed circuit board 1, ultimately completing the operation of the entire electronic device. However, since both the power 7 and the signal 8 enter and exit the chip 5 through the microbumps 4, the power 7 interferes with the transmission of the signal 8, thus affecting the quality of the signal 8. Summary of the Invention

[0003] This disclosure provides a semiconductor packaging structure, including:

[0004] A substrate, including power lines, one end of which is exposed from the substrate;

[0005] Electronic components are disposed on the substrate;

[0006] A metal layer covers the substrate and the electronic components, and the metal layer is in contact with and electrically connected to the power lines.

[0007] In some alternative implementations, it also includes:

[0008] A molding layer is used to encapsulate the electronic components.

[0009] In some alternative embodiments, the electronic component has opposing first and second surfaces, the first surface having a first electrical connection and the second surface having a second electrical connection, the first electrical connection being in contact with and electrically connected to the substrate, and the second electrical connection being in contact with and electrically connected to the metal layer.

[0010] In some alternative embodiments, the electronic component has a via that electrically connects the first electrical connector and the second electrical connector.

[0011] In some alternative embodiments, one end of the power line is exposed from the side surface of the substrate, and the one end of the power line is coplanar with the side surface of the substrate.

[0012] In some alternative embodiments, the substrate side surface and the molding layer side surface are coplanar.

[0013] In some alternative implementations, the metal layer is a circuit layer in a metal-based printed circuit board.

[0014] In some alternative implementations, the metal layer is a metal electromagnetic shielding layer.

[0015] In some alternative embodiments, the metallic electromagnetic shielding layer includes multiple electromagnetic shielding layers, each of which is electrically connected to a different power supply sub-line, the different power supply sub-lines being used to provide different voltages.

[0016] In some alternative embodiments, an insulating layer is provided between the plurality of electromagnetic shielding layers.

[0017] In some alternative embodiments, the power line is electrically connected to an external electrical connector to receive externally transmitted power, the external electrical connector being disposed on the lower surface of the substrate.

[0018] In some alternative embodiments, the power supply is transmitted from the external electrical connector to the substrate, then from the power lines in the substrate to the side surface of the substrate, and then from the metal layer to the first surface of the electronic component, and finally from the first electrical connector to the electronic component.

[0019] In some alternative implementations, the power supply is then transmitted to a second surface of the electronic component via a via within the electronic component.

[0020] The semiconductor packaging structure disclosed herein guides power lines from the side of the substrate to a metal layer (e.g., an electromagnetic shielding layer or a wiring layer within a metal-core printed circuit board (MCPCB)) located outside the electronic component. Power is then transferred to the electronic component via electrical connectors on its back side (or through-silicon vias (TSVs) within the electronic component) to provide the necessary power for its operation. Signals are still transmitted through electrical connectors on the active side of the electronic component, thus preventing power interference and ensuring signal quality. Simultaneously, heat generated during power operation is directly conducted through the metal layer and dissipated into the air, preventing heat from affecting the performance of the electronic component within the semiconductor packaging structure. Attached Figure Description

[0021] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a schematic diagram of the current semiconductor packaging structure;

[0023] Figure 2 This is a first structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0024] Figure 3 yes Figure 2 The diagram shows a top view of the semiconductor packaging structure.

[0025] Figure 4 This is a second structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0026] Symbol explanation:

[0027] 1-Printed circuit board, 2-Solder ball, 3-Existing substrate, 4-Micro bump, 5-Chip, 6-Electronic component, 7-Power supply, 8-Signal, 9-Substrate, 91-Power line, 92-Cavity, 10-Metal layer, 101-First electromagnetic shielding layer, 102-Second electromagnetic shielding layer, 103-Third electromagnetic shielding layer, 104-Fourth electromagnetic shielding layer, 11-Electronic component, 111-First surface, 112-Second surface, 113-First electrical connector, 1131-First power-on connector, 1132-Second power-on connector, 1133-Third power-on connector, 1134-Fourth power-on connector, 114-Second electrical connector, 115-Through hole, 12-Molding layer, 13-External electrical connector, 14-Insulating layer. Detailed Implementation

[0028] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0029] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0030] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0031] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0032] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] Figure 2 This is a first structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 2 As shown, the semiconductor package structure includes a substrate 9, an electronic component 11, and a metal layer 10. The substrate 9 includes a power line 91. One end of the power line 91 is exposed above the substrate 9. The electronic component 11 can be disposed on the substrate 9. The metal layer 10 covers the substrate 9 and the electronic component 11. The metal layer 10 is in contact with and electrically connected to the power line 91.

[0034] In this embodiment, electronic component 11 can be an active component or a passive component. Active components can be, for example, various chips (application-specific integrated circuit chips, high-bandwidth memory chips, power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips). Passive components can be, for example, capacitors, resistors, inductors, etc.

[0035] In this embodiment, the metal layer 10 can be a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof. The metal layer 10 can be used to provide an electrical connection path between the electronic component 11 and the substrate 9.

[0036] In this embodiment, the power line 91 can be a conductive material of metal or metal alloy. The power line 91 can be used to transmit power.

[0037] In one embodiment, electronic component 11 may have opposing first surfaces 111 and second surfaces 112. First surface 111 may be the active surface of electronic component 11. Second surface 112 may be the back surface of electronic component 11. First surface 111 may have a first electrical connection 113. Second surface 112 may have a second electrical connection 114. First electrical connection 113 may contact and be electrically connected to substrate 9. Second electrical connection 114 may contact and be electrically connected to metal layer 10. First electrical connection 113 and second electrical connection 114 may be, for example, conductive pillars, controlled collapse chip connection (C4) bumps, or microbumps. In one scenario, power can be transmitted through first electrical connection 113. Signals can be transmitted through second electrical connection 114, whereby power and signals can be transmitted without interference. In yet another embodiment, electronic component 11 may have a via 115. Via 115 may electrically connect first electrical connection 113 and second electrical connection 114. The via 115 can provide an alternative path for power transmission.

[0038] In one embodiment, the semiconductor enclosure structure may further include a molding layer 12. The molding layer 12 may encapsulate the electronic component 11. The molding layer 12 may be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0039] In one embodiment, one end of the power line 91 may be exposed from the side surface of the substrate 9. One end of the power line 91 may be coplanar with the side surface of the substrate 9. In yet another embodiment, the side surface of the substrate 9 may be coplanar with the side surface of the molding layer 12.

[0040] In one embodiment, the semiconductor package structure may further include an external electrical connector 13 disposed on the side of the substrate 9 away from the electronic component 11. The external electrical connector 13 may be, for example, solder balls or ball grid array (BGA) balls. A power line 91 may be electrically connected to the external electrical connector 13 to receive externally transmitted power. In another embodiment, power may be transmitted from the external electrical connector 13 to the substrate 9, then from the power line 91 in the substrate 9 to the side surface of the substrate 9, and then from the metal layer 10 to the first surface 111 of the electronic component 11, and finally from the first electrical connector 113 into the electronic component 11. In yet another embodiment, power may be further transmitted from a via 115 within the electronic component 11 to the second surface 112 of the electronic component 11.

[0041] In one embodiment, such as Figure 2 As shown, the metal layer 10 can be a metal electromagnetic shielding layer. This metal electromagnetic shielding layer not only provides electromagnetic shielding but also directly provides a path for power transmission. Simultaneously, the heat generated during power transmission can be conducted through the metal electromagnetic shielding layer and dissipated directly into the air. Furthermore, because the entire metal electromagnetic shielding layer has low resistance and inductance, the lower resistance reduces voltage fluctuations during DC power transmission, and the lower inductance also reduces voltage fluctuations during AC power transmission, both of which reduce the voltage difference transmitted from the power line 91 to the first electrical connector 113.

[0042] In another embodiment, the metallic electromagnetic shielding layer may include multiple electromagnetic shielding layers. Each electromagnetic shielding layer may be electrically connected to a different power supply sub-line. Different power supply sub-lines may be used to provide different voltages. In one scenario, the metallic electromagnetic shielding layer may be divided into multiple electromagnetic shielding layers according to the different voltage requirements of the electronic component 11. For example, as Figure 3 As shown, viewed from above, the first electromagnetic shielding layer 101 can be connected to a 0.9V voltage transmitted from the substrate 9, and then transmitted to a first power-on connector 1131 in the 0.9V region of the electronic component 11 for reception. The second electromagnetic shielding layer 102 can be connected to a 1.2V voltage transmitted from the substrate 9, and then transmitted to a second power-on connector 1132 in the 1.2V region of the electronic component 11 for reception. The third electromagnetic shielding layer 103 can be connected to a 2.5V voltage transmitted from the substrate 9, and then transmitted to a third power-on connector 1133 in the 2.5V region of the electronic component 11 for reception. The fourth electromagnetic shielding layer 104 can be connected to a 4V voltage transmitted from the substrate 9, and then transmitted to a fourth power-on connector 1134 in the 4V region of the electronic component 11 for reception. In another embodiment, an insulating layer 14 can be provided between the multiple electromagnetic shielding layers. The insulating layer 14 is used to isolate interference between the electromagnetic shielding layers. Specifically, an insulating layer 14 may be provided between the first electromagnetic shielding layer 101, the second electromagnetic shielding layer 102, the third electromagnetic shielding layer 103 and the fourth electromagnetic shielding layer 104.

[0043] In yet another embodiment, as in 2 and Figure 3 The difference in the semiconductor packaging structure shown is that, as Figure 4 The metal layer 10 in the semiconductor package structure shown can be a circuit layer in a metal-based printed circuit board. The metal layer 10 can also be a circuit layer in a ceramic substrate 9.

[0044] The semiconductor packaging structure disclosed herein guides the power supply line 91, used for transmitting power, from the side of the substrate 9 to a metal layer 10 (e.g., an electromagnetic shielding layer or a circuit layer within a metal-core printed circuit board (MCPCB)) located outside the electronic component 11. Power is then transmitted to the electronic component 11 via electrical connectors on its back side (or through-silicon vias (TSVs) in the electronic component 11), providing the electrical energy required for the operation of the electronic component 11. Signals are still transmitted through electrical connectors on the active surface of the electronic component 11, thus the power supply does not interfere with the signal and affect signal quality. Simultaneously, the heat generated by the power supply operation can be directly conducted through the metal layer 10 and dissipated into the air, preventing the heat generated by the power supply operation from affecting the performance of the electronic component 11 within the semiconductor packaging structure.

[0045] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: A substrate, including power lines, one end of which is exposed from a side surface of the substrate; Electronic components are disposed on the substrate; A metal layer covers the substrate and the electronic components. The metal layer is in contact with and electrically connected to the power lines. The metal layer is a circuit layer in a metal-based printed circuit board or a circuit layer in a ceramic substrate. The electronic component has a first surface and a second surface opposite to each other. The first surface has a first electrical connector, and the second surface has a second electrical connector. The first electrical connector is in contact with and electrically connected to the metal layer, and the second electrical connector is in contact with and electrically connected to the substrate. The first surface is the back surface of the electronic component, and the second surface is the active surface of the electronic component. Power lines for transmitting electricity are guided from the side surface of the substrate to the circuit layer of the metal-based printed circuit board or the circuit layer of the ceramic substrate located outside the electronic component, and then transmitted to the electronic component by the first electrical connector on the back side of the electronic component to provide the electrical energy required for the operation of the electronic component. Signals are transmitted from the second electrical connector on the active surface of the electronic component.

2. The semiconductor packaging structure according to claim 1, further comprising: A molding layer is used to encapsulate the electronic components.

3. The semiconductor packaging structure according to claim 1, wherein, The electronic component has a through hole inside, which electrically connects the first electrical connector and the second electrical connector.

4. The semiconductor packaging structure according to claim 1, wherein, One end of the power line is coplanar with the side surface of the substrate.

5. The semiconductor packaging structure according to claim 2, wherein, The side surface of the substrate and the side surface of the molding layer are coplanar.

6. The semiconductor packaging structure according to claim 1, wherein, The metal layer is a metal electromagnetic shielding layer.

7. The semiconductor packaging structure according to claim 6, wherein, The metal electromagnetic shielding layer includes multiple electromagnetic shielding layers, each of which is electrically connected to a different power supply sub-circuit, and the different power supply sub-circuit is used to provide different voltages.

8. The semiconductor packaging structure according to claim 7, wherein, An insulating layer is provided between the multiple electromagnetic shielding layers.

9. The semiconductor packaging structure according to claim 1, wherein, The power line is electrically connected to an external electrical connector to receive externally transmitted power. The external electrical connector is located on the lower surface of the substrate.

10. The semiconductor packaging structure according to claim 9, wherein, The power supply is transmitted from the external electrical connector to the substrate, then from the power lines in the substrate to the side surface of the substrate, and then from the metal layer to the first surface of the electronic component, and finally from the first electrical connector to the electronic component.

11. The semiconductor packaging structure according to claim 10, wherein, The power is then transmitted to the second surface of the electronic component through a via within the electronic component.

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