Semiconductor packaging device and manufacturing method thereof

Abstract

This disclosure proposes a semiconductor packaging device and a method for manufacturing the same. Different chips are connected by setting up a first line and a second line with different bandwidths. For short-distance / low data transmission rate chip-to-chip connections, a smaller bandwidth first line is used, while for long-distance / high data transmission rate chip-to-chip connections, a larger bandwidth second line is used. The larger bandwidth means a higher data transmission rate, lower signal loss, and less signal distortion. This solves the problem that signal loss and signal distortion may occur due to variables such as distance and bandwidth between transmission points, resulting in reduced signal transmission efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] In the field of semiconductor packaging technology, as technology and demands evolve, package sizes are becoming smaller, but the functions they implement and the number of chips they contain are increasing, leading to ever-growing demands for electrical performance and bandwidth. Different chips within a package have different functional requirements, and their corresponding process levels (such as 7nm and 10nm) will also differ. If a single-specification (such as 28nm) substrate is used for integration, it will result in yield loss. Therefore, one solution is to integrate different chips separately using corresponding substrates / carriers, and then connect them electrically, for example, through wire bonding.

[0003] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a longitudinal cross-section structure of chips on different substrates connected by wire bonding in the prior art. Two chips are integrated on two substrates to form two packaging modules. The first packaging module 11 is provided with a first chip 13, and the second packaging module 12 is provided with a second chip 14. The first chip 13 and the second chip 14 are then electrically connected by bonding wires 15 in a wire bonding manner.

[0004] Please refer to Figure 2 , Figure 2 This diagram illustrates the relationship between data transmission rate and transmission distance for several materials. As the diagram shows, the data transmission rate (or bandwidth) achievable by different materials varies significantly with increasing distance. Over longer distances, single-mode fiber has the highest bandwidth, followed by multimode fiber, while copper wire has the lowest bandwidth. Copper wire cannot achieve the required bandwidth over long distances.

[0005] In existing semiconductor packaging devices, chips at different distances are usually connected by electrical means (such as copper wires) to transmit signals. However, in high data transmission rate scenarios, long-distance signal transmission between chips may result in significant signal loss and distortion.

[0006] As mentioned above, in existing semiconductor packaging devices, electrical connections are used between chips to transmit signals. Due to variables such as transmission distance and bandwidth, signal loss and signal distortion may occur, resulting in reduced signal transmission efficiency. Summary of the Invention

[0007] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0008] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising: a first line for connecting a first pair of chips; a second line for connecting a second pair of chips; wherein the bandwidth of the first line is less than the bandwidth of the second line.

[0009] In some alternative implementations, the semiconductor packaging device includes a carrier plate on which both the first pair of chips and the second pair of chips are disposed.

[0010] In some alternative implementations, the second line provides signal amplification.

[0011] In some optional embodiments, the carrier board includes a redistribution layer and an active interposer layer. The chip disposed on the carrier board is connected to the active interposer layer through the redistribution layer. The active interposer layer is provided with electrical transmission lines, and the electrical transmission lines include electrical signal amplifiers. The second line includes the electrical transmission lines.

[0012] In some alternative embodiments, the semiconductor packaging device includes a substrate and two carrier plates disposed on the substrate, wherein the first pair of chips is disposed on one of the carrier plates, and the second pair of chips includes two chips respectively disposed on the two carrier plates.

[0013] In some alternative implementations, the second line includes an optical transmission line.

[0014] In some alternative implementations, the optical transmission line provides optical signal amplification.

[0015] In some optional embodiments, the carrier board includes a redistribution layer and an optical interposer layer. The chip disposed on the carrier board is connected to the optical interposer layer through the redistribution layer. The optical interposer layer is provided with an internal optical transmission line, which includes the internal optical transmission line of the carrier board.

[0016] In some alternative embodiments, the substrate is provided with an optical fiber connecting the two carrier plates, and the optical transmission line includes the optical fiber.

[0017] In some alternative implementations, the path of the second line is longer than that of the first line.

[0018] In a second aspect, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising: fabricating a first line and a second line, wherein the bandwidth of the first line is less than the bandwidth of the second line; connecting a first pair of chips using the first line; and connecting a second pair of chips using the second line.

[0019] In some alternative embodiments, fabricating the first and second lines includes: providing an interposer layer in which electrical transmission lines and / or optical transmission lines are formed, the electrical transmission lines including electrical signal amplifiers; forming a redistribution layer on the interposer layer, the redistribution layer having conductive lines disposed therein; and using the electrical transmission lines and / or optical transmission lines and the conductive lines to form the first and second lines.

[0020] In some alternative embodiments, forming the first line and the second line using the electrical transmission line and / or optical transmission line and the conductive line includes: forming the first line using the conductive line; and forming the second line using the conductive line and the electrical transmission line.

[0021] In some alternative embodiments, forming the first line and the second line using the electrical transmission line and / or optical transmission line and the conductive line includes: forming the first line using the conductive line; and forming the second line using the conductive line and the optical transmission line.

[0022] To address the issue that existing semiconductor packaging devices use electrical connections between chips to transmit signals, which can lead to signal loss and distortion due to variables such as transmission distance and bandwidth, resulting in reduced signal transmission efficiency, this disclosure provides a semiconductor packaging device and its manufacturing method. Considering the need for appropriate signal transmission methods for different chips, a first line and a second line with different bandwidths are provided to connect different chips. For short-distance / low data transmission rate chip connections, a smaller bandwidth first line is used; for long-distance / high data transmission rate chip connections, a larger bandwidth second line is used. A larger bandwidth implies a higher data transmission rate, lower signal loss, and less signal distortion. This solves the problem of reduced signal transmission efficiency due to signal loss and distortion caused by variables such as transmission distance and bandwidth. For example, in high data transmission rate scenarios, using a larger bandwidth line avoids the signal loss and distortion problems that may occur during long-distance signal transmission. Attached Figure Description

[0023] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of a longitudinal cross-sectional structure of chips on different substrates connected by wire bonding in the prior art;

[0025] Figure 2 This is a schematic diagram showing the relationship between data transmission rate and transmission distance for several materials;

[0026] Figure 3A This is a schematic diagram of the principle in top view of an embodiment 3a of the semiconductor packaging apparatus according to the present disclosure;

[0027] Figure 3B This is a schematic diagram of the principle in top view of an embodiment 3b of the semiconductor packaging device according to the present disclosure;

[0028] Figure 4 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 4a of the semiconductor packaging apparatus according to the present disclosure;

[0029] Figure 5 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 5a of the semiconductor packaging apparatus according to the present disclosure;

[0030] Figure 6 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 6a of the semiconductor packaging apparatus according to the present disclosure;

[0031] Figure 7 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 7a of the semiconductor packaging apparatus according to the present disclosure.

[0032] Explanation of reference numerals / symbols in the attached diagram:

[0033] 11-First packaging module; 12-Second packaging module; 13-First chip; 14-Second chip; 15-Bonding wire; 20-First carrier board; 21-Redistribution layer; 211-Conductive line; 22-Optical interposer; 221-Optical transmission line within the carrier board; 23-Active interposer; 231-Electrical transmission line; 232-Electrical signal amplifier; 30-Second carrier board; 40-Molding layer; 41-Electronic component; 42-Conduction structure; 50-Substrate; 51-Fiber optic cable; L1-Short-distance line; L2-Medium-distance line; L3-Long-distance line. Detailed Implementation

[0034] The specific embodiments of this disclosure are described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0035] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0036] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0037] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0038] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0039] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0040] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0041] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] refer to Figure 3A , Figure 3A This is a schematic diagram of the principle in top view of one embodiment 3a of the semiconductor packaging device according to the present disclosure.

[0043] like Figure 3A As shown, this semiconductor packaging device 3a includes a first carrier 20 on which a plurality of chips, such as A1 to A6, are disposed. To achieve interconnection between the chips, the semiconductor packaging device 3a is provided with:

[0044] The first line is used to connect the first pair of chips;

[0045] The second line is used to connect the second pair of chips;

[0046] The bandwidth of the first line is less than that of the second line.

[0047] Here, compared to the first pair of chips, the distance between the first pair of chips may be smaller than the distance between the second pair of chips, and / or the data transmission rate required between the first pair of chips may be lower than the data transmission rate required between the second pair of chips.

[0048] like Figure 3A As shown, for example: the first pair of chips may include chips A1 and A2, and the second pair of chips may include chips A1 and A6. Both the second pair of chips and the first pair of chips are disposed on the first carrier board 20, and the distance between the second pair of chips is greater than the distance between the first pair of chips. In this case, the first line may be... Figure 3A The second line, which is the short-distance line L1 shown in the diagram, may be... Figure 3A The medium-distance line L2 shown in the diagram has a longer path than the short-distance line L1.

[0049] Here, the first line (e.g., short-distance line L1) may be a low-bandwidth electrical connection line, while the second line (e.g., medium-distance line L2) may be a high-bandwidth electrical connection line. Optionally, the bandwidth of the second line can be made greater than that of the first line by designing impedance matching, line width / spacing, input / output (I / O), etc. Optionally, the second line may also be an electrical connection line with signal amplification function, utilizing signal amplification to increase bandwidth capability. Optionally, the path of the second line is longer than that of the first line.

[0050] The semiconductor packaging device disclosed herein can be used for wafer-level packaging and can also be extended to system-level packaging. The chip mentioned herein can be, for example, a die or a chiplet, specifically, an application-specific integrated circuit (ASIC), memory, input / output (I / O), etc.

[0051] refer to Figure 3B , Figure 3B This is a schematic diagram of the principle in top view of one embodiment 3b of the semiconductor packaging device according to the present disclosure. Figure 3B The semiconductor packaging device 3b shown is similar to Figure 3A The semiconductor packaging device 3a shown differs in that:

[0052] This semiconductor packaging device 3b includes two carrier plates, namely, a second carrier plate 30 in addition to the first carrier plate 20, on which a plurality of chips, such as chips B1 to B6, are disposed. The first carrier plate 20 and the second carrier plate 30 are disposed on a substrate 50. To achieve inter-chip interconnection, the semiconductor packaging device 3b is provided with:

[0053] The first line is used to connect the first pair of chips;

[0054] The second line is used to connect the second pair of chips;

[0055] The bandwidth of the first line is less than that of the second line.

[0056] Here, compared to the first pair of chips, the distance between the first pair of chips may be smaller than the distance between the second pair of chips, and / or the data transmission rate required between the first pair of chips may be lower than the data transmission rate required between the second pair of chips.

[0057] like Figure 3BAs shown in one example: the first pair of chips may include chips A1 and A2, and the second pair of chips may include chips A4 and B4. The first pair of chips is disposed on the first carrier board 20, and the two chips A4 and B4 in the second pair are disposed on the first carrier board 20 and the second carrier board 30, respectively. The distance between the second pair of chips is greater than the distance between the first pair of chips. In this case, the first line may be... Figure 3B The second line, which is the short-distance line L1 shown in the diagram, may be... Figure 3B The long-distance line L3 shown is longer than the short-distance line L1. In another example: the first pair of chips may include chips A1 and A2, and the second pair of chips may include chips A1 and B4. The first pair of chips is disposed on the first carrier board 20, and the two chips A1 and B4 of the second pair of chips are disposed on the first carrier board 20 and the second carrier board 30, respectively. The distance between the second pair of chips is greater than the distance between the first pair of chips.

[0058] like Figure 3B As shown, in another example: the first pair of chips may also include chips A1 and A6, and the second pair of chips may include chips A4 and B4. The first pair of chips is disposed on the first carrier board 20, and the two chips A4 and B4 in the second pair are disposed on the first carrier board 20 and the second carrier board 30 respectively. The distance between the second pair of chips is greater than the distance between the first pair of chips. Here, the first line may be... Figure 3B The medium-distance line L2 shown in the diagram, the second line may be... Figure 3B The long-distance line L3 shown is longer than the path of the medium-distance line L2. In another example: the first pair of chips may also include chips A1 and A6, and the second pair of chips may include chips A1 and B4. The first pair of chips is disposed on the first carrier board 20, and the two chips A1 and B4 of the second pair of chips are disposed on the first carrier board 20 and the second carrier board 30, respectively. The distance between the second pair of chips is greater than the distance between the first pair of chips.

[0059] Here, the first line may be an electrical connection line, which may or may not have signal amplification function (such as short-distance line L1) or may have signal amplification function (such as medium-distance line L2). Here, the second line (such as long-distance line L3) may include an optical transmission line. Optionally, the optical transmission line may include an in-carrier optical transmission line disposed within the carrier board and an optical fiber 51 disposed in the substrate 50 connecting the two carrier boards; the optical fiber 51 serves as an inter-carrier optical transmission line. In this case, the second line may also include a conductive line disposed within the carrier board, which is used to connect the chip on the carrier board and the in-carrier optical transmission line. Here, the optical fiber 51 may be, for example, multi-mode fiber or single-mode fiber. Optionally, the optical transmission line may also further provide optical signal amplification function to increase the bandwidth capability of the second line. Optionally, the path of the second line is longer than the path of the first line.

[0060] Below, in conjunction with Figure 4-6 To further explain, Figure 3A and 3B The specific implementation methods of the short-distance line L1, medium-distance line L2, and long-distance line L3 shown are illustrated.

[0061] refer to Figure 4 , Figure 4 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 4a of the semiconductor packaging apparatus according to the present disclosure. Figure 4 The specific implementation of the short-distance line L1 is shown.

[0062] Semiconductor packaging apparatus 4a includes a first substrate 20 on which chips A1 and A2 are disposed. The first substrate 20 includes a redistribution layer (RDL) 21. The RDL 21 contains conductive lines 211 that electrically connect chips A1 and A2, serving as a short-distance connection L1 between the first pair of chips A1 and A2 that are close to each other. That is, the RDL provides direct electrical connection between the chips in close proximity.

[0063] refer to Figure 5 , Figure 5 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 5a of the semiconductor packaging apparatus according to the present disclosure. Figure 5 The specific implementation of the medium-distance line L2 is shown.

[0064] Semiconductor packaging apparatus 5a includes a first substrate 20 on which chips A1 and A6 are disposed. The first substrate 20 includes an RDL 21 and an active interposer 23. Chips A1 and A6 on the first substrate 20 are connected to the active interposer 23 via the RDL 21. Here, the active interposer 23 may contain electrical transmission lines 231. Chips A1 and A6 are connected via a mid-distance line L2. The mid-distance line L2 may include the electrical transmission line 231 and conductive lines 211 in the RDL 21 for connecting the electrical transmission line 231 to chips A1 or A6. That is, the mid-distance connection is made using an active interposer.

[0065] Optionally, the bandwidth of the medium-distance line L2 can be made greater than that of the short-distance line L1 by designing impedance matching, line width / spacing, input / output (I / O) and other methods.

[0066] Optionally, the electrical transmission line 231 includes an electrical signal amplifier 232 to increase bandwidth by amplifying the signal. In this case, the intermediate-distance line L2 is an electrical connection line with signal amplification function. To provide signal amplification, the first carrier board 20 may also include IVR (Integrated Voltage Regulator) related components.

[0067] Here, the active interposer 23 is different from the ordinary interposer in that it may contain some active devices such as electrical signal amplifiers 232, hence it is called an active interposer.

[0068] Here, the distance between chips A1 and A6 is longer than the distance between chips A1 and A2 in embodiment 4a. When the electrical signal is transmitted over a longer distance, there may be problems such as weakening of signal strength or distortion. Therefore, an active interposer is used for electrical signal transmission (or appropriate amplification is performed at the same time) to alleviate the above problems.

[0069] Depending on the distance between chips, active interposers are used for longer distances, while RDLs are used for shorter distances. This division of labor brings the following advantages: the number of RDL layers does not need to be too thick, and active interposers are only used to place amplifiers between specific chips, making the design simpler.

[0070] refer to Figure 6 , Figure 6 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 6a of the semiconductor packaging apparatus according to the present disclosure. Figure 6 The specific implementation of the long-distance line L3 is shown.

[0071] The semiconductor packaging device 6a includes two carrier plates: a first carrier plate 20 and a second carrier plate 30. Chip A4 is disposed on the first carrier plate 20, and chip B4 is disposed on the second carrier plate 30. The two carrier plates have similar structures. Taking the first carrier plate 20 as an example, the first carrier plate 20 includes an RDL 21 and an optical interposer 22. Chip A4 on the first carrier plate 20 is connected to the optical interposer 22 via the RDL 21. An intra-carrier optical transmission line 221 is disposed in the optical interposer 221, which includes a photoelectric converter. The structure of the second carrier plate 30 is similar and will not be described in detail. An optical fiber 51 can be disposed between the first carrier plate 20 and the second carrier plate 30 as an inter-carrier optical transmission line. The optical fiber 51 can be disposed in the substrate 50 supporting the two carrier plates. Here, the intra-carrier optical transmission line 221 and the optical fiber 51 serving as the inter-carrier optical transmission line are connected to form the optical transmission line.

[0072] Chips A4 and B4 are connected via a long-distance line L3. The long-distance line L3 may include the optical transmission line consisting of the optical transmission line 221 in the carrier board and the optical fiber 51, as well as the conductive line 211 provided in RDL21 for connecting the optical transmission line 221 in the carrier board to chip A4 or B4.

[0073] Optionally, the optical transmission line may also include an optical signal amplifier to provide optical signal amplification and increase bandwidth capability.

[0074] Here, the optical interposer 22 is distinguished from ordinary interposers in that it contains circuits and electronic components for light transmission, hence the name optical interposer.

[0075] It should be noted that in some other embodiments, the long-distance line L3 can also be used to connect two chips on the same carrier board. In this case, the optical transmission line in the long-distance line L3 may only include the optical transmission line 221 within the carrier board, and not the optical fiber 51 which serves as the optical transmission line between carrier boards.

[0076] Here, the transmission distance between chips A4 and B4 is very long, but high data rate communication is required. If electrical signals are still used for transmission, the signal loss and distortion may be greater than in embodiments 4a and 5a. Therefore, this embodiment embeds a photoelectric converter in the optical interposer to convert the electrical signal into an optical signal and uses an optical transmission line to transmit the signal, thereby alleviating the above problems.

[0077] Here, the RDL layer does not need to be too thick, and the optical interposer layer can be used to embed the photoelectric converter only between specific chips, which is relatively simple in design.

[0078] Please continue to refer to this. Figure 4-6 ,from Figure 4-6 As can be seen, in some embodiments of this disclosure, the first carrier 20 may be a multilayer structure, comprising the following layers in sequence: RDL 21, optical interposer 22, and active interposer 23. The optical interposer 22 provides an internal optical transmission line 221, the active interposer 23 provides an electrical transmission circuit 231, and the RDL 21 provides a conductive line 211. Additionally, the substrate 50 supporting the first carrier 20 and the second carrier 30 may also provide an optical fiber 51 connecting the two carriers, serving as an inter-carrier optical transmission line.

[0079] Here, as needed, some or all of these lines, such as conductive lines 211, electrical transmission circuits 231, optical transmission lines 221 within the carrier board, and optical fibers 51, can be used to form connection lines between different chips. For example, a first line can be formed to connect a first pair of chips, and a second line with a bandwidth greater than that of the first line can be formed to connect a second pair of chips.

[0080] In some alternative implementations, for example, the short-distance line L1 described above can be used as the first line, and the medium-distance line L2 described above can be used as the second line.

[0081] In other alternative implementations, for example, the long-distance line L3 described above can be used as the second line, and the short-distance line L1 described above can be used as the first line, or the medium-distance line L2 described above can be used as the first line.

[0082] Additionally, it should be noted that the three-layer structure in the first carrier 20, namely RDL21, optical interposer 22, and active interposer 23, are configured as follows: Figure 5 As shown, optical interposer 22 is located between RDL 21 and active interposer 23. In some alternative embodiments, active interposer 23 may also be located between RDL 21 and optical interposer 22. In other alternative embodiments, optical interposer 22 and active interposer 23 may be implemented by a single interposer, that is, providing optical and electrical transmission lines in a single interposer to realize the functions of optical interposer 22 and active interposer 23. Here, RDL 21, optical interposer 22, and active interposer 23 together form a hybrid interposer with photoelectric conversion function.

[0083] refer to Figure 7 , Figure 7 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 7a of the semiconductor packaging apparatus according to the present disclosure. Figure 7 The semiconductor packaging device 7a shown is similar to Figure 5 The semiconductor packaging device 5a shown differs in that:

[0084] The semiconductor packaging device 7a also includes a molding layer 40 and a substrate 50. A first carrier 20 is disposed on the molding layer 40, and the molding layer 40 is disposed on the substrate 50. The molding layer 40 may be electrically connected to the substrate 50 via bumps. The molding layer 40 may encapsulate some electronic components 41 and may have some conductive structures 42.

[0085] It should be noted that the optical and electrical transmission lines mentioned above may require some electronic components 41, and other electronic components 41 may also be needed to achieve other functions. These electronic components 41 can be encapsulated in the molding layer 40. Here, electronic components 41 may include, for example, bare dies, power management ICs (PMICs), deep trench capacitors (DTCs), etc. Here, the molding layer 40 may be formed using molding materials such as epoxy resin. Here, some electronic components in the molding layer 40, especially optoelectronic components, can be stacked and packaged using through-silicon via (TSV) technology, for example, to reduce space occupation and package size.

[0086] Here, the conductive structure 42 may include, but is not limited to, vias, pillars, etc. The first carrier board 20 can be electrically connected to the substrate 50 through the conductive structure 42.

[0087] To facilitate understanding and implementation of this disclosure, one embodiment of this disclosure also provides a method for manufacturing a semiconductor packaging device, the method comprising the steps of:

[0088] S1. Create a first line and a second line, where the bandwidth of the first line is less than the bandwidth of the second line;

[0089] S2. Connect the first pair of chips using the first line and connect the second pair of chips using the second line.

[0090] In some alternative implementations, step S1 may include: providing an interposer layer, forming electrical transmission lines and / or optical transmission lines in the interposer layer, the electrical transmission lines including electrical signal amplifiers; forming a redistribution layer RDL on the interposer layer, the RDL having conductive lines, and forming a first line and a second line using the electrical transmission lines and / or optical transmission lines and the conductive lines.

[0091] In some alternative implementations, step S1, which involves forming the first line and the second line using electrical transmission lines and / or optical transmission lines as well as conductive lines, may include: forming the first line using conductive lines; and forming the second line using conductive lines and electrical transmission lines.

[0092] In some alternative implementations, the process of forming the first line and the second line in step S1 using electrical transmission lines and / or optical transmission lines and conductive lines may include: forming the first line using conductive lines; and forming the second line using conductive lines and optical transmission lines.

[0093] In summary, to address the problem that existing semiconductor packaging devices use electrical connections between chips to transmit signals, which can lead to signal loss and distortion due to variables such as transmission distance and bandwidth, resulting in reduced signal transmission efficiency, this disclosure provides a semiconductor packaging device and its manufacturing method. Considering the need to employ appropriate signal transmission methods for different chips, a first line and a second line with different bandwidths are provided to connect different chips. For short-distance / low data transmission rate chip connections, a smaller bandwidth first line is used; for long-distance / high data transmission rate chip connections, a larger bandwidth second line is used. A larger bandwidth implies a higher data transmission rate, lower signal loss, and less signal distortion. This solves the problem of reduced signal transmission efficiency due to signal loss and distortion caused by variables such as transmission distance and bandwidth. For example, in high data transmission rate scenarios, a larger bandwidth line is used to avoid signal loss and distortion that may occur during long-distance signal transmission.

[0094] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: The first line is used to connect the first pair of chips; The second line is used to connect the second pair of chips; The bandwidth of the first line is less than the bandwidth of the second line, and the path of the second line is longer than the path of the first line. The semiconductor packaging device includes a carrier plate, on which the first pair of chips and the second pair of chips are disposed; The second line provides signal amplification. The carrier board includes a redistribution layer and an active interposer layer. The chips disposed on the carrier board are connected to the active interposer layer through the redistribution layer. The active interposer layer is provided with electrical transmission lines, and the electrical transmission lines include electrical signal amplifiers. The second line includes the electrical transmission lines. The redistribution layer is provided with conductive lines, and the first line includes the conductive lines.

2. A semiconductor packaging apparatus, comprising: The first line is used to connect the first pair of chips; The second line is used to connect the second pair of chips; The bandwidth of the first line is less than the bandwidth of the second line, and the path of the second line is longer than the path of the first line. The semiconductor packaging device includes a substrate and two carrier plates disposed on the substrate, wherein the first pair of chips is disposed on one of the carrier plates, and the second pair of chips includes two chips respectively disposed on the two carrier plates; The second line includes an optical transmission line that provides optical signal amplification. The carrier board includes a redistribution layer and an optical interposer layer. The chip disposed on the carrier board is connected to the optical interposer layer through the redistribution layer. The optical interposer layer is provided with an internal optical transmission line of the carrier board. The optical transmission line includes the internal optical transmission line of the carrier board. The substrate is provided with an optical fiber connecting the two carrier plates, and the optical transmission line further includes the optical fiber; The redistribution layer is provided with conductive lines, and the first line includes the conductive lines.

3. The semiconductor packaging apparatus according to claim 2, wherein, The carrier board further includes an active interposer layer, in which an electrical transmission line is disposed, and the first line further includes the electrical transmission line.

4. A method for manufacturing a semiconductor packaging device, comprising: Create a first line and a second line, wherein the bandwidth of the first line is less than the bandwidth of the second line, and the path of the second line is longer than the path of the first line. The first pair of chips is connected using the first line, and the second pair of chips is connected using the second line. The fabrication of the first and second lines includes: providing an intermediary layer, forming an electrical transmission line and / or an optical transmission line in the intermediary layer, wherein the electrical transmission line includes an electrical signal amplifier; A redistribution layer is formed on the intermediary layer, and conductive lines are provided in the redistribution layer. The electrical transmission lines and / or optical transmission lines, as well as the conductive lines, are used to form a first line and a second line.

5. The method according to claim 4, wherein, The process of forming the first line and the second line using the electrical transmission line and / or optical transmission line and the conductive line includes: The first circuit is formed using the conductive line; the second circuit is formed using the conductive line and the electrical transmission line. or, The first line is formed using the conductive line; the second line is formed using the conductive line and the optical transmission line. or, The first line is formed using the conductive line and the optical transmission line; the second line is formed using the conductive line and the optical transmission line.

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