Structure, manufacturing method of composite power device and power electronic equipment
Patent Information
- Application Number
- CN202111583824.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-22
- Publication Date
- 2026-10-20
- Estimated Expiration
- 2041-12-22
AI Technical Summary
[0008]本申请的目的在于提供一种复合功率器件的结构、制造方法及电力电子设备，旨在解决相关的复合功率器件的效能无法得到提升的问题
[0040]本发明实施例与现有技术相比存在的有益效果是：由于在垂直于水平面的方向，相邻的堆叠层的相邻行的多个功率元件交错设置，且相邻的堆叠层的相邻列的多个功率元件交错设置；故通过交错布局的立体并联结构，可以在单位面积内制造更多的并联的功率元件，以在单位面积内实现更大的电流的驱动，提高了复合功率器件的效能。
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Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to the structure, manufacturing method and power electronic equipment of a composite power device. Background Technology
[0002] Power electronic devices utilize a large number of power components, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS) or insulated-gate bipolar transistor (IGBT). To provide high current, multiple power components need to be connected in parallel, which creates a demand for composite power devices.
[0003] In designing composite power devices, maximizing the number of parallel power elements within a given area has become a key challenge. However, limitations in doping processes necessitate maintaining sufficient distance between the doped regions of the two power elements to ensure the performance of the composite power device.
[0004] Currently, there are two types of related composite power devices.
[0005] The first approach is to use more advanced processes to reduce the distance between the doped regions of two power devices, thereby increasing the number of power devices per unit area. For example, the 0.25µm process can be improved to a 0.18µm process or a 0.13µm process.
[0006] The second approach involves designing power components with special shapes to increase the number of power components that can be accommodated per unit area. For example, designing hexagonal metal-oxide-semiconductor field-effect transistors (MOSFETs).
[0007] However, the first method is easily constrained by the manufacturing process of semiconductor equipment, and the second method cannot use power components of conventional shapes, so the performance of composite power devices cannot be improved. Summary of the Invention
[0008] The purpose of this application is to provide a structure, manufacturing method and power electronic device for a composite power device, which aims to solve the problem that the performance of the composite power device cannot be improved.
[0009] This application provides a structure for a composite power device, including:
[0010] It includes n stacked layers arranged parallel to the horizontal plane; where n is a natural number greater than 1.
[0011] In each of the stacked layers, multiple power elements are spaced apart in both the lateral and longitudinal directions;
[0012] In a direction perpendicular to the horizontal plane, the power elements in adjacent rows of adjacent stacked layers are staggered, and the power elements in adjacent columns of adjacent stacked layers are staggered.
[0013] In one embodiment, the plurality of power elements in the stacked layers of odd-numbered layers are first power elements;
[0014] The power elements in the even-numbered stacked layers are second power elements.
[0015] In one embodiment, the gates of each of the power elements in the n stacked layers are connected, the drains of each of the power elements in the n stacked layers are connected, and the sources of each of the power elements in the n stacked layers are connected.
[0016] This application also provides a method for manufacturing a composite power device, the method comprising:
[0017] Step A: Provide a substrate or grow an epitaxial layer;
[0018] Step B: A plurality of power elements are formed on the substrate or the epitaxial layer, and the plurality of power elements are spaced apart in both the lateral and longitudinal directions;
[0019] Step C: An etch stop layer and a metal contact layer are sequentially grown at the source and gate of the plurality of power elements;
[0020] Step D: Form a first via that is connected to the drain of the plurality of power elements, and grow a first metal layer connected to the first via on the substrate or the upper surface of the epitaxial layer;
[0021] Step E: Grow a dielectric layer on the surface of the plurality of power elements;
[0022] Step F: Form a second via that connects to the first metal layer inside the dielectric layer;
[0023] Repeat steps A through F n times to form n stacked layers; where n is a natural number greater than 1.
[0024] Step G: Form a plurality of third vias connected to the sources of the plurality of power elements inside the epitaxial layer and the dielectric layer; form a plurality of fourth vias connected to the gates of the plurality of power elements inside the epitaxial layer and the dielectric layer;
[0025] Step H: A second metal layer is formed on the upper surface of the nth stacked layer; wherein the second metal layer connects to a plurality of the third vias and a plurality of the fourth vias.
[0026] In one embodiment, when forming an odd number of stacked layers, step B specifically involves: forming a plurality of first power elements on the substrate or the epitaxial layer using a first set of semiconductor processes, wherein the plurality of first power elements are spaced apart in both the lateral and longitudinal directions;
[0027] When an even number of stacked layers are formed, step B specifically involves forming a plurality of second power elements on the substrate or the epitaxial layer using a second set of semiconductor processes. The plurality of second power elements are spaced apart in both the lateral and longitudinal directions.
[0028] In one embodiment, step C includes:
[0029] The etch stop layer is deposited at the source and gate of the plurality of power elements;
[0030] The metal contact layer is grown on the upper surface of the etching stop layer.
[0031] In one embodiment, step D includes:
[0032] A first via is formed by etching to connect to the drain of the plurality of power elements, and the first via is filled with metal;
[0033] The first metal layer connected to the first via is grown on the surface of the substrate or the epitaxial layer by vapor deposition or sputtering.
[0034] In one embodiment, step H includes:
[0035] A third metal layer is formed on the upper surface of the nth stacked layer;
[0036] The second metal layer is formed on the third metal layer by imaging;
[0037] The second metal layer connects to a plurality of the third through holes and to a plurality of the fourth through holes.
[0038] In one embodiment, in adjacent stacked layers, the drain of each power element in the upper stacked layer is connected to the second via in the lower stacked layer.
[0039] This application also provides a power electronic device, which includes the structure of the composite power device described above.
[0040] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: Since multiple power elements in adjacent rows of adjacent stacked layers are staggered in the direction perpendicular to the horizontal plane, and multiple power elements in adjacent columns of adjacent stacked layers are staggered, more parallel power elements can be manufactured in a unit area through the staggered three-dimensional parallel structure, so as to achieve a larger current drive in a unit area and improve the efficiency of composite power devices. Attached Figure Description
[0041] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 A schematic diagram of the horizontal plane of each stacked layer in a composite power device provided in an embodiment of this application;
[0043] Figure 2 A three-dimensional structural schematic diagram of a composite power device provided in an embodiment of this application;
[0044] Figure 3 A schematic diagram of a substrate provided in a method for manufacturing a composite power device according to an embodiment of this application;
[0045] Figure 4 A schematic diagram illustrating the formation of multiple power elements in a method for manufacturing a composite power device according to an embodiment of this application;
[0046] Figure 5 This is a schematic diagram of the growth of an etch stop layer and a metal contact layer in the manufacturing method of the composite power device provided in the embodiments of this application;
[0047] Figure 6 This is a schematic diagram illustrating the formation of a first through-hole and a first metal layer in a method for manufacturing a composite power device according to an embodiment of this application.
[0048] Figure 7 A schematic diagram of the growth of a dielectric layer in the manufacturing method of the composite power device provided in the embodiments of this application;
[0049] Figure 8 A schematic diagram illustrating the formation of a second through-hole in a method for manufacturing a composite power device according to an embodiment of this application;
[0050] Figure 9 This is a schematic diagram of a power element forming an upper stacked layer in a method for manufacturing a composite power device according to an embodiment of this application;
[0051] Figure 10 A schematic diagram illustrating the formation of a third through hole and a fourth through hole in a method for manufacturing a composite power device according to an embodiment of this application;
[0052] Figure 11 A schematic diagram illustrating the formation of a second metal layer in a method for manufacturing a composite power device according to an embodiment of this application;
[0053] Figure 12 This is a schematic diagram of the power element in a composite power device provided in an embodiment of this application. Detailed Implementation
[0054] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0055] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0056] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0058] Figure 1 The module structure of the composite power device provided in the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:
[0059] A composite power device comprising n stacked layers arranged parallel to a horizontal plane; n is a natural number greater than 1.
[0060] like Figure 1 As shown, in each stack layer, multiple power elements 11 are spaced apart in both the lateral and longitudinal directions.
[0061] like Figure 2 As shown, in the direction perpendicular to the horizontal plane, multiple power elements 11 in adjacent rows of adjacent stacked layers are staggered, and multiple power elements 11 in adjacent columns of adjacent stacked layers are staggered.
[0062] It should be noted that the embodiments of this application are applicable to composite power devices manufactured using silicon-based semiconductors and various compound semiconductors. These compounds include GaN and SiC.
[0063] As an example and not a limitation, multiple power elements in an odd-numbered stack layer are referred to as first power elements; multiple power elements in an even-numbered stack layer are referred to as second power elements.
[0064] It is worth emphasizing that the gates of the power elements in the n stacked layers are connected, the drains of the power elements in the n stacked layers are connected, and the sources of the power elements in the n stacked layers are connected.
[0065] Corresponding to one embodiment of a composite power device, the present invention also provides an embodiment of a method for manufacturing a composite power device.
[0066] A method for manufacturing a composite power device, the method comprising steps 401 to 408.
[0067] In step 401, as Figure 3 As shown, a substrate 10 is provided or an epitaxial layer 21 is grown.
[0068] It should be noted that when step 401 is performed for the first time, step 401 specifically involves providing a substrate 10. When step 401 is not performed for the first time, step 401 specifically involves growing an epitaxial layer 21 on the upper surface of the dielectric layer. The epitaxial layer 21 is used as a substrate for the stacked layers.
[0069] In step 402, as Figure 4 As shown, a plurality of power elements 11 are formed on the substrate 10 or the epitaxial layer 21, and the plurality of power elements 11 are spaced apart in both the lateral and longitudinal directions.
[0070] As an example and not a limitation, when forming an odd-numbered stacked layer, step 402 specifically involves forming a plurality of first power elements 11 on the substrate 10 or epitaxial layer 21 using a first set of semiconductor processes, wherein the plurality of first power elements 11 are spaced apart in both the lateral and longitudinal directions; when forming an even-numbered stacked layer, step 402 specifically involves forming a plurality of second power elements 11 on the substrate 10 or epitaxial layer 21 using a second set of semiconductor processes, wherein the plurality of second power elements 11 are spaced apart in both the lateral and longitudinal directions.
[0071] The first group of semiconductor processes refers to the collection of processes for manufacturing multiple first power devices; the second group of semiconductor processes refers to the collection of processes for manufacturing multiple second power devices.
[0072] The first power element 11 and the second power element 11 can both be either VDMOS or IGBT.
[0073] It should be noted that when step 402 is performed for the first time, step 402 specifically involves forming a plurality of power elements 11 on the substrate 10, with the plurality of power elements 11 spaced apart in both the lateral and longitudinal directions. When step 402 is not performed for the first time, step 402 specifically involves forming a plurality of power elements 11 on the epitaxial layer 21, with the plurality of power elements 11 spaced apart in both the lateral and longitudinal directions.
[0074] In step 403, as Figure 5 As shown, an etch stop layer 12 and a metal contact layer 13 are sequentially grown at the source of multiple power elements 11 and at the gate of multiple power elements.
[0075] In specific implementation, step 403 includes step 403-1 and step 403-2.
[0076] In step 403-1, an etch stop layer 12 is deposited at the source and gate of the multiple power elements.
[0077] In step 403-2, a metal contact layer 13 is grown on the upper surface of the etching stop layer 12.
[0078] In step 404, as Figure 6 As shown, a first via 14 is formed to connect to the drain of a plurality of power elements 11, and a first metal layer 15 connected to the first via 14 is grown on the upper surface of the substrate 10 or the epitaxial layer 21.
[0079] It should be noted that when step 404 is executed for the first time, step 404 specifically involves forming a first via 14 connected to the drain of the plurality of power elements 11, and growing a first metal layer 15 connected to the first via 14 on the upper surface of the substrate 10. When step 404 is not executed for the first time, step 404 specifically involves forming a first via 14 connected to the drain of the plurality of power elements 11, and growing a first metal layer 15 connected to the first via 14 on the upper surface of the epitaxial layer 21.
[0080] In specific implementation, step 404 includes steps 404-1 and 404-2.
[0081] In step 404-1, a first through hole 14 connected to the drain of a plurality of power elements 11 is formed by etching, and the first through hole 14 is filled with metal; wherein, the first through hole 14 may be one or more.
[0082] In step 404-2, a first metal layer 15 connected to the first via 14 is grown on the upper surface of the substrate 10 or epitaxial layer 21 by vapor deposition or sputtering.
[0083] Because in the direction perpendicular to the horizontal plane, multiple power elements 11 in adjacent rows of adjacent stacked layers are staggered, and multiple power elements 11 in adjacent columns of adjacent stacked layers are staggered, it is necessary to grow a first metal layer 15 to connect the first via 14 and the second via 17 described below.
[0084] In step 405, as Figure 7 As shown, a dielectric layer 16 is grown on the surface of multiple power elements 11.
[0085] In step 406, as Figure 8 As shown, a second through-hole 17 connected to the first metal layer 15 is formed inside the dielectric layer 16;
[0086] Repeat steps 401 to 406 n times to form n stacked layers; n is a natural number greater than 1. Each execution of steps 401 to 406 forms one stacked layer.
[0087] It needs to be emphasized that, such as Figure 9 As shown, in adjacent stacked layers, the drain of each power element 11 in the upper stacked layer is connected to the second via 17 in the lower stacked layer.
[0088] Since the drains of each power element 11 in the upper stacked layer are connected to the second via 17 in the lower stacked layer, and the first metal layer 15 connects the first via 14 and the second via 17, and the first via 14 connects to the drains of each power element 11 in the lower stacked layer, the connection of the drains of each power element 11 in each stacked layer is realized.
[0089] In step 407, as Figure 10 As shown, a plurality of third vias 18 connected to the source of a plurality of power elements 11 are formed inside the epitaxial layer 21 and the dielectric layer 16; a plurality of fourth vias 19 connected to the gate of a plurality of power elements 11 are formed inside the epitaxial layer 21 and the dielectric layer 16.
[0090] In a specific implementation, step 407 specifically involves: forming a plurality of third vias 18 connected to the source of a plurality of power elements 11 by etching inside the epitaxial layer 21 and the dielectric layer 16; forming a plurality of fourth vias 19 connected to the gate of a plurality of power elements 11 by etching inside the epitaxial layer 21 and the dielectric layer 16; and filling the plurality of third vias 18 and the plurality of fourth vias 19 with metal.
[0091] In step 408, as Figure 11 As shown, a second metal layer 20 is formed on the upper surface of the nth stacked layer; wherein the second metal layer 20 connects to a plurality of third through holes 18 and a plurality of fourth through holes 19.
[0092] In specific implementation, step 408 includes steps 408-1 and 408-2.
[0093] In step 408-1, a third metal layer is formed on the upper surface of the nth stacked layer. The third metal layer can be formed on the upper surface of the nth stacked layer by vapor deposition or sputtering.
[0094] In step 408-2, a second metal layer 20 is formed on the third metal layer by imaging. Imaging can be performed using an etching process.
[0095] Since multiple third vias are connected to the sources of multiple power elements, and multiple fourth vias are connected to the gates of multiple power elements, and the second metal layer connects multiple third vias and multiple fourth vias, the parallel connection of the gates of multiple power elements and the parallel connection of the sources of multiple power elements are realized.
[0096] It should be noted that the structure of power element 11 is as follows: Figure 12 As shown, it includes a gate 101, a source 102, and a drain 103.
[0097] It is worth noting that the dielectric layer 16 and the etch stop layer 12 can be silicon oxide or silicon nitride. The metal contact layer 13 can be cobalt silicide or titanium silicide.
[0098] This invention comprises n stacked layers arranged parallel to a horizontal plane; n is a natural number greater than 1; in each stacked layer, multiple power elements are spaced apart in both the horizontal and vertical directions; in the direction perpendicular to the horizontal plane, the power elements in adjacent rows of adjacent stacked layers are staggered, and the power elements in adjacent columns of adjacent stacked layers are staggered; therefore, through the staggered three-dimensional parallel structure, more parallel power elements can be manufactured within a unit area to achieve a larger current drive within a unit area, thereby improving the efficiency of the composite power device.
[0099] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0100] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for manufacturing a composite power device, characterized in that, The manufacturing method includes: Step A: Provide a substrate or grow an epitaxial layer; Step B: A plurality of power elements are formed on the substrate or the epitaxial layer, and the plurality of power elements are spaced apart in both the lateral and longitudinal directions; Step C: An etch stop layer and a metal contact layer are sequentially grown at the source and gate of the plurality of power elements; Step D: Form a first via that is connected to the drain of the plurality of power elements, and grow a first metal layer connected to the first via on the substrate or the upper surface of the epitaxial layer; Step E: Grow a dielectric layer on the surface of the plurality of power elements; Step F: Form a second via that connects to the first metal layer inside the dielectric layer; Repeat steps A through F n times to form n stacked layers; where n is a natural number greater than 1. Step G: Form a plurality of third vias connected to the sources of the plurality of power elements inside the epitaxial layer and the dielectric layer; form a plurality of fourth vias connected to the gates of the plurality of power elements inside the epitaxial layer and the dielectric layer; Step H: A second metal layer is formed on the upper surface of the nth stacked layer; wherein the second metal layer connects to a plurality of the third vias and a plurality of the fourth vias.
2. The method for manufacturing the composite power device according to claim 1, characterized in that, When an odd number of stacked layers are formed, step B specifically involves: forming a plurality of first power elements on the substrate or the epitaxial layer using a first set of semiconductor processes, wherein the plurality of first power elements are spaced apart in both the lateral and longitudinal directions; When an even number of stacked layers are formed, step B specifically involves forming a plurality of second power elements on the substrate or the epitaxial layer using a second set of semiconductor processes. The plurality of second power elements are spaced apart in both the lateral and longitudinal directions.
3. The method for manufacturing the composite power device according to claim 1, characterized in that, Step C includes: The etch stop layer is deposited at the source and gate of the plurality of power elements; The metal contact layer is grown on the upper surface of the etching stop layer.
4. The method for manufacturing the composite power device according to claim 1, characterized in that, Step D includes: A first via is formed by etching to connect to the drain of the plurality of power elements, and the first via is filled with metal; The first metal layer connected to the first via is grown on the surface of the substrate or the epitaxial layer by vapor deposition or sputtering.
5. The method for manufacturing the composite power device according to claim 1, characterized in that, Step H includes: A third metal layer is formed on the upper surface of the nth stacked layer; The second metal layer is formed on the third metal layer by imaging; The second metal layer connects to a plurality of the third through holes and to a plurality of the fourth through holes.
6. The method for manufacturing the composite power device according to claim 4, characterized in that, In adjacent stacked layers, the drain of each power element in the upper stacked layer is connected to the second via in the lower stacked layer.
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