3D memory device, metrology method thereof, and thin film metrology apparatus

Abstract

The application discloses a 3D memory device and a measuring method and a thin film measuring device thereof. The 3D memory device according to the embodiment of the application comprises a substrate, a laminated structure located above the substrate and used for forming a storage array, a channel hole arranged on the laminated structure, and a barrier layer arranged in the channel hole and used for blocking signals in a first wavelength range. The 3D memory device and the measuring method and the thin film measuring device thereof according to the embodiment of the application can accurately measure the thickness of the thin film of the 3D memory device.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese patent application filed on February 3, 2021, with application number 202110147527.7 and entitled "3D storage device and measurement method thereof, thin film measurement device". Technical Field

[0003] This invention relates to the field of semiconductor device technology, and in particular to a 3D memory device and its measurement method and thin film measurement device. Background Technology

[0004] As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases dramatically. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0005] To increase the bit density of 3D NAND flash memory devices, the number of stacked layers is increasing (e.g., dual decks), leading to a corresponding doubling of film thickness. Simultaneously, channel holes are being etched twice instead of once. Film thickness significantly impacts the device's structure and electrical performance, necessitating rigorous online monitoring during production. However, the increasing thickness of films presents significant challenges to current film thickness measurement methods. Existing technologies not only allow changes or fluctuations in the upstream process to interfere with subsequent film measurements, but also make it impossible to distinguish between changes originating from the upstream process and those occurring in the current process, potentially causing unreasonable deviations between calculated and actual process results.

[0006] Therefore, it is hoped that a new 3D storage device and its measurement method, as well as a thin film measurement device, can overcome the above problems. Summary of the Invention

[0007] In view of the above problems, the purpose of the present invention is to provide a 3D memory device and a method for measuring it, as well as a thin film measuring device, so as to accurately measure the thin film thickness of the 3D memory device.

[0008] According to one aspect of the present invention, a 3D memory device is provided, comprising a substrate; a stacked structure located above the substrate for forming a memory array; a channel via disposed on the stacked structure; and a blocking layer disposed in the channel via for blocking signals in a first wavelength range.

[0009] Preferably, the barrier layer extends through at least a portion of the stacked structure.

[0010] Preferably, the stacked structure includes:

[0011] A first stacked structure is located above the substrate and is used to form a memory array;

[0012] The second stacked structure is located above the first stacked structure and is used to form a storage array;

[0013] The channel orifice includes:

[0014] The first channel hole is disposed in the first stacked structure.

[0015] The barrier layer is disposed in the first channel hole.

[0016] Preferably, the barrier layer is a sacrificial layer retained from a previous process.

[0017] According to another aspect of the present invention, a method for measuring a 3D memory device is provided, comprising forming a substrate; forming a stacked structure over the substrate; forming a channel hole in the stacked structure; forming a blocking layer in the channel hole, the blocking layer being used to block signals in a first wavelength range; transmitting signals in the first wavelength range to the stacked structure; and obtaining the thickness of the stacked structure through which signals in the first wavelength range pass, based on signals in the first wavelength range that are not blocked by the blocking layer.

[0018] Preferably, forming a stacked structure over the substrate; forming a channel via in the stacked structure includes: forming a first stacked structure over the substrate; forming a first channel via in the first stacked structure; forming the barrier layer in the first channel via; and forming a second stacked structure on the first stacked structure; obtaining the thickness of the stacked structure of the signal passing through the first wavelength range based on the signal not blocked by the barrier layer includes: obtaining the thickness of the second stacked structure based on the signal in the first wavelength range not blocked by the barrier layer.

[0019] Preferably, forming the barrier layer in the first channel hole includes:

[0020] A sacrificial layer is filled into the first channel hole.

[0021] At least a portion of the sacrificial layer is used to form a barrier layer.

[0022] Preferably, the measurement method includes:

[0023] A first stacked structure is formed on the substrate;

[0024] Open the first channel mask and etch a first channel hole on the first stacked structure;

[0025] A second stacked structure is formed by stacking on the first stacked structure and the first channel hole;

[0026] Open the second channel mask, close the first channel mask, and etch a second channel hole onto the second stacked structure; and

[0027] Open the first channel mask, close the second channel mask, and clean the fabricated device.

[0028] Preferably, forming the stacked structure over the substrate includes alternately depositing a plurality of sacrificial layers and a plurality of interlayer insulating layers on the substrate to form the stacked structure.

[0029] Preferably, forming a stacked structure over the substrate includes: forming a first stacked structure over the substrate; and in the stacked structure over the first stacked structure, forming a subsequent stacked structure over the preceding stacked structure.

[0030] The measurement method further includes: measuring the thickness of the previous layer after forming the previous layer; and measuring the thickness of the next layer after forming the next layer.

[0031] Preferably, the angle of signal incidence within the first wavelength range is calculated based on the interval between adjacent blocking layers.

[0032] Preferably, the incident position of the signal within the first wavelength range includes the location of the channel aperture.

[0033] According to another aspect of the present invention, a thin film measurement apparatus is provided for measuring the thickness of a 3D memory device as described above. The thin film measurement apparatus includes an optical critical dimension measurement device for measuring the film layer to be measured in the 3D memory device to obtain a measurement spectrum; and a processor for obtaining the thickness of the film layer to be measured based on the measurement spectrum.

[0034] According to the 3D memory device and its measurement method and thin film measurement device of the present invention, by providing a blocking layer in the stacked structure of the memory device that can block signals within a specific range, the influence of other film layers can be avoided during thin film measurement, thereby accurately obtaining the thickness of the film (film layer) to be measured.

[0035] According to the embodiments of the present invention, the 3D memory device and its measurement method and thin film measurement device achieve isolation of the lower channel structure at the signal level without changing the current process flow or imposing additional burden on other modules, except for controlling the channel mask of the measurement area.

[0036] The 3D memory device and its measurement method and thin film measurement apparatus according to embodiments of the present invention can avoid the impact of changes in the upstream process (before the lower channel loop) on subsequent measurements in thin film thickness measurement.

[0037] According to the 3D memory device and its measurement method and thin film measurement device of the present invention, since there is a lower channel hole (LCH) structure on the measurement pad, for some process nodes with a relatively serious loading effect, the actual thin film thickness can be reflected by the measurement pad, avoiding the problems caused by the complex modeling structure of the core array. Attached Figure Description

[0038] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0039] Figure 1 The structure of 3D memory devices and the principle of thin film thickness measurement according to the prior art are illustrated.

[0040] Figure 2 A schematic diagram of the structure of a 3D storage device according to Embodiment 1 of the present invention is shown;

[0041] Figure 3 A flowchart of a measurement method for a 3D storage device according to Embodiment 1 of the present invention is shown;

[0042] Figure 4 A schematic diagram of the structure of a 3D storage device according to Embodiment 2 of the present invention is shown;

[0043] Figure 5 A flowchart of a measurement method for a 3D storage device according to Embodiment 2 of the present invention is shown;

[0044] Figures 6 to 8 A cross-sectional schematic diagram of each stage of the 3D storage device measurement method according to Embodiment 2 of the present invention is shown;

[0045] Figure 9 The principle of thin film thickness measurement for 3D memory devices according to Embodiment 2 of the present invention is illustrated;

[0046] Figure 10 A flowchart of a measurement method for a 3D storage device according to Embodiment 3 of the present invention is shown;

[0047] Figure 11A schematic diagram illustrating simulation results of a 3D storage device according to an embodiment of the present invention is shown. Detailed Implementation

[0048] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings.

[0049] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0050] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0051] To increase the bit density of 3D NAND memory devices, the number of stacked layers is increasing (e.g., dual decks), and the film thickness is correspondingly increasing exponentially. At the same time, the vias are being etched twice instead of once. Since film thickness has a significant impact on the device's structure and electrical performance, strict online monitoring is necessary during the manufacturing process.

[0052] The inventors discovered that increasingly thicker thin films pose significant challenges to current film thickness measurement methods. Changes or fluctuations in the upstream process can interfere with subsequent film measurements. Film measurement based on regression analysis algorithms cannot avoid the interrelationships between multiple variables and cannot distinguish between changes caused by upstream processes and those caused by the current process, potentially leading to unreasonable deviations between calculated results and actual process results. Furthermore, this problem becomes increasingly pronounced as film thickness increases, potentially reducing the reliability of measurement results. Additionally, due to the loading effect caused by pattern density, pad measurements may not accurately reflect the actual film thickness (e.g., core array film thickness). Figure 1 This illustrates the structure of 3D memory devices and the principle of thin-film thickness measurement according to existing technology. For example... Figure 1As shown, existing 3D memory devices have a stacked structure. When measuring thickness, a single measurement signal may be emitted, but multiple feedback signals may be received, resulting in inaccurate film thickness measurements.

[0053] The inventors also discovered that as the thickness of 3D NAND memory devices increases, the number of process steps increases accordingly, and thin film thickness monitoring becomes increasingly critical. Current regression analysis methods and equipment used for thin film thickness measurement face challenges such as model reliability when establishing measurement stations on the upper deck due to limitations in principles, algorithms, and hardware. Furthermore, they may face the risk of insufficient capability or even failure as device thickness continues to increase in the future. At dual-deck stations, for the pure film pad, the results of upstream processes, especially the completed lower deck, significantly affect the current measurement spectrum. Due to the similarity of materials, the upper deck and lower deck films are highly correlated from a modeling perspective, making it impossible to properly distinguish the source of information in the raw measurement data using modeling methods. Moreover, there is currently a lack of effective means to block the influence of upstream processes on the current station's measurement at the signal level. Pure film measurements may not accurately reflect the actual film thickness due to the loading effect caused by differences in pattern density.

[0054] Figure 2 A schematic diagram of the structure of a 3D storage device according to an embodiment of the present invention is shown. Figure 2 As shown, the 3D memory device according to an embodiment of the present invention includes a substrate 10, a stacked structure 20, a channel via 30, and a barrier layer 40.

[0055] Specifically, substrate 10 is, for example, a semiconductor substrate.

[0056] The stacked structure 20 is located above the substrate 10 and is used to form a memory array.

[0057] The channel hole 30 is provided on the laminated structure 20.

[0058] A blocking layer 40 is disposed in the channel aperture 30 to block signals within a first wavelength range. Optionally, the first wavelength range is a short wavelength range.

[0059] In an optional embodiment of the invention, the barrier layer 40 penetrates at least a portion of the laminated structure. Optionally, the barrier layer 40 is disposed on the sidewall of the channel hole 30.

[0060] Figure 3 A flowchart illustrating a measurement method for a 3D storage device according to Embodiment 1 of the present invention is shown. Figure 3 As shown, the measurement method for 3D storage devices according to Embodiment 1 of the present invention includes the following steps:

[0061] Step S301: Forming a substrate.

[0062] Forming a substrate, such as a semiconductor substrate, as a substrate for a 3D memory device.

[0063] Step S302: Form a stacked structure on the substrate.

[0064] A stacked structure is formed on top of a substrate to form a memory array. Optionally, multiple sacrificial layers and multiple interlayer insulating layers are alternately deposited on the substrate to form the stacked structure.

[0065] Step S303: Forming channel holes in the stacked structure.

[0066] Channels are formed in the laminated structure. For example, channels are formed in the laminated structure by etching.

[0067] Step S304: Form a barrier layer in the channel hole.

[0068] A blocking layer is formed in the channel aperture to block signals within a first wavelength range. For example, a blocking layer is formed on the sidewall of the channel aperture.

[0069] Step S305: Transmit a signal within the first wavelength range to the stacked structure;

[0070] A signal within the first wavelength range is emitted into the stacked structure.

[0071] Step S306: Based on the signal within the first wavelength range that is not blocked by the blocking layer, obtain the thickness of the stacked structure that transmits the signal within the first wavelength range.

[0072] The thickness of the stacked structure through which the signal in the first wavelength range is transmitted is obtained based on the signal within that range that is not blocked by the blocking layer. Specifically, the first wavelength range of the signal is transmitted to the stacked structure. Signals within the first wavelength range whose transmission path passes through the blocking layer are blocked; signals within the first wavelength range whose transmission path does not pass through the blocking layer are not blocked. The thickness of the stacked structure through which the signal in the first wavelength range is transmitted can be obtained based on the signal within that range that is not blocked by the blocking layer. Optionally, the thickness of the unblocked portion, i.e., the thickness of the stacked structure after removing the thickness of the blocking layer, is obtained based on the received reflected signal, after transmitting a signal within the first wavelength range to the stacked structure.

[0073] In an optional embodiment of the present invention, forming a stacked structure above a substrate includes forming a first stacked structure above the substrate; in the stacked structure above the first stacked structure, a subsequent stacked structure is formed above a previous stacked structure, that is, a second stacked structure, a third stacked structure, and so on are sequentially formed above the first stacked structure. After forming the previous stacked structure, the thickness of the previous stacked structure is measured; after forming the subsequent stacked structure, the thickness of the subsequent stacked structure is measured. Optionally, after forming the previous stacked structure and measuring its thickness, a barrier layer is formed in the previous stacked structure. After forming the barrier layer in the previous stacked structure, a subsequent stacked structure is formed on the previous stacked structure, and the thickness of the subsequent stacked structure is measured.

[0074] In an optional embodiment of the present invention, the angle of signal incidence within a first wavelength range is calculated based on the spacing between adjacent blocking layers. Optionally, the stacked structure includes a first stacked structure and a second stacked structure located above the first stacked structure. The first stacked structure has multiple blocking layers. The angle of signal incidence within the first range is calculated based on the spacing between adjacent blocking layers, ensuring that all signals within the first range incident into the first stacked structure are blocked, thereby accurately measuring the thickness of the second stacked structure.

[0075] In an optional embodiment of the invention, the incident position of the signal within the first wavelength range includes the location of the channel aperture (blocking layer). Optionally, the channel aperture (blocking layer) is located on the transmission path of the signal within the first wavelength range.

[0076] In an optional embodiment of the invention, the measurement method for the 3D memory device further includes filling a sacrificial layer into the channel via. At least a portion of the sacrificial layer is used to form a barrier layer.

[0077] In an optional embodiment of the present invention, the position, depth, diameter, etc. of the first channel hole can be determined according to actual needs to form a barrier layer at different locations. The barrier layer can block signals in the short (first) wavelength range, so that the thickness at the location of the barrier layer will not be measured, thereby achieving accurate measurement of the thickness of the film to be measured.

[0078] Figure 4 A schematic diagram of the structure of a 3D storage device according to Embodiment 2 of the present invention is shown. Figure 4 As shown, the 3D memory device according to Embodiment 2 of the present invention includes a substrate 10, a stacked structure 20, a channel via 30, and a barrier layer 40. The stacked structure 20 includes a first stacked structure 21 and a second stacked structure 22. The channel via 30 includes a first channel via 31.

[0079] Specifically, substrate 10 is, for example, a semiconductor substrate.

[0080] The first stacked structure 21 is located above the substrate 10 and is used to form a memory array.

[0081] The second stacked structure 22 is located above the first stacked structure 21 and is used to form a storage array.

[0082] The first channel hole 31 is disposed on the first stacked structure 21.

[0083] A barrier layer 40 is disposed in the first channel hole 31.

[0084] In an optional embodiment of the present invention, the channel hole 30 includes a first channel hole 31 and a second channel hole (not shown in the figure). The second channel hole is disposed in the second stacked structure. Optionally, the first channel hole 31 and the second channel hole are connected, that is, the first channel hole 31 and the second channel hole are in communication. Optionally, the axis of the first channel hole 31 coincides with the axis of the second channel hole.

[0085] In an optional embodiment of the present invention, the 3D storage device according to the present invention further includes a blocking layer located above the first stacked structure and below the second stacked structure. In this embodiment, the blocking layer is formed directly between the two stacked structures (the first stacked structure and the second stacked structure), which can block all signals incident on the first stacked structure (e.g., the bottom stacked layer).

[0086] In an optional embodiment of the present invention, the stacked structure is not limited to two layers; there can be multiple layers, i.e., above the second stacked structure, there can be a third, fourth, fifth, and so on. Optionally, after forming the first stacked structure, the thickness of the first stacked structure is measured; after forming the second stacked structure, the thickness of the second stacked structure is measured; and so on; if there are more stacked structures, this operation is repeated, and finally the thickness of all stacked structures is calculated. Optionally, a barrier layer is provided between two adjacent stacked structures. Optionally, after forming the first stacked structure, the thickness of the first stacked structure is measured, and then a barrier layer is formed on the first stacked structure; after forming the second stacked structure, the thickness of the second stacked structure is measured, and then a barrier layer is formed on the second stacked structure; and so on; if there are more stacked structures, the above operation is repeated.

[0087] In an optional embodiment of the present invention, the barrier layer is a sacrificial layer retained from the preceding process.

[0088] Figure 5 A flowchart of a measurement method for a 3D storage device according to Embodiment 2 of the present invention is shown. Figures 6 to 8 A cross-sectional schematic diagram of each stage of the 3D storage device measurement method according to Embodiment 2 of the present invention is shown. Figure 5 As shown, the measurement method for 3D storage devices according to Embodiment 2 of the present invention includes the following steps:

[0089] Step S501: Forming a substrate.

[0090] Forming a substrate, such as a semiconductor substrate, as a substrate for a 3D memory device.

[0091] Step S502: Form a first stacked structure on the substrate.

[0092] A first stacked structure is formed on top of a substrate, the first stacked structure being used to form a memory array. Optionally, multiple sacrificial layers and multiple interlayer insulating layers are alternately deposited on the substrate to form the first stacked structure. Optionally, a monitor pad is formed on top of the substrate as part of the first stacked structure. The monitor pad is, for example, located in a dicing channel of the wafer. The thin film and structure on the dicing channel may or may not be consistent with the core array. Optionally, by controlling the opening (development) or closing (non-development) of the mask, the thin film and structure on the dicing channel may or may not be consistent with the core array. Step S503: A first channel via is formed in the first stacked structure.

[0093] A first channel hole is formed in the first stacked structure. For example, the first channel hole is formed by etching in the first stacked structure. Optionally, the first stacked structure is etched to form a first channel hole that extends through the first stacked structure. Optionally, the first channel hole extends to the substrate and forms a silicon trench within the substrate.

[0094] like Figure 6 As shown, a first stacked structure 21 is formed on top of the substrate 10. A first channel hole 31 is provided in the first stacked structure 21. For example, at least one first channel hole is formed in the first stacked structure 21 by a first etching (e.g., lower channel etch). Optionally, the first stacked structure 21 also includes a data line (gate line). Figure 6 As shown, for example, multiple sacrificial layers and multiple interlayer insulating layers are alternately deposited on substrate 10 to form a first stacked structure 21.

[0095] Step S504: Form a barrier layer in the first channel hole.

[0096] A barrier layer is formed in the first channel hole. For example, a barrier layer is formed on the sidewall of the first channel hole.

[0097] like Figure 7 As shown, a barrier layer 40 is filled in the first channel hole 21.

[0098] In an alternative embodiment of the invention, a sacrificial layer is filled in the first channel hole 21. At least a portion of the sacrificial layer is used to form the barrier layer 40. Optionally, the sacrificial layer (SAC Poly-Si or Carbonfill in) filled in the first channel hole 21 serves as the barrier layer 40.

[0099] Step S505: Form a second stacked structure above the first stacked structure and the first channel hole.

[0100] A second stacked structure is formed on top of the first stacked structure and the first channel via, the second stacked structure being used to form a memory array. Optionally, multiple sacrificial layers and multiple interlayer insulating layers are alternately deposited on top of the first stacked structure and the first channel via to form the second stacked structure.

[0101] like Figure 8 As shown, a second layered structure 22 (Upper film dep) is formed above the first layered structure 21 and the first channel via 31. A barrier layer 40 is retained in the first layered structure 21 (SAC Poly-Si (Carbon) remains untouched on the monitor pad). Optionally, the monitor pad (first layered structure) is located, for example, in a wafer dicing. The film and structure on the dicing can be consistent with or inconsistent with the core array. Optionally, by controlling the opening (development) or closing (non-development) of the mask, the consistency or inconsistency of the film and structure on the dicing with the core array can be achieved.

[0102] Step S506: Transmit a signal within the first wavelength range to the stacked structure;

[0103] A signal within a first wavelength range is transmitted to the stacked structures (first stacked structure and second stacked structure).

[0104] Step S507: Obtain the thickness of the second stacked structure based on the signal within the first wavelength range that is not blocked by the blocking layer.

[0105] The thickness of the second stacked structure is obtained from the signal within the first wavelength range that is not blocked by the blocking layer (i.e., the signal reflected by the stacked structure from the signal within the first wavelength range emitted).

[0106] In an optional embodiment of the present invention, the measurement method for 3D storage devices further includes:

[0107] Step S508: Form a second channel hole in the second stacked structure.

[0108] A second channel hole is formed in the second stacked structure. For example, the second channel hole is formed by etching in the second stacked structure. Optionally, the second stacked structure is etched to form a second channel hole that penetrates the second stacked structure. Optionally, the second channel hole extends to the upper surface of the first stacked structure.

[0109] In an optional embodiment of the invention, a first stacked structure is formed on a substrate, and a first pillar is formed penetrating the first stacked structure. A second stacked structure is formed on the first stacked structure, and a second pillar is formed penetrating the second stacked structure. At least a portion of the first pillar and the second pillar is removed to form a first channel hole and a second channel hole. Optionally, the axis of the first channel hole coincides with the axis of the second channel hole.

[0110] In an optional embodiment of the present invention, a first stacked structure and a second stacked structure are sequentially formed on the substrate. A first channel hole is provided on the first stacked structure; a second channel hole is provided on the second stacked structure. The second channel hole is horizontally offset from the first channel hole. Optionally, the first channel hole and the second channel hole are not interconnected.

[0111] In an optional embodiment of the present invention, a barrier layer is provided in the (first) channel hole in the front-end process. No matter how the front-end process is changed, the barrier layer is always provided in the (first) channel hole, and the change in the front-end process will not affect the subsequent measurement.

[0112] Figure 9 The principle of thin film thickness measurement for a 3D memory device according to Embodiment 2 of the present invention is illustrated. Figure 9 As shown, the optical signal (with a specific wavelength range) of the measurement film (as indicated by the solid arrows in the figure) is provided from the outside to the film to be measured. Signals that would otherwise pass through a blocking layer are blocked and cannot be reflected back to the outside (as indicated by the blocked dashed lines in the figure). The portion of the film to be measured (e.g., the second stacked structure) does not have a blocking layer, and the signal can return normally (as indicated by the solid arrows in the figure), thus accurately determining the thickness of the film to be measured.

[0113] Figure 10 A flowchart illustrating a measurement method for a 3D storage device according to Embodiment 3 of the present invention is shown. Figure 10 As shown, the measurement method for 3D storage devices according to Embodiment 3 of the present invention includes the following steps:

[0114] Step S1001: Form a first stacked structure on the substrate; form a first channel via in the first stacked structure;

[0115] A first stacked structure is formed on the substrate. A first channel hole is formed through the first stacked structure.

[0116] Step S1002: Form a barrier layer in the first channel hole;

[0117] A barrier layer is formed in the first channel via. For example, a sacrificial layer of poly-Si and / or a sacrificial layer of carbon is filled in the first channel via. The sacrificial layer filled in the first channel via serves as a barrier layer.

[0118] Step S1003: Open the first channel mask, close the second channel mask, and perform cleaning.

[0119] Without modifying existing processes, by controlling the mask in the measurement (pad) area—that is, opening (developing) the first channel mask and closing (not developing) the second channel mask—the sacrificial layer (barrier layer) filled in the first channel is completely preserved in the subsequent (WET, wet) cleaning process. This ensures that the signal of the lower deck portion of the first stacked structure is blocked in the first wavelength range (e.g., 190-700 nm). Devices fabricated using this method can avoid the influence of changes in the first stacked structure on the measurement of subsequent stacked structures (e.g., the second stacked structure) during thin-film measurement.

[0120] In an optional embodiment of the present invention, combined with Figures 6 to 8 As shown, the measurement method for 3D memory devices includes: stacking and forming a first layered structure on a substrate; opening (developing) a first channel mask and etching a first channel hole in the first layered structure; stacking and forming a second layered structure on the first layered structure and the first channel hole; opening (developing) a second channel mask, closing (not developing) the first channel mask, and etching a second channel hole in the second layered structure; opening (developing) the first channel mask, closing (not developing) the second channel mask, and cleaning the fabricated portion (fabricated device).

[0121] In the above embodiments of the present invention, by simply controlling the switching of the lower channel hole and the upper channel hole mask in the measurement (pad) area, the sacrificial material filled in the lower channel in the measurement (pad) area is preserved in the subsequent cleaning process. Its strong light absorption characteristics in the short (first) band prevent the downward propagating signal from returning to the sensor. The formed barrier layer physically isolates the bottom structure from the interference of the measurement at the current station.

[0122] According to another aspect of the present invention, a thin film measurement apparatus is provided for thickness measurement of a 3D memory device as described above. The thin film measurement apparatus includes an optical critical dimension (OCD) measurement device for measuring the film layer to be measured in the 3D memory device to obtain a measurement spectrum; and a processor for obtaining the thickness of the film layer to be measured based on the measurement spectrum. Optionally, the processor is connected to the optical critical dimension measurement device to receive the measurement spectrum. The working principle of the two sides of this thin film measurement apparatus can be found in [reference needed]. Figure 9 .

[0123] In an optional embodiment of the invention, a plurality of channel holes are formed in the stacked structure, and a barrier layer is formed in at least two of the channel holes. The thin film measurement device calculates the angle of incidence of the measurement signal based on the interval between adjacent barrier layers. Optionally, the plurality of channel holes are arranged in an array. Optionally, the plurality of barrier layers are arranged in an array in the stacked structure.

[0124] In an optional embodiment of the invention, the location with the channel structure (hole) is selected as the incident location of the measurement signal. Optionally, multiple channel holes are arranged in an array, and a blocking layer is formed in each channel hole.

[0125] Figure 11 A schematic diagram illustrating simulation results of a 3D storage device according to an embodiment of the present invention is shown. Figure 11 As shown in the OCD simulation results, the CD change of the lower channel structure (LCH) filled with sacrificial layer (barrier layer) has a low SNR (signal to noise) for spectra below 700nm, which is close to the noise level. In other words, the LCH structure change filled with sacrificial layer has basically no impact on subsequent measurements. Figure 11 The curves in the figure represent, for example, the simulation results of Poly-Si FillLCH+TCD 70.dat, Poly-Si Fill LCH+TCD 72.dat, and Poly-Si Fill LCH+TCD 74.dat, respectively.

[0126] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0127] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A 3D storage device, characterized in that, include: A stacked structure, the stacked structure comprising: a first stacked structure and a second stacked structure located above the first stacked structure; A first channel hole is disposed in the first stacked structure and a blocking layer is disposed in the first channel hole; the blocking layer is used to block signals with wavelengths in a first range and to obtain the thickness of the second stacked structure.

2. The 3D storage device according to claim 1, characterized in that, Also includes: A substrate, the substrate including a device region and a dicing region located around the device region; The stacked structure is located above the substrate, wherein the stacked structure is located in the dicing region.

3. The 3D storage device according to claim 1, characterized in that, The blocking layer is used to block signals with wavelengths in the range of 190nm to 700nm.

4. The 3D storage device according to claim 1, characterized in that, Also includes: A second channel hole is disposed in the second stacked structure; wherein the second channel hole extends into the barrier layer in the first channel hole.

5. The 3D storage device according to claim 1, characterized in that, The barrier layer penetrates the first stacked structure.

6. The 3D storage device according to claim 1, characterized in that, The barrier layer is a sacrificial layer retained from the previous process.

7. The 3D storage device according to claim 6, characterized in that, The material of the sacrificial layer includes polycrystalline silicon and / or carbon.

8. A measurement method for a 3D storage device, characterized in that, include: Provide substrate; A first stacked structure is formed on the substrate; A first channel hole is formed in the first stacked structure; A barrier layer is formed in the first channel hole; A second stacked structure is formed on the first stacked structure; the first stacked structure and the second stacked structure constitute a stacked structure; A signal with a wavelength within a first range is transmitted to the stacked structure; The thickness of the second stacked structure is obtained based on the reflected signal detected within the first range.

9. The measurement method for 3D storage devices according to claim 8, characterized in that, The first range is from 190nm to 700nm.

10. The measurement method for 3D storage devices according to claim 8, characterized in that, The formation of a barrier layer in the first channel hole includes: A sacrificial layer is filled into the first channel hole. At least a portion of the sacrificial layer is used to form a barrier layer.

11. The measurement method for 3D storage devices according to claim 8, characterized in that, The measurement method includes: The first stacked structure is formed by stacking on the substrate; Open the first channel mask and etch the first channel hole on the first stacked structure; The second stacked structure is formed by stacking on the first stacked structure and the first channel hole; Open the second channel mask, close the first channel mask, and etch a second channel hole onto the second stacked structure; and Open the first channel mask, close the second channel mask, and clean the fabricated device.

12. The measurement method for 3D storage devices according to claim 8, characterized in that, The formation of the first stacked structure over the substrate includes: Multiple sacrificial layers and multiple interlayer insulating layers are alternately deposited on the substrate to form the first stacked structure.

13. The measurement method for 3D storage devices according to claim 8, characterized in that, The process of forming a second stacked structure on the first stacked structure includes: In the stacked structure above the first stacked structure, a subsequent stacked structure is formed above the previous stacked structure; The measurement method further includes: After the previous layer of the stacked structure is formed, the thickness of the previous layer of the stacked structure is measured; and After the latter layer of the stacked structure is formed, the thickness of the latter layer of the stacked structure is measured.

14. The measurement method for 3D storage devices according to claim 8, characterized in that, The angle at which the signal with wavelength within the first range is incident is calculated based on the interval between adjacent blocking layers.

15. The measurement method for 3D storage devices according to claim 8, characterized in that, The incident position of the signal with wavelength within the first range includes the location of the first channel aperture.

16. A method for manufacturing a 3D storage device, characterized in that, include: Provide substrate; A first stacked structure is formed on the substrate; A first channel hole is formed in the first stacked structure, and a barrier layer is formed in the first channel hole; A second stacked structure is formed on the first stacked structure; the blocking layer is used to block signals with wavelengths within a first range, and to obtain the thickness of the second stacked structure.

17. The method for manufacturing a 3D storage device as described in claim 16, characterized in that, After forming the second stacked structure on the first stacked structure, the manufacturing method further includes: A second channel hole is formed in the second stacked structure, the second channel hole extending into the barrier layer in the first channel hole.

18. The method for manufacturing a 3D storage device as described in claim 16, characterized in that, The substrate includes a device region and a dicing region located around the device region; The formation of the first stacked structure over the substrate includes: The first stacked structure is formed in the diced area of ​​the substrate.

19. The method for manufacturing a 3D storage device as described in claim 16, characterized in that, The barrier layer is made of polycrystalline silicon and / or carbon.

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