Three-dimensional memory and methods of making the same, memory systems

Abstract

The application provides a three-dimensional memory and a preparation method and a memory system thereof. The preparation method comprises: forming a first stack structure comprising alternating dielectric layers and gate sacrificial layers on a substrate; forming a top selection gate cut through at least one gate sacrificial layer, and forming a first sacrificial layer in the top selection gate cut; removing the first sacrificial layer, and removing the gate sacrificial layers to form a sacrificial gap, and forming a gate conductive layer in the sacrificial gap. The three-dimensional memory and the preparation method and the memory system thereof provided by the application have strong controllability, can reduce the influence on the gate conductive layer, avoid increasing the load of the gate conductive layer, and solve the problem that the gate sacrificial layer between adjacent top selection gate cuts cannot be replaced by the gate conductive layer in the process of forming the top selection gate cut first in the conventional preparation method.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory and its fabrication method and memory system. Background Technology

[0002] In three-dimensional memory (e.g., 3D NAND), as storage density requirements increase, designing more strings of memory cells within a single memory block has become mainstream. This necessitates increasing the number of corresponding top select gate (TSG) cut structures within the memory block to drive individual strings of memory cells.

[0003] In some practical applications, the conductive layer in the stacked structure is usually formed using a process known as "gate replacement". However, based on the need to increase the number of corresponding top select gate cut-out structures, some examples use top select gate cut-out structures formed after the process of forming the gate line gaps to achieve complete "gate replacement". However, this process method affects the process window for forming the top select gate cut-out structures. Summary of the Invention

[0004] This application provides a three-dimensional memory and its fabrication method that can at least partially solve the above-mentioned problems existing in related technologies.

[0005] This application provides a method for fabricating a three-dimensional memory, comprising: forming a first stacked structure on a substrate including alternating dielectric layers and gate sacrificial layers; forming a top select gate cut through at least one gate sacrificial layer and forming a first sacrificial layer within the top select gate cut; removing the first sacrificial layer; removing the gate sacrificial layer to form a sacrificial gap; and forming a gate conductive layer within the sacrificial gap.

[0006] In some embodiments, after the step of forming a first sacrificial layer within the top selected gate cutout, the fabrication method further includes: forming gate wire gaps through the first stacked structure.

[0007] In some implementations, the material of the first sacrificial layer has the same etch selectivity as the material of the gate sacrificial layer, and the step of removing the first sacrificial layer and the gate sacrificial layer to form a sacrificial gap includes: removing the first sacrificial layer and the gate sacrificial layer via the gate line gap.

[0008] In some embodiments, after the step of forming a portion of the gate conductive layer within the sacrificial gap, the fabrication method further includes forming a filling structure within the top selected gate notch and the gate line gap in the same process.

[0009] In some embodiments, the step of forming a filling structure within the top selected gate cutout and the gate line slot includes: sequentially forming a high dielectric constant layer, a second insulating layer, and a conductive layer within the top selected gate cutout and the gate line slot.

[0010] In some embodiments, the fabrication method further includes: forming a first insulating layer located on the substrate-away side of the first stacked structure and covering the first sacrificial layer; and removing a portion of the first insulating layer to form a trench exposing the first sacrificial layer.

[0011] In some implementations, the material of the first insulating layer has different etching selectivity than the material of the first sacrificial layer.

[0012] In some implementations, the material of the first insulating layer has the same etching selectivity as the material of the first stacked structure.

[0013] In some embodiments, at least two gate line slots extend along a first direction parallel to the substrate, and at least two top-select gate cutouts extending along the first direction are located between adjacent gate line slots.

[0014] In some embodiments, the preparation method further includes forming a plurality of channel structures arranged in a row, wherein the top selection gate cutout has an overlapping portion with an adjacent channel structure or the top selection gate cutout structure has an overlapping portion with a row of channel structures.

[0015] Another aspect of this application provides a three-dimensional memory, comprising: a semiconductor layer; a second stacked structure including alternating dielectric layers and gate conductive layers; a top select gate cutout structure passing through at least one gate conductive layer; and a gate line slot structure passing through the second stacked structure, wherein the top select gate cutout structure and the gate line slot structure have the same configuration.

[0016] In some embodiments, the three-dimensional memory further includes: a first insulating layer located on the side of the second stacked structure away from the semiconductor layer; and a trench structure penetrating the first insulating layer and contacting the top select gate cutout structure.

[0017] In some implementations, the critical dimensions of the trench structure gradually decrease along the direction toward the top selected grid cutout structure.

[0018] In some embodiments, the top selected gate cutout structure and gate wire slot structure include, from the outside in, a high dielectric constant layer, a second insulating layer, and a conductive layer.

[0019] In some embodiments, at least two gate line slot structures extend along a first direction parallel to the substrate, and at least two top-select gate cutout structures extending along the first direction are located between adjacent gate line slot structures.

[0020] In some embodiments, the three-dimensional memory further includes a plurality of channel structures arranged in a row, wherein a top select gate cutout structure overlaps with an adjacent channel structure or the top select gate cutout structure overlaps with a row of the channel structures.

[0021] This application also provides a memory system comprising: at least one three-dimensional memory as described in any of the embodiments above; and a controller electrically connected to the at least one three-dimensional memory.

[0022] According to the three-dimensional memory and its fabrication method and memory system provided in the embodiments of this application, the top select gate notch is formed before the "gate replacement" process. This allows the formation process of the top select gate notch to employ conventional etching processes for dielectric layers and gate sacrificial layers, such as NO stacked structures, which offers strong process controllability. Furthermore, forming the top select gate notch before the "gate replacement" process reduces the impact on the gate conductive layer and avoids increasing the load (stress) on the gate conductive layer. Additionally, it solves the problem in conventional fabrication methods where the gate sacrificial layer between adjacent top select gate notches cannot be replaced with the gate conductive layer during the top select gate notch formation process. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0024] Figure 1A This is a top-view schematic diagram of the fabrication process for three-dimensional memory in related technologies;

[0025] Figure 1B It is based on Figure 1A A schematic cross-sectional view of the three-dimensional memory is shown.

[0026] Figure 2 This is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0027] Figures 3A to 3E It is based on Figure 2 A schematic cross-sectional view of the preparation method is shown.

[0028] Figure 4 This is a flowchart of a method for fabricating a three-dimensional memory according to another embodiment of this application;

[0029] Figures 5A to 5E It is based on Figure 4 A schematic cross-sectional view of the preparation method is shown.

[0030] Figure 6 This is a flowchart of a method for fabricating a three-dimensional memory according to another embodiment of this application;

[0031] Figures 7A to 7D It is based on Figure 6 A schematic cross-sectional view of the preparation method is shown.

[0032] Figure 8 This is a top view schematic diagram of the process for forming a trench according to an embodiment of this application;

[0033] Figure 9A and 9B This is a top view schematic diagram of the process for forming the channel structure according to different embodiments of this application;

[0034] Figure 10 This is a cross-sectional schematic diagram of a three-dimensional memory according to an embodiment of this application;

[0035] Figure 11 This is a cross-sectional schematic diagram of a three-dimensional memory according to another embodiment of this application; and

[0036] Figure 12A and 12B This is a schematic diagram of a memory system according to an embodiment of this application. Detailed Implementation

[0037] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and the first channel structure may also be referred to as the second structure, and vice versa.

[0039] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0040] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0041] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0044] As used herein, when a substrate or semiconductor layer is located in the lowest plane of a three-dimensional memory, whether a component (e.g., a layer or device) of the three-dimensional memory is "above," "on top of," or "below" another component (e.g., a layer or device) is in the vertical direction, i.e., perpendicularly opposite to the extension of the substrate or semiconductor layer of the three-dimensional memory. The same concepts are applied throughout this application to describe spatial relationships.

[0045] A three-dimensional memory can be a memory chip (package), a memory die, or any part of a memory die, and may include one or more memory planes, each memory plane may include multiple memory blocks. The same and concurrent operations can occur on each memory plane. A memory block may include multiple memory cells, where each memory cell can be addressed via interconnects such as bit lines and word lines. The orientation of the bit lines and word lines is... Figure 1AThe bits are labeled "BL" and "WL" respectively. Bit lines and word lines can be arranged vertically or substantially vertically (e.g., in rows and columns respectively). Therefore, the memory block is also called a "memory array" or "array". The memory array is the core area in the memory used to perform storage functions.

[0046] Figure 1A This is a top-view schematic diagram of the process for fabricating three-dimensional memory in related technologies.

[0047] like Figure 1A As shown, multiple gate line slots 141 and 142 extending along the word line direction are formed in the memory array, and filling structures are formed in the gate line slots 141 and 142 to form a gate line slot structure. Each memory block may include a multi-row channel structure 130 arranged, for example, in an interleaved manner between two adjacent gate line slot structures (see...). Figure 1B ).

[0048] As storage density requirements increase, i.e., the number of channel structures 130 increases, in related technologies, at least two top select gate cutouts 151 and 152 are formed in each storage block, and filling structures are formed in the top select gate cutouts 151 and 152 to form top select gate cutout structures 151' and 152'. The storage cells divided by the top select gate cutout structures 151' and 152' and sharing the same word line form programmable (or readable) memory pages.

[0049] Figure 1B It is based on Figure 1A A schematic cross-sectional view of the three-dimensional memory is shown. Figure 1B As shown, the three-dimensional memory 100 includes a substrate 110 and a stacked structure 120 formed on the substrate 110. The stacked structure 120 may be composed of alternating stacks of insulating layers 121 and gate conductive layers 122 different from the insulating layers 121. Multiple insulating layers 121 and multiple gate conductive layers 122 extend in a lateral direction parallel to the surface of the substrate 110. Exemplarily, the insulating layer 121 may include, but is not limited to, silicon oxide. The gate conductive layers 122 may include, but are not limited to, conductive materials such as tungsten, cobalt, copper, aluminum, or doped polysilicon.

[0050] For example, the gate conductive layer 122 can be formed as follows: An initial stacked structure (not shown) is formed on the substrate 110, which may consist of an insulating layer 121 and a gate sacrificial layer (which is subsequently replaced by a gate conductive layer) stacked alternately. The initial stacked structure may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0051] The gate sacrificial layer is removed via gate gaps 141 and 142, thereby forming a sacrificial gap in the initial stacked structure. The method for removing the gate sacrificial layer can be, for example, wet etching. In a subsequent step, conductive material is filled into the sacrificial gap to form the gate conductive layer 122 of the three-dimensional memory 100.

[0052] However, as Figure 1B As shown, when at least two top selective gate cutout structures 151' and 152' are formed between the two gate line gaps 141 and 142, during the removal of the gate sacrificial layer to form a sacrificial gap, due to the different etching selectivity between different materials, the top selective gate cutout structures 151' and 152' have a blocking effect on the etching material used to etch the gate sacrificial layer, so that the etching material cannot reach the gate sacrificial layer 123 and 124 located between the two top selective gate cutout structures 151' and 152', thereby preventing the gate sacrificial layer 123 and 124 between the two top selective gate cutout structures 151' and 152' from being replaced by the gate conductive layer.

[0053] For the reasons mentioned above, in related technologies, to achieve complete gate conductive layer replacement, the top select gate notch is formed after the entire gate sacrificial layer has been replaced with the gate conductive layer. This significantly impacts the process window for the top select gate notch. Furthermore, since the top select gate notch needs to penetrate at least one gate sacrificial layer, etching the top select gate notch after complete gate layer replacement requires etching a stacked structure of insulating and gate conductive layers. This differs from the conventional process of etching stacked insulating and gate sacrificial layers, increasing the difficulty of forming the top select gate notch. Additionally, replacing the gate sacrificial layer with the gate conductive layer before forming the top select gate notch increases the load (stress) on the already formed gate conductive layer, potentially damaging it.

[0054] Figure 2 This is an exemplary flowchart of a method 2000 for fabricating a three-dimensional memory according to an embodiment of this application. Figure 2 As shown, the preparation method 2000 of this embodiment includes the following steps:

[0055] S210, a first stacked structure comprising alternating dielectric layers and gate sacrificial layers is formed on a substrate;

[0056] S220, a top select gate cutout is formed through at least one gate sacrificial layer, and a first sacrificial layer is formed within the top select gate cutout;

[0057] S230, the first sacrificial layer is removed, and the gate sacrificial layer is removed to form a sacrificial gap, and a gate conductive layer is formed within the sacrificial gap.

[0058] It should be understood that the steps shown in preparation method 2000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 2 The execution is performed in the order shown.

[0059] Figures 3A to 3E This is a schematic cross-sectional view of the fabrication method 2000 of the three-dimensional memory 200 according to an embodiment of this application. The following is in conjunction with... Figures 3A to 3E , Figure 8 as well as Figure 9A Steps S210 to S230 described above are further described in 9B.

[0060] S210, a first stacked structure comprising alternating dielectric layers and gate sacrificial layers is formed on the substrate. .

[0061] In step S210, substrate 210 (reference) Figure 3A It can be a semiconductor substrate, such as a silicon substrate (Si), a germanium substrate (Ge), a silicon germanide substrate (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI), etc. Figure 3A The substrate 210 shown may have undergone some necessary processing, such as the formation of a common active region or necessary cleaning. It should be noted that the substrate 210 can be removed in subsequent processes, and a semiconductor layer can be formed at approximately the spatial location of the substrate 210.

[0062] In this step, in some embodiments, a first stacked structure 220 may be formed on the substrate 210 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The first stacked structure 220 includes alternately stacked dielectric layers 221 and gate sacrificial layers 222. The dielectric layer 221 may, for example, comprise silicon oxide, and the gate sacrificial layer 222 may, for example, comprise silicon nitride. In other words, in the first stacked structure 220, multiple silicon oxide layers and multiple silicon nitride layers are alternately stacked in a direction perpendicular to the substrate 210.

[0063] In some embodiments, the various dielectric layers 221 may have the same thickness or different thicknesses. For example, the thickness of each dielectric layer 221 may be in the range of 10 nm to 100 nm, optionally about 25 nm. Similarly, the gate sacrificial layers 222 may have the same thickness or different thicknesses. For example, the thickness of each gate sacrificial layer 222 may be in the range of 10 nm to 100 nm, optionally about 35 nm.

[0064] It should be noted that, in this application, the dielectric layer 221 may also include any suitable oxide material, and the gate sacrificial layer 222 may also include any suitable nitride material.

[0065] In some implementations, such as Figure 3A As shown, the channel structure 230 extends into the substrate 210 in a direction toward the substrate 210, for example, perpendicular to the substrate 210. Exemplarily, the channel structure 230 may have a general outline shape such as a cylinder, frustum, or prism. The channel structure 230 may include, for example, an outer wall structure of a functional layer 232 and a channel layer 231 arranged sequentially from the outside in. Optionally, the functional layer 232 may include, for example, a charge blocking layer 2321, a charge trapping layer 2322, and a tunneling layer 2323 arranged sequentially from the outside in. The materials of the charge blocking layer 2321, the charge trapping layer 2322, and the tunneling layer 2323 may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide, thereby forming a functional layer 232 with an ONO structure. The material of the channel layer 231 may include, for example, a semiconductor material such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon). For example, multiple channel structures 230 may be arranged in rows (e.g., staggered rows) on a plane parallel to the substrate 210.

[0066] In some embodiments, the channel structure 230 may be formed using photolithography and etching processes (e.g., dry or wet etching processes) and thin film deposition processes. Exemplarily, a channel hole extending through the first stacked structure 220 and into the substrate 210 may first be formed using photolithography and etching processes. Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to sequentially form a functional layer 232, including a charge blocking layer 2321, a charge trapping layer 2322, and a tunneling layer 2323, and a channel layer 231 on the inner wall of the channel hole. Optionally, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the channel hole where the functional layer 232 and the channel layer 231 are formed with a dielectric material such as silicon oxide.

[0067] In some embodiments, after the channel structure 230 is formed, a first dielectric layer 280 may be formed on the side of the first stack structure 220 and the channel structure 230 away from the substrate 210 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the first dielectric layer 280 may comprise any suitable oxide material, such as silicon oxide.

[0068] S220, forming a top select gate cutout through at least one gate sacrificial layer, and within the top select gate cutout... Forming the first sacrificial layer .

[0069] In step S220, a top select gate notch 241, penetrating at least one gate sacrificial layer 222, may be formed in a predetermined region of the first stacked structure 220 using photolithography and etching processes (e.g., wet or dry etching). For example, the top select gate notch 241 penetrates the first dielectric layer 280 and passes through at least one gate sacrificial layer 222, as shown in Figure S220. Figure 3A The top gate cutout 241 can be in a direction parallel or substantially parallel to the substrate 210 (e.g., perpendicular or substantially perpendicular to). Figure 3A The direction of the top select gate notch 241 cross-section shown extends to separate the gate sacrificial layers 222 located on both sides of the top select gate notch 241, thereby allowing the gate conductive layers 222' located on both sides of the top select gate notch 241 to be formed in subsequent processes (see...). Figure 3E Electrical isolation.

[0070] In this step, a first sacrificial layer 242 may be formed within the top selected gate notch 241 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, as shown below. Figure 3B As shown. Optionally, during the process of forming the first sacrificial layer 242, the first sacrificial layer 242 may cover the surface of the first dielectric layer 280. Optionally, a process such as mechanical chemical polishing (CMP) may be used to remove the portion of the first sacrificial layer 242 located on the surface of the first dielectric layer 280, thereby exposing the first dielectric layer 280 again, such as... Figure 3C As shown. In other words, a portion of the first sacrificial layer 242 can be removed, leaving the first sacrificial layer 242 within the top select gate notch 241. It should be noted that, during the process of forming the first sacrificial layer 242, the first sacrificial layer 242 can be formed only within the top select gate notch 241 and not on the surface of the first dielectric layer 280, for example, by controlling the thin film deposition process. This application does not specifically limit this.

[0071] It should be noted that the first sacrificial layer 242 formed by the above process can, for example, be used to maintain the flatness and / or balance the stress of the intermediate structure during the preparation process.

[0072] In some embodiments, as described above, multiple channel structures (e.g., 230) are formed in the first stacked structure 220. Optionally, these channel structures are arranged in rows (alternating). Optionally, the top selection gate cutout 241 overlaps with the channel structures 230 in the two adjacent rows of channel structures (see reference). Figure 9A Alternatively, the top selection gate cutout structure 241 and the row channel structure 230' may have an overlapping portion (see reference). Figure 9BFor example, when the top selection gate cutout structure 241 overlaps with a row channel structure 230', this row channel structure 230' can be referred to as a dummy channel structure, which does not have storage functionality.

[0073] S230, remove the first sacrificial layer and remove the gate sacrificial layer to form a sacrificial gap, and form within the sacrificial gap... Gate conductive layer .

[0074] In this step, different processes can be used to remove the first sacrificial layer 242 depending on the material of the first sacrificial layer 242, thereby exposing the top selection gate cutout 241.

[0075] In some implementations of this step, such as Figure 3D As shown, a gate line slot 251 can be formed in the first stacked structure 220 using photolithography and etching processes (e.g., dry or wet etching processes), and a sacrificial gap (not shown) can be formed by removing the gate sacrificial layer 222 via the gate line slot 251 and / or the top selected gate notch 241. Exemplarily, the gate line slot 251 penetrates the first dielectric layer 280 and the first stacked structure 220, and at least exposes the substrate 210, as shown in the figure. Figure 3D .

[0076] In some embodiments, the material of the first sacrificial layer 242 may have the same etch selectivity as the material of the gate sacrificial layer 222. For example, the first sacrificial layer 242 and the gate sacrificial layer 222 may be made of the same material. When the first sacrificial layer 242 is made of the same material as the gate sacrificial layer 222, such as silicon nitride, a wet etching process and / or a dry etching process may be used to remove the first sacrificial layer 242 and the gate sacrificial layer 222, for example, through the gate line gap 251, thereby forming a sacrificial gap in the space where the gate sacrificial layer 222 has been removed, exposing the top select gate notch 241 after the first sacrificial layer 242 has been removed. In other words, the first sacrificial layer 242 and the gate sacrificial layer 222 may be removed in the same process.

[0077] For example, such as Figure 8 As shown, in the first stacked structure 220 (refer to...) Figure 3DIn the case where at least two gate line gaps 251 and 255 are formed in the gate line gaps, and at least two top select gate cutouts 241 and 245 and multiple channel structures (e.g., 230) are formed between two adjacent gate line gaps 251 and 255, the etching material can remove the gate sacrificial layer 222 exposed in the gate line gaps 251 and 255 to form a sacrificial gap, and then remove the first sacrificial layer 242 in the top select gate cutouts 241 and 245 through the sacrificial gap to expose the top select gate cutouts 241 and 245. Thus, the gate sacrificial layer 222 located between the two top select gate cutouts 241 and 245 can also be removed in this step to form a complete sacrificial gap, providing conditions for the subsequent formation of a complete gate conductive layer.

[0078] In another embodiment, the material of the first sacrificial layer 242 may have a different etch selectivity than the material of the gate sacrificial layer 222. For example, the first sacrificial layer 242 may be made of amorphous carbon. When the first sacrificial layer 242 is made of amorphous carbon and the gate sacrificial layer 222 is made of silicon nitride, the first sacrificial layer 242 may first be removed using a process such as ashering, thereby exposing the top select gate notch 241 after the removal of the first sacrificial layer 242. Then the gate sacrificial layer 222 is removed via at least one of the gate line gap 251 and the top select gate notch 241, thereby forming a sacrificial gap in the space of the removed gate sacrificial layer 222.

[0079] For example, such as Figure 8 As shown, in the first stacked structure 220 (refer to...) Figure 3D In the case where at least two gate line gaps 251, 255 are formed in the gate line gaps, and at least two top select gate cutouts 241, 245 and multiple channel structures (e.g., 230) are formed between two adjacent gate line gaps 251, 255, an asher process can be used to first remove the first sacrificial layer 242 within the top select gate cutouts 241, 245 to reform the top select gate cutouts 241, 245. Then, an etching process is used to remove the gate sacrificial layer 222. Optionally, the etchant can remove the gate sacrificial layer 222 exposed in the gate line gaps 251 and 255 through the gate line gaps 251 and 255, and remove the gate sacrificial layer 222 located between the two top select gate cutouts 241 and 245 through the top select gate cutouts 241 and 245 to form a complete sacrificial gap. Alternatively, the etchant can remove all of the gate sacrificial layer 222 through one of the gate line gaps 251 and 255 and the top select gate cutouts 241 and 245, providing conditions for the subsequent formation of a complete gate conductive layer.

[0080] After the above process, such as Figure 3EAs shown, a thin-film deposition process can be used to form the gate conductive layer 222' within the sacrificial gap. Optionally, during the process of forming the gate conductive layer 222' within the sacrificial gap, the gate conductive layer 222' can be formed on the inner wall of the top selected gate notch 241 and the inner wall of the gate line slot 251. Optionally, a dry etching process or a wet etching process can be used to remove the portion of the gate conductive layer 222' located outside the sacrificial gap (not shown). After the "gate replacement" process, the second stacked structure 220' may include alternating stacked dielectric layers 221 and gate conductive layers 222'.

[0081] In the above-described scheme of this application, the top select gate notch 241 is formed before the "gate replacement" process, allowing the formation process of the top select gate notch 241 to employ conventional etching processes for the dielectric layer and gate sacrificial layer, such as NO stacked structures. This process technology offers strong controllability. Furthermore, forming the top select gate notch 241 before the "gate replacement" process also reduces the impact on the gate conductive layer, avoiding an increase in the load (stress) on the gate conductive layer.

[0082] Furthermore, the fabrication method of the three-dimensional memory provided in this application solves the problem in conventional fabrication methods where the gate sacrificial layer between adjacent top select gate cuts cannot be replaced with a gate conductive layer during the top select gate cut-out formation process.

[0083] Figure 4 This is an exemplary flowchart of a method 3000 for fabricating a three-dimensional memory according to another embodiment of this application. Figure 4 As shown, the preparation method 3000 of this embodiment includes the following steps:

[0084] S310, a first stacked structure including alternating dielectric layers and gate sacrificial layers is formed on a substrate;

[0085] S320, a top select gate cutout is formed through at least one gate sacrificial layer, and a first sacrificial layer is formed within the top select gate cutout;

[0086] S330, forming a first insulating layer located on a first side of the first stacked structure away from the substrate and covering the first sacrificial layer, forming a gate line slot penetrating the first insulating layer and the first stacked structure; and removing a portion of the first insulating layer to form a trench exposing the first sacrificial layer;

[0087] S340, remove the first sacrificial layer and remove the gate sacrificial layer to form a sacrificial gap;

[0088] S350, a gate conductive layer is formed within the sacrificial gap; and

[0089] S360, in the same process, forms a filling structure in the trench, the top selected grid cut, and the grid line gap.

[0090] Figures 5A to 5E This is a schematic cross-sectional view of the fabrication method of a three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 5A to 5E Steps S330 to S360 described above are further described. Steps S310 and S320 are the same as steps S210 and S220 described with reference to FIG3, respectively, and therefore will not be repeated here.

[0091] S330, forming a first insulating layer located on the first side of the first stacked structure away from the substrate and covering the first sacrificial layer. Layer, forming a gate wire gap that penetrates the first insulating layer and the first stacked structure; and removing a portion of the first insulating layer to form trenches that expose the first sacrificial layer .

[0092] In step S330, as Figure 5A As shown, a first insulating layer 370 can be formed on top of the first stacked structure 320 and the first sacrificial layer 342 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, a first dielectric layer 380 is formed on the surface of the first stacked structure 320, and the first insulating layer 370 can be formed on the surface of the first dielectric layer 380. Optionally, the material of the first insulating layer 370 may include, but is not limited to, silicon oxide.

[0093] In some implementations, such as Figure 5B As shown, a trench 361 can be formed in the first insulating layer 370 using photolithography and etching processes to expose the first sacrificial layer 342. The first sacrificial layer 342 may include silicon nitride or amorphous carbon. Optionally, the materials of the first insulating layer 370 and the first sacrificial layer 342 may have different etching selectivity. During the etching process, the etching material (e.g., etchant) cannot continue etching downwards because it touches the pre-filled first sacrificial layer 342, and the first sacrificial layer 342 has different etching selectivity than the first insulating layer 370. This forms the trench 361 in the first insulating layer 370 to expose the first sacrificial layer 342, which helps to control the uniformity of the etching process in forming the trench 361.

[0094] In some embodiments, the material of the first insulating layer 370 and the material of the first stacked structure 320 may have the same etch selectivity. Thus, the steps of forming the gate line gap 351 penetrating the first insulating layer 370, the first dielectric layer 380, and the first stacked structure 320, and forming the trench 361 exposing the first sacrificial layer 342, can be performed simultaneously using the same process, such as... Figure 5BAs shown. Exemplarily, the etching processes forming the gate slots 351 and the trenches 361 can be performed simultaneously through mask design. In one example, a pattern for the top-select gate notch 341 is simultaneously designed on the mask forming the gate slots 351. When the material of the first insulating layer 370 and the material of the first stacked structure 320 have the same etching selectivity, the first insulating layer 370, the first dielectric layer 380, and a portion of the first stacked structure 320 are etched away using the mask pattern and an anisotropic etching material in a direction generally perpendicular to the substrate 310, forming the gate slots 351 that at least expose the substrate 310. In the same process, a portion of the first insulating layer 370 is etched away to form the trenches 361 that expose the first sacrificial layer 342.

[0095] S340, remove the first sacrificial layer and remove the gate sacrificial layer to form a sacrificial gap. .

[0096] In some embodiments of this step, the material of the first sacrificial layer 342 has the same etch selectivity as the material of the gate sacrificial layer 322. Optionally, when the first sacrificial layer 342 is made of the same material as the gate sacrificial layer 322, such as silicon nitride, a wet etching or dry etching process can be used to remove the first sacrificial layer 342 and the gate sacrificial layer 322 through the gate line gap 351 to form a sacrificial gap (not shown), exposing the top select gate notch 341 after the first sacrificial layer 342 is removed.

[0097] In some embodiments, where at least two gate line gaps (e.g., 351) are formed in the first stacked structure 320, and at least two top select gate cutouts (e.g., 341) and a plurality of channel structures (e.g., 330) are formed between two adjacent gate line gaps (e.g., 351), the etching material can remove the gate sacrificial layer 322 exposed in the two gate line gaps (e.g., 351) to form a sacrificial gap, and then remove the first sacrificial layer 342 in the top select gate cutout (e.g., 341) through the sacrificial gap to expose the top select gate cutout (e.g., 341). Thus, the gate sacrificial layer 322 located between the two top select gate cutouts (e.g., 341) can also be removed in this step to form a complete sacrificial gap, providing conditions for the subsequent formation of a complete gate conductive layer.

[0098] In other embodiments of this step, the material of the first sacrificial layer 342 has different etch selectivity than the material of the gate sacrificial layer 322. Optionally, when the first sacrificial layer 342 is made of amorphous carbon (C) and the gate sacrificial layer 322 is made of silicon nitride, the first sacrificial layer 342 can be removed via trench 361 to expose the top select gate cutout 341 (see reference). Figure 5CThen, the gate sacrificial layer 322 is removed via the top selected gate cutout 341 and / or gate line slot 351 to form a sacrificial gap (not shown).

[0099] In some embodiments, where at least two gate line gaps (e.g., 351) are formed in the first stacked structure 320, and at least two top select gate cutouts (e.g., 341) and multiple channel structures (e.g., 330) are formed between two adjacent gate line gaps (e.g., 351), an asher process can be used to first remove the first sacrificial layer 342 within the top select gate cutout 341 to reform the top select gate cutout 341. Then, an etching process is used to remove the gate sacrificial layer 322. Optionally, the etchant can remove the gate sacrificial layer 322 exposed in the gate line gap 351 through two gate line gaps (e.g., 351) and remove the gate sacrificial layer 322 located between the two top select gate cutouts (e.g., 341) through a top select gate cutout (e.g., 341) to form a complete sacrificial gap. Alternatively, the etchant can remove all of the gate sacrificial layer 322 through one of the gate line gaps (e.g., 351) and the top select gate cutout (e.g., 341) to provide conditions for the subsequent formation of a complete gate conductive layer.

[0100] For example, in the above embodiments, the first sacrificial layer 342 is made of amorphous carbon material, which is easier to remove than silicon nitride and helps to reduce the risk of residual problems of the first sacrificial layer 342.

[0101] S350, forming a gate conductive layer within the sacrificial gap. .

[0102] In some implementations of this step, such as Figure 5D As shown, after the sacrificial gap is formed, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a gate conductive layer 322' within the sacrificial gap. Optionally, the material of the gate conductive layer 322' may include conductive materials such as tungsten, cobalt, copper, aluminum, doped polysilicon, silicide, or any combination thereof.

[0103] In some embodiments, during the process of forming the gate conductive layer 322' within the sacrificial gap, the inner walls of the top selective gate notch 341, the trench 361, and the gate line slot 351 may also be formed with the gate conductive layer 322'. In subsequent processes, the portion of the gate conductive layer 322' located outside the sacrificial gap is removed. For example, a back-etching process can be used to remove the portion of the gate conductive layer 322' located outside the sacrificial gap, thereby re-exposing the inner walls of the top selective gate notch 341, the trench 361, and the gate line slot 351. Optionally, removing the portion of the gate conductive layer 322' exposed to the gate line slot 351 forms a groove relative to the sidewall of the gate line slot 351 to ensure that no conductive material remains in adjacent gate conductive layers 322', thereby preventing short circuits and leakage between adjacent gate conductive layers 322'.

[0104] S360, in the same process, forms a filler within the trench, the top selected grid cut, and the grid line gaps. structure .

[0105] In some implementations of this step, such as Figure 5E As shown, after the above-described process, the same filling structure can be formed in the trench 361, the top selective gate notch 341, and the gate line slot 351 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. In other words, the formation of the filling structure in the trench 361, the top selective gate notch 341, and the gate line slot 351 can be performed in the same process, thereby reducing process steps, saving process time, and improving production efficiency.

[0106] Exemplarily, high-dielectric-constant layers 362, 342, and 352 may be formed within the trench 361, the top selected gate notch 341, and the gate line slot 351 using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. In some examples, second insulating layers 363, 343, and 353 may be formed within the trench 361, the top selected gate notch 341, and the gate line slot 351 where the high-dielectric-constant layers are formed using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, conductive layers 364, 344, and 354 may be formed by filling the trench 361, the top selected gate notch 341, and the gate line slot 351 where the second insulating layer is formed using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof with conductive material. Optionally, the material of the second insulating layers 363, 343, and 353 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The conductive layers 364, 344, and 354 may include, for example, tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, or any combination thereof.

[0107] In the above scheme, the high dielectric constant layer 352, the second insulating layer 353, and the conductive layer 354 are used to form the gate line gap structure 350; the high dielectric constant layer 342, the second insulating layer 343, and the conductive layer 344 are used to form the top select gate cutout structure 340; the high dielectric constant layer 362, the second insulating layer 363, and the conductive layer 364 are used to form the trench structure 360, such as... Figure 5E As shown.

[0108] In other examples, at least one insulating material may be used to fill the trench 361, the top select gate cutout 341, and the gate line slot 351 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, a high dielectric constant layer and a second insulating layer may be sequentially formed in the trench 361, the top select gate cutout 341, and the gate line slot 351, such that the filling structure in the trench 361, the top select gate cutout 341, and the gate line slot 351 does not include a conductive layer (not shown).

[0109] It should be noted that thin film deposition processes such as CVD, PVD, ALD or any combination thereof can be used stepwise to form filling structures in the trench 361, the top selective gate cutout 341 and the gate line gap 351. This allows different filling structures to be formed in the trench 361, the top selective gate cutout 341 and the gate line gap 351. No specific limitation is made here.

[0110] The top select gate notch 341 is formed before the "gate replacement" process, allowing the formation of the top select gate notch 341 to employ conventional etching processes for the dielectric layer and gate sacrificial layer, such as NO stacked structures. This process technology offers high controllability. Furthermore, forming the top select gate notch 341 before the "gate replacement" process also reduces the impact on the gate conductive layer 322', avoiding an increase in the load (stress) on the gate conductive layer.

[0111] Furthermore, the fabrication method of the three-dimensional memory provided in this application solves the problem in conventional fabrication methods where the gate sacrificial layer between adjacent top select gate cuts cannot be replaced with a gate conductive layer during the top select gate cut-out formation process.

[0112] Figure 6 This is an exemplary flowchart of a method 4000 for fabricating a three-dimensional memory according to an embodiment of this application. Figure 6 As shown, the preparation method 4000 of this embodiment includes the following steps:

[0113] S410, a first stacked structure including alternating dielectric layers and gate sacrificial layers is formed on a substrate;

[0114] S420, a top select gate cutout is formed through at least one gate sacrificial layer, and a first sacrificial layer is formed within the top select gate cutout;

[0115] S430, forming a grid line gap that penetrates the first stacked structure;

[0116] S440, the first sacrificial layer and the gate sacrificial layer are removed through the gate line gap to form a sacrificial gap;

[0117] S450, a gate conductive layer is formed within the sacrificial gap; and

[0118] S460, in the same process, forms a filling structure within the top selected grid cutout and grid line gap.

[0119] Figures 7A to 7D This is a schematic cross-sectional view of the fabrication method 4000 for the three-dimensional memory 400 according to this application. The following is in conjunction with... Figures 7A to 7D Steps S430 to S460 described above are further described. Steps S410 and S420 are the same as steps S210 and S220 described with reference to FIG3, respectively, and therefore will not be repeated here.

[0120] S430, forming a grid line gap that penetrates the first stacked structure. .

[0121] In some embodiments of this step, a plurality of gate line gaps (e.g., 451) that expose at least the substrate 410 may be formed simultaneously in the first stacked structure 420 and the first dielectric layer 480, for example, by mask design and photolithography and etching processes (e.g., wet or dry etching processes).

[0122] In some embodiments, at least two gate line slots (e.g., 451) are formed in the first stack structure 420, and at least two top select gate cutouts (e.g., 441) and a plurality of channel structures (e.g., 430) arranged in a row are formed between two adjacent gate line slots (e.g., 451), wherein the channel structure 430 may have been formed before the top select gate cutouts 441 are formed.

[0123] S440, through the gate line gap, remove the first sacrificial layer and the gate sacrificial layer to form a sacrificial gap. .

[0124] In some embodiments of this step, the gate sacrificial layer 422 in the first stacked structure 420 can be removed via the gate line slot 451 using, for example, wet etching or dry etching processes. During the removal process, more than one (e.g., two) first sacrificial layers 442 (pre-formed within the top selected gate notch 441, see [link]) are included between adjacent gate line slots (e.g., 451). Figure 7AIn the case of ), the etching material (e.g., etchant) can remove the first sacrificial layer 442 within the top select gate cutout 441 via the gap formed after removing the gate sacrificial layer 422, re-form the top select gate cutout 441, and then remove the gate sacrificial layer 422 located between the two top select gate cutouts 441 via the top select gate cutout 441, thereby forming a sacrificial gap 423 corresponding to the gate sacrificial layer 422, as shown. Figure 7B As shown. In the above scheme, the first sacrificial layer 442 and the gate sacrificial layer 422 have the same etching selectivity. Therefore, the same etching material (e.g., etchant) can be used to remove the above structure in the same process. After the above process, a sacrificial gap 423 is formed in the space of the gate sacrificial layer 422.

[0125] S450, forming a gate conductive layer within the sacrificial gap. .

[0126] In some implementations of this step, such as Figure 7C As shown, after the sacrificial gap 423 is formed, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a gate conductive layer 422' within the sacrificial gap 423. Optionally, the material of the gate conductive layer 422' may include conductive materials such as tungsten, cobalt, copper, aluminum, doped polysilicon, silicide, or any combination thereof.

[0127] In some embodiments, during the process of forming the gate conductive layer 422' within the sacrificial gap 423, the gate conductive layer 422' may also be formed on the inner wall of the top selective gate cutout 441 and the inner wall of the gate line slot 451. In subsequent processes, the portion of the gate conductive layer 422' located outside the sacrificial gap 423 is removed. For example, an etch-back process can be used to remove the portion of the gate conductive layer 422' located outside the sacrificial gap 423, thereby re-exposing the inner wall of the top selective gate cutout 441 and the inner wall of the gate line slot 451. Optionally, removing the portion of the gate conductive layer 422' exposed to the gate line slot 451 forms a groove relative to the sidewall of the gate line slot 451 to ensure that no conductive material remains in adjacent gate conductive layers 422', thereby preventing short circuits and leakage between adjacent gate conductive layers 422'.

[0128] S460, in the same process, forms a filling structure within the top selected grid cutout and grid line gaps. .

[0129] In some embodiments of this step, after the gate conductive layer 422' is formed, a filling structure can be formed within the exposed top selective gate cutout 441 and gate line gap 451 in the same process.

[0130] In some embodiments, after the above-described process, such as Figure 7DAs shown, high dielectric constant layers 442 and 452 (e.g., aluminum oxide) can be formed within the top selected gate notch 441 and the gate line gaps 451 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, second insulating layers 443 and 453 can be formed within the top selected gate notch 441 and the gate line gaps 451 where the high dielectric constant layers 422 and 452 are formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, conductive layers 444 and 454 can be filled within the top selected gate notch 441 and the gate line gaps 451 where the second insulating layers 443 and 453 are formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, the material of the second insulating layers 443 and 453 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The conductive layers 444 and 454 may include, for example, tungsten, cobalt, copper, aluminum, doped polysilicon, or any combination thereof.

[0131] In the above scheme, the high dielectric constant layer 452, the second insulating layer 453, and the conductive layer 454 are used to form the gate line gap structure 450, and the high dielectric constant layer 442, the second insulating layer 443, and the conductive layer 444 are used to form the top select gate cutout structure 440. See [link to relevant documentation]. Figure 7D .

[0132] The top select gate notch 341 is formed before the "gate replacement" process, allowing the formation of the top select gate notch 341 to employ conventional etching processes for the dielectric layer and gate sacrificial layer, such as NO stacked structures. This process technology offers high controllability. Furthermore, forming the top select gate notch 341 before the "gate replacement" process also reduces the impact on the gate conductive layer 322', avoiding an increase in the load (stress) on the gate conductive layer.

[0133] Furthermore, the fabrication method of the three-dimensional memory provided in this application solves the problem in conventional fabrication methods where the gate sacrificial layer between adjacent top select gate cuts cannot be replaced with a gate conductive layer during the top select gate cut-out formation process.

[0134] Figure 10 A cross-sectional schematic diagram of a three-dimensional memory 500 prepared according to one embodiment of this application. (See attached diagram.) Figure 10 As shown, another aspect of this application provides a three-dimensional memory 500. This three-dimensional memory 500 can be fabricated using the above-described fabrication method 3000. The three-dimensional memory 500 may include: a semiconductor layer 510', a second stacked structure 520', a top select gate cutout structure 540, a first insulating layer 570, a trench structure 560, and a gate line slot structure 550.

[0135] In one embodiment of this application, the semiconductor layer 510' may be located on the substrate 310 (reference 310). Figure 5E The semiconductor layer 510' is located in the general space of the space. The material of the semiconductor layer 510' includes, but is not limited to, polycrystalline silicon, monocrystalline silicon, or any other suitable doped or undoped semiconductor material. The semiconductor layer 510' may contact the channel layer (e.g., 531) in a plurality of channel structures (e.g., 530) to achieve electrical connection with the plurality of channel structures (e.g., 530).

[0136] In one embodiment of this application, the second stacked structure 520' may be located on one side of the semiconductor layer 510'. The second stacked structure 520' may include alternately stacked dielectric layers 521 and gate conductive layers 522'. A portion of each gate conductive layer 522' that contacts the channel structure 530 may serve, for example, as a control gate of a memory cell, and other portions of each gate conductive layer 522' may serve, for example, as word lines connecting multiple memory cells.

[0137] In one embodiment of this application, the three-dimensional memory 500 may further include a first dielectric layer 580, which may be located on the side of the second stacked structure 520' away from the semiconductor layer 510', for example, for covering the end face of a plurality of channel structures (e.g., 530) away from the semiconductor layer 510'. It is worth noting that the first dielectric layer 580 may be omitted in the three-dimensional memory 500.

[0138] In one embodiment of this application, a top-select gate cutout structure 540 passes through, for example, a first dielectric layer 580 and at least one gate conductive layer 522', such as three. A first insulating layer 570 may be located, for example, on the side of the first dielectric layer 580 away from the second stack structure 520'. The top-select gate cutout structure 540 may be used, for example, to electrically isolate the gate conductive layers 522' located on both sides thereon, thereby enabling the gate conductive layers 522' divided by the top-select gate cutout structure 540 to control their corresponding top-select transistors relatively independently. A trench structure 560 may penetrate the first insulating layer 570 and contact the top-select gate cutout structure 540. Exemplarily, in a stacking direction perpendicular to the second stack structure 520', the critical dimensions of the trench structure 560 gradually decrease along the direction toward the top-select gate cutout structure. As described above, by providing the trench structure 560, alternating dielectric layers 521 and gate conductive layers 522' are included between two adjacent top select gate cutout structures (e.g., 540) in the second stacked structure 520' of the three-dimensional memory 500. This satisfies the electrical performance requirements of the three-dimensional memory 500.

[0139] In one embodiment of this application, the gate slot structure 550 penetrates, for example, a first insulating layer 570, a first dielectric layer 580, and a second stacked structure 520', wherein the trench structure 560, the top select gate cutout structure 540, and the gate slot structure 550 have the same configuration. Exemplarily, the trench structure 560 includes, from the outside in, a high dielectric constant layer 562, a second insulating layer 563, and a conductive layer 564. The top select gate cutout structure 540 includes, from the outside in, a high dielectric constant layer 542, a second insulating layer 543, and a conductive layer 544. The gate slot structure 550 includes, from the outside in, a high dielectric constant layer 552, a second insulating layer 553, and a conductive layer 554. Optionally, the high dielectric constant layers 562, 552, and 542 may include, for example, alumina. Optionally, the material of the second insulating layers 563, 553, and 543 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The conductive layers 564, 554, and 544 may include, for example, tungsten, cobalt, copper, aluminum, doped polysilicon, or any combination thereof. As described above, the trench structure 560, the top select gate cutout structure 540, and the gate line slot structure 550 have the same configuration and can be formed in the same process, thereby reducing process steps, saving process time, and improving production efficiency. It should be noted that in some other examples, the trench structure 560, the top select gate cutout structure 540, and the gate line slot structure 550 include a high dielectric constant layer and a second insulating layer from the outside to the inside, but do not include a conductive layer; this is not specifically limited here.

[0140] In one embodiment of this application, at least two gate line slot structures (e.g., 550) extend along a first direction parallel to the semiconductor layer 510', and at least two top select gate cutout structures (e.g., 540) extending along the first direction are located between adjacent gate line slot structures (e.g., 550). Exemplarily, when a memory block is defined by adjacent gate line slot structures (e.g., 550), by providing at least two top select gate cutout structures (e.g., 540) between adjacent gate line slot structures (e.g., 550), it is beneficial to achieve control efficiency and control accuracy of the memory cells within the memory block. Furthermore, the above solution can improve the storage density of the three-dimensional memory and make the design of the channel structure 530 more flexible.

[0141] In one embodiment of this application, the channel structure 530 penetrates the second stacked structure 520' and extends into the semiconductor layer 510' in a direction toward the semiconductor layer 510', for example, perpendicular to the semiconductor layer 510'. Exemplarily, the channel structure 530 may have a generally cylindrical, frustum-shaped, or prism-like outline. The channel structure 530 may, for example, include a functional layer and a channel layer 531 sequentially disposed from the outside in. Exemplarily, multiple channel structures (e.g., 530) may be arranged in rows (e.g., staggered rows) on a plane parallel to the semiconductor layer 510'.

[0142] In one embodiment of this application, the top selection gate cutout structure 540 overlaps with the adjacent channel structure 530 (see reference). Figure 10 Alternatively, the top selection gate cutout can overlap with a row of channel structures.

[0143] Figure 11 This is a cross-sectional schematic diagram of a three-dimensional memory 600 prepared according to one embodiment of this application. For example... Figure 11 As shown, another aspect of this application provides a three-dimensional memory 600. This three-dimensional memory 600 can be fabricated using the above-described fabrication method 4000. The three-dimensional memory 600 may include: a semiconductor layer 610', a second stacked structure 620', a top select gate notch structure 640, and a gate line slot structure 650.

[0144] The semiconductor layer 610', the second stacked structure 620', the top select gate notch structure 640, and the gate line slot structure 650 in the three-dimensional memory 600 can be the same as the various structures in the three-dimensional memory 500, and will not be described again here. It should be noted that the three-dimensional memory 600 does not include the first insulating layer and the trench structure, and as described above, by controlling the selection and holding state of the internal materials during the fabrication process of the top select gate notch structure 640, it is also possible to make two adjacent top select gate notch structures (e.g., 640) in the second stacked structure 620' of the three-dimensional memory 600 include alternately stacked dielectric layers 621 and gate conductive layers 622', thereby satisfying the electrical performance of the three-dimensional memory 600.

[0145] In one embodiment of this application, the gate slot structure 650 penetrates, for example, the first dielectric layer 680 and the second stacked structure 620', wherein the top select gate cutout structure 640 and the gate slot structure 650 have the same configuration. Exemplarily, the top select gate cutout structure 640 includes, from the outside in, a high dielectric constant layer 642, a second insulating layer 643, and a conductive layer 644. The gate slot structure 650 includes, from the outside in, a high dielectric constant layer 652, a second insulating layer 653, and a conductive layer 654. As described above, the identical configuration of the top select gate cutout structure 640 and the gate slot structure 650 can be formed in the same process, thereby reducing process steps, saving process time, and improving production efficiency. It should be noted that in other examples, the top select gate cutout structure 640 and the gate slot structure 650 include, from the outside in, a high dielectric constant layer and a second insulating layer, but do not include a conductive layer; this is not specifically limited here.

[0146] Since the content and structure described above regarding the preparation method can be fully or partially applied to the three-dimensional memory described herein, related or similar content will not be repeated.

[0147] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. For example, the semiconductor structure used to form peripheral devices. Furthermore, the materials of the exemplified layers are merely exemplary.

[0148] Figure 12A and Figure 12B These are schematic diagrams of memory systems 2000a and 2000b according to embodiments of this application. Figure 12A and Figure 12B As shown, the memory system 2000a or 2000b includes at least one three-dimensional memory 2100 and a memory controller 2200.

[0149] The three-dimensional memory 2100 may include the structures described in any of the embodiments above, which will not be repeated here. The memory controller 2200 may control the three-dimensional memory 2100 via, for example, a channel (not shown), and the three-dimensional memory 2100 may perform operations based on the control of the memory controller 2200. Exemplarily, the three-dimensional memory 2100 may receive commands and addresses from the memory controller 2200 via a channel and access regions of the channel structure responsive to the address. In other words, the three-dimensional memory 2100 may perform internal operations corresponding to commands on regions selected by addresses.

[0150] In some examples, the storage controller 2200 and one or more three-dimensional memories 2100 can be integrated into various types of storage devices; in other words, the memory systems 2000a and 2000b can be implemented and packaged into different types of end electronic products. Figure 12A In one example shown, the storage controller 2200 and a single three-dimensional memory 2100 may be integrated into a memory card-type memory system 2200a. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card-type memory system 2200a may also include a memory card connector 2300a that couples it to a host (not shown).

[0151] In such Figure 12B In another example shown, a storage controller 2200 and multiple 3D memories 2100 may be integrated into a memory system 2000b formed by a solid-state drive (SSD). The SSD may also include an SSD connector 2300b that couples it to a host. In some embodiments, the storage capacity and / or operating speed of the SSD may be higher than that of a memory card.

[0152] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, wherein, The preparation method includes: A first stacked structure comprising alternating dielectric layers and gate sacrificial layers is formed on a substrate; A top-select gate cutout is formed through at least one of the gate sacrificial layers and extends along a first direction, and a first sacrificial layer is formed within the top-select gate cutout; Forming a grid line slot that penetrates the first stacked structure and extends along the first direction; Remove the first sacrificial layer and the gate sacrificial layer to form a sacrificial gap; A gate conductive layer is formed within the sacrificial gap; and The same material is filled into the top selected grid cutout and the grid line slot to form the top selected grid cutout structure and the grid line slot structure.

2. The preparation method according to claim 1, wherein, The material of the first sacrificial layer has the same etch selectivity as the material of the gate sacrificial layer. The step of removing the first sacrificial layer and the gate sacrificial layer to form a sacrificial gap includes: The first sacrificial layer and the gate sacrificial layer are removed through the gate line gap.

3. The preparation method according to claim 2, wherein, After the step of forming a portion of the gate conductive layer within the sacrificial gap, the fabrication method further includes: In the same process, a filling structure is formed within the top selected grid cut and the grid line gap.

4. The preparation method according to claim 3, wherein, The step of forming a filling structure within the selected top grid cut and the grid line gaps includes: A high dielectric constant layer, a second insulating layer, and a conductive layer are sequentially formed within the top selected gate cutout and the gate line gap.

5. The preparation method according to claim 1, wherein, The preparation method further includes: A first insulating layer is formed on the side of the first stacked structure away from the substrate and covers the first sacrificial layer; and A portion of the first insulating layer is removed to form a trench that exposes the first sacrificial layer.

6. The preparation method according to claim 5, wherein, The material of the first insulating layer has different etching selectivity than the material of the first sacrificial layer.

7. The preparation method according to claim 5, wherein, The material of the first insulating layer has the same etching selectivity as the material of the first stacked structure.

8. The preparation method according to any one of claims 1 to 7, wherein, At least two of the grid line slots extend parallel to the first direction, and at least two of the top selected grid cutouts extending along the first direction are located between adjacent grid line slots.

9. The preparation method according to any one of claims 1 to 7, wherein, The preparation method further includes: Multiple channel structures are formed in multiple rows along a second direction perpendicular to the first direction, wherein the top selection gate cutout structure overlaps with two adjacent rows of the channel structure or the top selection gate cutout structure overlaps with one row of the channel structure.

10. A three-dimensional memory, wherein, include: Semiconductor layer; The second stacked structure includes alternating dielectric layers and gate conductive layers; A top-selected gate cutout structure extends through at least one of the gate conductive layers; as well as A grid line slot structure extends through the second stacked structure, wherein the top selected grid cutout structure and the grid line slot structure both extend along a first direction, and the top selected grid cutout structure and the grid line slot structure have the same composition.

11. The three-dimensional memory according to claim 10, wherein, Also includes: A first insulating layer is located on the side of the second stacked structure away from the semiconductor layer; as well as The trench structure penetrates the first insulating layer and contacts the top selected gate cutout structure.

12. The three-dimensional memory according to claim 11, wherein, The critical dimensions of the trench structure gradually decrease along the direction toward the top selected grid cutout structure.

13. The three-dimensional memory according to claim 10, wherein, The top selected gate cutout structure and the gate wire slot structure, from the outside to the inside, include a high dielectric constant layer, a second insulating layer, and a conductive layer, respectively.

14. The three-dimensional memory according to any one of claims 10 to 13, wherein, At least two of the gate line slot structures extend along a first direction parallel to the semiconductor layer, and at least two of the top selected gate cutout structures extending along the first direction are located between adjacent gate line slot structures.

15. The three-dimensional memory according to any one of claims 10 to 13, wherein, Also includes: Multiple channel structures arranged in multiple rows along a second direction perpendicular to the first direction, wherein the top selection gate cutout structure overlaps with two adjacent rows of the channel structures or the top selection gate cutout structure overlaps with one row of the channel structures.

16. A memory system, comprising: At least one three-dimensional memory as described in claims 10 to 15; as well as A controller, electrically connected to at least one of the three-dimensional memories, is used to control at least one of the three-dimensional memories.

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