Glitch detection and handling circuitry

Abstract

A glitch detection and processing circuit is disclosed, comprising: a glitch detection module for detecting glitches appearing in an input signal of the glitch detection and processing circuit, wherein the glitch has a first pulse width; and a glitch expansion module for generating a glitch expansion signal with a pulse having a pre-configured second pulse width in response to the glitch detection module detecting a glitch in the input signal, wherein the pulse in the glitch expansion signal corresponds to the glitch in the input signal, and the second pulse width is greater than the first pulse width.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic circuits, and more specifically, to circuits for detecting and processing glitches in electronic signals. Background Technology

[0002] In electronic circuit systems or integrated circuit systems such as System-on-a-Chip (SoC), the lines and the signals conducted on them are susceptible to various electrical noises, introducing unwanted interference into the signals.

[0003] For example, glitches in signals are sometimes unavoidable, and these glitches may affect the normal operation of logic circuits. Therefore, it is necessary to detect and process glitches in signals to reduce or avoid their impact. Summary of the Invention

[0004] In one embodiment, a glitch detection and processing circuit is disclosed, comprising: a glitch detection module for detecting glitches appearing in an input signal of the glitch detection and processing circuit, wherein the glitch has a first pulse width; and a glitch expansion module for generating a glitch expansion signal with a pulse having a pre-configured second pulse width in response to the glitch detection module detecting the glitch in the input signal, wherein the pulse in the glitch expansion signal corresponds to the glitch in the input signal, and the second pulse width is greater than the first pulse width.

[0005] In one embodiment, a glitch detection and processing circuit is disclosed, comprising: a first SR flip-flop, the set input of which receives an input signal from the glitch detection and processing circuit; a second SR flip-flop, the set input of which receives an inverted signal of the input signal; a first pulse forming submodule, the first output of the first SR flip-flop being connected to the input of the first pulse forming submodule, the output signal of the first pulse forming submodule being inverted and input to the reset input of the second SR flip-flop; and a second pulse forming submodule, the first output of the second SR flip-flop being connected to the input of the second pulse forming submodule, the output signal of the second pulse forming submodule being inverted and input to the reset input of the first SR flip-flop.

[0006] In one embodiment, a delay circuit for a system-on-a-chip is disclosed, comprising: a delay unit array including a plurality of delay units; and a glitch detection and processing circuit provided in various embodiments herein, the output of which is connected to the plurality of delay units in the delay array.

[0007] In one embodiment, an on-chip system is disclosed, comprising: a low-voltage domain system that receives an enable signal and operates under the control of the enable signal to provide a low voltage; a delay circuit provided in various embodiments herein for receiving the enable signal and providing a delayed enable signal; and a high-voltage domain system that receives the delayed enable signal and the low voltage and operates under the control of the delayed enable signal to provide a high voltage.

[0008] In one embodiment, a storage device is disclosed, comprising: a storage unit; and peripheral circuitry configured to include glitch detection and processing circuitry or delay circuitry provided in the various embodiments herein.

[0009] The technical solution of this disclosure uses a glitch detection and processing circuit to detect glitches in the enable signal for the on-chip system and correspondingly expands the glitches into pulses of a predetermined width. This ensures that all delay units in the delay array can be reliably reset, thereby avoiding the problem caused by the variable width of the glitch signal, where some delay units are reset while others are not. This disclosure also has other advantages, which will be described in detail below. Attached Figure Description

[0010] The accompanying drawings of the embodiments disclosed herein are briefly described below, and the same or corresponding parts in the drawings are represented by the same or similar reference numerals.

[0011] Figure 1A A schematic block diagram of a system-on-a-chip 10 is shown according to an embodiment of the present disclosure.

[0012] Figure 1B A schematic waveform diagram of an enable signal en and a delayed enable signal en_d is shown according to an embodiment of the present disclosure.

[0013] Figure 2A A schematic block diagram of a delay circuit 110A is shown according to one embodiment of the present disclosure.

[0014] Figure 2B According to one embodiment of this disclosure, schematic waveforms of the enable signal en and the delayed enable signals en_d1 and en_d2 are shown in the presence of no glitches in the enable signal en.

[0015] Figure 2C According to one embodiment of this disclosure, schematic waveforms of the enable signal en and the delayed enable signals en_d1 and en_d2 are shown when a glitch occurs in the enable signal en.

[0016] Figure 3AA schematic block diagram of a delay circuit 110B is shown according to an embodiment of the present disclosure.

[0017] Figure 3B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en.

[0018] Figure 3C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0019] Figure 4A A schematic block diagram of a burr detection and processing circuit 400 is shown according to an embodiment of the present disclosure.

[0020] Figure 4B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en.

[0021] Figure 4C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0022] Figure 5A A schematic block diagram of a burr detection and processing circuit 500 is shown according to an embodiment of the present disclosure.

[0023] Figure 5B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en.

[0024] Figure 5C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0025] Figure 6A A schematic block diagram of a burr detection and processing circuit 600 is shown according to an embodiment of the present disclosure.

[0026] Figure 6B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en.

[0027] Figure 6C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0028] Figure 7 A schematic block diagram of a burr detection and processing circuit 700 is shown according to an embodiment of the present disclosure.

[0029] Figure 8A schematic block diagram of a delay circuit 800 is shown according to an embodiment of the present disclosure.

[0030] Figure 9 A schematic block diagram of a storage system 900 is shown according to an embodiment of the present disclosure. Detailed Implementation

[0031] Specific embodiments of the present disclosure will be described below. Those skilled in the art will understand that obvious variations of the described embodiments can be used without departing from the scope of the present disclosure.

[0032] Figure 1A A schematic block diagram of a system-on-a-chip 10 is shown according to an embodiment of the present disclosure. Figure 1B A schematic waveform diagram of an enable signal en and a delayed enable signal en_d is shown according to an embodiment of the present disclosure.

[0033] The system-on-chip 10 includes a delay circuit 110, a first voltage domain system 120, and a second voltage domain system 130. The first voltage domain system 120 provides a low voltage (lv) to other components of the system-on-chip, and the second voltage domain system 130 provides a high voltage (hv) to other components of the system-on-chip. Both the first voltage domain system 120 and the second voltage domain system 130 operate under the control of an enable signal (en). To ensure correct system operation, the second voltage domain system 130 must be started and operating normally after the first voltage domain system 120 has been started, and it will operate using the low voltage (lv) provided by the first voltage domain system 120. The delay circuit 110 receives the enable signal (en), delays it, and outputs a delayed enable signal (en_d) to control the operation of the second voltage domain system 130.

[0034] like Figure 1B As shown, the delay circuit 110 delays the enable signal en by a specific time and then provides the delayed enable signal en_d to the second voltage domain system 130. Figure 1B In the illustrated embodiment, both the enable signals en and en_d are active high. Those skilled in the art will understand that in other embodiments, the enable signals en and en_d may also be active low.

[0035] Figure 2A A schematic block diagram of a delay circuit 110A is shown according to an embodiment of the present disclosure. Figure 2B shows schematic waveforms of the enable signal en and the delayed enable signals en_d1 and en_d2 without glitches in the enable signal en, according to an embodiment of the present disclosure. Figure 2C According to one embodiment of this disclosure, schematic waveforms of the enable signal en and the delayed enable signals en_d1 and en_d2 are shown when a glitch occurs in the enable signal en.

[0036] Figure 2A The delay circuit 110A shown is Figure 1A An example of a delay circuit 110 is shown. The delay circuit 110A includes a delay array 1110, which includes multiple D flip-flops (DFFs). Figure 2A Only four of the D flip-flops 1111-1114 are shown in the diagram. Multiple D flip-flops in the delay array 1110 are used to provide different delay times for the enable signal en. For example, the Q output of flip-flop 1113 outputs a delayed enable signal en_d1, and the Q output of flip-flop 1114 outputs a delayed enable signal en_d2.

[0037] exist Figure 2A In the example shown, the delay enable signal en_d2 is input to the input of inverter 1101. The output of inverter 1101 is connected to one input of three-input NAND gate 1102. The enable signal en and clock signal clk are input to the other two inputs of three-input NAND gate 1102. The output of NAND gate 1102 is connected to the clock input of D flip-flop 1103 and the input of inverter 1105. The enable signal en is input to the D input (also called the data input) and reset input of D flip-flop 1103, as well as the reset inputs of multiple D flip-flops in delay array 1110. The Q output (also called the data latch output) of D flip-flop 1103 and the output of inverter 1105 are connected to the input of AND gate 1104. The output of AND gate 1104 is connected to the clock input of the first D flip-flop 1111 in delay array 110. (Also known as the inverting data latch output) is connected to its own D input and the clock input of the next D flip-flop 1112. The connections of D flip-flop 1112 and subsequent D flip-flops are similar to those of D flip-flop 1111, as follows: Figure 2A As shown.

[0038] The logic function of the D flip-flop is known in the art and is briefly described below. When the reset input signal is high, the signal at the Q output is equal to the signal at the D input at the rising edge of the clock input signal. The signal at the output terminal is inverted compared to the signal at the Q output terminal. When the reset input signal is low, the signal at the Q output terminal is reset to low or 0.

[0039] The delay circuit 110A can provide multiple delay enable signals with different delay time amounts during normal operation, such as the delay enable signals en_d1 and en_d2 shown. Figure 2BThe waveforms of the enable signal en and the delay enable signals en_d1 and en_d2 are shown. In the specific implementation shown in Figure 1, the delay enable signal can be selected as the delay enable signal en_d output by the delay circuit 110 as needed. For example, en_d1 can be used as the delay enable signal en_d output by the delay circuit 110. Therefore, the delay array 1110 can flexibly provide delay enable signals according to the signal delay requirements of a specific application.

[0040] When glitches appear in the enable signal 'en', such as due to a CDC problem, the delay circuit 110A may malfunction. Figure 2C As shown, a glitch appears in the enable signal en. The glitch is typically a very short pulse with a variable pulse width. When a glitch occurs, the level of the enable signal en changes from high to low, causing the D flip-flops in the corresponding D flip-flop array 1110 to be reset. However, because the low-level duration of the glitch is very short, it may be filtered out by wiring resistors and capacitors. Therefore, it is possible that during the process of the en signal being transmitted along the line to the reset input of each D flip-flop in the delay array 1110, the glitch may be filtered out at some point. This results in some D flip-flops in the delay array 1110 receiving the glitch, while others do not. Consequently, the glitch in the en signal only resets some of the D flip-flops in the delay array 1110, without resetting the rest. For example, a low level of the glitch in the enable signal en resets D flip-flop 1113, causing its Q output signal en_d1 to change from 1 to 0; however, the enable signal en reaching the reset input of D flip-flop 1114 no longer has a glitch, so D flip-flop 1114 will not be reset, and its Q output signal en_d2 remains 1. Since en_d2 remains 1, the output of AND gate 1104 remains 0, that is, the clock input signal of delay array 1110 remains 0. Therefore, the clock delay enable signal en_d output of D flip-flop 1113 remains 0, as shown below. Figure 2C As shown.

[0041] Since in certain applications the delay enable signal en_d1 can be configured as the output delay enable signal en_d of the delay circuit 110, therefore, when the above situation occurs, see Figure 1A and 2CThe delay enable signal en_d provided to the second voltage domain system 130 cannot toggle from 0 to 1 again, causing the second voltage domain system 130 to be disabled, thus leading to a circuit failure. Furthermore, it is understood that if a glitch occurs and only resets a portion of the delay cells in the delay array, there may be unknown potential risks due to this uncertainty in the circuit. Therefore, it is desirable to eliminate such unknown risks as much as possible during the circuit design phase.

[0042] Figure 3A A schematic block diagram of a delay circuit 110B is shown according to an embodiment of the present disclosure. Figure 3B shows schematic waveforms of various signals in the absence of glitches in the enable signal en, according to an embodiment of the present disclosure. Figure 3C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0043] Delay circuit 110B can be used as Figure 1A The delay circuit 110 is shown. The delay circuit 110B includes, in addition to... Figure 2A The circuit portion of the delay circuit 110A shown also includes a glitch detection and processing circuit 300.

[0044] exist Figure 3A In the illustrated embodiment, the glitch detection and processing circuit 300 receives the enable signal en and outputs the processed glitch expansion enable signal en_p, and provides the glitch expansion enable signal en_p to the reset input of each D flip-flop in the delay array 1110.

[0045] The glitch detection and processing circuit 300 includes a first SR flip-flop 3101 and a second SR flip-flop 3201. SR flip-flops, also known as set (S) reset (R) flip-flops, have a logic function known in the art, briefly described below. When the input signal at the S input terminal is high ("1") and the input signal at the R input terminal is low ("0"), the signal at the Q output terminal is high ("1"). The output signal is low level "0"; when S is 0 and R is 1, Q is 0. =1; when S and R are both 0, Q and Maintain the original state.

[0046] The S-input of the first SR flip-flop 3101 is connected to the input of the glitch detection and processing circuit 300, and receives the enable signal en. The inverter 3205 is connected to the input of the glitch detection and processing circuit 300, receives the enable signal en, and provides the inverted enable signal en_b to the S-input of the second SR flip-flop 3201. Figure 3AIn this diagram, s1 represents the input signal at the S input terminal of the first SR flip-flop 3101, and s2 represents the input signal at the S input terminal of the second SR flip-flop 3201. That is, s1 is the enable signal en, and s2 is the inverted enable signal en_b.

[0047] like Figure 3B As shown, under normal operating conditions with no glitches in the enable signal en, s1 is high and s2 is low. Figure 3B The values ​​q1 and q2 are represented as 1 and 0 respectively. The output signal q1 of the Q output terminal of the first SR flip-flop 3101 is 1, and the output signal q2 of the Q output terminal of the second SR flip-flop 3201 is 0.

[0048] The Q output of the first SR flip-flop 3101 is connected to the input of the rising edge delay unit 3102. The rising edge delay unit 3102 is used to delay the rising edge of its input signal by a configured amount of time, for example, as... Figure 3A As shown, the rising edge delayer 3102 can delay the rising edge of signal q1 by 20ns and output the delayed signal q1_rd. In one implementation, the rising edge delayer 3102 can be implemented using an RC delay circuit. By setting appropriate values ​​for resistor R and capacitor C, the amount of time that the rising edge delayer 3102 can delay can be configured. The advantage of implementing the rising edge delayer 3102 using an RC delay circuit is its simple circuit structure. The RC delay circuit itself is a known circuit in the art, and its specific structure will not be described in detail.

[0049] The Q output of the first SR flip-flop 3101 is connected to the input of the inverter 3103, and the output of the inverter 3103 and the output of the rising edge delay unit 3102 are connected to the input of the OR gate 3104. For example... Figure 3B As shown, when signal q1 is 1, the output signal q1_rd of the rising edge delay is also 1, the output signal q1_b of inverter 3103 is 0, and the output signal q1_p of OR gate 3104 is 1. The control signal active_n remains 0, so the output signal of inverter 3305 remains 1. The output terminals of OR gate 3104 and inverter 3305 are connected to NAND gate 3302. Because the output signal of inverter 3305 remains 1, the output of NAND gate 3302 is the inverted version of the input signal q1_p, represented as q1_pb, at which time signal q1_pb is 0.

[0050] The Q output of the second SR flip-flop 3201 is connected to the input of the rising edge delay unit 3202, which is configured the same as the rising edge delay unit 3102. For example... Figure 3A As shown, the rising edge delayer 3102 can delay the rising edge of signal q2 by 20ns and output the delayed signal q2_rd.

[0051] The Q output of the second SR flip-flop 3201 is connected to the input of the inverter 3203, and the output of the inverter 3203 and the output of the rising edge delay unit 3202 are connected to the input of the OR gate 3204. For example... Figure 3B As shown, when signal q2 is 0, signal q2_rd is also 0, the output signal q2_b of inverter 3203 is 1, and the output signal q2_p of OR gate 3204 is 1. The control signal active_n remains 0, therefore the output signal of inverter 3305 remains 1. The outputs of OR gate 3204 and inverter 3305 are connected to NAND gate 3301. Because the output signal of inverter 3305 remains 1, the output of NAND gate 3301 is the inverted version of the input signal q2_p, represented as q2_pb, at which point signal q2_pb is 0.

[0052] The glitch filtering module 3401 in the glitch detection and processing circuit 300 receives an enable signal and filters out glitches in the enable signal en to output a clean enable signal en_f without glitches. In one implementation, the glitch filtering module 3401 may include multiple buffers connected in series, the wiring capacitance and resistance contained in the multiple buffers being sufficient to filter out glitches in the enable signal en, and the output clean enable signal en_f remains 1.

[0053] The outputs of the glitch filter module 3401 and the NAND gate 3302 are connected to the input of the NOR gate 3303. Since the clean enable signal en_f remains 1, the output of the NOR gate 3303 remains 0. The outputs of the NOR gate 3303 and the NAND gate 3301 are connected to the input of the NOR gate 3304. Since the output of the NOR gate 3303 remains 0, the output signal en_p of the NOR gate 3304 depends on another input signal q2_pb, specifically the inverted version of q2_pb, therefore the output signal en_p is 1. Figure 3B As shown, when there are no glitches in the enable signal en, the output signal en_p of the glitch detection and processing module 300 remains at 1. The enable signal en_p serves as the reset signal for the reset input of each D flip-flop in the delay array 1110.

[0054] See Figure 3A and 3C When a glitch occurs in the enable signal en at time t1, signal s1 changes from 1 to 0, and signal s2 changes from 0 to 1. The R input of the second SR flip-flop is connected to the output of NAND gate 3302, and the output signal q1_pb of NAND gate 3302 serves as the R input signal of the second SR flip-flop 3201. At this time, the S input signal of the second SR flip-flop is 1, and the R input signal is 0 (see...). Figure 3B The signal q1_pb in the second SR flip-flop changes the Q output signal q2 from 0 to 1, thus detecting a glitch in the enable signal en.

[0055] When signal q2 changes from 0 to 1, the output signal q2_b of inverter 3203 changes from 1 to 0, and the output signal q2_rd of rising edge delay unit 3202 remains 0 for 20ns and changes from 0 to 1 at time t2 after a 20ns delay. Correspondingly, the output signal q2_p of OR gate 3204 changes from 1 to 0 and remains 0 for 20ns from t1 to t2, thus forming a 20ns pulse signal corresponding to the glitch. Correspondingly, the output signal q2_pb of NAND gate 3301 changes from 0 to 1. Correspondingly, the output signal en_p of NAND gate 3304 changes from 1 to 0.

[0056] The output of NAND gate 3301 is connected to the R input of the first SR flip-flop. Therefore, during the duration of the glitch in signal s1, the S input signal of the first SR flip-flop is 0, the R input signal is 1, the Q output signal q1 changes from 1 to 0, and remains 0 under the control of the reset signal q2_pb.

[0057] When signal q1 changes from 1 to 0, the output signal q1_b of inverter 3103 changes from 0 to 1, and the output signal q1_rd of rising edge delay unit 3102 changes from 1 to 0. Correspondingly, the output signal q1_p of OR gate 3104 remains 1. Correspondingly, the output signal q2_pb of NAND gate 3302 remains 0. While signal q2_pb remains 0, the Q output signal q2 of the second SR flip-flop 3201 remains 1.

[0058] At time t2, the output signal q2_rd of the rising edge delay unit 3202 changes from 0 to 1. Correspondingly, the output signal q2_p of the OR gate 3204 changes from 0 to 1. Correspondingly, the output signal q2_pb of the NAND gate 3301 changes from 1 to 0. At this time, the S-input signal s1 of the first SR flip-flop is 1, and the R-input signal is 0, therefore the Q-output signal q1 changes from 0 to 1.

[0059] When signal q1 changes from 0 to 1 at time t2, the output signal q1_b of inverter 3103 changes from 1 to 0, and the output signal q1_rd of rising edge delay unit 3102 remains 0 for 20ns and changes from 0 to 1 after a 20ns delay. Correspondingly, the output signal q1_p of OR gate 3104 changes from 1 to 0 and remains 0 for 20ns after t2. Correspondingly, the output signal q1_pb of NAND gate 3302 changes from 0 to 1. At this time, the S input signal s2 of the second SR flip-flop is 0, the R input signal q1_pb is 1, and therefore its Q output signal q2 changes from 1 to 0.

[0060] When signal q2 changes from 1 to 0, the output signal q2_b of inverter 3203 changes from 0 to 1, and the output signal q2_rd of rising edge delay 3202 changes from 1 to 0. Correspondingly, the output signal q2_p of OR gate 3204 remains 1. Correspondingly, the output signal q2_pb of NAND gate 3301 remains 0. Correspondingly, the output signal en_p of NAND gate 3304 remains 1. Thus, the glitch detection and processing circuit 300 provides an enable signal en_p with a pulse width of 20ns, which may be referred to as the glitch extension enable signal en_p.

[0061] At time t3, 20 ns after t2, the output signal q1_rd of the rising edge delay unit 3102 changes from 0 to 1. Correspondingly, the output signal q1_p of the OR gate 3104 changes from 0 to 1. Correspondingly, the output signal q1_pb of the NAND gate 3302 changes from 1 to 0. After time t3, and before the next glitch occurs, the waveforms of all signals are... Figure 3B The signal waveforms shown are the same.

[0062] Through the above process, the glitch detection and processing circuit 300 can detect glitch occurrences in the enable signal en, and generate a glitch-extended enable signal en_p with a pulse width of 20ns in response to the occurrence of the glitch. It can be understood that in... Figures 3A-3C In the illustrated embodiment, configuring the extended pulse width to 20 ns is exemplary; in a specific implementation, the extended pulse width can be configured to other values.

[0063] like Figure 3A As shown, the output of the glitch detection and processing circuit 300 is connected to the reset input of each D flip-flop in the delay array 1110. When a glitch occurs in the enable signal en, a glitch extension signal en_p with a pulse width of 20ns is input to the reset input of each D flip-flop in the delay array 1110. The 20ns pulse width is sufficient to reset all D flip-flops in the delay array 1110, thus avoiding the problem described above in conjunction with Figure 2, where a glitch might only reset some of the D flip-flops.

[0064] Those skilled in the art will understand that, although Figure 3A The diagram shows a specific circuit diagram of the delay circuit 110B and its glitch detection and processing circuit 300. However, the embodiments of this disclosure are not limited to the specific circuit and the specific components used therein shown in FIG. 3A. Other circuits and components that achieve the same or corresponding functions may be used in other embodiments.

[0065] Figure 4A A schematic block diagram of a burr detection and processing circuit 400 is shown according to an embodiment of the present disclosure. Figure 4BAccording to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en. Figure 4C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en. Figure 4B and 4C Some signals in Figure 3B and 3C Some of the signals in the diagram correspond to each other, so the details of all the signals in the diagram will not be described in detail.

[0066] The glitch detection and processing circuit 400 can be used as a glitch detection and processing circuit in delay circuits 110 and 110B. For example... Figure 4A As shown, the burr detection and processing circuit 400 includes a burr detection module 410, a pulse forming module 420, a logic combination module 430, and a burr filtering module 440.

[0067] The glitch detection module 410 is used to detect glitches in the input signal of the glitch detection and processing circuit 400, the glitch having a first pulse width. The first pulse width is variable for different glitch types. Figure 4A In the illustrated embodiment, the input signal to the glitch detection and processing circuit 400 is an on-chip system enable signal en, which is input to the input terminal of the glitch detection module 410 after passing through an inverter 4101. Although Figure 4A The inverter 4101 is shown as a component outside the glitch detection module 410, used to invert the enable signal en and provide it to the glitch detection module 410. However, the inverter 4101 can also be understood as a component included within the glitch detection module 410. In one implementation, the glitch detection module 410 includes an SR flip-flop, for example, combined with... Figure 3A The described SR trigger 3201.

[0068] The glitch detection module 410 responds to a glitch appearing in the input signal en by flipping its output signal, thereby detecting the presence of a glitch. Figure 4C In the example shown, a glitch appears in the input signal en at time t1. Correspondingly, the input signal s2 of the glitch detection module 410 changes from 0 to 1, and its output signal q2 changes from 0 to 1, thus detecting the glitch. It can be understood that although at time t1... Figure 3A and 4AThe glitch detection module 410 is described using an SR flip-flop as an example, but other components or modules capable of toggling their output signal in response to the presence of a glitch in the input signal can also be used to implement the glitch detection module 410. For ease of description, in the specific embodiments described herein, the glitch detection module 410 toggles its output signal from a low level to a high level, i.e., from 0 to 1, in response to the presence of a glitch in the input signal. Those skilled in the art will understand that in specific implementations, depending on whether the overall or partial circuit design is based on a rising edge or a falling edge, the glitch detection module 410 may also toggle its output signal from 1 to 0 in response to the presence of a glitch in the input signal, and the design of subsequent processing circuitry will need to be adjusted accordingly to respond to the change of the output signal from 1 to 0.

[0069] In response to the glitch detection module 410 detecting a glitch in the input signal en, the pulse forming module 420 generates a pulse forming signal q2_p with a pre-configured second pulse width, wherein the pulse in the pulse forming signal q2_p corresponds to the glitch in the detected input signal, and the second pulse width is greater than the first pulse width. In some specific implementations, the second pulse width can be configured to be much larger than the first pulse width. For example, the second pulse width can be configured to 20 ns or other appropriate values, while in general, the width of the glitch may be on the order of a few nanoseconds or a few nanoseconds.

[0070] In one implementation, the pulse forming module 420 responds to the toggling of the output signal q2 of the glitch detection module 410, for example, a change in the output signal q2 from 0 to 1, by generating a pulse forming signal q2_p with a second pulse width. The pulse forming signal q2_p ultimately determines the pulse width of the glitch expansion output signal en_p of the glitch detection and processing circuit 400.

[0071] exist Figure 4A In the implementation shown, the pulse forming module 420 includes an SR flip-flop 4201, a first pulse forming submodule 4202, and a second pulse forming submodule 4203. The Q output of the SR flip-flop 410 is connected to the input of the pulse forming submodule 4203, so that the rising edge of the output signal q2 of the SR flip-flop 410 triggers the pulse forming submodule 4203 to form a pulse forming signal q2_p with a second pulse width, as shown in the waveform. Figure 4C As shown. In one specific implementation, the pulse forming submodule 4203 can be... Figure 3AThe specific components 3202, 3203, and 3204 shown are used to implement this. That is, the pulse forming submodule 4203 may include a rising edge delay 3202, an inverter 3203, and an OR gate 3204. The advantage of this pulse forming submodule 4203 is its simple structure. However, those skilled in the art will understand that the pulse forming submodules 4203 and 4202 can also be implemented using other components or modules capable of generating pulse signals with a specific width in response to the trigger signal q2.

[0072] like Figure 4C As shown, the output signal q2_p of the pulse forming submodule 4203 is used to control the reset input operation of the SR flip-flop 4201. Specifically, the output signal q2_p is inverted by the NAND gate 4302 to obtain the inverted output signal q2_pb, which has a high-level pulse with a second pulse width. This high-level pulse q2_pb is input to the R input terminal of the SR flip-flop to control its Q output signal q1 to be 0 for the duration of the corresponding second pulse width. The output signal q1_p of the pulse forming submodule 4202 is used to control the reset input operation of the SR flip-flop 410. Specifically, the output signal q1_p is inverted by the NAND gate 4301 to obtain the inverted output signal q1_pb, which has a high-level pulse with a second pulse width during the time period t2 to t3. This high-level pulse q2_pb is input to the R input terminal of the SR flip-flop 410 to control its Q output signal q2 to return to 0 at time t2.

[0073] exist Figure 4A In the illustrated embodiment, the logic combination module 430 includes a first NAND gate 4301 for toggling the output signal q1_p of the pulse forming submodule 4202, and a second NAND gate 4302 for toggling the output signal q2_p of the pulse forming submodule 4203. The logic combination module 430 also includes NOR gates 4303 and 4304, and ultimately generates a glitch extension signal en_p based on the pulse forming signal q2_p as the output signal of the glitch detection and processing circuit 400 through logic combination. Figure 4A As shown, in a specific implementation, the combinational logic circuit 430 can be connected to... Figure 3A The specific components 3301, 3302, 3303, and 3304 shown are implemented using logic components 4301, 4302, 4303, and 4304 respectively. However, those skilled in the art will understand that the combinational logic circuit 430 can also be implemented using other specific circuits for generating the corresponding glitch extension signal en_p in response to the pulse forming signal q2_p.

[0074] Although Figure 4AIn the illustrated embodiment, NAND gates 4301 and 4302 are shown as part of combinational logic module 430. However, those skilled in the art will understand that NAND gates 4301 and 4302 can also be shown as part of pulse forming module 420, wherein the output signal q1_pb of NAND gate 4301 is used to control the set operation of SR flip-flop 410, and the output signal q2_pb of NAND gate 4302 is used to control the set operation of SR flip-flop 4201.

[0075] The glitch filtering module 440 filters out glitches in the input signal en to output a clean signal en_f without glitches. The combinational logic module 430 generates a glitch-spread signal en_p based on the pulse forming signal q2_p and the clean signal en_f. For example... Figure 4A and 4C As shown, the clean signal en_f is always 1, therefore it determines that the output of NOR gate 4303 is 0, and the corresponding input of NOR gate 4304 is 0; the signal active_n is always 0, therefore the pulse forming signal q2_p determines the output q2_pb of NAND gate 4302, and thus determines the output en_p of NOR gate 4304. Figure 4A As shown, in one specific implementation, the burr filtering module 440 can... Figure 3A The specific component 3401 shown is used to implement this, but those skilled in the art will understand that the glitch filtering module 440 can also be implemented using other specific circuits for filtering glitch in the signal.

[0076] By combining Figures 4A-4C The process described above describes a glitch detection and processing circuit that can detect glitch occurrences in the enable signal en and generate a glitch extension enable signal en_p with a second pulse width of, for example, 20 ns in response to the occurrence of the glitch.

[0077] Figure 5A A schematic block diagram of a burr detection and processing circuit 500 is shown according to an embodiment of the present disclosure. Figure 5B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en. Figure 5C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en. Figure 5A and 5C Some signals in Figure 3B and 3C , Figure 4B and 4C Some of the signals in the diagram correspond to each other, so the details of all the signals in the diagram will not be described in detail.

[0078] The glitch detection and processing circuit 500 can be used as a glitch detection and processing circuit in delay circuits 110 and 110B. For example... Figure 5A As shown, the burr detection and processing circuit 500 includes a burr detection module 510, a burr expansion module 520, and a burr filtering module 530.

[0079] The glitch detection module 510 is used to detect glitch in the input signal en, wherein the glitch has a variable first pulse width. The glitch expansion module 520 is used to generate a glitch expansion signal en_p with a pre-configured second pulse width in response to the glitch detection module 510 detecting a glitch, wherein the pulse in the glitch expansion signal en_p corresponds to a glitch in the signal en, and the second pulse width is greater than the first pulse width.

[0080] The glitch expansion module 520 includes a pulse forming module 5210 and a logic combination module 5220. The implementation methods of the pulse forming module 5210 and the logic combination module 5220 can respectively correspond to... Figure 4A The pulse forming module 420 and logic combination module 430 shown are therefore not described in detail. The implementation of the glitch filtering module 530 can be corresponding to... Figure 4A The burr filter module 440 shown is therefore not described in detail.

[0081] Figure 6A A schematic block diagram of a burr detection and processing circuit 600 is shown according to an embodiment of the present disclosure. Figure 6B According to one embodiment of this disclosure, schematic waveforms of the various signals are shown in the case where there are no glitches in the enable signal en. Figure 6C According to one embodiment of this disclosure, schematic waveforms of various signals are shown when a glitch occurs in the enable signal en.

[0082] The glitch detection and processing circuit 600 can be used as a glitch detection and processing circuit in delay circuits 110 and 110B. For example... Figure 6A As shown, the glitch detection and processing circuit 600 includes a glitch detection module 610 and a glitch expansion module 620. The glitch detection module 610 detects glitch in the input signal en, where the glitch has a variable first pulse width. The glitch expansion module 620 generates a glitch expansion signal en_p with a pre-configured second pulse width in response to the glitch detection module 610 detecting a glitch, wherein the pulse in the glitch expansion signal en_p corresponds to a glitch in the signal en, and the second pulse width is greater than the first pulse width.

[0083] and Figure 3A , 4AUnlike the burr detection and processing circuit shown in 5A, the burr detection and processing circuit 600 does not include a burr filtering module. Instead, the output of the inverter 6225 is connected to the input of the XOR gate 6223.

[0084] The glitch expansion module 620 includes a pulse forming module 6210 and a logic combination module 6220. The implementation methods of the pulse forming module 6210 and the logic combination module 6220 can respectively correspond to... Figure 4A The pulse forming module 420 and logic combination module 430 shown are not described in detail here.

[0085] The above text combined Figure 3A , 4A Documents 5A and 6A describe glitch detection and processing circuits provided in various embodiments of this disclosure. Embodiments of this disclosure provide a glitch detection and processing circuit comprising: a first SR flip-flop whose set input receives an input signal from the glitch detection and processing circuit; a second SR flip-flop whose set input receives an inverted signal of the input signal; a first pulse forming submodule, wherein a first output of the first SR flip-flop is connected to an input of the first pulse forming submodule, and an inverted output signal of the first pulse forming submodule is input to a reset input of the second SR flip-flop; and a second pulse forming submodule, wherein a first output of the second SR flip-flop is connected to an input of the second pulse forming submodule, and an inverted output signal of the second pulse forming submodule is input to a reset input of the first SR flip-flop.

[0086] In one embodiment, the first pulse forming submodule includes a first single-sided delay unit, a first inverter, and a first OR gate. The first single-sided delay unit delays the rising or falling edge of its input signal by a predetermined time. The first output of the first SR flip-flop is connected to the input of the first inverter and the input of the first single-sided delay unit. The output of the first inverter and the output of the first single-sided delay unit are connected to the input of the first OR gate. The second pulse forming submodule includes a second single-sided delay unit, a second inverter, and a second OR gate. The second single-sided delay unit delays the rising or falling edge of its input signal by the predetermined time. The first output of the second SR flip-flop is connected to the input of the second inverter and the input of the second single-sided delay unit. The output of the second inverter and the output of the second single-sided delay unit are connected to the input of the second OR gate.

[0087] In one embodiment, the glitch detection and processing circuit further includes: a first inverting unit, the output of the first OR gate being connected to the input of the first inverting unit, and the output of the first inverting unit being connected to the reset input of the second SR flip-flop; and a second inverting unit, the output of the second OR gate being connected to the input of the second inverting unit, and the output of the second inverting unit being connected to the reset input of the first SR flip-flop.

[0088] In one embodiment, the first inverting unit includes a first NAND gate, the first input of which is connected to the output of a first OR gate, and the second input of which receives a high-level signal. The second inverting unit includes a second NAND gate, the first input of which is connected to the output of a second OR gate, and the second input of which receives a high-level signal.

[0089] In one embodiment, the burr detection and processing circuit further includes: a burr filtering module that receives the input signal and filters burrs from the input signal to output a clean signal without burrs at its output terminal; a first NOR gate, with its first input terminal connected to the output terminal of the burr filtering module and its second input terminal connected to the output terminal of the first NAND gate; and a second NOR gate, with its first input terminal connected to the output terminal of the first NOR gate and its second input terminal connected to the output terminal of the second NAND gate. The output of the second NOR gate serves as the output of the burr detection and processing circuit.

[0090] Figure 7 A schematic block diagram of a burr detection and processing circuit 700 is shown according to an embodiment of the present disclosure.

[0091] The glitch detection and processing circuit 700 can be used as a glitch detection and processing circuit in delay circuits 110 and 110B. In one embodiment, such as Figure 7 As shown, the glitch detection and processing circuit 700 includes a glitch detection module 710 for detecting glitches appearing in the input signal of the glitch detection and processing circuit 700, wherein the glitch has a first pulse width; and a glitch expansion module 720 for generating a glitch expansion signal with a pulse having a pre-configured second pulse width in response to the glitch detection module 710 detecting a glitch in the input signal, wherein the pulse in the glitch expansion signal corresponds to a glitch in the input signal, and the second pulse width is greater than the first pulse width.

[0092] In one embodiment, such as Figure 7As shown, the burr expansion module 720 includes a pulse forming module 7210, which generates a pulse forming signal with a second pulse width in response to the burr detection module 710 detecting the burr; and a logic combination module 7220, which generates the burr expansion signal based on the pulse forming signal.

[0093] In one embodiment, such as Figure 7 As shown, the glitch detection and processing circuit 700 also includes a glitch filtering module 730, used to filter out glitch in the input signal to output a clean signal without glitch. The logic combination module 7220 generates the glitch extension signal based on the pulse forming signal and the clean signal.

[0094] In one embodiment, the glitch detection module 710 flips its first output signal in response to a glitch appearing in the input signal. The pulse forming module 7210, in response to the flipped first output signal of the glitch detection module 710, generates the pulse forming signal having a pulse with a second pulse width.

[0095] In one embodiment, the pulse forming module 7210 generates a control signal for the burr detection module 710 in response to the flipped first output signal of the burr detection module 710, so as to control the burr detection module 710 to maintain the output of the flipped first output signal during the time corresponding to the second pulse width.

[0096] In one embodiment, the control signal for the burr detection module 710 also controls the burr detection module 710 to flip its first output signal again at the end of a time period corresponding to the second pulse width.

[0097] In one embodiment, the pulse forming module 7210 includes a first SR flip-flop, a first pulse forming submodule, and a second pulse forming submodule. The glitch detection module 710 includes a second SR flip-flop. The first output terminal of the first SR flip-flop is connected to the input terminal of the first pulse forming submodule, and the first output terminal of the second SR flip-flop is connected to the input terminal of the second pulse forming submodule. The output signal of the second pulse forming submodule is used to control the reset operation of the first SR flip-flop, and the output signal of the first pulse forming submodule is used to control the reset operation of the second SR flip-flop. The input signal of the glitch detection and processing circuit 700 is used to control the set operation of the second SR flip-flop and the first SR flip-flop.

[0098] In one embodiment, the output signal of the second pulse forming submodule is inverted and input to the reset input of the first SR flip-flop to control the reset operation of the first SR flip-flop. The output signal of the first pulse forming submodule is inverted and input to the reset input of the second SR flip-flop to control the reset operation of the second SR flip-flop. The input signal of the glitch detection and processing circuit 700 is input to the S input of the first SR flip-flop to control the set operation of the first SR flip-flop. This input signal is inverted and input to the S input of the second SR flip-flop to control the set operation of the second SR flip-flop.

[0099] In one embodiment, a first pulse forming submodule includes a first single-sided delay unit, a first inverter, and a first OR gate. The first single-sided delay unit delays the rising or falling edge of its input signal by a predetermined time corresponding to the width of a second pulse. The first output of a first SR flip-flop is connected to the input of the first inverter and the input of the first single-sided delay unit. The outputs of the first inverter and the first single-sided delay unit are connected to the input of the first OR gate. A second pulse forming submodule includes a second single-sided delay unit, a second inverter, and a second OR gate. The second single-sided delay unit delays the rising or falling edge of its input signal by a predetermined time corresponding to the width of a second pulse. The first output of the second SR flip-flop is connected to the input of the second inverter and the input of the second single-sided delay unit. The outputs of the second inverter and the second single-sided delay unit are connected to the input of the second OR gate. Figures 3A-6C The embodiments described above illustrate implementations of rising edge delayers, such as 20ns rising edge delayers 3102 and 3202. Those skilled in the art will understand that when the circuit design is triggered by a falling edge, a falling edge delayer can be used to replace the rising edge delayer described in the specific embodiments. Rising edge delayers and falling edge delayers can be collectively referred to as single-sided delayers.

[0100] In one embodiment, the logic combination module 7220 includes a first inverting unit and a second inverting unit. The first inverting unit is used to invert the output signal of the first OR gate and provide the inverted signal to the reset input of the second SR flip-flop. The second inverting unit is used to invert the output signal of the second OR gate and provide the inverted signal to the reset input of the first SR flip-flop.

[0101] In one embodiment, the first inverting unit includes a first NAND gate, the first input of which is connected to the output of a first OR gate, and the second input of which receives a high-level signal. The second inverting unit includes a second NAND gate, the first input of which is connected to the output of a second OR gate, and the second input of which receives a high-level signal.

[0102] In one embodiment, the logic combination module 7220 includes a first NOR gate and a second NOR gate. The first input of the first NOR gate is connected to the output of a glitch filtering module 730, which filters glitches in the input signal to output a clean signal without glitches. The second input of the first NOR gate is connected to the output of the first NAND gate. The first input of the second NOR gate is connected to the output of the first NOR gate, and the second input of the second NOR gate is connected to the output of the second NAND gate. The second NOR gate outputs a glitch-spread signal. In one embodiment, the glitch filtering module 730 includes multiple buffers.

[0103] In one embodiment, the glitch detection and processing circuit 700 further includes a third inverter, wherein the set input of the first SR flip-flop receives the input signal of the glitch detection and processing circuit 700, and the third inverter receives the input signal and provides the inverted input signal to the set input of the second SR flip-flop. In one embodiment, the input signal of the glitch detection and processing circuit 700 is an enable signal for the on-chip system.

[0104] Figure 8 According to one embodiment of this disclosure, a delay circuit for a system-on-a-chip is shown.

[0105] The delay circuit 800 includes a delay unit array 810, which includes a plurality of delay units. The delay circuit 800 also includes elements incorporated herein by reference. Figure 3A-8 The burr detection and processing circuit 820 in the various embodiments described has its output connected to multiple delay units in the delay array 810.

[0106] In one embodiment, the multiple delay units of the delay array 810 include multiple D flip-flops, wherein the output of the glitch detection and processing circuit 820 is connected to the reset input of the multiple D flip-flops in the delay array 810.

[0107] In one embodiment, the delay circuit 800 further includes: a first inverter that receives a first output signal from the delay array 810; a NAND gate, the first input of which receives an enable signal, the second input of which receives the output signal of the first inverter, and the third input of which receives a clock signal; a first D flip-flop, the data input of which receives the enable signal, the clock input of which receives the output signal of the NAND gate, and the reset input of the first inverter receiving the enable signal; a second inverter, the input of which receives the output signal of the NAND gate; and an AND gate, the first input of which receives the first output signal of the first D flip-flop, the second input of which receives the output signal of the second inverter, and the output of which is connected to the delay array.

[0108] In one embodiment, multiple D flip-flops in the delay array 810 are connected in series, wherein the second output of the preceding D flip-flop is connected to its own D input and the clock input of the following D flip-flop, and the output of the AND gate is connected to the clock input of the first D flip-flop in the delay array 810.

[0109] In one embodiment, this disclosure also provides an on-chip system, such as Figure 1A The illustrated on-chip system includes: a low-voltage domain system that receives an enable signal and operates under the control of the enable signal to provide a low voltage; this disclosure incorporates... Figure 1A-7 The various embodiments described include a delay circuit for receiving the enable signal and providing a delayed enable signal; and a high-voltage domain system that receives the delayed enable signal and the low voltage and operates under the control of the delayed enable signal to provide a high voltage.

[0110] Figure 9 A storage system 900 is shown according to one embodiment of the present disclosure.

[0111] The storage system 900, also known as the memory 900, includes peripheral circuitry 910 and storage cells 920. Figure 9 In the illustrated embodiment, the peripheral circuit 910 includes a power supply system comprising a first voltage domain system 120, a second voltage domain system 130, and a delay circuit 110.

[0112] In one embodiment, the power supply system, through appropriate timing control via a first voltage domain system 110, a second voltage domain system 120, and a delay circuit 130, outputs a voltage hv to the memory cell 920 for read, write, and erase operations. Those skilled in the art will understand that... Figure 9The embodiments shown only illustrate components relevant to the embodiments of this disclosure; the storage system 900 or peripheral circuitry 910 may also include other components.

[0113] In one embodiment of this disclosure, a storage device 900 is disclosed, which includes a storage unit 920 and peripheral circuitry 910, the peripheral circuitry 910 being configured to include glitch detection and processing circuitry or delay circuitry provided in the various embodiments herein.

[0114] The specific embodiments described above with reference to the accompanying drawings are exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of the claims. For the purpose of providing an understanding of the described technology, the specific embodiments include detailed descriptions. However, these technologies can be implemented without these detailed descriptions. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0115] The foregoing description of this disclosure is provided to enable any person skilled in the art to implement or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A delay circuit for an on-chip system, comprising: A delay unit array, wherein the delay unit array comprises a plurality of delay units; as well as A burr detection and processing circuit, the output of which is connected to the plurality of delay units in the delay unit array, wherein the burr detection and processing circuit includes: A burr detection module is used to detect burrs appearing in the input signal of the burr detection and processing circuit, wherein the burrs have a first pulse width; A glitch expansion module is configured to generate a glitch expansion signal with a pre-configured second pulse width in response to the glitch detection module detecting a glitch in the input signal, wherein the pulse in the glitch expansion signal corresponds to the glitch in the input signal, and the second pulse width is greater than the first pulse width.

2. The delay circuit as described in claim 1, wherein, The burr expansion module includes: A pulse forming module, configured to generate a pulse forming signal having a pulse width of the second pulse in response to the burr detection module detecting the burr; and A logic combination module is used to generate the glitch expansion signal based on the pulse forming signal.

3. The delay circuit as described in claim 2, wherein, The burr detection and processing circuit also includes: A glitch filtering module is used to filter out the glitch in the input signal so as to output a clean signal without the glitch; The logic combination module generates the glitch expansion signal based on the pulse forming signal and the clean signal.

4. The delay circuit as described in claim 2, wherein, The burr detection module, in response to the burr appearing in the input signal, flips its first output signal; The pulse forming module responds to the flipped first output signal of the burr detection module to generate the pulse forming signal having a pulse with the second pulse width.

5. The delay circuit as described in claim 4, wherein, The pulse forming module, in response to the flipped first output signal of the burr detection module, generates a control signal for the burr detection module to control the burr detection module to maintain the output of the flipped first output signal during a time period corresponding to the second pulse width.

6. The delay circuit as described in claim 5, wherein, The control signal for the burr detection module also controls the burr detection module to flip its first output signal again at the end of the time period corresponding to the second pulse width.

7. The delay circuit as described in claim 2 or 4, wherein, The pulse forming module includes a first SR trigger, a first pulse forming submodule, and a second pulse forming submodule; as well as The burr detection module includes a second SR trigger; Wherein, the first output terminal of the first SR flip-flop is connected to the input terminal of the first pulse forming submodule, the first output terminal of the second SR flip-flop is connected to the input terminal of the second pulse forming submodule, the output signal of the second pulse forming submodule is used to control the reset operation of the first SR flip-flop, the output signal of the first pulse forming submodule is used to control the reset operation of the second SR flip-flop, and the input signal is used to control the set operation of the second SR flip-flop and the first SR flip-flop.

8. The delay circuit as described in claim 7, wherein, The output signal of the second pulse forming submodule is inverted and input to the reset input terminal of the first SR flip-flop to control the reset operation of the first SR flip-flop. The output signal of the first pulse forming submodule is inverted and input to the reset input terminal of the second SR flip-flop to control the reset operation of the second SR flip-flop. The input signal is input to the S input terminal of the first SR flip-flop to control the set operation of the first SR flip-flop. The input signal is inverted and input to the S input terminal of the second SR flip-flop to control the set operation of the second SR flip-flop.

9. The delay circuit as described in claim 7, wherein, The first pulse forming submodule includes a first single-sided delay, a first inverter, and a first OR gate. The first single-sided delay is used to delay the rising edge or falling edge of its input signal by a predetermined time corresponding to the width of the second pulse. The first output terminal of the first SR flip-flop is connected to the input terminal of the first inverter and the input terminal of the first single-sided delay. The output terminal of the first inverter and the output terminal of the first single-sided delay are connected to the input terminal of the first OR gate. The second pulse forming submodule includes a second single-sided delay, a second inverter, and a second OR gate. The second single-sided delay is used to delay the rising or falling edge of its input signal by a predetermined time corresponding to the width of the second pulse. The first output terminal of the second SR flip-flop is connected to the input terminal of the second inverter and the input terminal of the second single-sided delay. The output terminals of the second inverter and the second single-sided delay are connected to the input terminal of the second OR gate.

10. The delay circuit as claimed in claim 9, wherein, The logic combination module includes a first inversion unit and a second inversion unit; The first inverting unit is used to invert the output signal of the first OR gate and provide the inverted signal to the reset input of the second SR flip-flop; The second inverting unit is used to invert the output signal of the second OR gate and provide the inverted signal to the reset input of the first SR flip-flop.

11. The delay circuit as claimed in claim 10, wherein, The first inversion unit includes a first NAND gate, the first input of which is connected to the output of the first OR gate, and the second input of which receives a high-level signal. The second inversion unit includes a second NAND gate, the first input of the second NAND gate is connected to the output of the second OR gate, and the second input of the second NAND gate receives a high-level signal.

12. The delay circuit as claimed in claim 11, wherein, The logic combination module includes a first NOR gate and a second NOR gate; The first input terminal of the first NOR gate is connected to the output terminal of the glitch filtering module, which is used to filter the glitch in the input signal to output a clean signal without the glitch. The second input terminal of the first NOR gate is connected to the output terminal of the first NAND gate. The first input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, the second input terminal of the second NOR gate is connected to the output terminal of the second NAND gate, and the second NOR gate outputs the glitch extension signal.

13. The delay circuit as claimed in claim 12, wherein, The burr filtering module includes multiple buffers.

14. The delay circuit as claimed in claim 13, wherein, The glitch detection and processing circuit further includes a third inverter, wherein the set input terminal of the first SR flip-flop receives the input signal, the third inverter receives the input signal, and provides the inverted input signal to the set input terminal of the second SR flip-flop.

15. The delay circuit as claimed in claim 1, wherein, The input signal is an enable signal for the system-on-chip.

16. The delay circuit as claimed in claim 1, wherein, The plurality of delay units include a plurality of D flip-flops, wherein the output of the glitch detection and processing circuit is connected to the reset input of the plurality of D flip-flops in the delay unit array.

17. The delay circuit of claim 16, further comprising: A first inverter receives a first output signal from the delay unit array; The NAND gate receives an enable signal at its first input, an output signal from the first inverter at its second input, and a clock signal at its third input. The first D flip-flop receives the enable signal at its data input terminal, the clock input terminal of the first D flip-flop receives the output signal of the NAND gate, and the reset input terminal of the first inverter receives the enable signal. The second inverter receives the output signal of the NAND gate at its input terminal. The AND gate has its first input receiving the first output signal of the first D flip-flop, its second input receiving the output signal of the second inverter, and its output connected to the delay unit array.

18. The delay circuit as claimed in claim 17, wherein, The plurality of D flip-flops in the delay unit array are connected in series, wherein the second output of the previous D flip-flop is connected to its own D input and the clock input of the next D flip-flop, and the output of the AND gate is connected to the clock input of the first D flip-flop in the delay unit array.

19. A burr detection and processing circuit, comprising: The first SR flip-flop receives the input signal from the glitch detection and processing circuit at its set input terminal; The second SR flip-flop receives the inverted signal of the input signal at its set input terminal; The first pulse forming submodule has its first output terminal connected to the input terminal of the first pulse forming submodule, and its output signal is inverted and input to the reset input terminal of the second SR flip-flop. The second pulse forming submodule has its first output terminal connected to the input terminal of the second SR flip-flop, and its output signal is inverted and input to the reset input terminal of the first SR flip-flop. The first pulse forming submodule includes a first single-sided delay unit, a first inverter, and a first OR gate. The first single-sided delay unit is used to delay the rising edge or falling edge of its input signal by a predetermined time. The first output terminal of the first SR flip-flop is connected to the input terminal of the first inverter and the input terminal of the first single-sided delay unit. The output terminal of the first inverter and the output terminal of the first single-sided delay unit are connected to the input terminal of the first OR gate. The second pulse forming submodule includes a second single-sided delay, a second inverter, and a second OR gate. The second single-sided delay is used to delay the rising or falling edge of its input signal by the predetermined time. The first output terminal of the second SR flip-flop is connected to the input terminal of the second inverter and the input terminal of the second single-sided delay. The output terminals of the second inverter and the second single-sided delay are connected to the input terminal of the second OR gate.

20. The burr detection and processing circuit as described in claim 19, further comprising: The first inverting unit has its output connected to the input of the first inverting unit, and its output connected to the reset input of the second SR flip-flop. The second inverting unit has its output connected to the input of the second OR gate, and its output connected to the reset input of the first SR flip-flop.

21. The burr detection and processing circuit as described in claim 20, wherein, The first inversion unit includes a first NAND gate, the first input of which is connected to the output of the first OR gate, and the second input of which receives a high-level signal. The second inversion unit includes a second NAND gate, the first input of the second NAND gate is connected to the output of the second OR gate, and the second input of the second NAND gate receives a high-level signal.

22. The burr detection and processing circuit as described in claim 21, further comprising: A burr filtering module receives the input signal and filters out burrs in the input signal to output a clean signal without the burrs at its output terminal. The first NOR gate, the first input of the first NOR gate is connected to the output of the burr filter module, and the second input of the first NOR gate is connected to the output of the first NAND gate; The second NOR gate has its first input connected to the output of the first NOR gate, and its second input connected to the output of the second NAND gate.

23. A delay circuit for an on-chip system, comprising: A delay unit array, wherein the delay unit array comprises a plurality of delay units; The burr detection and processing circuit as described in any one of claims 19 to 22, wherein the output of the burr detection and processing circuit is connected to the plurality of delay units in the delay unit array.

24. The delay circuit as claimed in claim 23, wherein, The plurality of delay units include a plurality of D flip-flops, wherein the output of the glitch detection and processing circuit is connected to the reset input of the plurality of D flip-flops in the delay unit array.

25. The delay circuit of claim 24, further comprising: A first inverter receives a first output signal from the delay unit array; The NAND gate receives an enable signal at its first input, an output signal from the first inverter at its second input, and a clock signal at its third input. The first D flip-flop receives the enable signal at its data input terminal, the clock input terminal of the first D flip-flop receives the output signal of the NAND gate, and the reset input terminal of the first inverter receives the enable signal. The second inverter receives the output signal of the NAND gate at its input terminal. The AND gate has its first input receiving the first output signal of the first D flip-flop, its second input receiving the output signal of the second inverter, and its output connected to the delay unit array.

26. The delay circuit as claimed in claim 25, wherein, The plurality of D flip-flops in the delay unit array are connected in series, wherein the second output of the previous D flip-flop is connected to its own D input and the clock input of the next D flip-flop, and the output of the AND gate is connected to the clock input of the first D flip-flop in the delay unit array.

27. A system-on-a-chip, comprising: A low-voltage domain system that receives an enable signal and operates under the control of the enable signal to provide a low voltage; The delay circuit as described in any one of claims 1-18 and 23-26 is configured to receive the enable signal and provide a delayed enable signal; and A high-voltage domain system that receives the delayed enable signal and the low voltage and operates under the control of the delayed enable signal to provide a high voltage.

28. A storage device, comprising: Storage unit; as well as The peripheral circuitry is configured to include a glitch detection and processing circuit as described in any one of claims 19-22 or a delay circuit as described in any one of claims 1-18, 23-26.

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