Hybrid logic circuit and control method thereof, chip

Abstract

The application discloses a hybrid logic circuit, a control method thereof and a chip, and relates to the technical field of logic circuits. The hybrid logic circuit comprises a logic assignment module, a voltage regulating module, a pull-up transistor network and a current source structure. The drain of each NMOS transistor arranged in the voltage regulating module is connected with the drain of a corresponding PMOS transistor arranged in the pull-up transistor network. The source of each NMOS transistor arranged in the voltage regulating module is connected with the drain of a corresponding NMOS transistor arranged in the current source structure. The output end of the logic assignment module is connected with the gate of a corresponding NMOS transistor in the voltage regulating module. The gate of each PMOS transistor arranged in the pull-up transistor network is connected with the output end of an operational amplifier arranged in the voltage regulating module.

Description

Technical Field

[0001] This invention relates to the technical field of CMOS circuits, and specifically to a mixed logic circuit and its control method and chip. Background Technology

[0002] In the field of integrated circuit design, power consumption of CMOS circuits has become a significant challenge. In recent years, with the rapid development of chip manufacturing technology, chip feature sizes have progressed from the micrometer level to the deep submicrometer level and then to the nanometer level. While the process size of CMOS circuits is shrinking, the integration density, the distribution density of MOS transistors, and the exponential growth rate of power consumption are constantly increasing. These factors lead to a sharp increase in the total power consumption of the chip, exacerbating the burden on the chip during mixed logic computation and slowing down the computation speed. Mixed logic computation consists of various logic operations composed of the three basic logic operators (AND, OR, and NOT), including logic operations other than AND, OR, and NOT.

[0003] From the perspective of constructing complex visual image processing models, it is necessary to design a well-structured hybrid logic circuit as a basic logic calculation circuit unit for some complex gate circuit logic functions, and as a hardware tool for performing relevant binary data calculations. Summary of the Invention

[0004] To provide a hybrid logic circuit that saves on related hardware resource overhead, this technical solution discloses the following structurally sound hybrid logic circuit and its control method and chip, specifically including: A hybrid logic circuit includes a logic assignment module, a voltage regulation module, a pull-up transistor network, and a current source structure. The drain of each NMOS transistor in the voltage regulation module is connected to the drain of a corresponding PMOS transistor in the pull-up transistor network. The source of each NMOS transistor in the voltage regulation module is connected to the drain of a corresponding NMOS transistor in the current source structure. The output of the logic assignment module is connected to the gate of a corresponding NMOS transistor in the voltage regulation module. The gate of each PMOS transistor in the pull-up transistor network is connected to the output of an operational amplifier in the voltage regulation module.

[0005] Further, the pull-up transistor network includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the voltage regulation module includes a first operational amplifier, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor; the connection point between the drain of the first PMOS transistor and the drain of the first NMOS transistor is the first signal output terminal of the mixed logic circuit; the source of the first PMOS transistor, the substrate of the first PMOS transistor, the source of the second PMOS transistor, the substrate of the second PMOS transistor, the source of the third PMOS transistor, and the substrate of the third PMOS transistor are all connected to... The circuit is powered by a power supply. The substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected to the same node. The non-inverting input of the first operational amplifier is connected to the drain of the second NMOS transistor, and the inverting input of the first operational amplifier is connected to the gate of the second NMOS transistor. The inverting input of the first operational amplifier is the signal input of the voltage regulation module. The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the output of the first operational amplifier. The gate of the first NMOS transistor is connected to the drain of the third NMOS transistor, and this connection is the second signal output of the hybrid logic circuit.

[0006] Furthermore, the logic assignment module includes a fourth PMOS transistor and a fifth PMOS transistor; the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected, the gate of the fourth PMOS transistor and the drain of the fifth PMOS transistor are connected, the drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor are connected, the gate of the fourth PMOS transistor is the first signal input terminal of the hybrid logic circuit, and the gate of the fifth PMOS transistor is the second signal input terminal of the hybrid logic circuit; the connection between the source of the fourth PMOS transistor and the source of the fifth PMOS transistor is the signal output terminal of the logic assignment module, and the gate of the third NMOS transistor is connected to the signal output terminal of the logic assignment module.

[0007] Furthermore, the current source structure includes a fourth NMOS transistor, the gate of which is the signal input terminal of the current source structure; the source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor and the substrate of the fourth NMOS transistor are both grounded.

[0008] Furthermore, the first signal input terminal of the hybrid logic circuit is connected to the first input signal, and the second signal input terminal of the hybrid logic circuit is connected to the second input signal; wherein, when the second input signal is the inverted signal of the first input signal, the third NMOS transistor is turned on.

[0009] A control method based on the aforementioned hybrid logic circuit includes inputting a first input signal to a first signal input terminal of the hybrid logic circuit and simultaneously inputting a second input signal to a second signal input terminal of the hybrid logic circuit; when the second input signal and the first input signal are different logic signals, the first signal output terminal of the hybrid logic circuit outputs a high level and the second signal output terminal of the hybrid logic circuit outputs a low level; when the second input signal and the first input signal are the same logic signal, the first signal output terminal of the hybrid logic circuit outputs a low level and the second signal output terminal of the hybrid logic circuit outputs a high level.

[0010] Furthermore, when both the first and second input signals are high, the second signal output terminal of the mixed logic circuit outputs a high level to indicate that the two input signals of the mixed logic circuit are logic signals with the same level, and the first signal output terminal of the mixed logic circuit outputs a low level to indicate that the two input signals of the mixed logic circuit are not inverted signals; when both the first and second input signals are low, the second signal output terminal of the mixed logic circuit outputs a high level, and the first signal output terminal of the mixed logic circuit outputs a low level; when the first input signal is high and the second input signal is low, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level; when the first input signal is low and the second input signal is high, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level.

[0011] Further, the current source structure of the hybrid logic circuit includes a fourth NMOS transistor; the pull-up transistor network of the hybrid logic circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the voltage regulation module of the hybrid logic circuit includes a first operational amplifier, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor; the connection point between the drain of the first PMOS transistor and the drain of the first NMOS transistor is the first signal output terminal of the hybrid logic circuit; the source, substrate, and other components of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the third PMOS transistor are all connected to a power supply; the substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded; the source, the second NMOS transistor, and the third NMOS transistor are all connected to a power supply. The sources of the S-transistors are connected to the same node; the non-inverting input of the first operational amplifier is connected to the drain of the second NMOS transistor, and the inverting input of the first operational amplifier is connected to the gate of the second NMOS transistor; wherein, the inverting input of the first operational amplifier is the signal input of the voltage regulation module; the gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the output of the first operational amplifier; the gate of the first NMOS transistor is connected to the drain of the third NMOS transistor, and this connection is the second signal output of the hybrid logic circuit; the gate of the fourth NMOS transistor is the signal input of the current source structure; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor and its substrate are both grounded; wherein, the signal input of the voltage regulation module is configured to input a high level; the signal input of the current source structure is configured to input a high level; wherein, the hybrid logic circuit includes a voltage regulation module, a pull-up transistor network, and a current source structure.

[0012] Furthermore, the hybrid logic circuit includes a logic assignment module, which includes a fourth PMOS transistor and a fifth PMOS transistor; the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected, the gate of the fourth PMOS transistor and the drain of the fifth PMOS transistor are connected, the drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor are connected, the gate of the fourth PMOS transistor is the first signal input terminal of the hybrid logic circuit, and the gate of the fifth PMOS transistor is the second signal input terminal of the hybrid logic circuit; the connection between the source of the fourth PMOS transistor and the source of the fifth PMOS transistor is the signal output terminal of the logic assignment module, and the gate of the third NMOS transistor is connected to the signal output terminal of the logic assignment module.

[0013] A chip including the aforementioned hybrid logic circuitry is configured to perform the aforementioned control method.

[0014] The hybrid logic circuit disclosed in this invention shares the same pull-up transistor network and the same current source structure with the logic assignment module and voltage regulation module. Compared with the voltage swing control circuit in the prior art, it saves the number of MOS transistors in the corresponding differential structure. Therefore, in the process of training image information in the neural network model of artificial intelligence, the chip disclosed in this invention is used to perform small-scale XOR calculation operations, which can ensure the processing capability of the chip to which the hybrid logic circuit belongs with fewer input ports and fewer MOS transistors. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a hybrid logic circuit disclosed in an embodiment of the present invention. Detailed Implementation

[0016] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings: The technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "comprising," "including," "having," and any variations thereof used in this application are intended to cover non-exclusive inclusion, such as: a process, method, system product, or apparatus that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules not listed, or may also include other steps or units inherent to these processes, methods, products, or apparatuses. The terms "first," "second," "third," etc., used in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0017] This invention discloses a hybrid logic circuit for performing hybrid logic calculations. The hybrid logic circuit includes a logic assignment module, a voltage regulation module, a pull-up transistor network, and a current source structure. In this embodiment, the drain of each NMOS transistor in the voltage regulation module is connected to the drain of a corresponding PMOS transistor in the pull-up transistor network; the gate of each PMOS transistor in the pull-up transistor network is connected to the output of an operational amplifier in the voltage regulation module; the pull-up transistor network is composed of PMOS transistors and is equivalent to providing pull-up resistors for the voltage regulation module. The source of each NMOS transistor in the voltage regulation module is connected to the drain of a corresponding NMOS transistor in the current source structure. The voltage regulation module, composed of NMOS transistors and their associated operational amplifiers, can control the electrical state of the pull-up transistor network (including entering the saturation region, linear region, or cutoff region), providing a reasonable bias voltage for the hybrid logic circuit and outputting the results of hybrid logic calculations with fewer MOS transistors. The output of the logic assignment module is connected to the gate of a corresponding NMOS transistor in the voltage regulation module. The output signal of the logic assignment module is driven by this NMOS transistor and converted into the logic operation output signal and its inverted signal of the hybrid logic circuit. The connection method of the signal input terminals of the logic assignment module or the logical relationship between the input signals can realize a matching type of hybrid logic calculation function, making the hybrid logic circuit the basic circuit of the computing device required by the corresponding algorithm logic, and capable of simultaneously generating XOR signals to control the operation mode of other circuits. The current source structure is composed of NMOS transistors, which provide stable current to the voltage regulation module and the logic assignment module under the control of the external voltage, ensuring the driving capability of the hybrid logic circuit.

[0018] As one example, such as Figure 1As shown, the pull-up transistor network includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the voltage regulation module includes a first operational amplifier D1, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3; the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, and the drain of the third PMOS transistor P3 is connected to the drain of the third NMOS transistor N3; the connection between the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 is the first signal output terminal of the hybrid logic circuit, which is used to output a first output signal Y as a result of the aforementioned hybrid logic calculation. The source of the first PMOS transistor P1, the substrate of the first PMOS transistor P1, the source of the second PMOS transistor P2, the substrate of the second PMOS transistor P2, the source of the third PMOS transistor P3, and the substrate of the third PMOS transistor P3 are all connected to the power supply Vdd. The substrates of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are all grounded. The sources of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected to the same node, which is the current supply terminal of the current source structure. The non-inverting input terminal + of the first operational amplifier D1 is connected to the drain of the second NMOS transistor N2, and the inverting input terminal - of the first operational amplifier D1 is connected to the gate of the second NMOS transistor N2. The connection between the inverting input terminal - of the first operational amplifier D1 and the gate of the second NMOS transistor N2 is a signal input terminal of the voltage regulation module. The inverting input terminal - of the first operational amplifier D1 is used to receive the first voltage signal VL. The gates of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are all connected to the output terminal of the first operational amplifier D1. The output terminal of the first operational amplifier D1 outputs a voltage VP, which is used to simultaneously control the on / off state of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3. Specifically, when the gate voltage of the second NMOS transistor N2 is greater than its drain voltage, the first operational amplifier D1 outputs a low level, turning on the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3; when the gate voltage of the second NMOS transistor N2 is less than its drain voltage, the first operational amplifier D1 outputs a high level, causing the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 to all turn off; the gate of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3, and this connection terminal is the second signal output terminal of the mixed logic circuit. The second signal output terminal is used to output the second output signal Yb, and if an analog signal is output, it can be used as the inverted signal of the first output signal Y.

[0019] like Figure 1 As shown, the logic assignment module includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5; the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected, the gate of the fourth PMOS transistor P4 and the drain of the fifth PMOS transistor P5 are connected, and the drain of the fifth PMOS transistor P5 and the gate of the fourth PMOS transistor P4 are connected. Preferably, the substrates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both connected to a power supply Vdd; the gate of the fourth PMOS transistor P4 is the first signal input terminal of the hybrid logic circuit, used to receive a first logic signal A; the gate of the fifth PMOS transistor P5 is the second signal input terminal of the hybrid logic circuit, used to receive a second logic signal B, thus the logic assignment module becomes a 2-input logic circuit; the connection between the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 is the signal output terminal of the logic assignment module, and the gate of the third NMOS transistor N3 is connected to the signal output terminal of the logic assignment module. In conjunction with the foregoing embodiments, the logic assignment module composed of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a first output signal Y at the drain of the first NMOS transistor N1, corresponding to the XOR logic result of the first logic signal A and the second logic signal B; the logic assignment module composed of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a second output signal Yb at the drain of the third NMOS transistor N3, corresponding to the XOR logic result of the first logic signal A and the second logic signal B. Specifically, the first signal input terminal of the hybrid logic circuit is connected to a first input signal, corresponding to... Figure 1 The first logic signal A; the second signal input terminal of the hybrid logic circuit is connected to the second input signal, corresponding to... Figure 1 The second input signal B; wherein, when the second input signal is the inverted signal of the first input signal, the third NMOS transistor is turned on, wherein when the logic signal corresponding to the second input signal is 1, the logic signal corresponding to the first input signal is 0; when the logic signal corresponding to the second input signal is 0, the logic signal corresponding to the first input signal is 1. When the second input signal and the first input signal input the same logic signal, the third NMOS transistor is turned off, wherein when the logic signal corresponding to the second input signal is 1, the logic signal corresponding to the first input signal is 1; when the logic signal corresponding to the second input signal is 0, the logic signal corresponding to the first input signal is 0. Therefore, the hybrid logic circuit is equivalent to a composite gate logic circuit composed of an XOR gate and an XNOR gate.

[0020] like Figure 1As shown, the current source structure includes a fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is the signal input terminal of the current source structure, used to connect to the second voltage signal VN. This is generally achieved by biasing a simple current mirror, so that the fourth NMOS transistor N4 can provide a constant current source. The sources of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are all connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 and its substrate are both grounded.

[0021] In summary, within the hybrid logic circuit disclosed in this invention, the logic assignment module and the voltage regulation module share the same pull-up transistor network and the same current source structure. Compared with the voltage swing control circuit composed of a fully differential pull-down network in the prior art, the number of MOS transistors arranged in the differential structure between the pull-up transistor network and the current source structure is reduced. That is, the first operational amplifier D1 is only driven and controlled by a pair of second NMOS transistors N2 and second PMOS transistors P2, without the need to connect a pair of MOS transistors to each input terminal to construct a fully differential structure.

[0022] As one embodiment, the specific working principle of the hybrid logic circuit is as follows: The power supply voltage Vdd connected to the voltage regulation module is equal to 2.5V. The first voltage signal VL = 1V is connected to the inverting input terminal of the first operational amplifier D1 and the gate of the second NMOS transistor N2. The second voltage signal VN = 1.5V is connected to the signal input terminal of the current source structure. The second NMOS transistor N2 is turned on. The voltage at the inverting input terminal of the first operational amplifier D1 is greater than that at its non-inverting input terminal. The output voltage VP at the output terminal of the first operational amplifier D1 is low, causing the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 to all be turned on.

[0023] The standard operating voltage that needs to be supplemented is that, in this embodiment, a signal with a voltage greater than 2V is a high level, corresponding to logic signal 1; a signal with a voltage less than or equal to 0.8V is a low level, corresponding to logic signal 0.

[0024] When the first logic signal A=0 and the second logic signal B=0, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the third NMOS transistor N3 are all turned off. The drain of the third NMOS transistor N3 is charged to a high level, and the signal Yb output by the second signal output terminal of the mixed logic circuit is at a high level. At this time, the first NMOS transistor N1 is turned on, and the drain of the first NMOS transistor N1 is discharged to a low level. Then, the signal Y output by the first signal output terminal of the mixed logic circuit is at a low level, realizing the output of XOR logic result and XNOR logic result.

[0025] When the first logic signal A=0 and the second logic signal B=1, the fourth PMOS transistor P4 and the third NMOS transistor N3 are both turned on, the fifth PMOS transistor P5 is turned off, and the drain of the third NMOS transistor N3 is discharged to a low level. The signal Yb output by the second signal output terminal of the mixed logic circuit is at a low level. At this time, the first NMOS transistor N1 is turned off, and the second signal output terminal of the mixed logic circuit is charged to a high level. Then, the signal Y output by the first signal output terminal of the mixed logic circuit is at a high level, realizing the output of XOR logic result and XNOR logic result.

[0026] When the first logic signal A=1 and the second logic signal B=0, the fifth PMOS transistor P5 and the third NMOS transistor N3 are both turned on, the fourth PMOS transistor P4 is turned off, and the drain of the third PMOS transistor N3 is discharged to a low level. The signal Yb output by the second signal output terminal of the hybrid logic circuit is at a low level. At this time, the first NMOS transistor N1 is turned off, and the second signal output terminal of the hybrid logic circuit is charged to a high level. Then, the signal Y output by the first signal output terminal of the hybrid logic circuit is at a high level, realizing the output of XOR logic result and XNOR logic result.

[0027] When the first logic signal A=1 and the second logic signal B=1, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the third NMOS transistor N3 are all turned off. The drain of the third NMOS transistor N3 is charged to a high level, and the signal Yb output by the second signal output terminal of the mixed logic circuit is at a high level. At this time, the first NMOS transistor N1 is turned on, and the drain of the first NMOS transistor N1 is discharged to a low level. Then, the signal Y output by the first signal output terminal of the mixed logic circuit is at a low level, realizing the output of XOR logic result and XNOR logic result.

[0028] It should be added that an n-channel metal-oxide-semiconductor field-effect transistor is represented as an NMOS transistor. Figure 1 The N-channel metal-oxide-semiconductor field-effect transistor is represented as an N-channel; the p-channel is represented as a PMOS transistor. Figure 1 The symbol in the middle is P.

[0029] Compared to existing XOR gate circuit structures, this invention does not employ a large number of CMOS devices, nor does it increase the number of interconnects. It can implement a hybrid logic system with the same function using fewer devices. This hybrid logic circuit becomes the foundational circuit for the computational devices required by the corresponding algorithm logic, and can be based on MOS transistors using fully depleted silicon technology. Figure 1Each MOS transistor structure shown generates an XOR signal (including bias voltage) that controls the operation of other circuits, which can increase the stability of the circuit system and improve the overall performance of the circuit system. In the process of training and reasoning image information in the neural network model of artificial intelligence, the hybrid logic circuit disclosed in this invention can perform small-scale XOR calculation operations, which can ensure the processing capability of the system-on-chip to which the hybrid logic circuit belongs with fewer input ports and fewer MOS transistors.

[0030] Based on the hybrid logic circuit disclosed in the foregoing embodiments, the present invention also discloses a control method based on the hybrid logic circuit, the control method comprising: A first input signal is input to the first signal input terminal of the hybrid logic circuit. Specifically, a signal source outside the hybrid logic circuit inputs the first input signal to the first signal input terminal of the hybrid logic circuit, including configuring the input to be high level (corresponding to logic 1) or low level (corresponding to logic 0). At the same time, a second input signal is input to the second signal input terminal of the hybrid logic circuit. Specifically, a signal source outside the hybrid logic circuit inputs the second input signal to the second signal input terminal of the hybrid logic circuit, including configuring the input to be high level (corresponding to logic 1) or low level (corresponding to logic 0).

[0031] Combination Figure 1 It can be seen that when the second input signal B and the first input signal A are different logic signals, the second input signal B is at a high level and the first input signal A is at a low level, or the second input signal B is at a low level and the first input signal A is at a high level. If implemented as an analog input signal, the second input signal B is the inverted signal of the first input signal A. This can be achieved when the associated module inside the mixed logic circuit detects that the signal A at the first signal input terminal is the inverted signal of the signal B at the second signal input terminal (which can be understood as two voltage signals with the same amplitude but opposite directions of change). In this case, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level. That is, the fourth PMOS transistor P4 is turned on to transmit the second input signal B received at the drain of the fourth PMOS transistor P4 to the source of the fourth PMOS transistor P4, or the fifth PMOS transistor P5 is turned on to transmit the first input signal A received at the drain of the fifth PMOS transistor P5 to the source of the fifth PMOS transistor P5.

[0032] When the second input signal B and the first input signal A are the same logic signals, the associated module inside the hybrid logic circuit can detect that the level states of signal A at the first signal input terminal and signal B at the second signal input terminal are within the voltage range of the same type of logic signal. If implemented using digital circuits, the second input signal B and the first input signal A are both represented as logic signal 1 or logic signal 0. If implemented using analog circuits, the second input signal B and the first input signal A are both Vdd or 0. Then, the first signal output terminal of the hybrid logic circuit outputs a low level, and the second signal output terminal of the hybrid logic circuit outputs a high level. In this case, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are simultaneously turned off (the MOS transistors are in the off state), so the second input signal B received at the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4, and the first input signal A received at the drain of the fifth PMOS transistor P5 cannot be transmitted to the source of the fifth PMOS transistor P5.

[0033] Specifically, in combination Figure 1 It can be seen that when both the first and second input signals are high, the first input signal being high corresponds to the first logic signal A=1, and the second input signal being high corresponds to the second logic signal B=1. Therefore, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the third NMOS transistor N3 are all turned off. The second input signal B received at the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4. Simultaneously, the first input signal A received at the drain of the fifth PMOS transistor P5 also cannot be transmitted normally to the source of the fifth PMOS transistor P5. Therefore, the signal Yb output from the second signal output terminal of the mixed logic circuit is charged to a high level to indicate that the two input signals of the mixed logic circuit are logic signals at the same level. The signal Y output from the first signal output terminal of the mixed logic circuit is pulled down to a low level to indicate that the two input signals of the mixed logic circuit are not inverse signals.

[0034] When both the first and second input signals are low, the first input signal being low corresponds to the first logic signal A=0, and the second input signal being low corresponds to the second logic signal B=0. Therefore, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the third NMOS transistor N3 are all turned off. The second input signal B received at the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4. Simultaneously, the first input signal A received at the drain of the fifth PMOS transistor P5 also cannot be transmitted to the source of the fifth PMOS transistor P5. Therefore, the signal Yb output from the second signal output terminal of the mixed logic circuit is charged to a high level to indicate that the two input signals of the mixed logic circuit are logic signals at the same level. The signal Y output from the first signal output terminal of the mixed logic circuit is pulled down to a low level to indicate that the two input signals of the mixed logic circuit are not inverse signals.

[0035] When the first input signal is high and the second input signal is low, the high level of the first input signal corresponds to the first logic signal A=1, and the low level of the second input signal corresponds to the second logic signal B=0. The fifth PMOS transistor P5 and the third NMOS transistor N3 are both turned on, and the fourth PMOS transistor P4 is turned off. The second input signal B received at the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4. At the same time, the first input signal A received at the drain of the fifth PMOS transistor P5 is transmitted to the source of the fifth PMOS transistor P5. The third PMOS transistor N3 is turned on, and the drain of the third PMOS transistor N3 is pulled down and discharged to a low level. The first NMOS transistor N1 is turned off. The signal Y output from the first signal output terminal of the mixed logic circuit is charged to a high level to indicate that the two input signals of the mixed logic circuit are inverse signals. The signal Yb output from the second signal output terminal of the mixed logic circuit is low to indicate that the two input signals of the mixed logic circuit are not logic signals with the same level state.

[0036] When the first input signal is low and the second input signal is high, the low level of the first input signal corresponds to the first logic signal A=0, and the high level of the second input signal corresponds to the second logic signal B=1. The fourth PMOS transistor P4 and the third NMOS transistor N3 are both turned on, and the fifth PMOS transistor P5 is turned off. The second input signal B received at the drain of the fourth PMOS transistor P4 is transmitted to the source of the fourth PMOS transistor P4. At the same time, the first input signal A received at the drain of the fifth PMOS transistor P5 cannot be transmitted to the source of the fifth PMOS transistor P5. The third PMOS transistor N3 is turned on, and the drain of the third PMOS transistor N3 is pulled down and discharged to a low level. The first NMOS transistor N1 is turned off. The signal Y output from the first signal output terminal of the mixed logic circuit is charged to a high level to indicate that the two input signals of the mixed logic circuit are inverse signals. The signal Yb output from the second signal output terminal of the mixed logic circuit is low to indicate that the two input signals of the mixed logic circuit are not logic signals with the same level state.

[0037] In the foregoing embodiments, such as Figure 1As shown, the pull-up transistor network includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the voltage regulation module includes a first operational amplifier D1, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3; the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, and the drain of the third PMOS transistor P3 is connected to the drain of the third NMOS transistor N3; the connection between the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 is the first signal output terminal of the hybrid logic circuit, which is used to output a first output signal Y as a result of the aforementioned hybrid logic calculation. The source of the first PMOS transistor P1, the substrate of the first PMOS transistor P1, the source of the second PMOS transistor P2, the substrate of the second PMOS transistor P2, the source of the third PMOS transistor P3, and the substrate of the third PMOS transistor P3 are all connected to the power supply Vdd. The substrates of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are all grounded. The sources of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected to the same node, which is the current supply terminal of the current source structure. The non-inverting input terminal + of the first operational amplifier D1 is connected to the drain of the second NMOS transistor N2, and the inverting input terminal - of the first operational amplifier D1 is connected to the gate of the second NMOS transistor N2. The connection between the inverting input terminal - of the first operational amplifier D1 and the gate of the second NMOS transistor N2 is a signal input terminal of the voltage regulation module. The inverting input terminal - of the first operational amplifier D1 is used to receive the first voltage signal VL, and the signal input terminal of the voltage regulation module is configured to input a high level. The gates of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are all connected to the output terminal of the first operational amplifier D1. The output terminal of the first operational amplifier D1 outputs a voltage VP, which is used to simultaneously control... The first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are controlled to switch on and off. When the gate voltage of the second NMOS transistor N2 is high, the second NMOS transistor N2 is turned on. When the gate voltage of the second NMOS transistor N2 is greater than the drain voltage of the second NMOS transistor N2, the first operational amplifier D1 outputs a low level, turning on the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3. The gate of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3, and this connection terminal is the second signal output terminal of the mixed logic circuit. The second signal output terminal is used to output the second output signal Yb. If an analog signal is output, it can be used as the inverted signal of the first output signal Y.

[0038] like Figure 1As shown, the logic assignment module includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5; the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected, the gate of the fourth PMOS transistor P4 and the drain of the fifth PMOS transistor P5 are connected, and the drain of the fifth PMOS transistor P5 and the gate of the fourth PMOS transistor P4 are connected. Preferably, the substrates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both connected to a power supply Vdd; the gate of the fourth PMOS transistor P4 is the first signal input terminal of the hybrid logic circuit, used to receive a first logic signal A; the gate of the fifth PMOS transistor P5 is the second signal input terminal of the hybrid logic circuit, used to receive a second logic signal B, thus the logic assignment module becomes a 2-input logic circuit; the connection between the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 is the signal output terminal of the logic assignment module, and the gate of the third NMOS transistor N3 is connected to the signal output terminal of the logic assignment module. In conjunction with the foregoing embodiments, the logic assignment module composed of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a first output signal Y at the drain of the first NMOS transistor N1, corresponding to the XOR logic result of the first logic signal A and the second logic signal B; the logic assignment module composed of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a second output signal Yb at the drain of the third NMOS transistor N3, corresponding to the XOR logic result of the first logic signal A and the second logic signal B. As can be seen from the foregoing embodiments, the hybrid logic circuit is equivalent to a composite gate logic circuit composed of XOR gates and XNOR gates.

[0039] like Figure 1 As shown, the current source structure includes a fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is the signal input terminal of the current source structure, used to connect to the second voltage signal VN. This is generally achieved by biasing a simple current mirror, enabling the fourth NMOS transistor N4 to provide a constant current source. The signal input terminal of the current source structure is configured to input a high level to turn on the fourth NMOS transistor N4, ensuring that the current source structure forms a constant current source. The sources of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are all connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 and its substrate are both grounded.

[0040] This invention also discloses a chip comprising the hybrid logic circuit described in the foregoing embodiments. When a first input signal A is input to the first signal input terminal of the hybrid logic circuit, and a second input signal B is input to the second signal input terminal of the hybrid logic circuit, the chip is configured to execute the control method described above, thereby outputting XOR and XNOR logic results. Furthermore, during the image information training process of an artificial intelligence neural network model, using the chip disclosed in this invention to perform small-scale XOR calculations can ensure the processing power of the chip containing the hybrid logic circuit with fewer input ports and fewer MOS transistors.

[0041] Preferably, the first signal input terminal, the second signal input terminal, the second signal output terminal, and the first signal output terminal of the hybrid logic circuit can all be configured as pins of the chip for receiving external high and low levels; the signal input terminal of the voltage regulation module and the signal input terminal of the current source structure can both be configured as pins of the chip for connecting to the corresponding constant signal source.

[0042] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

Claims

1. A hybrid logic circuit, characterized in that, The hybrid logic circuit includes a logic assignment module, a voltage regulation module, a pull-up transistor network, and a current source structure; The logic assignment module includes a fourth PMOS transistor and a fifth PMOS transistor; The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth PMOS transistor is the first signal input terminal of the hybrid logic circuit, used to receive the first logic signal. The gate of the fifth PMOS transistor is the second signal input terminal of the hybrid logic circuit, used to receive the second logic signal; The connection between the source of the fourth PMOS transistor and the source of the fifth PMOS transistor is the signal output terminal of the logic assignment module, and the gate of the third NMOS transistor is connected to the signal output terminal of the logic assignment module. The voltage regulation module includes a third NMOS transistor; The logic assignment module composed of the fourth PMOS transistor and the fifth PMOS transistor outputs a first output signal at the drain of the first NMOS transistor, which corresponds to the XOR logic result of the first logic signal and the second logic signal; the logic assignment module composed of the fourth PMOS transistor and the fifth PMOS transistor outputs a second output signal at the drain of the third NMOS transistor, which corresponds to the XOR logic result of the first logic signal and the second logic signal. The pull-up transistor network includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; The voltage regulation module also includes a first operational amplifier, a first NMOS transistor, and a second NMOS transistor; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor; the connection point between the drain of the first PMOS transistor and the drain of the first NMOS transistor is the first signal output terminal of the mixed logic circuit. The source, substrate, source, substrate, and third PMOS transistors are all connected to a power source. The substrates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected to the same node and then connected to the current source structure. The non-inverting input of the first operational amplifier is connected to the drain of the second NMOS transistor, and the inverting input of the first operational amplifier is connected to the gate of the second NMOS transistor; wherein, the inverting input of the first operational amplifier is the signal input of the voltage regulation module. The gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the output of the first operational amplifier. The gate of the first NMOS transistor is connected to the drain of the third NMOS transistor, and this connection point is the second signal output point of the hybrid logic circuit. The current source structure includes a fourth NMOS transistor, and the gate of the fourth NMOS transistor is the signal input terminal of the current source structure. The source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor and the substrate of the fourth NMOS transistor are both grounded.

2. The hybrid logic circuit according to claim 1, characterized in that, The first signal input terminal of the hybrid logic circuit is connected to a first input signal, and the second signal input terminal of the hybrid logic circuit is connected to a second input signal. When the second input signal is the inverted signal of the first input signal, the third NMOS transistor is turned on.

3. A control method based on the hybrid logic circuit according to any one of claims 1 to 2, characterized in that, The control method includes: A first input signal is input to the first signal input terminal of the hybrid logic circuit, and a second input signal is input to the second signal input terminal of the hybrid logic circuit at the same time; When the second input signal and the first input signal are different logic signals, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level. When the second input signal is the same logic signal as the first input signal, the first signal output terminal of the mixed logic circuit outputs a low level, and the second signal output terminal of the mixed logic circuit outputs a high level.

4. The control method according to claim 3, characterized in that, when both the first input signal and the second input signal are high level, the second signal output terminal of the hybrid logic circuit outputs a high level to indicate that the two input signals of the hybrid logic circuit are logic signals with the same level state, and the first signal output terminal of the hybrid logic circuit outputs a low level to indicate that the two input signals of the hybrid logic circuit are not inverse signals. When both the first input signal and the second input signal are low, the second signal output terminal of the mixed logic circuit outputs a high level, and the first signal output terminal of the mixed logic circuit outputs a low level. When the first input signal is high and the second input signal is low, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level. When the first input signal is low and the second input signal is high, the first signal output terminal of the mixed logic circuit outputs a high level, and the second signal output terminal of the mixed logic circuit outputs a low level.

5. The control method according to claim 3, wherein the signal input terminal of the voltage regulation module is configured to input a high level; and the signal input terminal of the current source structure is configured to input a high level.

6. A chip, characterized in that, The chip includes the hybrid logic circuitry of any one of claims 1 to 2 and is configured to perform the control method of any one of claims 3 to 5.

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