A multiplier

Abstract

A multiplier (500) is provided for simultaneously performing multiple low-bit-width multiplication operations. The multiplier (500) includes a multiplier input (550) receiving two low-bit-width multipliers, a multiplicand input (560) receiving two low-bit-width multiplicands, a masking circuit (540) performing masking processing on each low-bit-width multiplier, and a multiplication operation circuit (502) multiplying the masked result by the multiplicands. When the sum of the bit widths of the multipliers is less than that of the multiplier input (550) and the sum of the bit widths of the multiplicands is less than that of the multiplicand input (560), by performing masking processing on each low-bit-width multiplier, the multiplier (500) can perform two low-bit-width multiplication operations separately, improving the problem of wasted hardware resources caused by a single multiplier only being able to handle multiplication operations of one data format.

Description

Technical Field

[0001] This application relates to digital circuit technology, and more particularly to a multiplier. Background Technology

[0002] Convolutional Neural Networks (CNNs) have a wide range of applications in fields such as image and speech recognition. Whether it's training or inference, CNN hardware requires performing a large number of multiplication operations, which are typically performed on different data formats. For example, current mainstream processors or accelerators for implementing neural network computations can support 4-bit integers (integer 4, INT 4), 8-bit integers (integer 8, INT 8), or 16-bit floating-point numbers (flow point 16, FP16).

[0003] like Figure 1 The diagram shows a multiplier group 100 supporting different data bit widths, including an FP16 multiplier 110 for processing 16-bit floating-point numbers, an INT8 multiplier 120 for processing 8-bit integers, and two INT4 multipliers 130 and 140 for processing 4-bit integers. These four multipliers are connected in parallel, and the calculated results are output to an adder 150, which accumulates the results and calculates the final value. To accommodate 4-bit integer multiplication on top of 16-bit floating-point and 8-bit integer multiplication, the multiplier 100 introduces the INT4 multipliers 130 and 140, increasing the area by approximately 90% and power consumption by approximately 20%. While higher-bit-width multipliers can also handle lower-bit-width multiplication operations—for example, the FP16 multiplier 110 can handle a 4-bit integer multiplication—this approach wastes the resources of the FP16 multiplier, thus reducing the computational efficiency of the multiplier group 100. Summary of the Invention

[0004] This application provides a multiplier that can simultaneously perform multiple low-bit-width multiplication operations.

[0005] In a first aspect, embodiments of this application provide a multiplier, including a multiplier input terminal for receiving multiplier data, a multiplicand input terminal for receiving multiplicand data, a masking circuit for masking, and a multiplication operation circuit. The sum of the bit widths of the first multiplier and the second multiplier included in the multiplier data is less than the bit width of the multiplier data, i.e., less than the bit width of the multiplier input terminal. Similarly, the sum of the bit widths of the first multiplicand and the second multiplicand included in the multiplicand data is also less than the bit width of the multiplicand input terminal. The masking circuit performs masking processing on the multiplier data to mask the first multiplier and the second multiplier, respectively, to obtain a first masking result and a second masking result. The multiplication operation circuit multiplies the first masking result and the second masking result by the first multiplicand and the second multiplicand, respectively, to obtain two multiplied results.

[0006] The masking circuit in a multiplier can mask multiple low-bit-width multipliers, thus allowing the calculation of partial products for different multipliers. Therefore, the multiplier can adapt to multiplication operations with multiple low-bit-width multipliers and multiplicands of different data formats, improving upon the hardware resource waste caused by a single multiplier handling only one data format. Using a multiplier to implement multiplication operations with different data formats saves hardware area and power consumption.

[0007] In one possible implementation, the multiplication circuit described above includes a Booth encoder. This Booth encoder can be a Radix-4, Radix-8, or other mode-based Booth encoder. Using a Booth encoder to perform multiplication operations can reduce the hardware area of ​​the multiplier and save power.

[0008] In one possible implementation, the multiplication circuit further includes a partial product calculation circuit for calculating partial products based on the encoding results generated by the Booth encoder, and an accumulator for accumulating the multiple partial products generated by the partial product calculation circuit. Encoding the multiplicand, calculating the partial product of the mask results corresponding to the multiplicand, and finally accumulating the obtained partial products to perform the multiplication operation can further save hardware resources.

[0009] In one possible implementation, the Booth encoder includes multiple sub-encoders for Booth encoding the first multiplicand to obtain a first encoding result, and for Booth encoding the second multiplicand to obtain a second encoding result, wherein the encoding result can be one or more; the partial product calculation circuit is specifically used to calculate a first partial product of the first encoding result and the first mask result, and to calculate a second partial product of the second encoding result and the second mask result, wherein the number of partial products is the same as the number of encoding results; the accumulator is specifically used to accumulate the first partial product to obtain the result of multiplying the first multiplier and the first multiplicand, and to accumulate the second partial product to obtain the result of multiplying the second multiplier and the second multiplicand.

[0010] In one possible implementation, the multiplier further includes an adder for adding the result of multiplying the first multiplier and the first multiplicand obtained from the accumulator, and the result of multiplying the second multiplier and the second multiplicand. The adder can sum the results of each low-bit-width multiplication operation to achieve the function of convolution calculation.

[0011] In one possible implementation, the multiplier further includes shifters for shifting the results of the multiplication operations obtained from the accumulator. By shifting the multiplication results, the final calculation result can be obtained.

[0012] In one possible implementation, the data in the multiplicand input includes a first multiplicand located in the lower bits, a second multiplicand located in the higher bits, a 1-bit extension bit (0) inserted at the end of the least significant bit of the first multiplicand, and other bits in the multiplicand input that are set to 0, excluding the first multiplicand, the second multiplicand, and the extension bit. The multiplier data includes a first multiplier located in the lower bits, a second multiplier located in the higher bits, and other bits in the multiplier input that are set to 0, excluding the first and second multipliers. The position of the first multiplier in the multiplier input is the same as the position of the first multiplicand in the multiplicand input, and the position of the second multiplier in the multiplier input is the same as the position of the second multiplicand in the multiplicand input. Setting the other bits to 0 ensures that the encoding result of the 0 bits does not affect the subsequent partial product calculation and accumulation. Since the two multipliers and two multiplicands are in the same position, the accumulator does not require additional shift operations to align the partial products when accumulating them, thus saving hardware resources.

[0013] In one possible implementation, a 1-bit 0 interval is placed between the first and second multiplicands at the multiplicand input, and a 1-bit 0 interval is also placed between the first and second multipliers at the multiplier input. The multiplier further includes a selector for outputting the most significant bit of the first multiplicand to the most significant bit of the corresponding first sub-encoder, and outputting the data 0 to the least significant bit of the sub-encoder adjacent to the first sub-encoder that encodes idle bits, where the idle bits are the bits set to 0 between the first and second multiplicands. When the multiplicand and multiplier are stored in the multiplicand and multiplier inputs in the above manner, the selector can allocate valid data and 0, thereby enabling the sub-encoder to correctly encode the data in the multiplicand input.

[0014] In one possible implementation, the most significant bit of the first multiplicand and the least significant bit of the second multiplicand are adjacent in the multiplicand input, and the most significant bit of the first multiplier and the least significant bit of the second multiplier are also adjacent in the multiplier input. The multiplier further includes a selector for outputting the most significant bit of the first multiplicand to the most significant bit of the corresponding first sub-encoder and outputting 0 to the least significant bit of the corresponding second sub-encoder. The second sub-encoder is adjacent to the first sub-encoder and encodes the second multiplicand. When the multiplicand and multiplier are stored in the multiplicand and multiplier inputs in the above manner, the selector can allocate valid data and 0, thereby enabling the sub-encoders to correctly encode the data in the multiplicand input.

[0015] In one possible implementation, the aforementioned partial integrator circuit includes multiple first partial integrator circuits, multiple second partial integrator circuits, and multiple third partial integrator circuits. The multiple first partial integrator circuits are used to calculate multiple first partial products based on a first mask result, using multiple encoded results of a first multiplicand as control signals. The multiple second partial integrator circuits are used to calculate multiple second partial products based on a second mask result, using multiple encoded results of a second multiplicand as control signals. The multiple third partial integrator circuits are used to calculate multiple third partial products based on data in the multiplier input terminal, using idle bits as control signals, where idle bits are bits set to 0 in the multiplicand input terminal. Specifically, the accumulator is used to accumulate the multiple first partial products, the multiple second partial products, and the multiple third partial products.

[0016] In one possible implementation, the multiplier further includes a switch. This switch activates the mask circuit, shifter, and adder when closed, and disables the mask circuit when open, allowing the mask circuit, shifter, and adder to directly receive the data. By controlling the mask circuit, shifter, and adder with the switch, the multiplier can switch between two modes: multiple multiplication operations and a single multiplication operation, further enhancing its ability to handle multiplication operations.

[0017] In one possible implementation, the multiplier further includes a switch. This switch activates the masking circuit when closed and disables it when open, allowing the masking circuit to directly receive the data. By controlling the masking circuit with the switch, the multiplier can switch between multiple multiplication operations and a single multiplication operation mode, further enhancing its ability to handle multiplication operations.

[0018] In one possible implementation, the masking circuit includes two AND gates, used to perform masking processing on the multiplier data to mask the first multiplier and masking processing on the second multiplier, respectively, to output the two masking results. Using two AND gates to implement the masking circuit function can further simplify the circuit structure of the multiplier, save hardware resources, and reduce power consumption.

[0019] In one possible implementation, the first sub-encoder of the plurality of sub-encoders in the encoder is used to perform Booth encoding on the extended bits, LSB to (k-2)th bit data of the multiplicand input, and the i-th sub-encoder is used to perform Booth encoding on the i×(k-1)+1th bit to (i+1)×(k-1)+1th bit data of the multiplicand input, where k is the bit width of each sub-encoder, k≥2 and is an integer, and i≥2 and is an integer.

[0020] In one possible implementation, the multiplier further includes a selector for outputting the most significant bit of the first multiplicand to the most significant bit of the x-th sub-encoder and outputting 0 to the least significant bit of the (x+1)-th sub-encoder, where the x-th sub-encoder is the most significant bit of the first multiplicand. to( A sub-encoder that encodes using -k+1) bits.

[0021] In one possible implementation, the multiplier further includes a selector for: outputting 0 to the most significant bit of the x-th sub-encoder, and outputting the least significant bit of the second multiplicand to the least significant bit of the (x+1)-th sub-encoder, wherein the x-th sub-encoder is the most significant bit of the first multiplicand. to( The sub-encoder encodes the (-k+1) bits, and the (x+1)th sub-encoder is the least significant bit of the second multiplicand. to( A sub-encoder that encodes using -k+1) bits.

[0022] Secondly, embodiments of this application provide a multiplication calculation method applied to a multiplier, the multiplier including a multiplier input terminal and a multiplicand input terminal. The multiplication calculation method includes: receiving multiplier data, wherein the multiplier data includes a first multiplier and a second multiplier, the sum of the bit widths of the first multiplier and the second multiplier being less than the bit width of the multiplier data; performing a masking process on the multiplier data to mask the second multiplier to obtain a first masking result, and performing a masking process on the multiplier data to mask the first multiplier to obtain a second masking result; receiving a first multiplicand and a second multiplicand, wherein the sum of the bit widths of the first multiplicand and the second multiplicand being less than the bit width of the multiplicand input terminal; performing a multiplication operation on the first masking result and the first multiplicand to obtain a result of multiplying the first multiplier and the first multiplicand, and performing a multiplication operation on the second masking result and the second multiplicand to obtain a result of multiplying the second multiplier and the second multiplicand.

[0023] The masking circuit in a multiplier can mask multiple low-bit-width multipliers, thus allowing the calculation of partial products for different multipliers. Therefore, the multiplier can adapt to multiplication operations with multiple low-bit-width multipliers and multiplicands of different data formats, improving upon the hardware resource waste caused by a single multiplier handling only one data format. Using a multiplier to implement multiplication operations with different data formats saves hardware area and power consumption.

[0024] In one possible implementation, the steps of multiplying the first mask result and the first multiplicand to obtain the product of the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the product of the second multiplier and the second multiplicand, include: performing Booth encoding on the first multiplicand and the second multiplicand. Using a Booth encoder to implement the multiplication operation can reduce the hardware area of ​​the multiplier and save power consumption.

[0025] In one possible implementation, the steps of multiplying the first mask result and the first multiplicand to obtain the product of the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the product of the second multiplier and the second multiplicand, further include: calculating partial products based on the encoding result generated by the Booth encoding to obtain multiple partial products; and accumulating the multiple partial products. Encoding the multiplicand, calculating the partial products of the mask results corresponding to the multiplicand, and finally accumulating the partial products to implement the multiplication operation can further save hardware resources.

[0026] In one possible implementation, the step of performing Booth encoding on the first and second multiplicands includes: Booth encoding the first multiplicand using multiple sub-encoders to obtain at least one first encoding result, and Booth encoding the second multiplicand to obtain at least one second encoding result; the step of calculating partial products based on the encoding results generated by Booth encoding to obtain multiple partial products includes: calculating at least one first partial product of at least one first encoding result and a first mask result, and calculating at least one second partial product of at least one second encoding result and a second mask result; and the step of accumulating the multiple partial products includes: accumulating at least one first partial product to obtain a result of multiplying the first multiplier and the first multiplicand, and accumulating at least one second partial product to obtain a result of multiplying the second multiplier and the second multiplicand.

[0027] In one possible implementation, the multiplication calculation method further includes: adding the result of multiplying the first multiplier and the first multiplicand obtained from the accumulator, and adding the result of multiplying the second multiplier and the second multiplicand. Adding the results of each low-bit-width multiplication operation enables the convolution calculation function.

[0028] In one possible implementation, the multiplication calculation method further includes: shifting the result of multiplying the first multiplier and the first multiplicand obtained by the accumulator, and shifting the result of multiplying the second multiplier and the second multiplicand, respectively.

[0029] In one possible implementation, the data in the multiplicand input includes a first multiplicand located in the lower bits of the multiplicand input, a second multiplicand located in the higher bits of the multiplicand input, a 1-bit extension bit (0) inserted at the end of the least significant bit of the first multiplicand, and other bits in the multiplicand input that are set to 0, excluding the first multiplicand, the second multiplicand, and the extension bit. The multiplier data includes: a first multiplier located in the lower bits of the multiplier input, a second multiplier located in the higher bits of the multiplicand input, and other bits in the multiplier input that are set to 0, excluding the first and second multipliers. The position of the first multiplier in the multiplier input is the same as the position of the first multiplicand in the multiplicand input, and the position of the second multiplier in the multiplier input is the same as the position of the second multiplicand in the multiplicand input. Setting the other bits to 0 ensures that the encoding result of the 0 bits does not affect the subsequent partial product calculation and accumulation. The two multipliers and two multiplicands are in the same position, so that the accumulator does not need additional shift operations to align the partial products when accumulating them, thus saving hardware resources.

[0030] In one possible implementation, the first multiplicand and the second multiplicand are separated by at least 1 bit of 0, and the first multiplier and the second multiplier are separated by at least 1 bit of 0. The multiplication calculation method further includes: outputting the most significant bit of the first multiplicand to the most significant bit of the corresponding first sub-encoder, and outputting the data 0 to the least significant bit of the sub-encoder adjacent to the first sub-encoder that encodes idle bits, where idle bits are the bits set to 0 between the first multiplicand and the second multiplicand. When the multiplicand and multiplier are stored in the multiplicand input and multiplier input in the above manner, the allocation of valid data and 0 can be achieved, thereby enabling the sub-encoder to correctly encode the data in the multiplicand input.

[0031] In one possible implementation, the most significant bit of the first multiplicand and the least significant bit of the second multiplicand are adjacent, and the most significant bit of the first multiplier and the least significant bit of the second multiplier are adjacent. The multiplication calculation method further includes: outputting the most significant bit of the first multiplicand to the most significant bit of the corresponding first sub-encoder, and outputting the data 0 to the least significant bit of the corresponding second sub-encoder. The second sub-encoder is an encoder adjacent to the first sub-encoder that encodes the second multiplicand. When the multiplicand and multiplier are stored in the multiplicand input and multiplier input in the above manner, the allocation of valid data and 0 can be achieved, thereby enabling the sub-encoder to correctly encode the data in the multiplicand input.

[0032] In one possible implementation, the multiplication calculation method further includes using a switch to perform masking when the switch is closed and to disable masking when the switch is open. This switch control allows the multiplier to switch between multiple multiplication operations and a single multiplication operation mode, further enhancing the multiplier's ability to handle multiplication operations.

[0033] In one possible implementation, the steps of masking the multiplier data to obtain a first mask result and masking the multiplier data to obtain a second mask result include: using two AND gates to perform masking processes on the multiplier data for both the first and second multiplier functions, respectively, to output two mask results. Using two AND gates to implement the masking function further simplifies the circuit structure of the multiplier, saves hardware resources, and reduces power consumption.

[0034] Thirdly, embodiments of this application provide a data processing system, including an encoder for encoding a first multiplicand and a second multiplicand to obtain multiple encoded results, wherein the sum of the bit widths of the first multiplicand and the second multiplicand is less than the bit width of the multiplicand input terminal of the encoder; and multiple multipliers, wherein each multiplier includes: a masking circuit for masking the first multiplier and the second multiplier respectively to obtain two masked results, wherein the sum of the bit widths of the first multiplier and the second multiplier is less than the bit width of the multiplier input terminal of each multiplier; a partial product calculation circuit for calculating multiple partial products based on the two masked results corresponding to the multiple encoded results, using the multiple encoded results as control signals respectively; and an accumulator for accumulating the multiple partial products to obtain an accumulated result.

[0035] Since multiple multipliers can share the encoding results of the encoder, the multiplier no longer needs to use the encoder for repeated encoding, which simplifies the internal hardware design of the multiplier, reduces hardware complexity, and improves the processing efficiency of the multiplier due to the simplified processing steps.

[0036] In one possible implementation, each multiplier further includes a multiplier input for receiving a first multiplier and a second multiplier; wherein the masking circuit includes two masks for performing masking processing on the data in the multiplier input by AND gates to mask the first multiplier and mask the second multiplier, respectively, to output the first masking result and the second masking result.

[0037] In one possible implementation, the encoder includes a multiplicand input for receiving a first multiplicand and a second multiplicand; wherein the encoder includes a plurality of sub-encoders for performing Booth encoding on the data in the multiplicand input.

[0038] In one possible implementation, the partial product calculation circuit includes a plurality of first partial product circuits and a plurality of second partial product circuits, wherein: the plurality of first partial product circuits are used to calculate a plurality of first partial products based on a first mask result, using a plurality of encoded results of a first multiplicand as control signals respectively; and the plurality of second partial product circuits are used to calculate a plurality of second partial products based on a second mask result, using a plurality of encoded results of a second multiplicand as control signals respectively.

[0039] In one possible implementation, the multiplicand input is further configured to: store the first multiplicand in the low-order bits of the multiplicand input, store the second multiplicand in the high-order bits of the multiplicand input, insert a 1-bit extension bit 0 at the end of the least significant bit of the first multiplicand, and set the idle bits to 0, where the idle bits are the bits in the multiplicand input other than the first multiplicand, the second multiplicand, and the extension bit; the partial product calculation circuit further includes multiple third partial product sub-circuits, each configured to calculate multiple third partial products based on the data in the multiplier input, using the idle bits as control signals.

[0040] In one possible implementation, the first sub-encoder among the plurality of sub-encoders is used to perform Booth encoding on the extended bits, LSB to (k-2)th bits of the multiplicand input, and the ith sub-encoder is used to perform Booth encoding on the i×(k-1)+1th bits to (i+1)×(k-1)+1th bits of the multiplicand input, where k is the bit width of each sub-encoder, k≥2 and is an integer, and i≥1 and is an integer.

[0041] In one possible implementation, the accumulator is used to accumulate a plurality of first partial products, a plurality of second partial products, and a plurality of third partial products, respectively.

[0042] In one possible implementation, the multiplicand input is further configured to: store the first multiplicand in the low-order bits of the multiplicand input, store the second multiplicand in the high-order bits of the multiplicand input, and such that the first multiplicand and the second multiplicand are separated by at least 1 bit of 0; the multiplier input is further configured to: store the first multiplier in the low-order bits of the multiplier input, store the second multiplicand in the high-order bits of the multiplicand input, and such that the first multiplier and the second multiplicand are separated by at least 1 bit of 0, wherein the positions where the first multiplier and the second multiplier are stored in the multiplier input are the same as the positions where the first multiplicand and the second multiplicand are stored in the multiplicand input.

[0043] In one possible implementation, the multiplier further includes a selector, which is configured to: output the most significant bit of the first multiplicand to the most significant bit of the x-th sub-encoder, and output 0 to the least significant bit of the (x+1)-th sub-encoder, where the x-th sub-encoder is the most significant bit of the first multiplicand. to( A sub-encoder that encodes using -k+1) bits.

[0044] In one possible implementation, the multiplier further includes an adder for adding the result of a plurality of first-part cumulative additions and a plurality of second-part cumulative additions.

[0045] In one possible implementation, the multiplicand input is further configured to: store the first multiplicand in the low-order bits of the multiplicand input, store the second multiplicand in the high-order bits of the multiplicand input, and make the least significant bit of the second multiplicand adjacent to the most significant bit of the first multiplicand; the multiplier input is further configured to: store the first multiplier in the high-order bits of the multiplier input, store the second multiplier in the low-order bits of the multiplier input, and make the least significant bit of the first multiplier adjacent to the most significant bit of the second multiplier, wherein the position where the first multiplier is stored in the multiplier input is the same as the position where the second multiplicand is stored in the multiplicand input, and the position where the second multiplier is stored in the multiplier input is the same as the position where the first multiplicand is stored in the multiplicand input.

[0046] In one possible implementation, the multiplier further includes a selector, which is configured to: output 0 to the most significant bit of the x-th sub-encoder, and output the least significant bit of the second multiplicand to the least significant bit of the (x+1)-th sub-encoder, where the x-th sub-encoder is the most significant bit of the first multiplicand. to( The sub-encoder encodes (-k+1) bits, and the (x+1)th sub-encoder is the least significant bit of the second multiplicand. to( A sub-encoder that encodes using -k+1) bits.

[0047] In one possible implementation, the multiplier further includes a shifter for shifting the result of a plurality of first-part cumulative additions and a plurality of second-part cumulative additions.

[0048] In one possible implementation, each partial product sub-circuit in the partial product calculation circuit is specifically used for: multiple first partial product sub-circuits being specifically used for multiplying multiple encoded results of the first multiplicand with the first mask result respectively to calculate multiple first partial products; multiple first partial product sub-circuits being specifically used for multiplying multiple encoded results of the second multiplicand with the second mask result respectively to calculate multiple second partial products; and multiple third partial product sub-circuits being specifically used for multiplying multiple encoded results of the idle bits with the data received at the multiplier input terminal respectively to calculate multiple third partial products.

[0049] In one possible implementation, the multiplier further includes a switch for activating a mask circuit, selector, shifter, or adder when it is in an on state.

[0050] In one possible implementation, the first multiplicand and the second multiplicand are convolution kernel data, and the first multiplier and the second multiplier are feature layer data; or, the first multiplicand and the second multiplicand are feature layer data, and the first multiplier and the second multiplier are convolution kernel data.

[0051] In one possible implementation, the multiple multipliers further include multiple storage units, wherein one storage unit of every two multipliers is used to receive multiple encoded results, and the other storage unit is used to read multiple encoded results.

[0052] Fourthly, embodiments of this application provide a multiplication processing system that reads a configuration file from a memory coupled thereto, such that the multiplication processing system can be configured as a multiplier as described in any possible implementation of the first aspect, or as a data processing system as described in any possible implementation of the third aspect.

[0053] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any of the possible implementations of the second aspect.

[0054] In a sixth aspect, embodiments of this application provide a computer program that includes instructions that, when executed by a computer, cause the computer to perform the method as described in any of the possible implementations of the second aspect. Attached Figure Description

[0055] Figure 1 This is a multiplier group in the prior art.

[0056] Figure 2 This is a schematic diagram illustrating a convolution processing principle in an embodiment of this application.

[0057] Figure 3 This is a data processing system for convolution processing in an embodiment of this application.

[0058] Figure 4 This is a multiplier in one embodiment of this application.

[0059] Figure 5 This is another multiplier in the embodiments of this application.

[0060] Figure 6 This is another specific multiplier in the embodiments of this application.

[0061] Figure 7 This is another, more specific, multiplier in the embodiments of this application.

[0062] Figure 8This is yet another specific multiplier in the embodiments of this application.

[0063] Figure 9 This is yet another more specific multiplier in the embodiments of this application.

[0064] Figure 10 This is a data processing system described in an embodiment of this application.

[0065] Figure 11 This is a multiplication calculation method in the embodiments of this application.

[0066] Figure 12 This is a multiplication processing system as described in the embodiments of this application. Detailed Implementation

[0067] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0068] like Figure 2 This diagram illustrates the convolutional processing principle of a Convolutional Neural Network (CNN). Figure 2 In this process, for a feature map (including convolutional kernel data and feature layer data), the convolutional neural network performs convolution processing on the convolutional kernel data A1, A2, ..., An and the feature layer data w1, w2, and w3. Specifically, for each convolutional kernel, it starts from the first pixel of the feature map and moves pixel by pixel along the row direction. When it reaches the end of the row, it moves down one pixel in the column direction, while returning to the starting position in the row direction, and repeats the above row-direction movement process until all pixels in the feature map have been traversed.

[0069] like Figure 3The diagram shows a data processing system 300 for convolutional processing in a convolutional neural network (CNN), including multipliers 302, 304, 306, and 308 for multiplication calculations. Multiplier 302 receives multiplier data stored in multiplier register 312 and multiplicand data stored in multiplicand register 322 and performs multiplication. Multiplier 304 receives multiplier data stored in multiplier register 314 and multiplicand data stored in multiplicand register 324 and performs multiplication. Multiplier 306 receives multiplier data stored in multiplier register 316 and multiplicand data stored in multiplicand register 326 and performs multiplication. Multiplier 308 receives multiplier data stored in multiplier register 318 and multiplicand data stored in multiplicand register 328 and performs multiplication. Adder 332 in data processing system 300 adds the multiplication results obtained by multipliers 302 and 304; adder 334 in data processing system 300 adds the multiplication results obtained by multipliers 306 and 308. Finally, adder 336 in data processing system 300 adds the results obtained by adders 332 and 334 again to obtain the final result. Since data processing system 300 can perform a large number of multiplication and accumulation operations, it can be used for convolution processing of convolutional neural networks (CNNs). In one embodiment, convolution kernel data can be stored in the multiplier registers, and feature layer data can be stored in the multiplicand registers; in another embodiment, convolution kernel data can be stored in the multiplicand registers, and feature layer data can be stored in the multiplier registers.

[0070] The above multiplier can be as follows: Figure 4 The multiplier 400 shown includes an encoder 410, a partial product calculation circuit 420, and an accumulator 430. Figure 4 Let's take an example where both the multiplier and multiplicand input to multiplier 400 are 12 bits. In multiplier 400, firstly, a 1-bit 0 is inserted at the end of the 12-bit multiplicand (in... Figure 4 (represented by x in the original text) to expand the multiplicand to 13 bits. Next, the expanded 13-bit multiplicand is encoded. Specifically, encoder 410 includes, as shown in the original text. Figure 4 The sub-encoders 0, 1, 2, 3, 4, and 5 shown are used, where each sub-encoder encodes every 3 bits of data in the expanded multiplicand at 2-bit intervals. For example, sub-encoder 0 encodes the 0s inserted at the end of the multiplicand (in... Figure 4The encoding is done by sub-encoder 1, which encodes bits 1, 2, and 3, and sub-encoder 2 encodes bits 3, 4, and 5. (The text then repeats the encoding steps.) Figure 4 As shown, and so on. The LSB, 1st bit, and 2nd bit mentioned above all refer to... Figure 4 The data shown is in the bits before expansion.

[0071] The sub-encoder can encode each 3 bits of data using Booth encoding. Booth encoding can follow the rules described in Table 1:

[0072] Table 1

[0073]

[0074] Where i is an integer. X represents the multiplicand, consisting of 3 consecutive bits. Under the rules described in the table above, the encoded result can also be represented as:

[0075] ( )X

[0076] For example, if the multiplicand is represented in binary as 010010111011, then the expanded multiplicand is represented as 0100101110110. Sub-encoder 0 encodes the lower 3 bits of the expanded multiplicand, i.e., 110, according to the rules described in the table above, resulting in an encoding result of -X; sub-encoder 1 encodes 101 according to the rules described in the table above, resulting in an encoding result of -X; sub-encoder 2 encodes 111 according to the rules described in the table above, resulting in an encoding result of 0; sub-encoder 3 encodes 101 according to the rules described in the table above, resulting in an encoding result of -X; sub-encoder 4 encodes 001 according to the rules described in the table above, resulting in an encoding result of X; sub-encoder 5 encodes 010 according to the rules described in the table above, resulting in an encoding result of X. The encoding process is shown in Table 2.

[0077] Table 2

[0078]

[0079] Partial product calculation circuit 420 includes, for example: Figure 4The partial integrator circuits 0, 1, 2, 3, 4, and 5 shown each receive the encoding result generated by the corresponding sub-encoder and output the corresponding partial product based on the received multiplier. Specifically, each partial integrator circuit uses the received encoding result as the control signal and determines the output partial product based on the input multiplier. For example, partial integrator circuit 0 uses the encoding result -X as the control signal and the multiplier as the input, so the output partial product is -X; partial integrator circuit 1 uses the encoding result -X as the control signal and the multiplier as the input, so the output partial product is -X; partial integrator circuit 2 uses the encoding result 0 as the control signal and the multiplier as the input, so the output partial product is 0, and so on. X in the above partial products represents a 12-bit multiplier.

[0080] Accumulator 430 receives multiple partial products generated by the aforementioned partial product sub-circuits and accumulates these partial products according to the weight of the bits of the multiplicand corresponding to each partial product. For example, the partial products generated by partial product sub-circuits 0 to 5 are -X, -X, 0, -X, X, and X, respectively. Since the multiplicands are encoded with 2-bit intervals, the weights of each adjacent partial product sub-circuit are 4 times, meaning the partial product generated by partial product circuit 0 is multiplied by 4. (-X) is accumulated, and the partial product generated by partial integrator circuit 1 is... (-X) is accumulated, and the partial product generated by the partial integrator circuit 2 is... × (0) is accumulated, and the partial product generated by the partial integrator circuit 3 is... (-X) is accumulated, and the partial product generated by the partial integrator circuit 4 is... (X) is accumulated, and the partial product generated by the partial integrator circuit 5 is... (X) is accumulated. The final accumulated result is the product of the multiplier and the multiplicand. The above accumulation process can be expressed as:

[0081] ( +-X)+0)-X)-X=1211X

[0082] like Figure 4The multiplier 400 shown can handle data in different formats, such as INT4 (4-bit integer), INT8 (8-bit integer), or FP16 (16-bit floating-point number). However, when using a multiplier with a higher bit width to process low-bit-width multiplication operations, a single multiplier 400 cannot handle multiple low-bit-width multiplication operations simultaneously, thus failing to meet the performance requirements of the multiplier. For example, when the multiplier has a bit width of 16 bits, it can handle one INT4, INT8, or FP16 multiplication operation, but it cannot handle two INT8 multiplication operations or two INT4 multiplication operations simultaneously. Therefore, when it is necessary to process two INT8 multiplication operations or two INT4 multiplication operations simultaneously, two multipliers are required, which wastes multiplier resources and slows down the hardware's computation speed.

[0083] like Figure 5 The diagram shows a multiplier 500 provided in an embodiment of this application, which can be used for, for example... Figure 3 This is illustrated in any multiplier of the data processing system 300. The multiplier 500 includes a multiplier input 550, a multiplicand input 560, a multiplication operation circuit 502, and a mask circuit 540. The multiplier input 550 receives multiplier data input to the multiplier 500. This multiplier data can be two or more multiplier data, and the sum of the bit widths of these multiplier data is less than the bit width of the multiplier input 550. For example, the multiplier input 550 has a bit width of 32 bits, and the aforementioned multiplier data consists of four 6-bit multipliers. Similarly, the multiplicand input 560 receives multiplicand data input to the multiplier 500. This multiplicand data can be two or more multiplicand data, and the sum of the bit widths of these multiplicand data is less than the bit width of the multiplicand input 560.

[0084] When the sum of the bit widths of the multiple multipliers involved in the multiplication operation is less than the bit width of the multiplier input terminal 550 of the multiplier 500, and the sum of the bit widths of the multiple multiplicands involved in the multiplication operation is less than the bit width of the multiplicand input terminal 560 of the multiplier 500, the multiplier 500 can be used to perform multiple sets of low-bit-width multiplication operations simultaneously. The embodiments provided in this application all use the multiplier 500 processing two sets of low-bit-width multiplication operations as an example to illustrate the specific structure and function of the multiplier 500. For example, in the embodiments of this application, the first multiplicand b0 and the first multiplier a0 are multiplied, and the second multiplicand b1 and the second multiplier a1 are multiplied. However, it is readily understood that the multiplier 500 provided according to the embodiments of this application can also implement more than two sets of low-bit-width multiplication operations. The aforementioned multiplication of the first multiplicand b0 and the first multiplier a0, and the multiplication of the second multiplicand b1 and the second multiplier a1 can be data in different formats, such as INT4, INT8, or FP16, or other data formats. It is important to note that in this application, "low bit width" and "high bit width" are two relative concepts. For example, if the bit width of the multiplier input or multiplicand input of a multiplier is greater than twice the bit width of the multiplier or multiplicand, then the bit width of the multiplier is the "high bit width," and the bit width of the multiplier or multiplicand is the "low bit width." Furthermore, in this application, "multiplier" and "multiplicand" are relative concepts. For example, convolution kernel data can be input as a multiplier to multiplier 500, and feature layer data can be input as a multiplicand to multiplier 500; convolution kernel data can also be input as a multiplicand to multiplier 500, and feature layer data as a multiplier to multiplier 500.

[0085] The masking circuit 540 in multiplier 500 is used to mask the multiplier data to obtain two masking results. Specifically, the masking circuit 540 masks the multiplier data to mask the second multiplier a1, thus obtaining a first masking result representing the first multiplier a0. Similarly, the masking circuit 540 masks the multiplier data to mask the first multiplier a1, thus obtaining a second masking result representing the second multiplier a1. For example, if the multiplier data is 12 bits 110100000101, where the lower four bits 0101 represent the first multiplier and the higher four bits 1101 represent the second multiplier, then the first masking result is 000000000101, and the second masking result is 110100000000.

[0086] The multiplication circuit 502 is used to multiply the first mask result and the first multiplicand b0 to obtain their product, and to multiply the second mask result and the second multiplicand b1 to obtain their product.

[0087] The masking circuit 540 in multiplier 500 can mask multiple low-width multipliers, thereby calculating partial products for different multipliers separately. Therefore, multiplier 500 can adapt to multiplication operations with multiple low-width multipliers and multiple low-width multiplicands of different data formats, improving upon the hardware resource waste caused by a single multiplier only handling multiplication operations of one data format. Using multiplier 500 to implement multiplication operations of different data formats saves hardware area occupied by the multiplier and also reduces power consumption.

[0088] like Figure 6 The diagram shows a specific multiplier 600 provided in an embodiment of this application. The multiplier 600 includes, as follows: Figure 5 The diagram shows a multiplication circuit 502, a multiplier input terminal 550, a multiplicand input terminal 560, and a mask circuit 540. Specifically, the multiplication circuit may include an encoder 510, a partial product calculation circuit 520, and an accumulator 530.

[0089] Specifically, the encoder 510 in the multiplier 500 is used to encode the first multiplicand b0 and the second multiplicand b1 to obtain a first encoded result and a second encoded result, respectively. Both the first and second encoded results can be multiple encoded results. The encoder 510 can use Booth encoding, meaning it can be a Booth encoder. In one embodiment, the encoder 510 can encode the first multiplicand b0 and the second multiplicand b1 using a radix-4 method, that is, encoding every 3 bits of data at 2-bit intervals according to the rules described in Table 1 above. In another embodiment, the encoder 510 can encode the first multiplicand b0 and the second multiplicand b1 using a radix-8 method, that is, encoding every 4 bits of data at 3-bit intervals according to a preset rule. The encoder 510 can also use other methods, such as radix-16. For ease of description, this application uses the radix-4 method as an example to illustrate the working principle of the encoder 510.

[0090] The partial product calculation circuit 520 is used to calculate partial products based on the above-mentioned encoding results. Specifically, the partial product calculation circuit 520 uses the first encoding result and the second encoding result obtained by the encoder 510 as control signals, respectively, and calculates multiple partial products based on the two mask results corresponding to these encoding results. That is, it calculates the first partial product between the first encoding result and the first mask result, and calculates the second partial product between the second encoding result and the second mask result. The partial product calculation circuit 520 can determine the relationship between the corresponding encoding result and the corresponding partial product based on the above-mentioned control signals. For example, when the control signal indicates that the encoding result is -X, the output partial product is the corresponding mask result of -1 times.

[0091] The accumulator 530 is used to accumulate multiple partial products (such as the first partial product and the second partial product mentioned above) obtained by the partial product calculation circuit 520 to obtain the accumulated result. Since the partial product calculation circuit 520 performs partial product calculations on multiple encoding results to obtain multiple partial products, the accumulator 300 accumulates the above multiple partial products to obtain the final result.

[0092] In one embodiment, the multiplier input 550 may include storage circuitry, such as a register or register group, for storing multiplier data including the first multiplier a0 and the second multiplier a1. Correspondingly, the multiplicand input 560 is used to receive the first multiplicand b0 and the second multiplicand b1. In one embodiment, the multiplier input 660 may include storage circuitry, such as a register or register group, for storing the first multiplicand b0 and the second multiplicand b1.

[0093] In one embodiment, the first multiplier a0 and the second multiplier a1 are stored in the same positions in the multiplier input 550 as the first multiplicand b0 and the second multiplicand b1 are stored in the same positions in the multiplicand input 560. For example, the first multiplier a0 and the second multiplier a1 are stored in the 3rd bit and the 4th to 7th bits of the LSB in the storage circuit of the multiplier input 550, respectively, and the first multiplicand b0 and the second multiplicand b1 are also stored in the 3rd bit and the 4th to 7th bits of the LSB in the storage circuit of the multiplicand input 560, respectively. In another embodiment, the first multiplier a0 is stored in the same position in the multiplier input 550 as the second multiplicand b1 is stored in the same position in the multiplicand input 560, and the second multiplier a1 is stored in the same position in the multiplier input 550 as the first multiplicand b0 is stored in the same position in the multiplicand input 560. For example, the first multiplier a0 and the second multiplier a1 are stored in the LSB~3rd bit and LSB~7th bit of the storage circuit of the multiplier input terminal 550, respectively, and the first multiplicand b0 and the second multiplicand b1 are stored in the LSB~7th bit and LSB~3rd bit of the storage circuit of the multiplicand input terminal 560, respectively. The LSB, 1st bit, etc. mentioned above all refer to the data in the bit position before expansion.

[0094] The masking circuit 540 may include two masks, used to mask the multiplier data by applying data from the AND gate at the multiplier input 650 to mask the first multiplier a0 and the second multiplier a1, respectively, to output the first masking result and the second masking result. In one embodiment, the masking circuit 540 may include more than two masks. It is readily understood that the number of masks in the masking circuit 540 is the same as the number of multipliers in the multiplier data.

[0095] Encoder 510 may include multiple sub-encoders for bootsing the data in the multiplicand input 560. The above encoding process includes bootsing the first multiplicand b0 and the second multiplicand b1, as well as bootsing other bits in the storage circuit in the multiplicand input 560.

[0096] In one embodiment, the multiplicand input 560 is further configured to store the first multiplicand b0 in the low-order bits of the storage circuit of the multiplicand input 560, store the second multiplicand b1 in the high-order bits, insert a 1-bit extension bit 0 at the end of the least significant bit of the first multiplicand b0, and set all other empty bits except the first multiplicand b0, the second multiplicand b1, and the aforementioned extension bit to 0. For example, the storage circuit of the multiplicand input 560 has a bit width of 12 bits, wherein the first multiplicand b0 is stored in bits LSB to 3, the second multiplicand b1 is stored in bits 8 to 11, and the multiplicand input 560 is further configured to insert a 1-bit extension bit 0 at the end of the least significant bit of the first multiplicand b0, and set the empty bits, i.e., bits 4 to 7, to 0. The same multiplier input terminal 550 is also used to store the first multiplier a0 in the low bit of the storage circuit of the multiplier input terminal 550, store the second multiplier a1 in the high bit, and set all other free bits except the first multiplier a0 and the second multiplier a1 to 0.

[0097] In one embodiment, the multiplicand input 560 is further configured to store the first multiplicand b0 in the low-order bit of the storage circuit of the multiplicand input 560, store the second multiplicand b1 in the high-order bit of the multiplicand input 560, and such that the first multiplicand b0 and the second multiplicand b1 are separated by at least one bit of 0.

[0098] The first sub-encoder in the encoder 510 is used to perform Booth encoding on the extended bits up to the (k-2)th bit of the multiplicand input 560, and the ith sub-encoder is used to perform Booth encoding on the i×(k-1)+1th bit to the (i+1)×(k-1)+1th bit of the multiplicand input 560, where k is the bit width of each sub-encoder, k≥2 and is an integer, and i≥1 and is an integer. For example, the first sub-encoder performs Booth encoding on the extended bits, LSB, and the first bit of the multiplicand input 560, the second sub-encoder performs Booth encoding on the first to third bits of the multiplicand input 560, the third sub-encoder performs Booth encoding on the third to fifth bits of the multiplicand input 560, and so on. When the storage circuit of the multiplicand input 560 has a bit width of 12 bits, where the first multiplicand b0 is stored in bits 3 through LSB and the second multiplicand b1 is stored in bits 8 through 11, the encoding results of the first multiplicand b0 are the encoding results of the 1st and 2nd sub-encoders, respectively, and the encoding results of the second multiplicand b1 are the encoding results of the 5th and 6th sub-encoders, respectively. When encoder 510 uses radix-4 encoding, k=3, meaning the bit width of each sub-encoder is 3 bits. When encoder 510 uses radix-8 encoding, k=4, meaning the bit width of each sub-encoder is 4 bits. When encoder 510 uses radix-n encoding, k= +1, meaning the bit width of each sub-encoder is + 1 bit.

[0099] The partial product calculation circuit 520 includes multiple partial product sub-circuits, used to calculate multiple partial products based on two mask results corresponding to the multiple encoding results, using multiple encoding results obtained from multiple sub-encoders in the encoder 510 as control signals. Specifically, the partial product calculation circuit 520 may include multiple first partial product sub-circuits and multiple second partial product sub-circuits. The first partial product sub-circuits are used to calculate multiple first partial products based on the first mask result, using multiple encoding results of the first multiplicand b0 as control signals; the second partial product sub-circuits are used to calculate multiple second partial products based on the second mask result, using multiple encoding results of the second multiplicand b1 as control signals. In one embodiment, the partial product calculation circuit 520 further includes multiple third partial product sub-circuits, used to calculate multiple third partial products based on the data in the multiplier input terminal, using the aforementioned idle bits as control signals. For example, if the first or second partial product sub-circuit receives an encoding result of -2X, the control signal indicates that the partial product corresponding to the encoding result and the mask result are -2 times, therefore the calculated partial product is the product of -2 and the mask result. For the third part integrator circuit, if the received encoding result is X, the control signal indicates that the partial product corresponding to the encoding result and the data stored in the multiplier input terminal 550 are in a 1:1 relationship. Therefore, the calculated partial product is the product of 1 and the data stored in the multiplier input terminal 550.

[0100] Accumulator 530 is used to accumulate the plurality of first partial products, the plurality of second partial products and the third partial products respectively.

[0101] In one embodiment, the multiplier 600 further includes a selector 670, an adder 680, and a switch 690. The selector 670 outputs the most significant bit of the first multiplicand b0 to the most significant bit of the corresponding sub-encoder, and outputs a data 0 to the least significant bit of the sub-encoder adjacent to that sub-encoder that encodes idle bits, where the idle bits are the bits set to 0 between the first multiplicand b0 and the second multiplicand b1. Specifically, the selector 670 outputs the most significant bit of the first multiplicand b0 to the most significant bit of the x-th sub-encoder, and outputs 0 to the least significant bit of the (x+1)-th sub-encoder, where the x-th sub-encoder is the bit with the most significant bit of the first multiplicand b0... to( The sub-encoder uses -k+1) bits for encoding. The adder 680 is used to add the results of the accumulation of the first part (i.e., the result of multiplying the first multiplier and the first multiplicand) and the results of the accumulation of the second part (i.e., the result of multiplying the second multiplier and the second multiplicand) to obtain the result of the multiplication accumulation a0×a1+b0×b1.

[0102] by Figure 7The working principle of multiplier 600 is illustrated using a more specific multiplier 600 as shown. Multiplier 600 is described using a 12-bit width as an example, but it is readily understood that this embodiment does not limit the bit width of multiplier 600. Multiplier 600 can be used to perform operations on at least two sets of low-bit-width multiplication data, for example, calculating... Figure 7 The four INT4 data shown are: the first multiplier a0, the second multiplier a1, the first multiplicand b0, and the sum of the products of the second multiplicand b1, i.e., a0×b0+a1×b1. It is easy to understand that the multiplier 600 can also perform more than two sets of low-bit-width multiplication operations, and this application does not limit the number of multiplication operations.

[0103] by Figure 7 For example, the first multiplier a0, the second multiplier a1, the first multiplicand b0, and the second multiplicand b1 all have a bit width of 4 bits and are all integers. The multiplicand input 560 inserts a 0 bit at the end of the least significant bit of the first multiplicand b0. After end-bit extension, the first multiplier a0, the second multiplier a1, the first multiplicand b0, and the second multiplicand b1 are... Figure 7 The data is stored in the format shown, where the first multiplier a0 corresponds to the 3rd bit of the LSB of the multiplier input 550, and the second multiplier a1 corresponds to the 8th to 11th bits of the multiplier input 550; the first multiplicand b0 corresponds to the 3rd bit of the LSB of the multiplicand input 560, and the second multiplicand b1 corresponds to the 8th to 11th bits of the multiplicand input 560. The selector 670 outputs the most significant bit of the first multiplicand b0 to sub-encoder 1 and outputs 0 to the least significant bit of sub-encoder 2.

[0104] Encoder 510 includes sub-encoder 0 (i.e., the first sub-encoder mentioned above, and so on), sub-encoder 1, sub-encoder 2, sub-encoder 3, sub-encoder 4, and sub-encoder 5. Specifically, sub-encoder 0 encodes the extension bit 0, LSB, and the first bit inserted at the end of the first multiplicand b0, while sub-encoder 1 encodes the first bit, second bit, and third bit, and sub-encoder 2 encodes the third bit, fourth bit, and fifth bit, as follows. Figure 7 As shown, and so on. The encoding method of the above sub-encoders can follow the rules described in Table 1 above.

[0105] The multiplier input 550 receives and stores the first multiplier a0 and the second multiplier a1 in the same way; that is, the 3rd bit of the LSB of the multiplier input 550 receives and stores the first multiplier a0, and the 8th to 11th bits receive and store the second multiplier a1. It should be noted that, as... Figure 7 In the multiplicand input shown, x represents a fixed value of 0.

[0106] The masking circuit 540 also includes a first mask 342 and a second mask 344. The first mask 342 is used to zero out the low-order part of the data stored at the multiplier input terminal 550, that is, to retain the second multiplier a1 and zero out the first multiplier a0 part. Specifically, the first mask 342 can be an AND gate that implements the AND 0xF00 logic, so that the 12 bits of data stored at the multiplier input terminal 550 are bitwise ANDed with 0xF00, thereby retaining the data from the 8th to the 11th bits and zeroing out the data from the LSB to the 7th bit. Correspondingly, the second mask 344 is used to zero out the high-order part of the data stored at the multiplier input terminal 550, that is, to retain the first multiplier a0 and zero out the second multiplier a1 part. Specifically, the second mask 342 can be an AND gate that implements the AND 0x00F logic, so that the 12 bits of data stored at the multiplier input 550 are bitwise ANDed with 0x00F, thereby making the data from LSB to the 3rd bit retained, while the data from the 4th to the 11th bit are zeroed.

[0107] Partial product calculation circuit 520 includes, for example: Figure 7 The partial product circuits 0, 1, 2, 3, 4, and 5 shown receive the encoding result generated by the corresponding sub-encoder in the encoder 510, and output the corresponding partial product based on the masking result generated by the first mask 342 or the second mask 344. Specifically, partial product circuits 0 and 1 use sub-encoders 0 and 1 as control signals, respectively, and determine the partial product based on the masking result generated by the second mask 344; partial product circuits 4 and 5 use sub-encoders 4 and 5 as control signals, respectively, and determine the partial product based on the masking result generated by the first mask 342; partial product circuits 2 and 3 use sub-encoders 2 and 3 as control signals, respectively, and determine the partial product based on the data stored in the multiplier input terminal 550. For example, if the encoding result generated by sub-encoder 0 is -2X and the masking result generated by second masker 560 is 0x00C, then the partial product circuit 0 takes the control signal corresponding to the above encoding result as input, the masking result 0x00C as input, and outputs the product of the masking result and the control signal as the partial product, that is, the partial product can be expressed as -2(0x00C) = 0xFE8.

[0108] Accumulator 530 is used to receive and accumulate multiple partial products generated by the various partial product sub-circuits in partial product calculation circuit 520. For example, the partial product generated by partial product sub-circuit 0 is pp0, the partial product generated by partial product sub-circuit 1 is pp1, the partial product generated by partial product sub-circuit 2 is pp2, the partial product generated by partial product sub-circuit 3 is pp3, the partial product generated by partial product sub-circuit 4 is pp4, and the partial product generated by partial product sub-circuit 5 is pp5. Since the multiplicand is encoded with 2-bit intervals, the corresponding weights of each adjacent partial product sub-circuit are 4 times, that is, the partial product generated by partial product sub-circuit 0 is multiplied by 4. (pp0) is accumulated, and the partial product generated by the partial integrator circuit 1 is... (pp1) is accumulated, and the partial product generated by the partial integrator circuit 2 is... (pp2) is accumulated, and the partial product generated by the partial integrator circuit 3 is... (pp3) Accumulation is performed, and the partial product generated by the partial integrator circuit 4 is... (pp4) is accumulated, and the partial product generated by the partial integrator circuit 5 is... (pp. 5) Perform the summation. The final summation result is the product of the multiplier and the multiplicand. The above summation process can be represented as:

[0109] ( + pp3)+ pp2)+ pp1)+ pp0

[0110] The bit width of the accumulation result obtained by the above accumulation process is 23 bits, of which bits 16 to 22 store the result of a1×b1, and bits LSB to 6 store the result of a0×b0.

[0111] Adder 680 is used to receive the accumulation result generated by the accumulator, and add bits 16 to 22 of the accumulation result to the data in bits LSB to 6 to obtain the result a0×b0+ a1×b1, and output the result.

[0112] In one embodiment, the multiplier 600 further includes a switch 690, used to activate the mask circuit 540, selector 670, and adder 680 respectively according to the mode control signal. When the mask circuit 540, selector 670, and adder 680 are activated, they respectively perform the functions described above. When the mask circuit 540, selector 670, and adder 680 are not activated (invalid), the mask circuit 540 is used to pass through the received multiplier, the selector 670 is used to output the most significant bit of the first multiplicand b0 to the most significant bit of sub-encoder 1 and the least significant bit of sub-encoder 2 respectively, and the adder 680 is used to pass through the received accumulation result. Specifically, when the mode control signal received by switch 690 is a low-bit-width multiplication mode, the mask circuit 540, selector 670, and adder 680 are activated to respectively perform the functions described above. Figure 7 As shown, multiplier 500 is used to perform operations on at least two sets of low-bit-width multiplication data. When the mode control signal received by switch 380 is in high-bit-width multiplication mode, the mask circuit 540, selector 670 and adder 680 are deactivated, and multiplier 500 is used to perform operations on one set of high-bit-width multiplication data.

[0113] like Figure 8 The illustration shows another specific multiplier 800 provided in this application embodiment. Multiplier 800 is similar to multiplier 600, including a multiplication operation circuit 502, a mask circuit 540, a multiplier input terminal 550, a multiplicand input terminal 560, a selector 670, and a switch 690. The multiplication operation circuit 502 includes an encoder 510, a partial product calculation circuit 520, and an accumulator 530. The difference is that, when processing the multiplicand, the multiplicand input terminal 560 in multiplier 800 is used to store the first multiplicand b0 in the low-order bits of the storage circuit of the multiplicand input terminal 560, and to store the second multiplicand b1 in the high-order bits, such that the most significant bit of the first multiplicand b0 is adjacent to the least significant bit of the second multiplicand b1. In one embodiment, the multiplier input terminal 550 is further configured to store the first multiplier a0 in the high-order bits of the multiplier input terminal 550 and the second multiplier a1 in the low-order bits of the multiplier input terminal 550, such that the least significant bit of the first multiplier a0 and the most significant bit of the second multiplier a1 are adjacent to each other, wherein the position where the first multiplier a0 is stored in the multiplier input terminal 550 is the same as the position where the second multiplicand b1 is stored in the multiplicand input terminal 560, and the position where the second multiplier a1 is stored in the multiplier input terminal 550 is the same as the position where the first multiplicand b0 is stored in the multiplicand input terminal 560.

[0114] The selector 680 in multiplier 800 is used to output the most significant bit of the first multiplicand b0 to the corresponding sub-encoder, and output the data 0 to the sub-encoder adjacent to that sub-encoder that encodes the second multiplicand b1. Specifically, selector 680 is used to output 0 to the most significant bit of the x-th sub-encoder, and output the least significant bit of the second multiplicand b1 to the least significant bit of the (x+1)-th sub-encoder, where the x-th sub-encoder is the one encoding the most significant bit of the first multiplicand b0. to( The sub-encoder encodes the least significant bit of the second multiplicand b1 using (-k+1) bits. to( The sub-encoder uses -k+1) bits for encoding. Furthermore, the multiplier 800 includes a shifter 882 for shifting the results of multiple first-part accumulations (i.e., the product of the first multiplier and the first multiplicand) and multiple second-part accumulations (i.e., the product of the first multiplier and the first multiplicand). Specifically, the number of bits shifted is equal to the bit width of the multiplier or multiplicand.

[0115] by Figure 9 The working principle of multiplier 800 is illustrated by another more specific multiplier 800. The multiplicand input 560 performs a trailing extension on the first multiplicand b0, that is, inserts a 0 bit at the end of the least significant bit of the first multiplicand b0. After the trailing extension, the first multiplier a0, the second multiplier a1, the first multiplicand b0, and the second multiplicand b1 are multiplied by... Figure 7 The data is stored in the format shown, where the first multiplier a0 corresponds to bits 4-7 of the multiplier input 550, and the second multiplier a1 corresponds to bits LSB-3 of the multiplier input 550; the first multiplicand b0 corresponds to bits LSB-3 of the multiplicand input 560, and the second multiplicand b1 corresponds to bits 4-7 of the multiplicand input 560. The selector 670 outputs 0 to sub-encoder 1 and outputs the least significant bit of the second multiplicand b0 to sub-encoder 2. It should be noted that... Figure 9 In the multiplicand input shown, x represents a fixed value of 0. Shifter 882 is used to shift the result obtained by accumulator 530 to the right by 4 bits to obtain the result a0×b0+ a1×b1, and then outputs the result.

[0116] This application also provides a data processing system, including an encoder and at least one multiplier sharing the encoder. Figure 10The data processing system 1000 shown is used as an example for illustration. This system includes an encoder 1005, a multiplier 1010, and a multiplier 1020. The multipliers 1010 and 1020 may each include a mask circuit 540, a multiplier input terminal 550, a multiplicand input terminal 560, a switch 790, a partial product calculation circuit 520, and an accumulator 540, as provided in any embodiment of this application. The encoder 1050 may be the encoder 510 provided in an embodiment of this application. The difference is that the encoding result of the encoder 1005 is shared by the multipliers 1010 and 1020. That is, the encoder 1005 encodes the input multiplicand (e.g., the first multiplicand b0 and the second multiplicand b1) and outputs the resulting multiple encoding results to the partial product calculation circuits 520 of the multipliers 1010 and 1020, respectively. In one embodiment, each of the multipliers may further include an adder 680 provided in the embodiments of this application. In one embodiment, each of the multipliers may further include a shifter 882 provided in the embodiments of this application. In one embodiment, the data processing system 1000 further includes a selector 670 provided in the embodiments of this application. It should be noted that the selector 670 is activated when both the switches in multipliers 1010 and 1020 are active.

[0117] In one possible implementation, the data processing system 1000 may further include multiple multipliers, which may include the mask circuit 540, the partial product calculation circuit 520, the accumulator 540, the multiplier input terminal 550, the multiplicand input terminal 560, the switch 690 and the selector 670 provided in the embodiments of this application, as well as the adder 680 or the shifter 882.

[0118] like Figure 11 The illustration shows a multiplication calculation method provided in an embodiment of this application, applied to a multiplier. The multiplier includes a multiplier input terminal and a multiplicand input terminal. The multiplication calculation method includes:

[0119] S1110: Receive multiplier data, wherein the multiplier data includes a first multiplier and a second multiplier, and the sum of the bit widths of the first multiplier and the second multiplier is less than the bit width of the multiplier data;

[0120] S1120: Perform masking processing on the multiplier data to mask the second multiplier, so as to obtain the first masking result; and perform masking processing on the multiplier data to mask the first multiplier, so as to obtain the second masking result.

[0121] S1130: Receive a first multiplicand and a second multiplicand, wherein the sum of the bit widths of the first multiplicand and the second multiplicand is less than the bit width of the multiplicand input terminal;

[0122] S1140: Perform a multiplication operation on the first mask result and the first multiplicand to obtain the result of multiplying the first multiplier and the first multiplicand, and perform a multiplication operation on the second mask result and the second multiplicand to obtain the result of multiplying the second multiplier and the second multiplicand.

[0123] In one embodiment, the steps of multiplying the first mask result and the first multiplicand to obtain the result of multiplying the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the result of multiplying the second multiplier and the second multiplicand, include: performing Booth coding on the first multiplicand and the second multiplicand.

[0124] In one embodiment, the steps of multiplying the first mask result and the first multiplicand to obtain the result of multiplying the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the result of multiplying the second multiplier and the second multiplicand, further include: performing partial product calculation based on the encoding result generated by the Booth encoding to obtain multiple partial products; and accumulating the multiple partial products.

[0125] In one embodiment, the step of performing Booth encoding on the first multiplicand and the second multiplicand includes: using multiple sub-encoders to perform Booth encoding on the first multiplicand to obtain at least one first encoding result, and performing Booth encoding on the second multiplicand to obtain at least one second encoding result; the step of calculating partial products based on the encoding results generated by Booth encoding to obtain multiple partial products includes: calculating at least one first partial product of at least one first encoding result and a first mask result, and calculating at least one second partial product of at least one second encoding result and a second mask result; and the step of accumulating the multiple partial products includes: accumulating at least one first partial product to obtain a result of multiplying the first multiplier and the first multiplicand, and accumulating at least one second partial product to obtain a result of multiplying the second multiplier and the second multiplicand.

[0126] In one embodiment, the multiplication calculation method further includes: adding the result of multiplying the first multiplier and the first multiplicand obtained by the accumulator, and the result of multiplying the second multiplier and the second multiplicand.

[0127] In one embodiment, the multiplication calculation method further includes: shifting the result of multiplying the first multiplier and the first multiplicand obtained by the accumulator, and shifting the result of multiplying the second multiplier and the second multiplicand, respectively.

[0128] In one embodiment, the data in the multiplicand input includes a first multiplicand located in the lower bits of the multiplicand input, a second multiplicand located in the higher bits of the multiplicand input, a 1-bit extension bit 0 inserted at the end of the least significant bit of the first multiplicand, and other bits in the multiplicand input that are set to 0 except for the first multiplicand, the second multiplicand, and the extension bit; the multiplier data includes: a first multiplier located in the lower bits of the multiplier input, a second multiplier located in the higher bits of the multiplicand input, and other bits in the multiplier input that are set to 0 except for the first multiplier and the second multiplier, wherein the position of the first multiplier in the multiplier input is the same as the position of the first multiplicand in the multiplicand input, and the position of the second multiplier in the multiplier input is the same as the position of the second multiplicand in the multiplicand input.

[0129] In one embodiment, the first multiplicand and the second multiplicand are separated by at least 1 bit of 0, and the first multiplier and the second multiplier are separated by at least 1 bit of 0. The multiplication calculation method further includes: outputting the most significant bit of the first multiplicand to the most significant bit of the corresponding first sub-encoder, and outputting the data 0 to the least significant bit of the sub-encoder adjacent to the first sub-encoder and encoding the idle bit, wherein the idle bit is the bit set to 0 between the first multiplicand and the second multiplicand.

[0130] In one embodiment, the most significant bit of the first multiplicand and the least significant bit of the second multiplicand are adjacent, and the most significant bit of the first multiplier and the least significant bit of the second multiplier are adjacent. The multiplication calculation method further includes: outputting the most significant bit data of the first multiplicand to the most significant bit of the corresponding first sub-encoder, and outputting data 0 to the least significant bit of the second sub-encoder. The second sub-encoder is a sub-encoder that is adjacent to the first sub-encoder and encodes the second multiplicand.

[0131] In one embodiment, the multiplication calculation method further includes: using a switch to perform masking when the switch is closed and to prevent masking when the switch is open.

[0132] In one implementation, the steps of masking the multiplier data by a second multiplier to obtain a first mask result, and masking the multiplier data by a first multiplier to obtain a second mask result, include: using two AND gates to mask the multiplier data by a first multiplier and a second multiplier respectively, to output two mask results.

[0133] like Figure 12The diagram illustrates a multiplication processing system 1200 provided in this embodiment. This system can be coupled to a memory 1210 and read data from or write data to the memory 1210. The multiplication processing system 1200 can be implemented using a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). The memory 1210 can be random access memory (RAM), read-only memory (ROM), or other types of memory. The multiplication processing system 1200 and the memory 1210 can be disposed on the same substrate and packaged within a single semiconductor package structure, or they can be packaged separately within different semiconductor package structures. The data can be data to be multiplied, such as multiplicand data, multiplier data, control signals and parameters related to the multiplication operation, the result of the multiplication operation, or an intermediate result. The multiplication processing system 1200 may include an IP core 1220 (intellectual property core). The IP core 1220 may be used to implement any of the methods provided in the embodiments of this application. The IP core 1220 may also include any of the multipliers or data processing systems provided in the embodiments of this application.

[0134] In one implementation, the IP core 1220 can be implemented using a DSP (Digital Signal Processor) or a CPU, for example, using a soft core. In another implementation, the IP core 1220 can also be implemented using a hard core. In yet another implementation, the IP core 1220 can be implemented using a hard core running on a DSP / CPU. For example, the multiplication processing system 1200 reads a configuration file (hard core) from a computer-readable storage medium. This configuration file is used to configure the multiplication processing system 1200 so that it can be configured to be any of the multipliers or data processing systems provided in the embodiments of this application, or configured to implement any of the methods provided in the embodiments of this application. The configuration file is a functionally verified circuit structure encoding file.

[0135] In one embodiment, this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the methods provided in this application.

[0136] In one embodiment, this application provides a computer program that includes instructions that, when executed by a computer, enable the computer to perform any of the methods provided in this application.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multiplier characterized by, The multiplier includes: a multiplier input terminal for receiving multiplier data, wherein the multiplier data includes a first multiplier and a second multiplier, and the sum of the bit widths of the first multiplier and the second multiplier is less than the bit width of the multiplier input terminal; wherein the multiplier input terminal is further configured to store the first multiplier in the low-order bits of the multiplier input terminal storage circuit, store the second multiplier in the high-order bits of the multiplier input terminal storage circuit, and set all other idle bits except for the first multiplier and the second multiplier to 0; The masking circuit includes a first mask and a second mask. The second mask is used to perform a masking process on the multiplier data to mask the second multiplier, so as to obtain a first masking result. The first mask is used to perform a masking process on the multiplier data to mask the first multiplier, so as to obtain a second masking result. The multiplicand input terminal is used to receive a first multiplicand and a second multiplicand, wherein the sum of the bit widths of the first multiplicand and the second multiplicand is less than the bit width of the multiplicand input terminal; wherein the data formats of the first multiplicand and the first multiplicand are different from the data formats of the second multiplicand and the second multiplicand; the positions where the first multiplicand and the second multiplicand are stored in the multiplier input terminal are the same as the positions where the first multiplicand and the second multiplicand are stored in the multiplicand input terminal; or, the positions where the first multiplier is stored in the multiplier input terminal are the same as the positions where the second multiplicand is stored in the multiplicand input terminal, and the positions where the second multiplier is stored in the multiplier input terminal are the same as the positions where the first multiplicand is stored in the multiplicand input terminal; and A multiplication circuit is used to perform a multiplication operation on the first mask result and the first multiplicand to obtain the result of multiplying the first multiplier and the first multiplicand, and to perform a multiplication operation on the second mask result and the second multiplicand to obtain the result of multiplying the second multiplier and the second multiplicand.

2. The multiplier of claim 1, wherein, The multiplication circuit includes a Booth encoder.

3. The multiplier as described in claim 2, characterized in that, The multiplication circuit also includes: Partial product calculation circuit, used to perform partial product calculation based on the encoding result generated by the Booth encoder; and An accumulator is used to accumulate multiple partial products generated by the partial product calculation circuit.

4. The multiplier as described in claim 3, characterized in that, The Booth encoder includes multiple sub-encoders for: performing Booth encoding on the first multiplicand to obtain at least one first encoding result, and performing Booth encoding on the second multiplicand to obtain at least one second encoding result; The partial product calculation circuit is specifically used for: calculating at least one first partial product of the at least one first encoding result and the first mask result, and calculating at least one second partial product of the at least one second encoding result and the second mask result; and The accumulator is specifically used to: accumulate the at least one first partial product to obtain the result of multiplying the first multiplier and the first multiplicand, and accumulate the at least one second partial product to obtain the result of multiplying the second multiplier and the second multiplicand.

5. The multiplier as described in claim 1, characterized in that, The multiplier also includes an adder, which is used for: Add the result of multiplying the first multiplier and the first multiplicand, and the result of multiplying the second multiplier and the second multiplicand.

6. The multiplier as described in claim 1, characterized in that, The multiplier also includes a shifter, which is used for: The result of multiplying the first multiplier and the first multiplicand, and the result of multiplying the second multiplier and the second multiplicand, are shifted respectively.

7. The multiplier according to any one of claims 4 to 6, characterized in that, The data in the multiplicand input terminal includes the first multiplicand located in the low-order bits of the multiplicand input terminal, the second multiplicand located in the high-order bits of the multiplicand input terminal, a 1-bit extension bit 0 inserted at the end of the least significant bit of the first multiplicand, and other bits in the multiplicand input terminal that are set to 0 except for the first multiplicand, the second multiplicand, and the extension bit. The multiplier data includes: The first multiplier is located in the lower bit of the multiplier input terminal, the second multiplier is located in the higher bit of the multiplicand input terminal, and the other bits in the multiplier input terminal other than the first multiplier and the second multiplier are set to 0, wherein the position of the first multiplier in the multiplier input terminal is the same as the position of the first multiplicand in the multiplicand input terminal, and the position of the second multiplier in the multiplier input terminal is the same as the position of the second multiplicand in the multiplicand input terminal.

8. The multiplier as described in claim 7, characterized in that, The first multiplicand and the second multiplicand are separated by at least 1 bit of 0, and the first multiplier and the second multiplier are separated by at least 1 bit of 0. The multiplier also includes a selector, which is used to: The most significant bit of the first multiplicand is output to the most significant bit of the corresponding first sub-encoder, and the data 0 is output to the least significant bit of the sub-encoder adjacent to the first sub-encoder that encodes the idle bits, wherein the idle bits are the bits set to 0 between the first multiplicand and the second multiplicand.

9. The multiplier as described in claim 7, characterized in that, The most significant bit of the first multiplicand and the least significant bit of the second multiplicand are adjacent, and the most significant bit of the first multiplier and the least significant bit of the second multiplier are adjacent. The multiplier also includes a selector, which is used for: The most significant bit of the first multiplicand is output to the most significant bit of the corresponding first sub-encoder, and the data 0 is output to the least significant bit of the second sub-encoder. The second sub-encoder is a sub-encoder that is adjacent to the first sub-encoder and encodes the second multiplicand.

10. The multiplier as claimed in claim 4, characterized in that, The partial integrated circuit includes multiple first partial integrated circuits, multiple second partial integrated circuits, and multiple third partial integrated circuits, wherein: The plurality of first partial product circuits are used to calculate a plurality of first partial products based on the first mask result, using the plurality of encoded results of the first multiplicand as control signals respectively. The plurality of second partial integrator circuits are used to calculate a plurality of second partial products based on the second mask result, using the plurality of encoded results of the second multiplicand as control signals respectively. The plurality of third-part multiplier circuits are used to calculate a plurality of third-part products based on the data in the multiplier input terminal, with the idle bit as the control signal. The idle bit is the bit in the multiplicand input terminal that is set to 0. The accumulator is specifically used to: accumulate the plurality of first partial products, the plurality of second partial products, and the plurality of third partial products.

11. The multiplier as claimed in claim 1, characterized in that, The multiplier also includes a switch that is used to activate the mask circuit when it is in a closed state and to disable the mask circuit when it is in an open state.

12. The multiplier as claimed in claim 1, characterized in that, The masking circuit includes two AND gates, which are used to perform masking processing on the multiplier data to mask the first multiplier and masking processing on the second multiplier, respectively, to output the two masking results.

13. A multiplication calculation method, characterized in that, Applied to a multiplier, the multiplier includes a multiplier input terminal and a multiplicand input terminal, and the multiplication calculation method includes: Receive multiplier data, wherein the multiplier data includes a first multiplier and a second multiplier, the sum of the bit widths of the first multiplier and the second multiplier is less than the bit width of the multiplier input terminal; wherein the first multiplier is stored in the low bit of the multiplier input terminal storage circuit, the second multiplier is stored in the high bit of the multiplier input terminal storage circuit, and other idle bits other than the first multiplier and the second multiplier are set to 0; The multiplier data is masked by a second mask to obtain a first mask result, and the multiplier data is masked by a first mask to obtain a second mask result. The system receives a first multiplicand and a second multiplicand, wherein the sum of the bit widths of the first multiplicand and the second multiplicand is less than the bit width of the multiplicand input terminal; wherein the data formats of the first multiplicand and the first multiplicand are different from the data formats of the second multiplicand and the second multiplicand; the positions where the first multiplicand and the second multiplicand are stored in the multiplier input terminal are the same as the positions where the first multiplicand and the second multiplicand are stored in the multiplier input terminal; or, the positions where the first multiplier is stored in the multiplier input terminal are the same as the positions where the second multiplicand is stored in the multiplicand input terminal, and the positions where the second multiplier is stored in the multiplier input terminal are the same as the positions where the first multiplicand is stored in the multiplicand input terminal. The first mask result and the first multiplicand are multiplied to obtain the result of multiplying the first multiplier and the first multiplicand, and the second mask result and the second multiplicand are multiplied to obtain the result of multiplying the second multiplier and the second multiplicand.

14. The multiplication calculation method as described in claim 13, characterized in that, The steps of multiplying the first mask result and the first multiplicand to obtain the product of the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the product of the second multiplier and the second multiplicand, include: The first multiplicand and the second multiplicand are subjected to Booth encoding.

15. The multiplication calculation method as described in claim 14, characterized in that, The steps of multiplying the first mask result and the first multiplicand to obtain the product of the first multiplier and the first multiplicand, and multiplying the second mask result and the second multiplicand to obtain the product of the second multiplier and the second multiplicand, further include: The partial product is calculated based on the encoding result generated by the Booth encoding to obtain multiple partial products; and the multiple partial products are accumulated.

16. The multiplication calculation method as described in claim 15, characterized in that, The step of performing Booth encoding on the first multiplicand and the second multiplicand includes: Booth encoding is performed on the first multiplicand using multiple sub-encoders to obtain at least one first encoding result, and Booth encoding is performed on the second multiplicand to obtain at least one second encoding result; The step of calculating partial products based on the encoding results generated by Booth encoding to obtain multiple partial products includes: Calculate at least one first partial product of the at least one first encoding result and the first mask result, and calculate at least one second partial product of the at least one second encoding result and the second mask result; and The steps for accumulating multiple partial products include: The product of the first multiplier and the first multiplicand is accumulated to obtain the result of multiplying the first multiplier and the first multiplicand, and the product of the second multiplier and the second multiplicand is accumulated to obtain the result of multiplying the second multiplier and the second multiplicand.

17. The multiplication calculation method according to any one of claims 13 to 16, characterized in that, The multiplication calculation method also includes: Add the result of multiplying the first multiplier and the first multiplicand, and the result of multiplying the second multiplier and the second multiplicand.

18. The multiplication calculation method according to any one of claims 13 to 16, characterized in that, The multiplication calculation method also includes: The result of multiplying the first multiplier and the first multiplicand, and the result of multiplying the second multiplier and the second multiplicand, are shifted respectively.

19. A multiplication processing system, characterized in that, The multiplication processing system reads a configuration file from a memory coupled to the multiplication processing system, such that the multiplication processing system can be configured as a multiplier as described in any one of claims 1 to 12.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 13 to 18.

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