Power efficient synchronous rectifier gate driver architecture

Abstract

A synchronous switching scheme with adaptive slew control is described to charge and discharge a capacitor adiabatically to recycle charge and create a boost voltage on the gate of a synchronous rectifier field effect transistor (FET). In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to the gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET and charge and discharge the capacitor adiabatically using the capacitor and an adaptive slew rate.

Description

[0001] Related applications

[0002] This application is an international application of U.S. non-provisional patent application number 16 / 721,377, filed December 19, 2019, which claims the benefit of U.S. provisional patent application number 62 / 903,548, filed September 20, 2019, both of which are incorporated herein by reference in their entirety. Background Technology

[0003] Various electronic devices (e.g., smartphones, tablets, laptops, notebook computers, hubs, chargers, adapters, etc.) are configured to transmit power via a USB connector according to the USB Power Delivery protocol defined in various revisions of the Universal Serial Bus (USB) Power Delivery (USB-PD) specification. For example, in some applications, an electronic device may be configured as a power consumer to receive power via a USB connector (e.g., for battery charging), while in other applications, it may be configured as a power supplier to provide power to another device connected to it via a USB connector. However, the USB-PD specification allows the power supplier and power consumer to dynamically negotiate the levels of voltage and current supplied. Under certain power supply conditions, fault conditions may occur on the voltage / current supplied by the power supplier, and other fault conditions may occur on the voltage / current received by the power consumer. Attached Figure Description

[0004] The disclosure is illustrated by way of example rather than limitation in the figures of the accompanying drawings.

[0005] Figure 1 This is a schematic diagram of a USB-PD power adapter in one embodiment, which has a synchronous rectifier gate driver (SRGD) with adaptive conversion rate control integrated on the secondary-side controller (also known as the power adapter secondary IC controller).

[0006] Figure 2 This is a timing diagram of a synchronous switching scheme according to one embodiment, which shows the switching current and voltage waveforms on the secondary side of the flyback converter.

[0007] Figure 3 This is a schematic diagram of the phase and conversion controller circuit of an SRGD integrated on the secondary-side controller in a secondary controlled flyback converter according to one embodiment.

[0008] Figure 4 It is a timing and voltage diagram according to one embodiment of the control signals generated by the phase and conversion controller to realize the operation phase of the SRGD on the secondary-side controller integrated in the secondary controlled flyback converter.

[0009] Figure 5 This is a block diagram of an SRGD integrated on a secondary-side controller in a secondary controlled flyback converter according to one embodiment.

[0010] Figure 6 This is a block diagram of an embodiment of a boost voltage generator circuit and a gate driver circuit coupled to a phase and slew rate controller circuit of an SRGD integrated on a secondary-side controller in a secondary controlled flyback converter.

[0011] Figure 7 This is a timing diagram showing the voltages on the gate capacitor and the gate of the synchronous rectifier FET during SRGD operation on the secondary-side controller integrated into a USB-PD power adapter according to one embodiment.

[0012] Figure 8 This is a block diagram of an SRGD with a delay-based phase generator integrated on the secondary-side controller of a secondary controlled flyback converter, according to one embodiment.

[0013] Figure 9 This is a timing diagram showing the voltages on the gate capacitor and the gate of the synchronous rectifier FET during SRGD operation with a delay-based phase generator integrated on the secondary-side controller of a USB-PD power adapter according to one embodiment.

[0014] Figure 10 This is a block diagram of an embodiment of a boost voltage generator circuit coupled to a phase and slew rate controller circuit of an SRGD integrated on a secondary-side controller in a secondary controlled flyback converter, and a gate driver circuit having a pull-up path.

[0015] Figure 11 This is a block diagram of an embodiment of a boost voltage generator circuit and a gate driver circuit coupled to a phase and slew rate controller circuit of an SRGD with diodes integrated into a secondary-side controller in a secondary controlled flyback converter.

[0016] Figure 12A This is a schematic diagram of a p-type metal-oxide-semiconductor (PMOS) drive intensity tracking current generator according to one embodiment.

[0017] Figure 12B This is a schematic diagram of an n-type metal-oxide-semiconductor (NMOS) drive intensity tracking current generator according to one embodiment.

[0018] Figure 13A This is a schematic diagram of a delay-based conversion generator for a PMOS device according to one embodiment.

[0019] Figure 13B This is a schematic diagram of a delay-based conversion generator for an NMOS device according to one embodiment.

[0020] Figure 14 This is a schematic diagram of a pull-up path with an adaptive bias controller for an SRGD according to one embodiment.

[0021] Figure 15A This is a graph showing the delay variation of the PMOS delay cells at both ends of the synchronous rectifier FET in an adaptive switching control block according to one embodiment.

[0022] Figure 15B This is a graph showing the delay variation of the NMOS delay cells at both ends of the synchronous rectifier FET in an adaptive switching control block according to one embodiment.

[0023] Figure 16 This is a schematic diagram of a USB-PD power adapter according to one embodiment, which has a synchronous rectifier gate driver (SRGD) integrated on a secondary-side controller (also known as a power adapter secondary IC controller) to deliver power from a power supply device to an attached power-consuming device.

[0024] Figure 17 This is a block diagram illustrating a system for a USB device used in USB power supply according to some embodiments.

[0025] Figure 18 This is a flowchart of a method according to one embodiment, which synchronously switches a synchronous rectifier FET by means of an SRGD with adaptive switching control to thermally charge and discharge the gate capacitor to recycle the charge and generate a boost voltage on the gate of the synchronous rectifier FET. Detailed Implementation

[0026] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of various embodiments of the techniques described herein, which use a synchronous switching scheme with adaptive conversion rate control to charge and discharge the gate capacitor (e.g., a 0.1uF gate capacitor) in a secondary controlled flyback converter (e.g., for USB-Powered applications) to reduce power consumption. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of the invention.

[0027] References to “embodiment,” “one embodiment,” “example embodiment,” “some embodiments,” and “various embodiments” in the specification mean that a particular feature, structure, step, operation, or characteristic described in connection with one or more embodiments is included in at least one embodiment of the invention. Furthermore, the phrases “embodiment,” “one embodiment,” “example embodiment,” “some embodiments,” and “various embodiments” appearing in various places in the specification do not necessarily refer to the same one or more embodiments.

[0028] The specification includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate exemplary embodiments. These embodiments (which may also be referred to herein as “examples”) are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0029] This document describes various embodiments of a technique for thermally charging and discharging the gate capacitor in a secondary controlled flyback converter of an electronic device coupled to power lines in a USB-Powered (USB-PD) electronic device. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptops, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smartphones, cellular phones, personal digital assistants, messaging devices, handheld PCs, etc.), connectivity and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can communicate, charge batteries, and / or power themselves using a USB connector (interface). The embodiments described herein can be used in AC to DC power adapters, GaN-based power adapters operating at 600 kHz, power adapters with primary or secondary side controllers, and power adapters operating in various operating modes, such as quasi-resonant mode (QR), discontinuous conduction mode (DCM), continuous conduction mode (CCM), etc. The embodiments described herein can be used in conjunction with Type-C PD capability in power adapter solutions.

[0030] USB-enabled electronic devices or systems may conform to at least one release of the USB specification. Examples of such USB specifications include, but are not limited to, USB Specification Revision 2.0, USB 3.0, USB 3.1, and / or various supplements thereto (e.g., On-The-Go or OTG), versions, and errata. The USB specification generally defines the characteristics (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.) of the differential serial bus required for designing and building standard communication systems and peripherals. For example, a USB-enabled peripheral is attached to a USB-enabled host device via a host device's USB port to form a USB-enabled system. A USB 2.0 port includes a 5V power supply line (denoted as VBUS), differential data pairs (denoted as D+ or DP, and D- or DN), and a ground line (denoted as GND) for power return. USB 3.0 ports also provide VBUS, D+, D-, and GND lines for backward compatibility with USB 2.0. Additionally, to support the faster differential bus (USB SuperSpeed ​​Bus), the USB 3.0 port provides differential transmitter data pairs (denoted as SSTX+ and SSTX-), differential receiver data pairs (denoted as SSRX+ and SSRX-), a power line for power supply (denoted as DPWR), and a ground line for power return (denoted as DGND). The USB 3.1 port provides the same wiring as the USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communication, but extends the SuperSpeed ​​Bus's performance through a set of features known as Enhanced SuperSpeed.

[0031] A newer technology for USB connectors, known as USB Type-C, is defined in various releases and / or versions of the USB Type-C specification (e.g., release 1.0 of August 11, 2014, release 1.1 of April 3, 2015, etc.). The USB Type-C specification defines Type-C receptacles, Type-C plugs, and Type-C cables that can support USB communication as well as power supply via the newer USB Power Delivery protocols defined in various revisions / releases of the USB-PD specification. Examples of USB Type-C functionality and requirements may include, but are not limited to, data and other communications according to USB 2.0 and USB 3.0 / 3.1, electromechanical definitions and performance requirements for Type-C cables, electromechanical definitions and performance requirements for Type-C receptacles, electromechanical definitions and performance requirements for Type-C plugs, requirements for Type-C to legacy cable assemblies and adapters, requirements for Type-C-based device detection and interface configuration, and requirements for optimized power supply for Type-C connectors, etc. According to one or more USB Type-C specifications, a Type-C port provides VBUS, D+, D-, GND, SSTX+, SSTX-, SSRX+, and SSRX- lines. Additionally, a Type-C port provides a Sideband Use (SBU) line for signaling of sideband functions and a Configuration Channel (CC) line for discovering, configuring, and managing connections across the Type-C cable. A Type-C port can be associated with a Type-C plug and / or a Type-C receptacle. For ease of use, Type-C plugs and receptacles are designed as a reversible pair, and their operation is independent of plug-to-receptacle orientation. Therefore, the standard USB Type-C connector, configured as a standard Type-C plug or socket, provides pins for four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D- lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX- lines (SSTXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX- lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2).

[0032] Some USB-enabled electronic devices may conform to specific revisions and / or versions of the USB-PD specification (e.g., revision 1.0 released July 5, 2012, revision 2.0 released August 11, 2014, etc., or later revisions / versions). The USB-PD specification defines a standard protocol designed to enable the maximum functionality of USB-enabled devices by providing more flexible power supply and data communication via a USB Type-C port through a single USB Type-C cable. The USB-PD specification also describes the architecture, protocols, power behaviors, parameters, and cable routing necessary for managing power supply through a USB Type-C cable at up to 100W. According to the USB-PD specification, devices with USB Type-C ports (e.g., such as USB-enabled devices) can negotiate higher or lower currents and / or voltages via a USB Type-C cable compared to those allowed in older USB specifications (e.g., such as the USB 2.0 specification, the USB 3.1 specification, USB Battery Charging Specification versions 1.1 / 1.2, etc.). For example, the USB-PD specification defines requirements for a power supply contract (PD contract) that can be negotiated between a pair of USB-enabled devices. The PD contract can specify the power level and direction of power transfer that can be adapted by both devices, and can be dynamically renegotiated (e.g., without the devices being unplugged) upon request from either device and / or in response to various events and conditions (e.g., power role swap, data role swap, hard reset, power failure, etc.).

[0033] According to the USB-PD specification, electronic devices are typically configured to supply power to another device via a power path configured on a USB VBUS line. The device providing power is typically referred to as (or includes) the "provider" (or power source), and the device consuming power is typically referred to as (or includes) the "consumer" (or power sink). The power path typically includes a power switch connected in series on the VBUS line and configured to turn power delivery on and off.

[0034] USB-PD power can be configured to draw power from an AC power adapter or another AC power source. Therefore, as part of the AC-DC conversion, some implementations use a large bulk capacitor on the power side of the VBUS line to remove the AC component of the power signal. The switching on and off of the power switch (also known as a power FET) allows for further circuit protection based on current and voltage condition analysis and fault detection.

[0035] In a flyback converter, one factor determining efficiency is the secondary-side FET (e.g., a MOSFET switch), which is coupled in parallel to a diode on the secondary side of the flyback converter. The on-resistance (RDSon) of the secondary-side FET, along with the rise and fall times of the gate driver on the secondary-side controller that drives the gate of the secondary-side FET, determines the efficiency of the flyback converter. In one embodiment, the gate driver supply can be as low as 3V; then, the gate driver may require at least 5V to achieve a lower on-resistance for the secondary-side FET. This necessitates the use of a boost power supply for the driver. The gate driver generates a boost voltage at the gate of the secondary-side FET. To do this, a charge pump power supply is then used for the gate driver. Generating a boost voltage supply using a charge pump requires a higher supply from the battery than the gate driver supply. Charge recycling is not possible with a charge pump, resulting in increased power losses during flyback converter operation. Additionally, flyback converters lack adaptive switching control, leading to higher peak currents at fast process-voltage-temperature (PVT) angles (e.g., for gate drivers with fast rise and fall times). The problems with flyback converters include increased power consumption, high peak currents in metal routing lines that cause reliability issues, and increased power / ground noise that affects the performance of critical analog blocks.

[0036] This document describes various embodiments of techniques that improve efficiency and reduce gate driver power consumption compared to conventional flyback converters by using a synchronous switching scheme with adaptive slew rate control to adiabatically charge and discharge the gate capacitor, recycling the charge, and generating a boost voltage at the gate of a synchronous rectifier FET (e.g., a secondary-side FET, a secondary-side power supply FET, etc.). Instead of directly supplying the boost voltage to the gate of the synchronous rectifier FET using a charge pump, the synchronous switching scheme described herein allows the gate of the synchronous rectifier FET to be charged to the supply voltage level of the secondary-side controller and allows the gate capacitor to be charged and discharged at appropriate timings (e.g., in various phases) to increase the supply voltage. This provides a means of indirectly generating a boost voltage (e.g., twice the supply voltage) at the gate of the synchronous rectifier FET. When the synchronous rectifier is to be turned off, excess charge (e.g., for generating the boost voltage) is recycled back to the gate capacitor to recharge it. When the synchronous rectifier FET is to be turned on and a boost voltage supply is required, the charge from the gate capacitor can be used again to boost the voltage supply at the gate of the synchronous rectifier FET. In one embodiment, the gate capacitor is a polarized capacitor, such as an electrolyte capacitor, a tantalum capacitor, etc. In another embodiment, the gate capacitor can be a non-polarized capacitor, such as a ceramic capacitor, a film capacitor, etc. In one embodiment, the gate capacitor is a bootstrap capacitor. This synchronous switching scheme is designed to minimize power consumption, recycle gate charge, and reduce peak current (e.g., from 3.381A to 1.33A) and noise of the gate driver without affecting transient performance. Embodiments of the synchronous switching scheme with adaptive slew rate control described herein address the above and other challenges by adiabatic charging and discharging of the gate capacitor to recycle charge and reduce power consumption, without requiring the additional logic units and circuitry and complex protocols described above. In some embodiments, charge can be recycled during the discharge phase of the gate capacitor. In some embodiments, the synchronous switching scheme with adaptive slew rate control described herein can be used in a secondary controlled flyback converter. In some embodiments, this synchronous switching scheme can reduce gate driver power consumption by 30%, peak current and power supply noise by 2.5 times, and reduce area compared to conventional schemes by using a 5V MOSFET instead of a 10V MOSFET. Adaptive slew rate control can track changes in the PVT of the gate driver and then dynamically adjust the drive strength of the gate driver to meet performance requirements (e.g., in slow-angle combinations) and reduce peak current and noise (in fast-angle combinations).

[0037] The embodiments described herein address the above and other challenges by providing a serial bus-compatible power supply device, such as a serial bus power supply (SBPD) device with a power control analog subsystem (which has hardware, firmware, or any combination thereof for transmitting information), in a synchronous switching scheme with adaptive conversion rate control, to thermally charge and discharge the gate capacitor and generate a boost voltage at the gate of the secondary-side FET (also referred to herein as a “synchronous rectifier FET”) and drive the primary-side FET across an electrical isolation barrier. In one embodiment, the electrical isolation barrier may be provided by a pulse transformer. In other embodiments, electrical isolation may be provided by an optocoupler, a capacitive isolator, etc. The SBPD device (also referred to herein as a “source device”) may be a USB-compatible power supply device. The embodiments described herein can also be implemented in other types of power adapters, power converters, power supply circuits, etc.

[0038] Figure 1 This is a schematic diagram of a USB-PD power adapter 100 in one embodiment, which has a synchronous rectifier gate driver (SRGD) 136 with adaptive slew rate control integrated on a secondary-side controller 116 (also referred to as a power adapter secondary IC controller). In one embodiment, the USB-PD power adapter 100 can transmit information across an isolation barrier via a pulse transformer 130. In another embodiment, the USB-PD power adapter 100 can transmit information across an opto-isolator (…). Figure 1 (Not shown) transmits information. The USB-PD power adapter 100 includes a primary IC controller 114 and a secondary IC controller 116. The secondary IC controller 116 may be housed in a chip package and includes a USB-PD subsystem configured according to the techniques for gate driver control described herein. The secondary IC controller 116 is configured to negotiate a PD contract with a power-consuming device (not shown) attached to the USB Type-C port 140 and control the desired VBUS voltage output from the flyback transformer 108 via an output pin (“PWM_DRV”). The USB Type-C port 140 is typically associated with a Type-C plug, but it should be understood that in various embodiments, the USB Type-C port may alternatively be associated with a Type-C receptacle.

[0039] Secondary IC controller 116 includes SRGD 136. SRGD has a boost voltage generator circuit, a gate driver circuit, and a phase and shift controller circuit. The boost voltage generator circuit generates a boost supply voltage (2*Vddd) on the plate SR_CPP of the gate capacitor 190. The boost voltage is a voltage greater than the supply voltage of secondary IC controller 116. The boost voltage generator block uses a bootstrap principle to drive the gate capacitor to generate a boost voltage on the gate of the synchronous rectifier FET 112. The gate driver circuit drives the synchronous rectifier FET of the flyback converter. The phase and shift controller is the control block of the SRGD, which generates control signals for different operating phases of the driver and the desired shifts. Flyback transformer 108 is coupled to the rectified DC power supply, and its output can be coupled to the synchronous rectifier FET 112 (e.g., SR_FET 412). VBUS_IN is regulated by an error amplifier connected to compensation network 150. The compensation network 150 may be a resistor-capacitor (RC) circuit specific to the design of the USB-PD power adapter 100. The compensation network 150 may be coupled to receive a feedback signal from a first output pin (“FB”) of the secondary IC controller 116. The compensation network 150 may also be coupled to a second output pin (“EA_out”) and a third output pin (“CC_Comp”). The flyback transformer 108 may be coupled to a large-capacity capacitor 133 and a buffer circuit 137. The USB-PD power adapter 100 may also include a pulse transformer 130 (or other feedback control mechanism) for transmitting information across the isolation barrier 124.

[0040] An SRGD 136 integrated on the secondary IC controller 116 is coupled to the VBUS line 111 and configured to control the operation and state of a power switch (e.g., the power-side FET 138, also referred to herein as the secondary power switch). The SRGD 136 provides a synchronous switching scheme with adaptive switching control to charge and discharge the gate capacitor 190 to recycle charge and generate a boost voltage on the gate of the synchronous rectifier FET 112. In some embodiments, the gate capacitor 190 may be thermally charged and discharged. The VBUS line 111 includes the power-side FET 138, which is configured as an on / off switching device controlled by a signal (“VBUS_Control”) from an output pin in the secondary IC controller 116. The power-side FET 138 may correspond to the power-side FET described herein. In one embodiment, the power-side FET 138 may be an nFET. In another embodiment, the power-side FET 138 may be a pEFT. On one side of the power supply switch 138, power node 105 on VBUS line 111 is coupled to the second winding of flyback transformer 108, which is coupled to large capacitor 135 configured to suppress the AC component of the power signal. Power node 105 is coupled to an input pin (“VBUS_IN”) of secondary IC controller 116. On the other side of the power supply FET 138, output node 107 on VBUS line 111 is coupled to USB Type-C port 140. Output node 107 is coupled to another input pin (“VBUS_C”) of secondary IC controller 116. The GND terminal 142 of USB Type-C port 140 is coupled to synchronous rectifier FET 112.

[0041] In operation, the direction of power flow on VBUS line 111 is from flyback transformer 108 to the power-consuming device attached to USB Type-C port 140, such as a laptop computer (not shown). During PD contract negotiation with the power-consuming device, secondary IC controller 116 turns on power-consuming FET 138 to supply power to the power-consuming device at the negotiated voltage(s) and / or current levels. A high-to-low voltage transition on VBUS line 111 may be required when the PD contract is dynamically renegotiated to reduce VBUS voltage and / or current, for example, when the power-consuming device has finished charging its battery and now only needs power to operate.

[0042] A control signal can be sent to limit the gate-source voltage of the power-side FET 138 and turn off the power switch 138, thereby disconnecting the USB Type-C port 140 from the flyback transformer 108. The power-side FET 138 is turned off by driving the output of VBUS_Control to zero. Limiting the gate-source voltage of the power switch 138 protects the FET from damage. This disconnection may be caused by overvoltage conditions, overcurrent conditions, or other conditions that may require disconnecting the USB Type-C port 140 from the flyback transformer 108 to protect the circuitry coupled to the USB Type-C port 140.

[0043] In another embodiment, auxiliary circuitry 170 may be coupled to primary IC controller 114. An auxiliary output pin (“AUX_IN”) and an overvoltage protection auxiliary pin (“OVP_AUX”) are coupled to auxiliary circuitry 170. Auxiliary circuitry 170 can operate to protect against overvoltage of VBUS_IN111 and, once startup is complete, also provides power (AUX_IN) to primary IC 114.

[0044] As described above, the USB-PD power adapter 100 allows for a synchronous switching scheme with adaptive slew rate control to charge and discharge the gate capacitor 190 (e.g., change the charge thereon) and generate a boost voltage at the gate of the secondary-side FET (also referred to herein as a “synchronous rectifier FET”) via SRGD 136. The PWM driver circuitry of the secondary IC controller 116 can output a signal on an output pin (“PWM_DRV”) to transmit information across the isolation barrier 124 via pulse transformer 130. As described herein, the PWM driver circuitry can be other driver circuitry that generates pulses on the output pin to transmit information across the isolation barrier 124. The primary IC controller 114 can include detection circuitry that receives a signal on an input pin (“Pulse_In”) and detects when the secondary IC controller 116 transmits information. In another embodiment, the primary IC controller 114 can transmit information across the isolation barrier 122 via flyback transformer 108. The primary IC controller 114 can include circuitry for modifying the pulses received from the secondary IC controller 116 via pulse transformer 130. By changing the pulse, the primary IC controller 114 can send information across the flyback transformer 108 via the primary power switch 110. The secondary IC controller 116 may include circuitry that measures the drain (SR_DRAIN) of the secondary power switch 112 (e.g., a synchronous rectifier FET).

[0045] In another embodiment, the AC-DC power adapter device includes a flyback converter (with a flyback transformer) coupled between AC terminals and DC terminals or an isolated power converter. The flyback transformer converts AC power at the AC terminals into DC power at the DC terminals, wherein there is electrical isolation between the AC terminals and the DC terminals. The AC-DC power adapter device also includes a primary-side controller coupled to the flyback transformer and a secondary-side controller coupled to the flyback transformer. A primary-side power switch (also referred to as a primary-side switch FET or primary FET) is coupled to the primary winding of the flyback transformer and the primary-side controller. A secondary-side FET (also referred to as a synchronous rectifier FET) is coupled to the secondary winding of the flyback transformer and the secondary-side controller. The primary-side controller is configured to receive a first signal from the secondary-side controller across the electrical isolation barrier and, in response to the first signal, apply a second signal to the primary-side power switch to turn the primary-side power switch on and off. The SRGD of the secondary-side controller is also configured to generate a synchronous switching scheme with adaptive slew rate control to charge and discharge the gate capacitor and generate a boost voltage at the gate of the synchronous rectifier FET, as described herein.

[0046] In another embodiment, the primary-side controller includes a pulse receiver and a gate driver. The pulse receiver receives a first signal from the secondary-side controller across an electrical isolation barrier. The first signal includes a first turn-on pulse for turning on the primary-side power switch and a first turn-off pulse for turning off the primary-side power switch. In response, the driver coupled to the pulse receiver and the primary-side power switch applies the first turn-on pulse and the first turn-off pulse to the primary-side power switch.

[0047] In another embodiment, the AC-DC power adapter device includes a pulse transformer coupled between a primary-side controller and a secondary-side controller. The primary-side controller is configured to receive a first signal as one or more pulses from the secondary-side controller via the pulse transformer. As described herein, the primary-side controller can detect when the secondary-side controller transmits information via the pulse transformer.

[0048] The embodiments described herein can be implemented in a power supply system, such as a serial bus-compatible power supply device. Examples of serial bus-compatible power supply devices may include a Serial Bus Power Delivery (SBPD) device, a USB-compatible power supply device, and the like. In some embodiments, the SBPD device is a USB-PD device compatible with the USB-PD standard or more generally with the USB standard. For example, an SBPD device may be used to provide an output voltage (e.g., Vbus_in, power supply voltage) based on an input voltage (e.g., Vbus_c, power supply voltage). SBPD devices may include various embodiments described herein to facilitate communication between a primary-side controller and a secondary-side controller. SBPD devices may include a power converter (e.g., an AC-DC converter) and a power control analog subsystem (e.g., a USB-PD controller). The power control analog subsystem may include circuitry, functionality, or both as described herein for transmitting information across electrical isolation barriers.

[0049] In one embodiment, the SBPD device is connected to a power source, such as a wall outlet power supply providing AC power. In other embodiments, the power source may be a different power source, such as a battery, and may provide DC power to the SBPD device. A power converter may convert the power received from the power source (e.g., convert the received power to Vbus_in, which may be in the range of 3.3V to 21.5V). For example, the power converter may be an AC-DC converter, converting AC power from the power source into DC power. In some embodiments, the power converter is a flyback converter, such as a secondary-controlled flyback converter, which provides electrical isolation between the input (e.g., the primary side) and the output (e.g., the secondary side). In another embodiment, the device may be a power-consuming device that receives power from the SBPD device, wherein the power-consuming device may employ a synchronous switching scheme with adaptive slew rate control to charge and discharge its gate capacitor, and utilize the SBPD integrated on the secondary-side controller of the power-consuming device to generate a boost voltage at the gate of its synchronous rectifier FET.

[0050] In some embodiments, the SBPD device (e.g., via a communication channel (CC) specifying a particular output voltage and possibly also an output current) provides Vbus_c to the sink device. The SBPD device may also provide the sink device with access to ground potential (e.g., ground). In some embodiments, the provision of Vbus_c is compatible with the USB-PD standard. A power control analog subsystem may receive Vbus_in from the power converter. The power control analog subsystem may output Vbus_in. In some embodiments, the power control analog subsystem is a USB Type-C controller compatible with the USB Type-C standard. The power control analog subsystem may provide a system interrupt in response to Vbus_in and Vbus_c.

[0051] In some embodiments, any component of the SBPD device can be part of an IC, or alternatively, any component of the SBPD device can be implemented in its own IC. For example, both the power converter and the power control analog subsystem can be discrete ICs with independent packages and pin configurations.

[0052] In some embodiments, the SBPD device can provide a complete USB Type-C and USB-PD port control solution for laptops, dongles, monitors, expansion ports, power adapters, vehicle chargers, power banks, mobile adapters, etc.

[0053] One component that determines the efficiency of the USB-PD power adapter 100 is the synchronous rectifier FET 112 (also known as the secondary-side FET), which is coupled in parallel to the synchronous rectifier diode 192. The on-resistance (RDSon) of the synchronous rectifier FET 112 determines the voltage drop across it. Additionally, the turn-on and turn-off times of the synchronous rectifier FET determine the power loss across the synchronous rectifier diode 192, as the diode conducts current during the turn-on process until the FET 112 is turned on. Furthermore, faster turn-off may be required because once the conductor current crosses zero, it creates a short circuit between Vbus and ground. A lower on-resistance for the synchronous rectifier FET 112 can be achieved by increasing the voltage at its gate (e.g., to ~10V). Faster turn-on and turn-off times (e.g., ~100ns) can be determined by the drive strength of the SRGD. Then, in order to meet faster turn-on and turn-off times at the slowest process-voltage-temperature (PVT) angle, there may be adverse effects of high peak current and increased power and ground noise at fast PVT angles. Figure 2 A synchronous switching scheme with adaptive conversion rate control is described in more detail, which is designed to minimize power consumption, recycle gate charge between the gate capacitor and the gate of the synchronous rectifier FET, and reduce the peak current and noise of the SRGD.

[0054] Figure 2 This is a timing diagram of a synchronous switching scheme according to one embodiment, showing the switching current and voltage waveforms on the secondary side of the flyback converter. See again... Figure 1Initially, with the primary-side FET 110 turned on and the synchronous rectifier FET 112 turned off, the primary current increases as shown in graph 202. Voltage graph 206 shows the voltage at the drain node (SR_DRAIN) of the synchronous rectifier FET 112 increasing to 100V. When the primary-side FET 110 should be turned off and the synchronous rectifier FET turned on, the primary current decreases as shown in graph 202, and the secondary current increases as shown in graph 204. The voltage at the drain node of the synchronous rectifier FET 112 drops to -0.7V, which triggers the negative sensing detection shown in voltage graph 208. The negative sensing detection trigger is delayed to turn on SRGD 136, as shown in voltage graph 210. When the primary-side FET 110 is turned off and the synchronous rectifier FET 112 is turned on, the current in graph 204 decreases. The voltage at the drain of the synchronous rectifier FET 112 decreases. When this voltage crosses zero, zero-crossing detection is triggered, as shown in curve 212. The voltage on the gate of the synchronous rectifier FET decreases and takes a certain amount of time to reach 0V. This amount of time is the delay before the synchronous rectifier FET is turned off.

[0055] Figure 3 This is a schematic diagram of the phase and conversion controller circuit 380 of the SRGD integrated on the secondary-side controller in a secondary-controlled flyback converter according to one embodiment. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1 The secondary controlled flyback converter of the USB-PD power adapter is shown with similar reference numerals in the accompanying drawings. A phase and conversion controller can compare a first signal with a voltage at terminal 311 coupled to the gate of the synchronous rectifier FET and generate a control signal to thermally charge and discharge the gate capacitor 390, and generate a boost voltage of 2*Vddd (e.g., twice the supply voltage) by phase-divisionally recycling the charge from terminal 311 coupled to the gate of the synchronous rectifier FET to the gate capacitor 390.

[0056] The first phase Ф1 can be the default phase of the SRGD. In the first phase, terminal 389, coupled to the first plate of gate capacitor 390, is pulled up to the supply voltage level (Vddd), while terminal 311, coupled to the gate of the synchronous rectifier FET, and terminal 391, coupled to the second plate of gate capacitor 390, are pulled down to ground (0V). During the first phase, the phase and conversion controller circuit 380 can measure a signal with a first voltage at the gate of the synchronous rectifier FET and compare the first voltage with a second voltage (e.g., the supply voltage or Vddd). During the first phase, the first voltage is lower than the second voltage. During the second phase, terminal 311, coupled to the gate of the synchronous rectifier FET, begins to charge up to the supply voltage level Vddd. During the second phase, the phase and conversion controller circuit 380 measures a second signal at the gate of the synchronous rectifier FET. When the voltage of the second signal equals the second voltage (e.g., Vddd), the third phase is triggered. In one embodiment, comparator 384 detects when the voltage at terminal 311, coupled to the gate of the synchronous rectifier FET, reaches the supply voltage level Vddd and triggers a third phase. In the third phase Ф3, terminal 391, coupled to the second plate of the gate capacitor, is pulled up to the supply voltage level Vddd, and terminal 311, coupled to the gate of the synchronous rectifier FET, can be pulled up to a boost voltage level 2*Vddd via terminal 389, coupled to the first plate of the gate capacitor. During the third phase, phase and conversion controller circuitry 380 measures a third signal. At the end of the third phase, the voltage of the third signal reaches a third voltage level greater than the second voltage level (e.g., 2*Vddd). During the fourth phase, charge recycling occurs, and charge moves from terminal 311, coupled to the gate of the synchronous rectifier FET, to terminal 389, coupled to the first plate of the gate capacitor 390. The phase cycle can then be repeated. It should be noted that the term "phase" is used for simplicity.

[0057] Figure 4 This is a timing and voltage diagram 400 according to one embodiment, corresponding to the phase of the control signal generated by the phase and conversion controller to realize the operation of the SRGD on the secondary-side controller integrated in the secondary controlled flyback converter. Figure 3 The phase of SRGD operation is described in [the document], and slightly later in [the document]... Figure 7 This will be described in more detail below. In one embodiment, the phase and conversion controller may be... Figure 3 The phase and conversion controller 380. See again. Figure 1Graph 402 shows the voltage level at the gate of the synchronous rectifier FET 112 at the output (SR_GDRV) of SRGD 136. Graph 404 shows a first phase where the phase and shift controller generates a first control signal to enable operation of the SRGD, wherein the gate of the synchronous rectifier FET 112 can be at 0V, the first plate of the gate capacitor 190 can be at a first voltage level (Vddd, e.g., 5V, 3.3V, 3.5V, etc.), and the second plate of the gate capacitor 190 can be at 0V. Graph 406 shows a second phase where the phase and shift controller generates a second control signal to enable operation of the SRGD, during which the gate of the synchronous rectifier FET begins to charge from 0V to the first voltage level (e.g., Vddd). Graph 408 shows a third phase where the phase and shift controller generates a third control signal to enable operation of the SRGD. When the voltage at the gate of the synchronous rectifier FET 112 reaches a first voltage level (Vddd), the phase and transition controller can be triggered to generate a third control signal to enable the third phase. During the third phase, the gate of the synchronous rectifier FET 112 is charged from the first voltage level (Vddd) to a second voltage level (2*Vddd, e.g., 10V, 6.6V, 7V, etc.), the first plate of the gate capacitor is charged from the first voltage level (Vddd) to the second voltage level (2*Vddd), and the second plate of the gate capacitor is charged from 0V to the first voltage level (Vddd). Charge cycling can occur during the transition between the third phase and the first phase (e.g., from the gate of the synchronous rectifier FET 112 to the first plate of the gate capacitor). It should be noted that although 5V and 10V are used for Vddd and 2*Vddd relative to the described embodiment, alternatively, Vddd and 2*Vddd can be other values. Similarly, in other embodiments, multipliers other than 2 or approximately 2 can be implemented.

[0058] Figure 5 This is a block diagram of the SRGD536 integrated on the secondary-side controller of a secondary-controlled flyback converter according to one embodiment. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1The secondary controlled flyback converter of the USB-PD power adapter is shown in the accompanying drawings, as indicated by similar reference numerals. The illustrated embodiment demonstrates a novel architecture for a highly efficient and reliable secondary-side gate driver (e.g., SRGD 536). The SRGD 536 can generate an output voltage twice the IC supply voltage (Vddd). The SRGD 536 includes a boost voltage generator circuit 560, a gate driver circuit 570, and a phase and conversion controller circuit 580. The SRGD 536 is coupled to a gate capacitor 590 via terminals 589 and 591 and to a synchronous rectifier FET via terminal 511. Figure 5 The gate (not shown in the diagram). The combination of the boost voltage generator circuit 560, the gate driver circuit 570, and the phase and conversion controller circuit 580 is configured to generate a boost voltage at terminal 511 of the synchronous rectifier FET.

[0059] The boost voltage generator circuit 560 is responsible for generating a boost voltage supply (2*Vddd) at the first terminal 589 (SR_CPP) of the gate capacitor 590. The boost voltage generator circuit drives the gate capacitor 590 and uses a bootstrap principle to generate the boost voltage supply at the first terminal 589 (SR_CPP) of the gate capacitor 590. In one embodiment, the gate capacitor 590 may have a capacitance of 100nF. The boost voltage generator circuit 560 includes a first pull-up path 561, a second pull-up path 562, and a pull-down path 563.

[0060] The gate driver circuit 570 is configured to drive the synchronous rectifier FET ( Figure 5 (Not shown in the image). The gate driver circuit 570 includes a first pull-up path 571, a second pull-up path 572, and a pull-down path 573.

[0061] Phase and transition controller circuit 580 is configured to generate control signals for different phases of operation of SRGD 536, and is further configured to generate the desired transition for SRGD 536. The phase and transition controller circuit generates control signals for different operating phases by tracking the voltage level at terminal 511 of the synchronous rectifier FET. In one embodiment, to track the voltage level at terminal 511 of the synchronous rectifier FET, the phase and transition controller circuit measures the voltage at the gate of the synchronous rectifier FET and compares it with the supply voltage (Vddd) of the IC. This comparison can be made by a comparator, such as a tracking comparator 584. Phase and transition controller circuit 580 includes a phase and drive strength controller 581, a current generator 582, a transition generator 583, a tracking comparator 584, and a bias generator 585.

[0062] Figure 6This is a block diagram illustrating an embodiment of a boost voltage generator circuit and a gate driver circuit coupled to the phase and slew rate controller circuit of an SRGD integrated on the secondary-side controller of a secondary-controlled flyback converter. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1 The secondary controlled flyback converter of the USB-PD power adapter is shown in similar reference numerals in the attached figure.

[0063] The voltage generator circuit (e.g., for generating a boost voltage) includes pull-up path 661, pull-up path 662, and pull-down path 663. Pull-up path 661 is coupled to a gate capacitor (e.g., Figure 1 The gate capacitor is 190. Figure 6 Terminal 689 (not shown). Pull-up path 661 is further coupled to node 602 at voltage level Vddd. Node 602 is coupled between pull-up path 662 and pull-up path 661. Pull-up path 662 is coupled to node 602 and gate capacitor (e.g., Figure 1 The gate capacitor is 190. Figure 6 Between terminals 691 (not shown in the diagram). A pull-down path 663 is coupled between terminals 691 of the gate capacitor and node 604. Node 604 is at voltage level Vgnd, which is lower than Vddd.

[0064] The gate driver circuit includes pull-up path 671, pull-up path 672, and pull-down path 673. Pull-up path 671 is coupled to terminal 689 of the gate capacitor and coupled to the synchronous rectifier FET (e.g., ...). Figure 1 The synchronous rectifier FET 112, Figure 6 Between the gate terminals 611 (not shown in the diagram). Pull-up path 672 is coupled to pull-up path 671 and further coupled between node 602 and terminal 611 of the synchronous rectifier FET. Pull-down path 673 is coupled to pull-up path 672 and node 604.

[0065] Pull-up paths such as 661, 662, 671, and 672 can be circuits to provide a low-resistance path to node 602 (at the Vddd voltage level) when enabled and a high-resistance path to node 602 when disabled. Pull-up paths such as 661, 662, 671, and 672 can be pull-up elements, current sources, resistive elements, etc. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-up paths 661, 662, 671, and 672. Pull-down paths such as 663 and 673 can be circuits to provide a low-resistance path to node 604 (at the Vgnd voltage level) when enabled and a high-resistance path to node 604 when disabled. Pull-down paths such as 663 and 673 can be pull-down elements, current sinks, resistive elements, etc. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-down paths 663 and 673. Control signals for enabling or disabling the pull-up and pull-down paths of SRGD can be provided from the phase and conversion controller.

[0066] Pull-up path 661 (SR_CPP pull-up) includes switch 664 (P2) coupled to drive strength and slew rate controller 686. In one embodiment, switch 664 may be a p-channel FET (pEFT). (See again...) Figure 5 The drive strength and slew rate controller may include a phase and drive strength controller 581, a current generator 582 (e.g., a drive strength tracking iref generator), and a slew rate generator 583 (e.g., a delay-based slew rate generator). The drive strength and slew rate controller 686 may provide control signals to enable or disable (e.g., turn on or off; or conduct or turn off) switch 664. Switch 664 is coupled to switch 665 (P3). Switch 665 is coupled to level shifter 692. In one embodiment, level shifter 692 is an SR_CPP level shifter. In some embodiments, level shifter 692 may be a logic level shifter or a voltage level converter. In some embodiments, level shifter 692 may be a unidirectional level shifter or a bidirectional level shifter. Switch 665 is coupled to resistor 666a, and resistor 666a is coupled to terminal 689 (SR_CPP) of the gate capacitor. Switch 664 is coupled to node 602 at voltage level Vddd.

[0067] Pull-up path 662 (SR_CPN pull-up) includes switch 667 (P1) coupled to node 602. Switch 667 is further coupled to drive strength and slew rate controller 686, which can provide control signals to enable or disable switch 667. Resistor 666b is coupled between switch 667 and terminal 691 (SR_CPN) of gate capacitor.

[0068] The pull-down path 663 (SR_CPN pull-down) includes a resistor 666c coupled between terminal 691 of the gate capacitor and switch 668 (N1). Switch 668 is coupled to drive strength and slew rate controller 686, which can provide control signals to enable or disable switch 668. Switch 668 is further coupled to node 604 at the Vgnd voltage level. In some embodiments, switch 668 may be an n-channel FET (nEFT).

[0069] The pull-up path 671 (boost drive pull-up) includes a resistor 676a coupled between terminal 611 (SR_GDRV) of the synchronous rectifier FET and switch 674 (P4). Switch 674 is coupled to adaptive bias controller 687 (adaptive bias SR_CPP). See again... Figure 5 The adaptive bias controller 687 may include a phase and drive strength controller 581, a comparator 584 (e.g., an SR_DGRV tracking comparator), and an adaptive bias generator 585 (e.g., an adaptive bias for boost pull-up). The adaptive bias controller 687 is used to send control signals to enable or disable (e.g., turn on or off) switch 674 (e.g., by generating a voltage at the gate of switch 674 to minimize peak current and meet the rise and fall time requirements of the gate driver (SRGD)) and to generate a voltage (e.g., a boost voltage or driver voltage) at terminal 611 of the synchronous rectifier FET. A resistor 676b is coupled between terminal 689 of the gate capacitor and switch 674.

[0070] The pull-up path 672 (Vddd pull-up) includes a resistor 676c coupled between terminal 611 of the synchronous rectifier FET and switch 675 (P5). Switch 675 is coupled to level shifter 692. Switch 675 is coupled to switch 677 (P6). Switch 677 is coupled to drive strength and slew rate controller 686, which can provide control signals to enable or disable switch 677. Switch 677 is further coupled to node 602 at voltage level Vddd.

[0071] The pull-down path 673 (pull-down) includes a switch 678 (N2) coupled to terminal 611 of the synchronous rectifier FET and a drive strength and slew rate controller 686. The drive strength and slew rate controller can provide a control signal to enable or disable switch 678. Switch 678 is further coupled to node 604 at the Vgnd voltage level.

[0072] Switches 664, 665, 667, 668, 674, 675, 677, and 678 can be n-channel FETs (nFETs), p-channel FETs (pEFTs), bipolar transistors, or any combination of different types of switches. The drive strength and slew rate controller 686 can be at the Vddd voltage level. The level shifter 692 and the adaptive bias controller 687 can be at 2*Vddd voltage level (e.g., twice the Vddd voltage level). The adaptive bias controller is used to send control signals to enable or disable (e.g., turn on or off) the switches (e.g., by generating a voltage at the gate of the switch to minimize peak current and meet the rise and fall time requirements of the gate driver (SRGD)). Resistors 666a, 666b, 676a, 676b, and 676c can be pull-up elements, resistive elements, etc. Resistor 666c can be a pull-down element, resistive element, etc.

[0073] Refer again Figure 5 Phase and transition controller circuit 580 generates control signals to enable or disable pull-up paths 661, 662, 671, and 672, and to enable or disable pull-down paths 663 and 673. By enabling or disabling pull-up paths 661, 662, 671, and 672 and pull-down paths 663 and 673, phase and transition controller circuit 580 can control the SRGD to operate in one of the first, second, third, or fourth phases to implement a synchronous switching scheme with adaptive transition rate control to thermally charge and discharge gate capacitor 590 and generate a boost voltage (e.g., 2*Vddd) at terminal 511 of the synchronous rectifier FET, as referenced. Figure 7 In more detail, the conversion rate can be controlled by enabling (e.g., turning on) more devices over time, and the adaptive delay can be controlled by an adaptive conversion control circuit, as described in the reference. Figures 12A-12B As described in more detail. It should be noted that in other embodiments, the multiple FETs can be configured differently to thermally charge and discharge the gate capacitor for generating a boost voltage on the synchronous rectifier FET.

[0074] Figure 7This is a timing diagram illustrating the voltages on the gate capacitor and the gate of the synchronous rectifier FET during SRGD operation on a secondary-side controller integrated into a USB-PD power adapter according to one embodiment. Exemplary timing diagrams 791, 789, and 711 are shown, respectively, of the voltages on the negative plate of the gate capacitor, the positive plate of the gate capacitor, and the gate of the synchronous rectifier FET. In some embodiments, a synchronous switching scheme with adaptive slew rate control is used to thermally switch the gate capacitor (e.g., Figure 1 Gate capacitor 190 or Figure 5 The gate capacitor 590 is charged and discharged, and in the synchronous rectifier FET (e.g., Figure 1 A boost voltage (e.g., 2*Vddd or approximately 2*Vddd) greater than the supply voltage (Vddd) of the secondary-side controller is generated at the gate of the synchronous rectifier FET 112, which can reduce the power consumption of the secondary-side controller by 30%. Instead of directly charging the gate capacitor to the boost voltage using a charge pump, the gate capacitor can be charged adiabatically (e.g., consuming very little or no energy). The gate capacitor can be charged and discharged in phases, where the phase transition depends on the relative voltage difference between the supply voltage (Vddd) and the voltage on the gate of the synchronous rectifier FET. The SRGD (e.g., ...) described in this disclosure Figure 1 SRGD 136 or Figure 5 The SRGD 536 can have a positive plate (e.g., a first plate) with respect to the gate capacitor. Figure 1 Plate 189 Figure 5 589 or electrode plate (or terminal) Figure 6 The electrode plate (or terminal) 689), the negative electrode plate of the synchronous rectifier FET (e.g., the second electrode plate), Figure 1 Plate 191 Figure 5 591 or electrode plate (or terminal) Figure 6 The electrode plate (or terminal) 691) and the gate (e.g., Figure 5 Gate (or terminal) 511 or Figure 6 Information on the voltage on the gate (or terminal) 611.

[0075] In the illustrated embodiment, the positive plate of the gate capacitor can have a boost switching power supply voltage, the value of which can range between the internal chip power supply voltage Vddd and 2*Vddd. The positive plate of the gate capacitor can act as a pull-up voltage (e.g., Figure 5 The first pull-up path 571 or Figure 6 The pull-up path 671) is the source. The voltage on the negative plate of the gate capacitor can be between 0V and Vddd, so as to generate a boost voltage supply (2*Vddd) on the positive plate of the gate capacitor. Figure 5Terminal 511 or Figure 6 Terminal 611 can be coupled to the output of the SRGD to drive the gate voltage of the synchronous rectifier FET. The SRGD is used to control the voltage on the positive plate of the gate capacitor, the negative plate of the gate capacitor, and the gate of the synchronous rectifier FET in a series of phases.

[0076] Reference Figures 5-6 Complete the Figure 7 The remaining description is as follows. Initially, the gate of the synchronous rectifier FET is at 0V, the negative plate of the gate capacitor is at 0V, and the positive plate of the gate capacitor is at voltage Vddd. During the first phase (Ф1), SRGD is turned on, and the phase and conversion controller 580 generates a control signal to enable pull-up path 672. The voltage on the gate of the synchronous rectifier FET increases from 0V to Vddd. During the first phase, the voltages on the positive and negative plates of the gate capacitor remain unchanged. To charge the gate driver terminal 611 (SR_GDRV) (e.g., which is coupled to the gate of the synchronous rectifier FET) to Vddd, pull-up path 672 (Vddd pull-up) is enabled (e.g., turned on). While the voltage on terminal 611 is being charged from 0V to Vddd, tracking comparator 584 compares the voltage on terminal 611 with the supply voltage Vddd. When the voltage on terminal 611 reaches Vddd, tracking comparator 584 indicates the end of the first phase and the beginning of the second phase.

[0077] During the second phase (Ф2), the phase and transition controller 580 generates control signals to disable (e.g., turn off) pull-up paths 672 and 661 and enable pull-up path 662 to pull high the negative plate of the gate capacitor (e.g., terminal 691). The voltage on the negative plate of the gate capacitor changes from 0V to Vddd, the voltage on the positive plate of the gate capacitor changes from Vddd to 2*Vddd, and the voltage on the gate of the synchronous rectifier FET at terminal 611 changes from Vddd to 2*Vddd. The path from the boost supply (SR_CPP) to terminal 611 (e.g., the SRGD output (SR_GDRV)) is turned on. The bias generator 585 (adaptive bias for boost pull-up) biases pull-up path 671, which charges terminal 611 to 2*Vddd (boost voltage supply). When the voltage at terminal 611 reaches 2*Vddd, the tracking comparator 584 indicates the end of the second phase. It can maintain the voltage on the negative plate of the gate capacitor, the positive plate of the gate capacitor, and the gate of the synchronous rectifier FET until the third phase is enabled.

[0078] During the third phase (Ф3), the phase and transition controller 580 generates a control signal to enable pull-down path 663, thereby pulling the positive plate of the gate capacitor from 2*Vddd to Vddd. Charge from the gate of the synchronous rectifier FET at terminal 611 is circulated back to the gate capacitor via pull-up path 671, and the gate of the synchronous rectifier FET changes from 2*Vddd to Vddd. The negative plate of the gate capacitor changes from Vddd to 0V. When the voltage at terminal 611 reaches (or nearly reaches) Vddd, the tracking comparator 584 indicates the end of the third phase and the beginning of the fourth phase.

[0079] During the fourth phase (Ф4), the phase and switching controller 580 generates a control signal to enable (e.g., turn on) the pull-down path 673 to pull terminal 611 to ground (0V). The pull-up path 661 is enabled to recharge the gate capacitor's charge loss during the switching cycle. When the voltage at terminal 611 reaches 0V, the tracking comparator 584 indicates the end of the fourth phase. The switching cycle can then be repeated.

[0080] Figure 8 This is a block diagram of an SRGD 836 with a delay-based phase generator 882 integrated on the secondary-side controller of a secondary-controlled flyback converter according to one embodiment. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1 The secondary controlled flyback converter of the USB-PD power adapter is shown in the accompanying drawings, as indicated by similar reference numerals. The illustrated embodiment demonstrates an architecture for a highly reliable secondary-side gate driver (e.g., SRGD 836) that consumes virtually no power. The SRGD 836 can generate an output voltage twice the chip supply voltage (Vddd). The SRGD 836 includes a boost voltage generator circuit 860, a gate driver circuit 870, and a phase and conversion controller circuit 880. The SRGD 836 is coupled to a gate capacitor 890 via terminals 889 and 891, and to a synchronous rectifier FET via terminal 811. Figure 8 The gate (not shown in the diagram). The combination of the boost voltage generator circuit 860, the gate driver circuit 870, and the phase and conversion controller circuit 880 is configured to generate a boost voltage at terminal 811 of the synchronous rectifier FET.

[0081] The boost voltage generator circuit 860 is responsible for generating a boost voltage supply (2*Vddd) at the first terminal 889 (SR_CPP) of the gate capacitor 890. The boost voltage generator circuit drives the gate capacitor 890 and uses a bootstrap principle to generate the boost voltage supply at the first terminal 889 (SR_CPP) of the gate capacitor 890. In one embodiment, the gate capacitor 890 may have a capacitance of 100nF. The boost voltage generator circuit 860 includes a first pull-up path 861, a second pull-up path 862, and a pull-down path 863.

[0082] The gate driver circuit 870 is configured to drive the synchronous rectifier FET ( Figure 8 (Not shown in the image). The gate driver circuit 870 includes a first pull-up path 871, a second pull-up path 872, and a pull-down path 873.

[0083] Phase and transition controller circuit 880 is configured to generate control signals for different phases of operation of SRGD 836, and is further configured to generate the required transitions for SRGD 836. The phase and transition controller circuit generates control signals for different operating phases by tracking the voltage level at terminal 811 of the synchronous rectifier FET. In one embodiment, to track the voltage level at terminal 811 of the synchronous rectifier FET, the phase and transition controller circuit measures the voltage at the gate of the synchronous rectifier FET and compares it with the supply voltage (Vddd) of the IC. This comparison can be made by a comparator, such as a tracking comparator 884. Phase and transition controller circuit 880 includes phase and drive strength controller 881, delay-based phase generator 882, transition generator 883, tracking comparator 884, and bias generator 888.

[0084] The operation of the SRGD 800 can be similar to... Figure 5 The operation of the SRGD 500, but instead of tracking the voltage at terminal 811 and comparing it with the supply voltage (Vddd) using a high-speed comparator (e.g., tracking comparator 884), can use a time-based method. In this embodiment, the phase and transition controller 880 generates control signals independent of the response of the tracking comparator 884. After a fixed time delay defined by the delay-based phase generator 882, a control signal for switching between the second and third phases is generated.

[0085] Figure 9This document illustrates timing diagrams of the voltages on the gate capacitor and the gate of the synchronous rectifier FET during operation of an SRGD with a delay-based phase generator integrated on the secondary side controller of a USB-PD power adapter according to one embodiment. Exemplary timing diagrams 991, 989, and 911 are shown, respectively, of the voltages on the negative plate of the gate capacitor, the positive plate of the gate capacitor, and the gate of the synchronous rectifier FET. The gate capacitor (e.g., ...) can be phase-separated. Figure 1 Gate capacitor 190 or Figure 8 The gate capacitor 890 is charged and discharged, wherein the phase transition depends on a fixed time. In one embodiment, a phase hold duration can be enabled that is independent of the relative voltage between the gate of the synchronous rectifier FET and the supply voltage (Vddd). In one embodiment, a first phase hold duration can be enabled that is independent of the relative voltage between the gate of the synchronous rectifier FET and the supply voltage (Vddd), but can be programmed based on the synchronous rectifier gate capacitance. The gate driver will be in phase one for this delay duration, and when the timer completes the delay, a phase generator based on the delay generates a control signal to enter the second phase, at which point the gate driver enters the second phase. In the second phase, the negative plate (SR_CPN) of the gate capacitor is charged to the Vddd level, the positive plate (SR_CPP) of the gate capacitor is charged to 2*Vddd level, and the gate of the synchronous rectifier FET is charged to 2*Vddd level. Similarly, during the discharge phase (e.g., the third phase), SR_CPN is pulled down to ground, and charge is circulated from the gate of the synchronous rectifier FET back to SR_CPP until a delay-based phase generator generates a control signal for entering the fourth phase, where a pull-down path on the gate of the synchronous rectifier FET is enabled to pull it down to ground. The delay set for changing the phase is programmable and can be set according to the capacitance of the attached synchronous rectifier FET. In some embodiments, the negative plate can reach 0V, the positive plate can reach Vddd, and the gate of the synchronous rectifier FET can simultaneously reach 0V. When SRGD needs to enter a high state (e.g., power supply), the negative plate of the gate capacitor (SR_CPN) is pulled high.

[0086] Figure 10 This is a block diagram of an embodiment of a boost voltage generator circuit coupled to a phase and slew rate controller circuit of an SRGD integrated on the secondary-side controller of a secondary-controlled flyback converter, and a gate driver circuit with a pull-up path. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1 The secondary controlled flyback converter of the USB-PD power adapter is shown in similar reference numerals in the attached figure.

[0087] The voltage generator circuit includes pull-up paths 1061, 1062, and pull-down paths 1063. Pull-up path 1061 is coupled to a gate capacitor (e.g., ...). Figure 1 The gate capacitor is 190. Figure 10 Terminal 1089 (not shown). Pull-up path 1061 is further coupled to pull-up path 1062. Pull-up path 1062 is coupled to gate capacitor (e.g., Figure 1 The gate capacitor is 190. Figure 10 Terminal 1091 (not shown). Pull-down path 1063 is coupled between terminal 1091 of the gate capacitor and node 1004. Node 1004 is at voltage level Vgnd, which is lower than Vddd.

[0088] The gate driver circuit includes a pull-up path 1071 and a pull-down path 1073. The pull-up path 1071 is coupled to terminal 1089 of the gate capacitor and to the synchronous rectifier FET (e.g., ...). Figure 1 The synchronous rectifier FET 112, Figure 10 Between terminals 1011 (not shown in the image).

[0089] Pull-up paths such as 1061, 1062, and 1071 can be circuits that provide a low-resistance path to node 1004 (at Vddd voltage level) when enabled and a high-resistance path to node 1004 (at Vddd voltage level) when disabled. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-up paths 1061, 1062, and 1071. Pull-down paths such as 1063 and 1073 can be circuits that provide a low-resistance path to node 1004 (at Vgnd voltage level) when enabled and a high-resistance path to node 1004 when disabled. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-down paths 1063 and 1073. Control signals for enabling or disabling the pull-up and pull-down paths of SRGD can be provided from a phase and conversion controller.

[0090] The pull-up path 1061 (SR_CPP pull-up) includes a switch 1064 (P2) coupled to the drive strength and slew rate controller 1086. In one embodiment, switch 1064 may be a p-channel FET (pEFT). (See again...) Figure 5The drive strength and slew rate controller may include a phase and drive strength controller 581, a current generator 582, and a slew rate generator 583. The drive strength and slew rate controller 1087 may provide control signals to enable or disable (e.g., turn on or off; or conduct or turn off) switch 1064. Switch 1064 is coupled to switch 1065 (P3). Switch 1065 is coupled to level shifter 1092. In one embodiment, the level shifter is an SR_CPP level shifter. In some embodiments, level shifter 1092 may be a logic level shifter or a voltage level converter. In some embodiments, level shifter 1092 may be a unidirectional level shifter or a bidirectional level shifter. Switch 1065 is coupled to resistor 1066a, and resistor 1066a is coupled to terminal 1089 (SR_CPP) of the gate capacitor.

[0091] The pull-up path 1062 (SR_CPN pull-up) includes a switch 1067 (P1) coupled to a drive strength and slew rate controller 1086, which can provide a control signal to enable or disable the switch 1067. A resistor 1066b is coupled between the switch 1067 and the gate capacitor and terminal 1091 (SR_CPN).

[0092] The pull-down path 1063 (SR_CPN pull-down) includes a resistor 1066c coupled between terminal 1091 of the gate capacitor and switch 1068 (N1). Switch 1068 is coupled to drive strength and slew rate controller 1086, which can provide control signals to enable or disable switch 1068. Switch 1068 is further coupled to node 1004 at the Vgnd voltage level. In some embodiments, switch 1068 may be an n-channel FET (nEFT).

[0093] The pull-up path 1071 (boost drive pull-up) includes a resistor 1076a coupled between terminal 1011 (SR_GDRV) coupled to the gate of the synchronous rectifier FET and switch 1074 (P4). Switch 1074 is coupled to adaptive bias controller 1087 (adaptive bias SR_CPP). See again... Figure 5 The adaptive bias controller 1087 includes an adaptive bias generator (e.g., a phase and drive strength controller 581 and a bias generator 585). The adaptive bias controller 1087 is used to send control signals to enable or disable (e.g., turn on or off) the switch 1074. A resistor 1076b is coupled between the terminal 1089 of the gate capacitor and the switch 1074.

[0094] The pull-down path 1073 (pull-down) includes a switch 1078 (N2) coupled to terminal 1011 of the synchronous rectifier FET and a drive strength and slew rate controller 1086. The drive strength and slew rate controller 1086 can provide control signals to enable or disable switch 1078. Switch 1078 is further coupled to node 1004 at the Vgnd voltage level.

[0095] Switches 1064, 1065, 1067, 1068, 1074, and 1078 can be n-channel FETs (nFETs), p-channel FETs (pEFTs), bipolar transistors, or any combination of different types of switches. The drive strength and slew rate controller 1086 can be at the Vddd voltage level. The level shifter 1092 and the adaptive bias controller 1087 can be at a 2*Vddd voltage level (e.g., twice the Vddd voltage level). The adaptive bias controller is used to send control signals to enable or disable (e.g., turn on or off) the switches (e.g., by generating a voltage at the gate of the switch to minimize peak current and meet the rise and fall time requirements of the gate driver (SRGD)).

[0096] Refer again Figure 5 The phase and transition controller circuit 580 generates control signals to enable or disable pull-up paths 1061, 1062, and 1071, and to enable or disable pull-down paths 1063 and 1073. By enabling or disabling pull-up paths 1061, 1062, and 1071 and pull-down paths 1063 and 1073, the phase and transition controller circuit 580 can control the SRGD to operate in one of the first, second, third, or fourth phases to implement a synchronous switching scheme with adaptive transition rate control to thermally charge and discharge the gate capacitor 590 and generate a boost voltage (e.g., 2*Vddd) at terminal 511 of the synchronous rectifier FET.

[0097] exist Figure 10 In the illustrated embodiment, the gate capacitor can supply charge to the gate of the synchronous rectifier FET at terminal 1011 during both the first and second phases. Since there is only one pull-up path in the gate driver circuit, the area of ​​the SRGD can be reduced, which allows for a reduction in the bill of materials (BOM).

[0098] Figure 11 This is a block diagram of an embodiment of a boost voltage generator circuit and a gate driver circuit coupled to a phase and slew rate controller circuit with a diode-based SRGD integrated on the secondary-side controller of a secondary-controlled flyback converter. Although not all components of the secondary-controlled flyback converter are shown, the secondary-controlled flyback converter is similar to... Figure 1 The secondary controlled flyback converter of the USB-PD power adapter is shown in similar reference numerals in the attached figure.

[0099] The voltage generator circuit includes a diode 1161, a pull-up path 1162, and a pull-down path 1163. Diode 1161 is coupled to a gate capacitor (e.g., ...). Figure 1 The gate capacitor is 190. Figure 11 Plate 1189 (not shown). Diode 1161 is further coupled to node 1102 at voltage level Vddd. Node 1102 is coupled between pull-up path 1162 and diode 1161. Pull-up path 1162 is coupled between node 1102 and gate capacitor (e.g., ...). Figure 1 The gate capacitor is 190. Figure 11 Between terminals 1191 (not shown in the diagram). A pull-down path 1163 is coupled between terminals 1191 of the gate capacitor and node 1104. Node 1104 is at voltage level Vgnd, which is lower than Vddd.

[0100] The gate driver circuit includes pull-up paths 1171, 1172, and pull-down paths 1173. Pull-up path 1171 is coupled to terminal 1189 of the gate capacitor and the synchronous rectifier FET (e.g., ...). Figure 1 The synchronous rectifier FET 112, Figure 11 Between terminals 1111 (not shown in the diagram). Pull-up path 1172 is coupled to pull-up path 1171 and further coupled between node 1102 and terminal 1111 of the synchronous rectifier FET. Pull-down path 1173 is coupled to pull-up path 1172 and node 1104.

[0101] Pull-up paths such as 1162, 1171, and 1172 can be circuits that provide a low-resistance path to node 1102 (at the Vddd voltage level) when enabled and a high-resistance path to node 1102 when disabled. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-up paths 1162, 1171, and 1172. Pull-down paths such as 1163 and 1173 can be circuits that provide a low-resistance path to node 1104 (at the Vgnd voltage level) when enabled and a high-resistance path to node 1104 when disabled. Switches, FETs, MOSFETs, etc., can be used to enable or disable pull-down paths 1163 and 1173. Control signals for enabling or disabling the pull-up and pull-down paths of SRGD can be provided from a phase and conversion controller.

[0102] Pull-up path 1162 (SR_CPN pull-up) includes switch 1167 (P1) coupled to node 1102. Switch 1167 is further coupled to drive strength and slew rate controller 1186, which can provide control signals to enable or disable switch 1167. Resistor 1166b is coupled between switch 1167 and terminal 1191 (SR_CPN) of gate capacitor.

[0103] The pull-down path 1163 (SR_CPN pull-down) includes a resistor 1166c coupled between terminal 1191 of the gate capacitor and switch 1168 (N1). Switch 1168 is coupled to drive strength and slew rate controller 1186, which can provide control signals to enable or disable switch 1168. Switch 1168 is further coupled to node 1104 at the Vgnd voltage level. In some embodiments, switch 1168 may be an n-channel FET (nEFT).

[0104] The pull-up path 1171 (boost drive pull-up) includes a resistor 1176a coupled between terminal 1111 (SR_GDRV) of the synchronous rectifier FET and switch 1174 (P4). Switch 1174 is coupled to adaptive bias controller 1187 (adaptive bias SR_CPP). See again... Figure 5 The adaptive bias controller 1187 includes a phase and drive strength controller 581 and a bias generator 585. The adaptive bias controller 1187 is used to send control signals to enable or disable (e.g., turn on or off) the switch 1174. A resistor 1176b is coupled between the plate 1189 of the gate capacitor and the switch 1174.

[0105] Pull-up path 1172 (Vddd pull-up) includes resistor 1176c coupled between terminal 1111 of the synchronous rectifier FET and switch 1175 (P5). Switch 1175 is coupled to level shifter 1192. Switch 1175 is coupled to switch 1177 (P6). Switch 1177 is coupled to drive strength and slew rate controller 1186, which can provide control signals to enable or disable switch 1177. Switch 1177 is further coupled to node 1102 at voltage level Vddd.

[0106] The pull-down path 1173 (pull-down) includes a switch 1178 (N2) coupled to terminal 1111 of the synchronous rectifier FET and a drive strength and slew rate controller 1186. The drive strength and slew rate controller can provide a control signal to enable or disable switch 1178. Switch 1178 is further coupled to node 1104 at the Vgnd voltage level.

[0107] Switches 1167, 1168, 1174, 1175, 1177, and 1178 can be n-channel FETs (nFETs), p-channel FETs (pEFTs), bipolar transistors, or any combination of different types of switches. The drive strength and slew rate controller 1186 can be at the Vddd voltage level. The level shifter 1192 and the adaptive bias controller 1187 can be at a voltage level of 2*Vddd (e.g., twice the Vddd voltage level).

[0108] Refer again Figure 5 The phase and transition controller circuit 580 generates control signals to enable or disable pull-up paths 1162, 1171, and 1172, and to enable or disable pull-down paths 1163 and 1173, and to enable or disable diode 1161. By enabling or disabling pull-up paths 1162, 1171, and 1172, pull-down paths 1163 and 1173, and diode 1161, the phase and transition controller circuit 580 can control the SRGD to operate in one of the first, second, third, or fourth phases to implement a synchronous switching scheme with adaptive slew rate control to thermally charge and discharge the gate capacitor 590 and generate a boost voltage (e.g., 2*Vddd) at terminal 511 of the synchronous rectifier FET.

[0109] In one embodiment, diode 1161 may be disposed inside the SRGD. In another embodiment, the diode may be disposed outside the SRGD, for example, on a circuit board having a power supply voltage (Vddd) circuit. Reference Figure 6 By using a diode instead of pull-up path 661 (SR_CPP pull-up), the board area can be reduced.

[0110] Figure 12A This is a schematic diagram of a p-type metal-oxide-semiconductor (PMOS) drive intensity tracking current generator 1282a according to one embodiment. See again... Figure 5The PMOS drive strength tracking current generator 1282a can be a current generator 582. The PMOS drive strength tracking current generator 1282a includes a current source 1202a coupled to switch 1204a (which can be complementary to an absolute temperature (CTAT) current source, in which the current decreases with temperature). Switch 1204a is coupled to resistor 1206a. Switch 1208a is coupled between resistor 1206a, ground potential 1226a, and resistor 1210a. Switch 1212a is coupled to resistor 1210a. Switch 1214a is coupled to switch 1212a. Switch 1216a is coupled between switch 1214a and current source 1218a. Current source 1218a can be a reference current source (can be a current source with current constant relative to temperature). Switch 1220a is coupled to switch 1216a. Switch 1222a is coupled to switch 1220a. The output of the PMOS drive strength tracking current generator 1282a can be a current of 1224a.

[0111] In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to Figure 6 Pull-up paths 661, 662, and 672. In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to... Figure 6 Switches 664, 667, and 677. In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to... Figure 10 The pull-up paths 1061 and 1062. In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to... Figure 10 Switches 1064 and 1067. In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to... Figure 11 The pull-up paths 1162 and 1172. In one embodiment, the PMOS drive strength tracking current generator 1282a can be coupled to... Figure 11 Switches 1167 and 1186.

[0112] The drive strength tracking current generator 1282a can be used to generate a current 1224a. The drive strength tracking current generator 1282a tracks the SRGD pull-up circuit (e.g., Figure 6 Pull-up components 661, 662 and 672; Figure 10 Pull-up elements 1061 and 1062; or Figure 11 The drive strength of the pull-up elements 1162 and 1172. The drive strength tracking current generator 1282a tracks the switch corresponding to the pull-up element (e.g., ...). Figure 6 Switches 664, 667, 674, and 677; Figure 10Switches 1065 and 1067; or Figure 11 The drive intensity (1167, 1174, and 1186) is used to generate a current 1224a that may be inversely proportional to the drive intensity. Current 1224a can be used (e.g., by a delay-based conversion generator described in more detail in Figure 13) to generate a delay. In one embodiment, a higher current can result in a smaller (e.g., lower) delay at a slower process angle, and a lower current can result in a larger (e.g., higher) delay at a faster process angle. The drive intensity tracking current generator 1282a is compared with... Figure 13A The delay-based conversion generator combination described in more detail forms an adaptive conversion control circuit, which can be coupled to... Figure 5 The boost voltage generator circuit 560 and the gate drive circuit 570 are used to adaptively control the conversion rate. The current 1224A used to generate the delay is...

[0113]

[0114] Where vtp is the PMOS threshold voltage, k1 is the current replication gain, and Rs1 is the resistance of resistor 1210A. It should be noted that in other embodiments and with slight modifications, higher current can result in greater (e.g., higher) delay, while lower current can result in smaller delay.

[0115] Figure 12B This is a schematic diagram of an n-type metal-oxide-semiconductor (NMOS) drive intensity tracking current generator 1282b according to one embodiment. See again... Figure 5 The NMOS drive strength tracking current generator 1282b can be a current generator 582. The NMOS drive strength tracking current generator 1282b includes a current source 1202b coupled to switch 1214b. Switch 1214b is coupled to switch 1212b. Switch 1212b is coupled to resistor 1210b. Resistor 1210b is coupled to switch 1208b. Switch 1208b is coupled to switch 1204b. Switch 1204b is coupled to ground potential 1226b. Switch 1214b is further coupled to switch 1216b. Switch 1216b is coupled to current source 1218b. Current source 1218b can be a reference current source (relative to a temperature-constant current source). Switch 1216b is coupled to switch 1220b. Switch 1220b is coupled to switch 1222b. The output of the NMOS drive strength tracking current generator 1282ab can be a current 1224b.

[0116] In one embodiment, the NMOS drive strength tracking current generator 1282b can be coupled to Figure 6The pull-down paths 663 and 673. In one embodiment, the NMOS drive strength tracking current generator 1282a can be coupled to... Figure 6 Switches 668 and 678. In one embodiment, the NMOS drive strength tracking current generator 1282b can be coupled to... Figure 10 The pull-down paths 1063 and 1073. In one embodiment, the NMOS drive strength tracking current generator 1282a can be coupled to... Figure 10 Switches 1068 and 1078. In one embodiment, the NMOS drive strength tracking current generator 1282b can be coupled to... Figure 11 The pull-down paths 1163 and 1173. In one embodiment, the NMOS drive strength tracking current generator 1282a can be coupled to... Figure 11 Switches 1168 and 1178.

[0117] The drive strength tracking current generator 1282b can be used to generate current 1224b. The drive strength tracking current generator 1282b tracks the SRGD pull-down circuit (e.g., Figure 6 The pull-down components 663 and 673; Figure 10 The pull-down elements 1063 and 1073; or Figure 11 The drive strength of the pull-down elements 1163 and 1173. The drive strength tracking current generator 1282b tracks the switch corresponding to the pull-down element (e.g., Figure 6 Switches 668 and 678; Figure 10 Switches 1068 and 1078; or Figure 11 The drive strength of current generator 1282b is tracked by current generator 1168 and 1178, and a current 1224b is generated that may be inversely proportional to the drive strength. Current 1224b can be used (e.g., by a delay-based conversion generator described in more detail in Figure 13) to generate a delay. In one embodiment, a higher current can result in a smaller (e.g., lower) delay at a slower process angle, and a lower current can result in a larger (e.g., higher) delay at a faster process angle. The drive strength tracking current generator 1282b is... Figure 13B The delay-based conversion generator combination described in more detail forms an adaptive conversion control circuit, which can be coupled to... Figure 5 The boost voltage generator circuit 560 and the gate drive circuit 570 are used to adaptively control the conversion rate. The current 1224b used to generate the delay is...

[0118]

[0119] Where vtn is the NMOS threshold voltage, k2 is the current replication gain, Rs2 is the resistance of resistor 1210b, and Rdson_Ns11 is the on-resistance of switch 1204b (linear MOSFET NS11).

[0120] Figure 13A This is a schematic diagram of a delay-based conversion generator 1383a for a PMOS device according to one embodiment. The delay-based conversion generator 1383a is coupled to a series of MOSFET branches 1304a. In one embodiment, the MOSFET branches may be pEFT. A current 1324a is input to the delay-based conversion generator 1383a. In one embodiment, the current 1324a may be the current 1224a of FIG. 12. In another embodiment, the current 1324a may be a current generated by an external component. The current source of the current 1324a is coupled to a series of current-starved inverters 1302a (e.g., current inverters). The current-starved inverters 1302a may be coupled to each other in a cascaded mode. A reference current 1342a in the current-starved inverters 1302a can determine the delay. To control the conversion rate of the driver, the MOSFET branches 1304a are turned on and off based on the delay generated by the delay-based conversion generator.

[0121] In one embodiment, the delay-based conversion generator 1383a can be coupled to the PMOS drive strength tracking current generator 1282a. The delay-based conversion generator coupled to the PMOS drive strength tracking current generator 1282a forms... Figure 6 The drive strength and slew rate controller 686. In one embodiment, the delay-based conversion generator 1383a can be coupled to... Figure 6 Pull-up paths 661, 662, and 672. In one embodiment, the delay-based conversion generator 1383a can be coupled to... Figure 6 Switches 664, 667, and 677. In one embodiment, a delay-based conversion generator 1383a can be coupled to... Figure 10 The pull-up paths 1061 and 1062. In one embodiment, the delay-based conversion generator 1383a can be coupled to... Figure 10 Switches 1064 and 1067. In one embodiment, a delay-based conversion generator 1383a can be coupled to... Figure 11 The pull-up paths 1162 and 1172. In one embodiment, the delay-based conversion generator 1383a can be coupled to... Figure 11 Switches 1167 and 1186.

[0122] Figure 13BThis is a schematic diagram of a delay-based conversion generator 1383b for an NMOS device according to one embodiment. The delay-based conversion generator 1383b is coupled to a series of MOSFET branches 1304b. In one embodiment, the MOSFET branches may be nEFT. A current 1324b is input to the delay-based conversion generator 1383b. In one embodiment, the current 1324b may be the current 1224b of FIG. 12. In another embodiment, the current 1324b may be a current generated by an external component. The current source of the current 1324b is coupled to a series of current-starved inverters 1302b. The current-starved inverters 1302b may be coupled to each other in a cascaded mode. A reference current 1342b in the current-starved inverters 1302b can determine the delay. To control the conversion rate of the driver, the MOSFET branches 1304b are turned on and off based on the delay generated by the delay-based conversion generator.

[0123] In one embodiment, the delay-based conversion generator 1383b can be coupled to the NMOS drive strength tracking current generator 1282b. The delay-based conversion generator coupled to the NMOS drive strength tracking current generator 1282b forms... Figure 6 The drive strength and slew rate controller 686. In one embodiment, the delay-based conversion generator 1383b can be coupled to... Figure 6 The dropdown paths 663 and 673. In one embodiment, the delay-based conversion generator 1383b can be coupled to... Figure 6 Switches 668 and 678. In one embodiment, the delay-based conversion generator 1383b can be coupled to... Figure 10 The drop-down paths 1063 and 1073. In one embodiment, the delay-based conversion generator 1383b can be coupled to... Figure 10 Switches 1068 and 1078. In one embodiment, a delay-based conversion generator 1383b can be coupled to... Figure 11 The dropdown paths 1163 and 1173. In one embodiment, the delay-based conversion generator 1383b can be coupled to... Figure 11 Switches 1168 and 1178.

[0124] Figure 14 This is a schematic diagram of a pull-up path 1471 with an adaptive bias controller for an SRGD according to one embodiment. Although not all components of the SRGD are shown, the SRGD is similar to... Figure 6 The SRGD, as shown by similar reference numerals in the accompanying drawings. In one embodiment, pull-up path 1471 can be... Figure 6 The pull-up path 671. In another embodiment, the pull-up path 1471 can be... Figure 10The pull-up path 1071. In another embodiment, the pull-up path 1471 can be... Figure 11 The pull-up path is 1171.

[0125] The pull-up path 1471 (boost drive pull-up) includes a resistor 1476a coupled between the output 1411 (SR_GDRV) of the synchronous rectifier FET gate and the switch 1474 (P4). Switch 1474 is coupled to an adaptive bias controller 1487 (adaptive bias SR_CPP). See again... Figure 5 The adaptive bias controller 1487 includes a phase and drive strength controller 581 and a bias generator 585. The adaptive bias controller 1487 is used to send control signals to enable or disable (e.g., turn on or off) the switch 1474. A resistor 1476b is coupled between the plate 1489 of the gate capacitor and the switch 1474. In one embodiment, the gate capacitor is... Figure 1 The gate capacitor 190. In another embodiment, the gate capacitor is... Figure 5 The gate capacitor 590. In another embodiment, the gate capacitor is... Figure 8 The gate capacitor is 890.

[0126] The adaptive bias controller 1487 includes a switch 1402 coupled to a switch 1474 and a switch 1404 coupled to both switches 1474 and 1402. Switch 1402 is coupled to a plate 1489 of a gate capacitor. Current 1406 flows between switches 1404 and 1474. Capacitor 1410 is coupled between switches 1402 and 1412. Switch 1414 is coupled to switch 1412. Resistor 1416 is coupled to switch 1414. Switch 1418 is coupled between resistors 1416 and 1420. Resistor 1420 is coupled to ground potential 1422. Current 1424 flows between resistors 1416 and 1420.

[0127] For example, such as Figures 12A-12B and Figures 13A-12B The adaptive delay occurs to help control the SRGD to operate at the supply voltage (Vddd) during the first and fourth phases, as described in the reference. Figure 7 As described above. (See reference) Figure 7During the second and third phases, the SRGD operates at a boost supply voltage (e.g., 2*Vddd). An adaptive bias controller 1487 can provide an adaptive bias scheme to mitigate these issues by tracking the drive strength and reducing the peak current on the pull-up path operating at the boost supply voltage. The adaptive bias scheme can be used in the path from the boost voltage supply (e.g., the plate 1489 of the gate capacitor) to the output 1411 of the SRGD, which supplies voltage at the gate of the synchronous rectifier FET. In one embodiment, the synchronous rectifier FET may be... Figure 1 The synchronous rectifier FET 112. The adaptive bias controller 1487 is configured to generate a bias based on the pull-up switch of the SRGD operating at the boost supply voltage (e.g., based on angle and temperature) to adaptively control the drive strength of the boost pull-up path, and can help control (e.g., at the output 1411 of the SRGD) the gate voltage to adaptively control the drive strength of the synchronous rectifier FET.

[0128] Figure 15A Graph 1500a illustrates the delay variation of PMOS delay cells at both ends of the SRGD pull-up path angle in an adaptive switching control block according to one embodiment. The horizontal axis labels from left to right represent fast PMOS and fast NMOS cells, fast PMOS and slow NMOS cells, slow PMOS and fast NMOS cells, slow PMOS and slow NMOS cells, and typical PMOS and typical NMOS cells. Graph 1503 corresponds to a 3V supply voltage level Vddd. Graph 1505a corresponds to a 5V supply voltage level Vddd.

[0129] Figure 15B This is graph 1500b, illustrating the delay variation of NMOS delay cells at both ends of the SRGD pull-down path angle in an adaptive switching control block according to one embodiment. The horizontal axis labels from left to right represent fast PMOS and fast NMOS cells, fast PMOS and slow NMOS cells, slow PMOS and fast NMOS cells, slow PMOS and slow NMOS cells, and typical PMOS and typical NMOS cells. Graph 1503b corresponds to a 3V supply voltage level Vddd. Graph 1505b corresponds to a 5V supply voltage level Vddd.

[0130] Figure 16This is a schematic diagram of a USB-PD power adapter 1600 according to one embodiment, which has a synchronous rectifier gate driver (SRGD) 1636a integrated on a secondary-side controller 1616a (also referred to as a power adapter secondary IC controller) to deliver power from a power-side device 1672a to an attached power-consuming device 1672b. When the power-consuming device 1672b is connected to the power-side device 1672a, the power-side SRGD 1636a can enable or disable a power-side FET 1638a (also referred to as a power-side nFET, power-side switch, or secondary-side FET) to deliver power to the attached power-consuming device 1672c. For example, the power-side secondary gate driver 1636a can enable the power-side FET 1638a when power is to be delivered to the attached power-consuming device 1672b. Alternatively or additionally, the power supply secondary gate driver 1636a may disable the power supply FET 1638a when no power is supplied to the attached power-consuming device 1672c.

[0131] In one embodiment, the power-consuming device 1672b may be a USB-PD power-consuming device having a synchronous rectifier gate driver (SRGD) 1636b integrated on a secondary-side controller 1616b of the power-consuming device to receive power from an attached power-consuming device 1672a (e.g., to charge the battery of the power-consuming device 1672b). When the power-consuming device 1672a is connected to the power-consuming device 1672b (e.g., acting as a power source), the power-consuming SRGD 1636b may enable or disable the power-consuming FET 1638b (e.g., a power-consuming nFET, a power-consuming switch) to receive power from the attached power-consuming device 1672a. For example, in one embodiment, the power-consuming SRGD 1636b may enable the power-consuming FET 1638b when it wants to receive power from the attached power-consuming device 1672a to charge a battery. Alternatively or additionally, the power-consuming SRGD 1636b can disable the power-consuming FET 1638b when it is not receiving power from the power-consuming device 1672a.

[0132] In another embodiment, the power-consuming device 1672b may be a USB-PD power-consuming device to receive power from the attached power-consuming device 1672a (e.g., to charge the battery of the power-consuming device 1672b). When the power-consuming device 1672a is connected to the power-consuming device 1672b (e.g., acting as a power source), the power-consuming device SRGD 1636a may enable or disable the power-consuming FET 1638a (e.g., a power-consuming nFET, a power-consuming switch) and the power-consuming FET 1638b (e.g., a power-consuming nFET, a power-consuming switch), such that the power-consuming device 1672a provides power to the power-consuming device 1672b, and the power-consuming device 1672b receives power from the attached power-consuming device 1672a. For example, in one embodiment, the power-consuming device SRGD 1636a may enable the power-consuming FET 1638a and the power-consuming FET 1638b when power is to be received from the attached power-consuming device 1672a to charge a battery. Alternatively or additionally, the power supply SRGD 1636b may disable the power supply FET 1638a and the power consumption FET 1638b when not receiving power from the power supply device 1672.

[0133] Although not all components of the power-consuming SRGD 1636b are shown, the power-consuming SRGD 1636b is similar to the power-generating SRGD 1636a, as indicated by similar reference numerals. The SRGD 1636b includes a boost voltage generator circuit, a gate driver circuit, and a phase and conversion controller circuit. The SRGD 1636b is coupled to a gate capacitor (…). Figure 16 (not shown in the image) and synchronous rectifier FET ( Figure 16 The gate (not shown). A combination of a boost voltage generator circuit, a gate driver circuit, and a phase and conversion controller circuit is configured to generate a boost voltage on the gate of the synchronous rectifier FET.

[0134] Figure 17 This is a block diagram illustrating a system 1700 for a USB device used in USB-Powered devices according to some embodiments. System 1700 may include a peripheral subsystem 1710, which includes multiple components used in USB-PD. Peripheral subsystem 1710 may include a peripheral interconnect 1711, which includes a clock module and a peripheral clock (PCLK) 1712 for providing clock signals to various components of peripheral subsystem 1710. Peripheral interconnect 1711 may be a peripheral bus, such as a single-level or multi-level Advanced High-Performance Bus (AHB), and may provide a data and control interface between peripheral subsystem 1710, CPU subsystem 1730, and system resource 1740. Peripheral interconnect 1711 may include controller circuitry, such as a direct memory access (DMA) controller, which can be programmed to transfer data between peripheral blocks without requiring input, control, or other overhead from CPU subsystem 1730.

[0135] Peripheral interconnect 1711 can be used to couple components of peripheral subsystem 1710 to other components of system 1700. Coupled to peripheral interconnect 1711 can be multiple general purpose input / output (GPIO) 1715s for transmitting and receiving signals. GPIO 1715s can include circuitry configured to implement various functions, such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single multiplexing, etc. Other functions can also be implemented by GPIO 1715s. One or more timer / counter / pulse width modulator (TCPWM) 1717s can also be coupled to peripheral interconnects and include circuitry for implementing timing circuitry (timers), counters, pulse width modulator (PWM) decoders, and other digital functions that can operate on I / O signals and provide digital signals to system components of system 1700. The peripheral subsystem 1710 may also include one or more serial communication blocks (SCBs) 1719 for implementing serial communication interfaces, such as I2C, serial peripheral interface (SPI), universal asynchronous receiver / transmitter (UART), controller area network (CAN), clock extended peripheral interface (CXPI), etc.

[0136] For USB-Powered applications, the peripheral subsystem 1710 may include a USB power supply system 1720 coupled to a peripheral interconnect and including a set of USB-PD modules 1721 for use in USB-Powered applications. The USB-PD modules 1721 may be coupled to the peripheral interconnect 1711 via a USB-PD interconnect 1723. The USB-PD module 1721 may include an analog-to-digital converter (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line according to the PD contract; a high-voltage (HV) regulator for converting the power supply voltage into a precise voltage (e.g., 3.5-5V) for supplying the power system 1700; a low-side current sense amplifier (LSCSA) for accurately measuring load current; an overvoltage protection (OVP) module and an overcurrent protection (OCP) module for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field-effect transistors (FETs) used in USB power supply in a provider-consumer configuration; and a communication channel PHY (CC BB PHY) module for supporting communication on the Type-C communication channel (CC) line. The USB-PD module 1721 may also include a charger detection module for determining the presence of a charging circuit and coupled to the system 1700, and a VBUS discharge module for controlling the discharge of the voltage on the VBUS line. Specifically, one or more gate drivers for the external power FET include a synchronous rectifier gate driver (SRGD) integrated on the secondary-side controller to provide a synchronous switching scheme with adaptive slew rate control for adiabatic charging and discharging of the gate capacitor and to generate a boost voltage (e.g., 2*Vddd) at the gate of the synchronous rectifier FET. As described in this disclosure, the SRGD includes boost voltage generator circuitry, gate driver circuitry, and phase and conversion controller circuitry. A discharge control module can be configured to be coupled to a power node on the VBUS line or an output (power receiving) node on the VBUS line and to discharge the voltage on the VBUS line to a desired voltage level (i.e., the voltage level negotiated in the PD contract). The USB power supply system 1720 may also include pads 1727 for external connections and electrostatic discharge (ESD) protection circuitry 1729 that may be required on the Type-C port. The USB-PD module 1721 may also include a communication module for retrieving information stored in non-volatile memory and transmitting information between one controller and another, for example, between the primary-side controller and the secondary-side controller of a flyback converter.

[0137] GPIO 1715, TCPWM 1717, and SCB 1719 can be coupled to the input / output (I / O) subsystem 1750, which may include a high-speed (HS) I / O matrix 1751 coupled to multiple GPIO 1753s. GPIO 1715, TCPWM 1717, and SCB 1719 can be coupled to GPIO 1753s via the HS I / O matrix 1751.

[0138] System 1700 may also include a central processing unit (CPU) subsystem 1730 for processing commands, stored program information, and data. CPU subsystem 1730 may include one or more processing units 1731 for executing instructions and reading from and writing to memory locations in a plurality of memories. Processing unit 1731 may be a processor adapted to operate in an integrated circuit (IC) or system-on-a-chip (SOC) device. In some embodiments, processing unit 1731 may be optimized for low-power operation with extensive clock gating. In this embodiment, various internal control circuitry may be implemented for processing unit operation in various power states. For example, processing unit 1731 may include a wake-up interrupt controller (WIC) configured to wake the processing unit from a sleep state, thereby allowing power to be cut off when the IC or SOC is in a sleep state. CPU subsystem 1730 may include one or more memories, including flash memory 1733, static random access memory (SRAM) 1735, and read-only memory (ROM) 1737. Flash memory 1733 may be a non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 1733 may include a read accelerator and may improve access time by integration within CPU subsystem 1730. SRAM 1735 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 1731. ROM 1737 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of system 1700. SRAM 1735 and ROM 1737 may have associated control circuitry. Processing unit 1731 and the memory may be coupled to system interconnect 1739 to route signals to and from various components of CPU subsystem 1730 to other blocks or modules of system 1700. System interconnect 1739 may be implemented as a system bus such as a single-level or multi-level AHB. System interconnect 1739 may be configured as an interface that couples various components of CPU subsystem 1730 to each other. System interconnect 1739 can be coupled to peripheral interconnect 1711 to provide a signal path between components of CPU subsystem 1730 and peripheral subsystem 1710.

[0139] System 1700 may also include multiple system resources 1740, including a power module 1741, a clock module 1743, a reset module 1745, and a test module 1747. Power module 1741 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a PWRSYS module. In some embodiments, power module 1741 may include circuitry that allows system 1700 to draw and / or supply power from / to an external source at different voltage and / or current levels and supports the controller to operate in different power states, such as running, low power, or sleep. In various embodiments, more power states may be implemented when system 1700 throttles its operation to achieve desired power consumption or output. Clock module 1743 may include a clock control module, a watchdog timer (WDT), an internal low-speed oscillator (ILO), and an internal master oscillator (IMO). Reset module 1745 may include a reset control module and an external reset (XRES) module. Test module 1747 may include modules for controlling and entering test modes, as well as test control modules for analog and digital functions (digital test and analog DFT).

[0140] System 1700 can be implemented in a single (e.g., a single) semiconductor die. In other embodiments, various portions or modules of system 1700 can be implemented on different semiconductor dies. For example, the memory module of CPU subsystem 1730 can be on-chip or discrete. In other embodiments, discrete die circuitry can be packaged into a single "chip" or kept discrete and disposed as discrete elements on a circuit board (or in a USB cable connector).

[0141] System 1700 can be implemented in various application scenarios to provide USB-PD functionality. In each application scenario, an IC controller or SOC implementing System 1700 can be set up and configured in an electronic device (e.g., a USB-enabled device) to perform operations according to the techniques described herein. In one example embodiment, System 1700 can be set up and configured in a power adapter for a personal computer (PC) such as a laptop computer, notebook computer, etc. In another example embodiment, System 1700 can be set up and configured in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smartphone, tablet computer, etc.). In another example embodiment, System 1700 can be set up and configured in a wall outlet configured to provide power through one or more USB Type-A and / or Type-C ports. In another example embodiment, System 1700 can be set up and configured in a vehicle charger configured to provide power through one or more USB Type-A and / or Type-C ports. In yet another example embodiment, system 1700 may be set up and configured in a power bank that can be charged and then supply power to another electronic device via a USB Type-A or Type-C port. In other embodiments, systems similar to system 1700 may be configured with the power switch gate control circuitry described herein and may be located in a variety of other USB-enabled electronic or electromechanical devices.

[0142] It should be understood that systems, such as system 1700 implemented on or as an IC controller, can be configured for different applications, which may vary depending on the type and direction of the power supply used. For example, in the case of a car charger, the power supply is a car battery providing DC power, while in the case of a power adapter, the power supply is an AC wall socket. Furthermore, in the case of a PC power adapter, the supply current is from the supplying device to the consuming device, while in the case of a power bank, the supply current can be in both directions, depending on whether the power bank operates as a power provider (e.g., supplying power to another device) or as a power consumer (e.g., charging itself). For these reasons, the various applications of system 1700 should be considered illustrative rather than limiting.

[0143] Figure 18This is a flowchart of method 1800 according to one embodiment, which synchronously switches a synchronous rectifier FET by means of an SRGD with adaptive switching control to thermally charge and discharge the gate capacitor to recycle the charge and generate a boost voltage on the gate of the synchronous rectifier FET. Method 1800 can be executed by a processing logic unit including hardware (e.g., circuitry, dedicated logic unit, programmable logic unit, microcode, etc.), software, firmware, or a combination thereof. In one embodiment, method 1800 is executed by an SRGD integrated on the secondary-side controller of a USB-PD power adapter. In another embodiment, Figure 1 The SRGD136 execution method 1800. In another embodiment, Figure 5 The SRGD 500 executes method 1800. In another embodiment, Figure 6 The SRGD 600 executes method 1800. In another embodiment, Figure 8 The SRGD 800 executes method 1800. In another embodiment, Figure 10 The SRGD 1000 executes method 1800. In another embodiment, Figure 11 The SRGD1100 executes method 1800. In another embodiment, Figure 16 The SRGD 1636a execution method 1800. In another embodiment, Figure 16 The SRGD 1636b execution method 1800. In another embodiment, Figure 17 SRGD 1736 execution method 1800.

[0144] refer to Figure 18 Method 1800 begins with the processing logic unit measuring the gate voltage at the gate of a synchronous rectifier FET coupled to an SRGD (block 1802), the SRGD being integrated on the secondary-side controller of a secondary-side controlled AC-DC converter. The secondary-side controlled AC-DC converter can be an AC-DC power supply or an AC-DC power converter. The AC-DC power converter can be a secondary-side controlled AC-DC flyback converter with an electrical isolation barrier. The processing logic unit controls the primary-side FET across the electrical isolation barrier of the AC-DC power converter (block 1804). The processing logic unit compares the gate voltage at the gate of the synchronous rectifier FET with a supply voltage (e.g., Vddd) from the secondary-side controller (block 1806). Based on the result of the comparison, the processing logic unit thermally charges or discharges the gate capacitor of the SRGD (block 1808). The processing logic unit outputs a control signal to the gate of the synchronous rectifier FET to drive the synchronous rectifier FET (block 1810). Once the logic unit outputs the control signal, method 1800 ends.

[0145] In another embodiment, the gate capacitor is thermally charged or discharged in one of the four phases. A control signal can further signal the SRGD to indicate the phase to be operated. During the first phase (Ф1), the SRGD is turned on, and the voltage on the gate of the synchronous rectifier FET changes from 0V to Vddd. During the first phase, the voltages on the positive and negative plates of the gate capacitor remain constant. During the second phase (Ф2), the voltage on the negative plate of the gate capacitor changes from 0V to Vddd, the voltage on the positive plate of the gate capacitor changes from Vddd to 2*Vddd, and the voltage on the gate of the synchronous rectifier FET at the output changes from Vddd to 2*Vddd. During the third phase (Ф3), the voltage on the positive plate of the gate capacitor changes from 2*Vddd to Vddd. The gate of the synchronous rectifier FET changes from 2*Vddd to Vddd. The negative plate of the gate capacitor changes from Vddd to 0V. During the fourth phase (Ф4), the voltage at terminal 611 reaches 0V. Then you can repeat the on / off cycle.

[0146] In another embodiment, the processing logic unit controls the delay of the control signal to control the conversion rate of the SRGD. The processing logic unit provides a control signal to the gate driver circuitry of the SRGD, enabling the gate driver circuitry to drive the synchronous rectifier FET using a gate capacitor.

[0147] In the above description, some parts of the specific implementation are presented according to algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are means used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of steps leading to a desired result. These steps are those requiring physical operations on physical quantities. Typically, although not always necessary, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0148] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, as is apparent from the above discussion, it can be understood that throughout the description, discussions using terms such as “receive” and “adjust” refer to the actions and processes of a computing system or similar electronic computing device that manipulate and transform data representing physical (e.g., electronic) quantities within the registers and memories of the computing system into other data representing physical quantities similarly represented within the memory or registers of the computing system or other such information storage, transmission, or display devices.

[0149] The terms “example” or “exemplary” are used herein to mean something used as an example, instance, or illustration. Any aspect or design described herein as an “example” or “exemplary” should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present concepts in a specific manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X comprises A or B” is intended to mean any natural inclusion. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Additionally, unless otherwise specified or clear from the context, the article “a” used herein and in the appended claims should generally be construed as meaning “one or more.” Furthermore, unless so described, the use of the terms “embodiment” or “an embodiment” throughout the text is not intended to represent the same embodiment.

[0150] The embodiments described herein may also relate to means for performing the operations described herein. Such means may be specifically constructed for the desired purpose, or it may comprise a general-purpose computer selectively started or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this embodiment. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this embodiment.

[0151] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. Various necessary structures for these systems will appear from the following description. Furthermore, no particular programming language is referenced in the description of this embodiment. It should be understood that the teachings of the embodiments described herein can be implemented using various programming languages.

[0152] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of this disclosure. It should be understood that the foregoing description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description. Therefore, the scope of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An AC-DC power supply, comprising: Synchronous rectifier field-effect transistor (FET); The transformer of the AC-DC converter is coupled to the field-effect transistor FET of the synchronous rectifier. as well as A secondary-side controller coupled to the synchronous rectifier field-effect transistor FET, wherein the secondary-side controller is configured to control the primary-side FET across an electrical isolation barrier, wherein the secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to the gate of the synchronous rectifier field-effect transistor FET, wherein the SRGD is configured to drive the synchronous rectifier field-effect transistor FET using a capacitor coupled to the gate of the synchronous rectifier field-effect transistor FET via a switch in the phase and switching controller circuit of the SRGD and an adaptive switching rate, wherein the capacitor is thermally charged and discharged.

2. The AC-DC power supply according to claim 1, wherein, The secondary-side controller further includes the capacitor coupled to the SRGD, and wherein the SRGD includes: A voltage generator circuit coupled to the first plate and the second plate of the capacitor; A gate driver circuit coupled to the first plate of the capacitor and the gate of the synchronous rectifier field-effect transistor FET; and A phase and slew rate controller circuit coupled to the voltage generator circuit and coupled to the gate driver circuit.

3. The AC-DC power supply according to claim 2, wherein, The voltage generator circuit includes: Coupled to the first plate and coupled to the first pull-up element at the first node at the first voltage level; Coupled to the first pull-up element and coupled to the second plate, and further coupled to the second pull-up element of the first node; and A first pull-down element is coupled to the second pull-up element, the second plate, and the second node at a second voltage level, wherein the second voltage level is lower than the first voltage level.

4. The AC-DC power supply according to claim 2, wherein, The gate driver circuit includes: A first pull-up element coupled between the first plate and the gate of the synchronous rectifier field-effect transistor FET; A second pull-up element coupled between a first node at a first voltage level and the gate of the synchronous rectifier field-effect transistor FET, and further coupled to the first pull-up element; and The first pull-up element is coupled to the first pull-up element, the second pull-up element and the gate of the synchronous rectifier field-effect transistor FET, and further coupled to the first pull-down element at the second node at the second voltage level, wherein the second voltage level is lower than the first voltage level.

5. The AC-DC power supply according to claim 2, wherein, The phase and slew rate controller includes a drive strength and slew rate controller, and wherein the voltage generator circuit includes: The first node is coupled to the second electrode plate; A first pull-down element coupled to the first node; Coupled between the first pull-down element, the drive strength and slew rate controller, and further coupled to the first switch at the second node at the first voltage level; A first pull-up element coupled to the first node; A second switch coupled between the first pull-up element and the drive strength and slew rate controller; A third switch coupled between the drive strength and slew rate controller and a third node, wherein the third node is coupled between the second switch and the third switch, and wherein the third node is at a second voltage level greater than the first voltage level and is coupled to the gate driver circuit; and A fourth switch coupled between the level shifter and the second pull-up element.

6. The AC-DC power supply according to claim 5, wherein, The phase and conversion rate controller includes an adaptive bias controller, and wherein the gate driver circuitry includes: Coupled to the fourth node of the first electrode plate; A fifth switch is coupled between the third pull-up element and the adaptive bias controller, wherein the third pull-up element is coupled to the fourth node; A fourth pull-up element coupled to the gate of the synchronous rectifier field-effect transistor FET, wherein the fifth switch is coupled between the third pull-up element and the fourth pull-up element; A sixth switch coupled between the level shifter and the fifth pull-up element, wherein the fifth pull-up element is coupled to the gate of the synchronous rectifier field-effect transistor FET; A seventh switch coupled between the drive strength and slew rate controller and the third node at the second voltage level; and The eighth switch is coupled between the drive strength and slew rate controller and the gate of the synchronous rectifier field-effect transistor FET, and further coupled to the first node at the first voltage level.

7. The AC-DC power supply according to claim 2, wherein, The phase and slew rate controller circuit includes a drive strength and slew rate controller, an adaptive bias controller, and a phase and drive strength controller. The phase and slew rate controller circuit is used to provide control signals to control the voltage generator circuit and the gate driver circuit. The drive strength and slew rate controller is used to control the delay of the control signals.

8. The AC-DC power supply according to claim 2, wherein, The phase and slew rate controller circuit includes a drive strength and slew rate controller and an adaptive bias controller, wherein the drive strength and slew rate controller is used to control the delay of a control signal to control the gate driver circuit, and the adaptive bias controller is used to generate a boost voltage at the gate of the synchronous rectifier field-effect transistor FET, wherein the boost voltage is greater than the power supply voltage of the secondary-side controller.

9. The AC-DC power supply according to claim 2, wherein, The phase and slew rate controller circuit is a control block coupled to the voltage generator circuit and coupled to the gate driver circuit, and the phase and slew rate controller circuit is configured to generate a control signal to enable one of the first, second, third, or fourth phases of the SRGD operation, wherein the phase and slew rate controller is used to: In the first phase: Maintain the second plate of the capacitor at a first voltage level; The first plate of the capacitor is maintained at a second voltage level higher than the first voltage level; and The gate of the synchronous rectifier field-effect transistor FET is charged to the second voltage level; In the second phase: Charge the second plate of the capacitor to the second voltage level; The first plate of the capacitor is charged to a third voltage level higher than the second voltage level; and Charge the gate of the synchronous rectifier field-effect transistor FET to the third voltage level; In the third phase: Discharge the second plate of the capacitor to the first voltage level; Discharge the first plate of the capacitor to the second voltage level; and The gate of the synchronous rectifier field-effect transistor FET is discharged to the second voltage level; and In the fourth phase: Maintain the second plate of the capacitor at the first voltage level; Maintain the first plate of the capacitor at the second voltage level; and The gate of the synchronous rectifier field-effect transistor FET is discharged to the first voltage level.

10. The AC-DC power supply according to claim 2, wherein, The phase and slew rate controller includes a drive strength and slew rate controller, the drive strength and slew rate controller comprising: A current generator for generating a current inversely proportional to the drive strength of the synchronous rectifier field-effect transistor FET; and A delay-based conversion generator, which generates a delay of a control signal based on the current, includes multiple current inverters positioned in a cascaded pattern.

11. The AC-DC power supply according to claim 2, wherein, The phase and conversion rate controller includes an adaptive bias controller, which includes: A comparator, wherein the comparator is used to compare the voltage of a control signal with the power supply voltage of the secondary-side controller; and An adaptive bias generator is used to generate a voltage level on the gate of the synchronous rectifier field-effect transistor FET, wherein the voltage level is greater than the power supply voltage.

12. An AC-DC power adapter device, comprising: USB-C connector; A transformer coupled between an AC terminal and a DC terminal, the transformer converting AC power used on the AC terminal into DC power used on the DC terminal, wherein there is electrical isolation between the AC terminal and the DC terminal; A controller coupled to the primary side of the transformer; A controller coupled to the secondary side of the transformer; and A synchronous rectifier field-effect transistor (FET), wherein the secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to the gate of the synchronous rectifier field-effect transistor (FET), wherein the SRGD is used to drive the synchronous rectifier field-effect transistor (FET) using a capacitor coupled to the gate of the synchronous rectifier field-effect transistor (FET) via a switch in the phase and conversion controller circuit of the SRGD and an adaptive conversion rate, and wherein the capacitor is thermally charged and discharged.

13. The AC-DC power adapter device according to claim 12, wherein, The secondary-side controller further includes the capacitor coupled to the SRGD, and wherein the SRGD includes: A voltage generator circuit coupled to the first plate and the second plate of the capacitor; A gate driver circuit coupled to the first plate of the capacitor and the gate of the synchronous rectifier field-effect transistor FET; and A phase and slew rate controller circuit coupled to the voltage generator circuit and coupled to the gate driver circuit.

14. The AC-DC power adapter device according to claim 13, wherein, The voltage generator circuit includes: Coupled to the first plate and coupled to the first pull-up element at the first node at the first voltage level; Coupled to the first pull-up element and coupled to the second plate, and further coupled to the second pull-up element of the first node; and A first pull-down element is coupled to the second pull-up element, the second plate, and the second node at a second voltage level, wherein the second voltage level is lower than the first voltage level.

15. The AC-DC power adapter device according to claim 13, wherein, The gate driver circuit includes: A first pull-up element coupled between the first plate and the gate of the synchronous rectifier field-effect transistor FET; A second pull-up element coupled between a first node at a first voltage level and the gate of the synchronous rectifier field-effect transistor FET, and further coupled to the first pull-up element; and It is coupled to the first pull-up element, the second pull-up element and the gate of the synchronous rectifier field-effect transistor FET, and further coupled to the first pull-down element at the second node at the second voltage level.

16. The AC-DC power adapter device according to claim 13, wherein, The phase and slew rate controller circuit includes a drive strength and slew rate controller, an adaptive bias controller, and a phase and drive strength controller, wherein the phase and slew rate controller circuit is used to provide control signals to control the voltage generator circuit and the gate driver circuit.

17. The AC-DC power adapter device according to claim 13, wherein, The phase and slew rate controller circuit is a control block coupled to the voltage generator circuit and coupled to the gate driver circuit, and the phase and slew rate controller circuit is configured to generate a control signal to enable one of the first, second, third, or fourth phases of the SRGD operation, wherein the phase and slew rate controller is used to: In the first phase: Maintain the second plate of the capacitor at a first voltage level; The first plate of the capacitor is maintained at a second voltage level higher than the first voltage level; and The gate of the synchronous rectifier field-effect transistor FET is charged to the second voltage level; In the second phase: Charge the second plate of the capacitor to the second voltage level; The first plate of the capacitor is charged to a third voltage level higher than the second voltage level; and Charge the gate of the synchronous rectifier field-effect transistor FET to the third voltage level; In the third phase: Discharge the second plate of the capacitor to the first voltage level; Discharge the first plate of the capacitor to the second voltage level; and The gate of the synchronous rectifier field-effect transistor FET is discharged to the second voltage level; and In the fourth phase: Maintain the second plate of the capacitor at the first voltage level; Maintain the first plate of the capacitor at the second voltage level; and The gate of the synchronous rectifier field-effect transistor FET is discharged to the first voltage level.

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