Dynamic successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration system and method

Abstract

Time-interleaved SAR-ADCs employ calibrated SAR-ADC circuits to convert sampled voltage levels into serial digital data. A variable delay clock circuit synchronizes a clock signal received at a respective SAR-ADC with a sampling point of the analog serial data. IC and environmental fluctuations cause a delay in the variable delay clock circuit, skewing the clock signal. The calibrated SAR-ADC detects changes in the delay in the variable delay clock circuit. By delaying a first clock signal in the variable delay clock circuit and comparing the phase of the delayed clock signal to a phase-shifted clock signal having a known phase shift relative to the first clock signal, changes in the delay of the variable delay clock circuit can be detected as a phase difference. Based on an indication of the phase difference, a delay control signal is generated to control the delay in the variable delay clock.

Description

Technical Field

[0001] The technology disclosed herein relates to analog-to-digital converter (ADC) circuitry, and more specifically, to receiving analog data on a high-speed serial interface and converting the serial data into digital / binary values ​​using a successive approximation register (SAR) ADC (SAR-ADC). Background Technology

[0002] The speed at which processors in integrated circuits (ICs) process binary data continues to increase. The binary data to be processed must be supplied to the processor at a sufficiently high rate to avoid the processor waiting for data. Video processors are an example of one type of processor where large amounts of binary data are transmitted to the processor at high rates, but other types of processors also have similar capabilities. Data communication interfaces periodically send and receive binary data from the IC at high frequencies. Data can be sent or received in each cycle of a reference clock, which can be derived from the periodically changing data. Large data buses can be used to transmit large amounts of data simultaneously in parallel each clock cycle, transmitting one or more binary bits at a time. However, each piece of data transmitted to the processor or other IC via the data bus corresponds to a physical electrical conductor (e.g., a wire) connected to the package containing the IC. Each wire connects to a physical pin / connector that occupies space on the package. As IC devices become smaller, the area available for pins / connectors also decreases. To avoid the need for a large number of pins / connectors, IC designers may choose to use a serial binary interface. Serial interfaces allow single data packets to be sent in each clock cycle using a very high frequency clock.

[0003] The data being transmitted and received can be represented as electrical signals, such as voltage levels, on wires. If the voltage level changes periodically, a new voltage level can be detected in each clock cycle and converted into binary form of data represented by the voltage. Therefore, the analog signal in voltage level form is converted into binary data by an analog-to-digital converter (ADC), which is the form required for processing in the IC. One type of ADC with relatively low power consumption compared to others is the successive approximation register (SAR) (SAR-ADC). However, the process of converting analog voltage into binary data in a SAR-ADC can take longer than a single period of the high-speed clock used by the serial interface. This problem can be addressed by employing multiple SAR-ADCs that are interleaved in time, as shown in the reference... Figure 1A As explained in the examples.

[0004] exist Figure 1A In the example, the analog data signal V IN The voltage level is sampled once per cycle. Analog data signal V IN The frequency corresponds to Figure 1A The frequency of the clock CLOCK is shown. In this example, the SAR-ADC 1 (which can be, for example, at the frequency of the clock CLOCK) is... Figure 1B The SAR-ADC shown requires five (5) clock cycles to convert the sampled voltage into a binary value. At this conversion rate, at the beginning of clock cycle 1, the voltage V... IN After the first voltage level is sampled, SAR-ADC 1 cannot be used to sample another voltage level until V is generated based on the data sampled in period 1. OUT The clock cycle 6 begins at time 1. Therefore, SAR-ADC 2 is used to measure V in cycle 2. IN The voltage level is sampled, and then when V is generated... OUT At time 2, sampling is performed again in period 7. SAR-ADC 3 samples V in period 3. IN The voltage level is sampled, and when V is generated... OUT At 3 o'clock, it resamples in period 8. SAR-ADC 4 samples V in period 4. IN The voltage level is sampled, and when V is generated... OUT At 4 o'clock, it resamples in period 9. SAR-ADC 5 samples V in period 5. IN The voltage level is sampled, and when V is generated... OUT At 5 o'clock, sampling is repeated in period 10. Each SAR-ADC in SAR-ADC 1–SAR-ADC 5 samples the data every five periods (e.g., continuously in turn) and generates the corresponding digital value (e.g., Figure 1A V in OUT 1-V OUT 9). In this respect, the time-interleaved SAR-ADC 1–SAR-ADC 5 performs analog-to-digital data conversion at a rate 5 times faster than the possible conversion rate in a standalone SAR-ADC. This interleaving requires each individual SAR-ADC to receive data with V... IN The sampling points of the SAR-ADC are synchronized with corresponding clock signals for the corresponding period. Therefore, a synchronization clock signal is provided on the IC for timing each SAR-ADC in the corresponding period. However, the physical layout of the corresponding SAR-ADCs at different locations on the IC causes the corresponding clock signals to have different propagation delays to the corresponding SAR-ADCs, resulting in the corresponding clock signals received at the SAR-ADCs being out of sync. Summary of the Invention

[0005] Exemplary aspects disclosed herein include a dynamic successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock calibration system and method. A time-interleaved SAR-ADC on an IC samples the voltage levels of an analog signal at corresponding sampling points in a sequential data cycle using separate SAR-ADCs in a time-interleaved manner. The time-interleaved SAR-ADC converts the sampled voltage levels into serial digital data. The voltage levels of a time-varying analog signal sampled outside of sampling points in a data clock cycle may not accurately represent the transmitted data. Therefore, each individual SAR-ADC must be synchronized with a corresponding sampling point in the data clock cycle. To achieve synchronization, a clock source provides a clock signal synchronized with the sampling points(s) of the sequential data cycle at the corresponding clock input to each individual SAR-ADC. Clock traces (e.g., wires) transmit the clock signal from the clock input to the corresponding individual SAR-ADC distributed across the IC. The clock trace length varies depending on the location of the corresponding SAR-ADC, resulting in each clock signal having a unique propagation delay, thus the clock signals received at the SAR-ADC are no longer synchronized.

[0006] During calibration, the clock calibration circuitry employed by the SAR-ADC includes a variable delay clock circuit to further delay each clock signal by a selected amount, resynchronizing the clock signal received at the corresponding SAR-ADC to the sampling points of the sequential data clock cycles. While the propagation delay through the clock trace remains nearly constant in the presence of IC and environmental fluctuations (e.g., voltage and / or temperature), the selected delay amount in each variable delay clock circuit can vary, causing the resynchronized signal to skew relative to the sampling points of the sequential data clock cycles. The calibration process does not dynamically address the skew in the clock signal caused by variations in the variable delay due to IC and environmental fluctuations.

[0007] In this respect, in the exemplary aspects disclosed herein, a calibrated SAR-ADC detects changes in delay in a variable-delay clock circuit. By delaying a first clock signal in the variable-delay clock circuit and comparing the phase of the delayed clock signal with a phase-shifted clock signal having a known phase shift relative to the first clock signal, the delay change of the variable-delay clock circuit can be detected as an indication of a phase difference. Based on the phase difference, a delay control signal is generated to control the phase difference by controlling the delay in the variable-delay clock.

[0008] In this regard, in the exemplary aspects disclosed herein, the calibrated SAR-ADC circuit includes a clock calibration circuit, a SAR-ADC circuit, and a delay control circuit. The clock calibration circuit includes: a clock input configured to receive a first clock signal having a first phase and a frequency; and a variable delay clock circuit configured to generate a plurality of delayed clock signals, each delayed clock signal being delayed relative to the first clock signal based on a delay adjustment signal. The SAR-ADC circuit is configured to sample the voltage level of an analog data signal in response to the calibrated delayed clock signal among the plurality of delayed clock signals, and generate a digital value corresponding to the sampled voltage level of the analog data signal. The delay control circuit includes a phase difference detection circuit and a delay adjustment circuit. The phase difference detection circuit is configured to receive a monitored delayed clock signal among the plurality of delayed clock signals that is delayed by a selected delay relative to the first clock signal, receive a phase-shifted clock signal having the frequency of the first clock signal and a second phase different from the first phase of the first clock signal, and generate an indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal. The delay adjustment circuit is configured to generate a delay adjustment signal based on the phase difference indication from the phase difference detection circuit.

[0009] In another embodiment, a method in a calibrated SAR-ADC circuit is disclosed. The method includes, in a clock calibration circuit, receiving a first clock signal having a frequency and a first phase, and generating a plurality of delayed clock signals, each delayed clock signal being delayed relative to the first clock signal based on a delay adjustment signal. The method further includes, in the SAR-ADC circuit, sampling a voltage level on an analog data signal in response to the calibrated delayed clock signal among the plurality of delayed clock signals, and generating a digital value corresponding to the sampled voltage level. The method further includes, in a delay control circuit, receiving a monitored delayed clock signal among the plurality of delayed clock signals that is delayed by a selected delay relative to the first clock signal, receiving a phase-shifted clock signal having the frequency of the first clock signal and a second phase different from the first clock signal, generating an indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal, and generating a delay adjustment signal based on the phase difference indication.

[0010] In another embodiment, a time-interleaved SAR-ADC system is disclosed. This time-interleaved SAR-ADC system includes: a plurality of clock inputs configured to receive a plurality of first clock signals, each first clock signal having a frequency and a corresponding phase; a plurality of calibrated SAR-ADC circuits; and a delay control circuit. Each of the plurality of calibrated SAR-ADC circuits includes a clock calibration circuit configured to generate a plurality of delayed clock signals, each delayed clock signal being delayed relative to a first of the plurality of first clock signals based on a delay adjustment signal. Each calibrated SAR-ADC circuit also includes a SAR-ADC circuit configured to sample the voltage level of an analog data signal in response to a calibrated delayed clock signal among the plurality of delayed clock signals, and to generate a digital value corresponding to the sampled voltage level of the analog data signal. The delay control circuit includes a phase difference detection circuit configured to: receive a monitored delayed clock signal from one of a plurality of calibrated SAR-ADC circuits; receive a phase-shifted clock signal having the same frequency and a different phase from a first clock signal received in one of the plurality of calibrated SAR-ADC circuits; and generate an indication of the phase difference between the phase of the monitored delayed clock signal and a second phase of the phase-shifted clock signal. The delay control circuit also includes a delay control modification circuit and a delay adjustment circuit configured to generate a delay control signal based on the phase difference indication from the phase difference detection circuit, and a delay adjustment circuit configured to generate a first delay adjustment signal based on the delay control signal. In a time-interleaved SAR-ADC system, the first delay adjustment signal is a delay adjustment signal from a clock calibration circuit in at least one of the plurality of calibrated SAR-ADC circuits.

[0011] In another embodiment, a method is disclosed in a time-interleaved SAR-ADC system. The method includes: receiving a first clock signal from a plurality of first clock signals in each of a plurality of calibrated SAR-ADC circuits, each first clock signal having a frequency and a corresponding first phase; generating a plurality of delayed clock signals in a clock calibration circuit, each delayed clock signal being delayed relative to one of the plurality of first clock signals based on a delay adjustment signal; sampling a voltage level of an analog data signal in the SAR-ADC circuit in response to the calibrated delayed clock signal among the plurality of delayed clock signals; and generating a digital value in the SAR-ADC circuit corresponding to the sampled voltage level of the analog data signal. The method further includes: in a delay control circuit, receiving a monitored delayed clock signal from one of a plurality of calibrated SAR-ADC circuits; receiving a phase-shifted clock signal having the same frequency and a second phase different from a corresponding first phase of one of the plurality of first clock signals received in the calibrated SAR-ADC circuit; generating an indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal in a phase difference detection circuit; generating a delay control signal based on the phase difference indication in a delay control modification circuit; and generating a first delay adjustment signal based on the delay control signal. In the method for a time-interleaved SAR-ADC system, the first delay adjustment signal is a delay adjustment signal in at least one of the plurality of calibrated SAR-ADC circuits. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0013] Figure 1A This is a timing diagram illustrating how a successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) performs time interleaving to sample data at a higher frequency than could be achieved using a single SAR-ADC;

[0014] Figure 1B This is a schematic diagram of a SAR-ADC circuit, which is configured to sample the voltage level of an analog data signal and convert the sampled voltage level into digital data.

[0015] Figure 2This is a schematic diagram of an exemplary calibrated SAR-ADC circuit and a timing diagram of an analog data signal sampled by the calibrated SAR-ADC circuit. The calibrated SAR-ADC circuit is configured to maintain a consistent selected clock delay by comparing the phase of a clock signal delayed by a variable delay clock circuit with the phase of a phase-shifted clock signal and generating a delay control signal based on the detected phase difference to control the clock delay.

[0016] Figure 3 It is control Figure 2 A flowchart of a method for clock delay in a calibrated SAR-ADC circuit;

[0017] Figure 4 It includes Figure 2 A schematic diagram of the clock calibration circuit of the variable delay clock circuit in the calibrated SAR-ADC circuit, and a timing diagram of the delayed clock signal delayed by a corresponding amount relative to the first clock signal.

[0018] Figure 5 This is a schematic diagram of a delay control circuit, which is configured to generate a delay control signal to control... Figure 2 The calibrated SAR-ADC circuit includes a delay adjustment circuit to control the clock delay through a variable delay clock circuit.

[0019] Figure 6 This is a diagram of a time-interleaved SAR-ADC system, which includes multiple... Figure 2 A separate, calibrated SAR-ADC circuit is configured to sample continuous voltage levels of analog data signals and generate digital values ​​to convert serial analog data into serial digital data.

[0020] Figure 7 This illustrates a method for a SAR-ADC system to convert voltage levels in consecutive periods of an analog data signal into serial digital data using a time-interleaved, calibrated SAR-ADC circuit; and

[0021] Figure 8 This is a block diagram of an exemplary processor-based system, which includes a processor configured to receive serial data in analog form via a serial data interface, and employs... Figure 6 A time-interleaved SAR-ADC system, which includes Figure 2 The calibrated SAR-ADC circuit converts analog serial data into a series of digital data for use by the processor. Detailed Implementation

[0022] Exemplary aspects disclosed herein include a dynamic successive approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock calibration system and method. A time-interleaved SAR-ADC on an IC samples the voltage levels of an analog signal at corresponding sampling points in a sequential data cycle using separate SAR-ADCs in a time-interleaved manner. The time-interleaved SAR-ADC converts the sampled voltage levels into serial digital data. The voltage levels of a time-varying analog signal sampled outside of sampling points in a data clock cycle may not accurately represent the transmitted data. Therefore, each individual SAR-ADC must be synchronized with its corresponding sampling point in the data clock cycle. To achieve synchronization, a clock source provides a clock signal synchronized with the sampling points(s) of the sequential data cycle at the corresponding clock input to each individual SAR-ADC. Clock traces (e.g., wires) transmit the clock signal from the clock input to the corresponding individual SAR-ADC distributed across the IC. The clock trace length varies depending on the location of the corresponding SAR-ADC, resulting in each clock signal having a unique propagation delay, thus desynchronizing the clock signals received at the SAR-ADC.

[0023] During calibration, the clock calibration circuitry employed by the SAR-ADC includes variable delay clock circuitry to further delay each clock signal by a selected amount, resynchronizing the clock signal received at the corresponding SAR-ADC to the sampling points of the sequential data clock cycle. While the propagation delay through the clock trace remains nearly constant in the presence of IC and environmental fluctuations (e.g., voltage and / or temperature), the selected delay amount in each variable delay clock circuitry depends on these conditions and can change, resulting in a skewed resynchronized signal relative to the sampling points of the sequential data clock cycle. The calibration process does not dynamically address this skew in the clock signal, which is caused by variations in the variable delay due to IC and environmental fluctuations.

[0024] In this respect, in the exemplary aspects disclosed herein, a calibrated SAR-ADC detects changes in delay in a variable-delay clock circuit. By delaying a first clock signal in the variable-delay clock circuit and comparing the phase of the delayed clock signal with a phase-shifted clock signal having a known phase shift relative to the first clock signal, the delay change of the variable-delay clock circuit can be detected as an indication of a phase difference. Based on the phase difference, a delay control signal is generated to control the phase difference by controlling the delay in the variable-delay clock.

[0025] A SAR-ADC is a low-power circuit used to convert sampled voltage levels into digital values. However, depending on certain components of the SAR-ADC, there exists at least a minimum amount of time required to perform the analog-to-digital conversion, and the duration of the data clock cycle in a high-speed serial interface may be shorter than this minimum. In such cases, a time-interleaved SAR-ADC can be employed by using a separate SAR-ADC that samples data in consecutive data clock cycles. For example, in... Figure 1A In the example, the analog-to-digital conversion time is five (5) times the data clock cycle of the serial interface, so five SAR-ADCs are used in a time-interleaved manner, such that each of the SAR-ADCs samples the voltage level of the analog signal every five data clock cycles (e.g., continuously in turn). Reference Figure 1B The schematic diagram of the SAR-ADC 100 shown is used to illustrate the operation of the SAR-ADC.

[0026] A SAR-ADC is a low-power circuit used to convert sampled voltage levels into digital values. However, depending on certain components of the SAR-ADC, there exists at least a minimum amount of time required to perform the analog-to-digital conversion, and the data clock cycle in a high-speed serial interface may be shorter than this minimum. In such cases, a time-interleaved SAR-ADC can be employed by using a separate SAR-ADC that samples data in consecutive data clock cycles. For example, in... Figure 1A In the example, the analog-to-digital conversion time is five (5) times the data clock cycle of the serial interface, so five SAR-ADCs are used in a time-interleaved manner, such that each SAR-ADC samples the voltage level of the input analog data signal every five data clock cycles (e.g., continuously in turn). Reference Figure 1B The schematic diagram of the SAR-ADC circuit 100 shown is used to describe the operation of the SAR-ADC.

[0027] Figure 1B The SAR-ADC circuit 100 includes a SAR 102, a digital-to-analog converter (DAC) 104, a sample-and-hold (S / H) circuit 106, and a comparator 108. The SAR 102 is based on data from the analog data signal V. IN Sampling voltage level (V) DATA Generate the numeric value D VAL (0)-D VAL (N). Initially, SAR 102 generated the digital value D. VAL (0)-D VAL (N), to correspond to the voltage level in the middle of the expected range, which has a reference voltage V. REF The maximum value indicated. Here, D VAL (0)-D VALThe most significant bit (MSB) of (N) is set to binary "1", while the remaining bits are set to "0". The DAC 104 then converts the digital value D... VAL (0)-D VAL (N) is converted to voltage level V SAR Voltage level V SAR Initially, it was the reference voltage V. REF Half of the voltage level V. Comparator 108 will convert the voltage level V to half of the voltage level V. SAR The voltage level V sampled and stored by the S / H circuit 106 DATA Comparison. The S / H circuit 106 controls V by briefly closing a switch coupled to the analog data input. DATA Sampling is performed, and analog data signal V is received at the analog data input. IN The switch is controlled by the clock signal CLOCK.

[0028] The output V of comparator 108 COMP Instruction V DATA Is the voltage level higher or lower than V? SAR voltage level, V SAR D corresponding to MSB being set VAL (0)-D VAL (N). If V DATA The voltage level is higher than V SAR The voltage level of D, then VAL (0)-D VAL The MSB of (N) is reset (i.e., reset to "0"). If V DATA The voltage level is lower than V SAR The voltage level of D, then VAL (0)-D VAL The MSB of (N) remains set (i.e., set to "1"). In either case, SAR 102 proceeds to the next step, in which the MSB of D is set to "1". VAL (0)-D VAL (N) sets the next MSB, and the resulting V SAR With V stored in S / H circuit 106 DATA Compare. If V DATA The voltage level is higher than V SAR The voltage level of D, then VAL (0)-D VAL The next MSB of (N) is reset (i.e., reset to "0"). If V DATA The voltage level is lower than V SAR The voltage level of D, then VAL (0)-D VAL The next MSB of (N) remains set (i.e., set to "1"). For D... VAL(0)-D VAL This process is repeated for each bit in (N) until all bits in bit N+1 are set or reset. When this process is complete, it is controlled by D. VAL (0)-D VAL The digital value indicated by (N) corresponds to the sampled voltage level V. DATA And this numerical value in V OUT Generate above.

[0029] As mentioned above, the propagation delay of the clock trace providing the clock signal to the SAR-ADC may cause the clock to lag behind the analog data signal V. IN The sampling points are out of sync. Therefore, a variable delay clock circuit is used to resynchronize the clock signal to the SAR-ADC, and the clock signal to the SAR-ADC is calibrated to the clock trace propagation delay. However, the delay in the variable delay clock circuit varies with IC and environmental conditions.

[0030] exist Figure 2 The diagram shows a calibrated SAR-ADC circuit 200, configured to control a selected clock delay amount via a variable delay clock circuit. This minimizes variations in the selected clock delay amount. The calibrated SAR-ADC circuit 200 includes a delay control circuit 202, a clock calibration circuit 204, and a SAR-ADC circuit 100. Although the description herein is directed towards... Figure 1B The SAR-ADC circuit 100 in the diagram is a calibrated SAR-ADC circuit 200, but the calibrated SAR-ADC circuit 200 is not limited to this and can be implemented using other embodiments of SAR-ADC (not shown). As described above, when the switch in the S / H circuit 106 is temporarily closed, the SAR-ADC circuit 100 processes the analog data signal V. IN Sampling was performed. Figure 2 In the process, the calibrated delayed clock signal CLOCK generated by the clock calibration circuit 204 CAL The calibrated delayed clock signal CLOCK is provided to the SAR-ADC circuit 100. CAL With analog data signal V IN The sampling points of the data clock cycle are synchronized and used in the SAR-ADC circuit 100 to control the switch (not shown).

[0031] Clock calibration circuit 204 includes a function configured to receive a first clock signal CLOCK. 1ST The clock input, the first clock signal CLOCK 1ST Having a first phase and analog data signal V INThe corresponding frequency. The clock calibration circuit 204 also includes a variable delay clock circuit 206. The clock input receives the first clock signal CLOCK from the clock source via the clock trace. 1ST Although the first clock signal CLOCK 1ST It can be used at the clock source with analog data signal V IN Synchronization is achieved, but due to the propagation delay of the clock trace, the first clock signal CLOCK received at SAR-ADC circuit 100 is delayed. 1ST It may not be related to the analog data signal V IN Synchronization. The variable delay clock circuit 206 is configured to generate multiple delayed clock signals, each delayed clock signal relative to the first clock signal CLOCK. 1ST A corresponding delay was applied. From multiple delayed clock signals, the analog data signal V was selected. IN The sampling point closest to the synchronous delayed clock signal is used as the calibrated delayed clock signal CLOCK. CAL This is then provided to the SAR-ADC circuit 100. The calibrated delayed clock signal CLOCK... CAL This can be achieved by, for example, delaying the first clock signal CLOCK. 1ST The rising edge corresponds to the analog data signal V IN The sampling points in the next cycle are used to compare with the analog data signal V. IN The sampling points are synchronized.

[0032] Controlling the delay in the variable delay clock circuit 206 is crucial for avoiding the calibrated delayed clock signal CLOCK. CAL Deviation from analog data signal V IN The skewness (i.e., time shift) of the sampling points is necessary. (Reference) Figure 2 The analog data signal V in IN The example shown, consisting of two cycles (CYCLE 0 and CYCLE 1), illustrates this necessity. As shown, during each cycle of CYCLE 0 and CYCLE 1, the analog data signal V... IN The voltage amplitude varies with time. Sampling points A and B in each cycle indicate the expected analog data signal V in each cycle. IN The time corresponding to the voltage level of the transmitted data value. In other embodiments, there may be more or fewer sampling points in each data clock cycle. In various embodiments, the voltage level at each sampling point may indicate a single data bit or multiple data bits. Due to the analog data signal V IN The nature of the variation means that voltage levels sampled earlier or later than sampling points A and B may be higher or lower than the expected data values. Therefore, avoid using a calibrated delayed clock signal CLOCK synchronized with one of sampling points A and B. CALThe skew ensures that the sampled voltage level corresponds to the expected transmitted data value.

[0033] In some embodiments, the variable delay clock circuit 206 is formed by a series of buffers BUF(0)-BUF(L), wherein each buffer BUF(0)-BUF(L) incrementally delays the first clock signal CLOCK. 1ST Furthermore, the outputs of the buffers BUF(0)-BUF(L) provide tap points where a corresponding delayed clock signal is generated. This is related to the analog data signal V. IN The output of the data clock cycle synchronized or closest synchronized buffers BUF(0)-BUF(L) is selected as the calibrated delayed clock signal CLOCK coupled to the SAR-ADC circuit 100. CAL Other embodiments may be employed that provide a variable delay clock circuit 206 with multiple tap points, each having a delayed clock signal, and these other embodiments are within the scope of this disclosure.

[0034] The variable delay clock circuit 206 can change its operating speed due to IC conditions and environmental conditions (e.g., voltage and / or temperature variations) experienced during operation, resulting in an increase or decrease in the delay amount of the selected delay clock signal. For example, the delay amount in each of the series of buffers BUF(0)-BUF(L) may increase. Although this increase occurs when the first clock signal CLOCK is provided... 1ST The output of the first buffer BUF(0) may be relatively small, but as the signal propagates through subsequent buffers BUF(1)-BUF(L), this increase becomes double, triple, and so on. As a result, the calibrated delayed clock signal CLOCK provided to the SAR-ADC circuit 100... CAL It may become significantly skewed and no longer correlated with the analog data signal V. IN synchronous.

[0035] To reduce clock skew in the variable delay clock circuit 206, the delay control circuit 202 includes a delay adjustment circuit 208 and a phase difference detection circuit 210. The delay adjustment circuit 208 provides a delay adjustment signal DEL_ADJ to the variable delay clock circuit 206 to compensate for delay variations caused by IC and / or environmental conditions. For example, in an embodiment where the variable delay clock circuit 206 includes a series of buffers BUF(0)-BUF(L), the increase or decrease in delay caused by conditions within the IC can be offset by decreasing or increasing the voltage and / or current levels provided to the buffers BUF(0)-BUF(L) to restore each buffer to the desired delay.

[0036] The delay adjustment circuit 208 is configured to respond to a determined monitored delay clock signal CLOCK.MON The clock delay has been changed to generate the delay adjustment signal DEL_ADJ, and the monitored delay clock signal CLOCK is used. MON It is one of multiple delayed clock signals generated by the variable delay clock circuit 206. This determination is based on the monitored delayed clock signal CLOCK. MON With phase-shifted clock signal CLOCK PS Phase comparison, phase-shifted clock signal CLOCK PS Relative to the first clock signal CLOCK 1ST A known phase shift has been made. The known phase shift (e.g., in degrees) corresponds to the analog data signal V. IN A portion of the clock cycle. The first clock signal CLOCK has the first phase. 1ST The phase-shifted clock signal CLOCK, which can be generated by the phase interpolator circuit 212, has a second phase. PS This can be generated by phase interpolator circuit 214. Each of phase interpolator circuits 212 and 214 receives a source clock, which can include multiple root clocks from a phase-locked loop (PLL). If the first clock signal is CLOCK... 1ST Delayed to generate the monitored delayed clock signal CLOCK MON The time quantity corresponds to a known phase shift, then in the monitored delayed clock signal CLOCK MON Phase and phase shift clock signal CLOCK PS There will be no phase difference between the second phase and the second phase. Therefore, the phase-shifted clock signal CLOCK PS Relative to the first clock signal CLOCK 1ST The phase shift is selected to correspond to the monitored delayed clock signal CLOCK. MON The delay. In some embodiments, the monitored delay clock signal CLOCK MON It is generated by the last of a series of buffers in the variable delay clock circuit 206 (e.g., buffer BUF(L)).

[0037] To compare the monitored delayed clock signal CLOCK MON With phase-shifted clock signal CLOCK PS The phase delay control circuit 202 includes a phase difference detection circuit 210. The phase difference detection circuit 210 is configured to receive a phase difference from a plurality of delayed clock signals relative to a first clock signal CLOCK. 1ST The monitored delay clock signal CLOCK is delayed by a selected delay. MON Receives a clock signal CLOCK 1STThe frequency and different from the first clock signal CLOCK 1ST The phase-shifted clock signal CLOCK of the first phase and the second phase PS And generate the monitored delayed clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases is indicated by PHASE_DIFF. If the monitored delayed clock signal CLOCK is not detected... MON Phase and phase shift clock signal CLOCK PS The delay control circuit 202 determines the delay via the variable delay clock circuit 206 as needed based on the phase difference indication PHASE_DIFF between the second phases, and accordingly generates a delay control signal DEL_ADJ (e.g., keeping DEL_ADJ constant) to maintain a constant delay. This is in response to the monitored delay clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The delay control circuit 202 generates a delay adjustment signal DEL_ADJ (e.g., increasing or decreasing) to compensate for or cancel the detected phase difference indication PHASE_DIFF between the second phases. When the delay in the variable delay clock circuit 206 has been slowed down, the monitored delay clock signal CLOCK... MON The phase lags behind the phase-shifted clock signal CLOCK. PS The second phase. In the case of delay acceleration in the variable delay clock circuit 206, the monitored delay clock signal CLOCK... MON The phase leads the phase-shift clock signal CLOCK. PS The second phase. Based on the phase difference indication PHASE_DIFF from the phase difference detection circuit 210, the delay adjustment circuit 208 generates a delay adjustment signal DEL_ADJ to adjust the monitored delayed clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS Phase alignment.

[0038] Figure 2 The SAR-ADC circuit 100 is configured to respond to a calibrated delayed clock signal CLOCK among a plurality of delayed clock signals DCLK(0)-DCLK(N). CAL For analog data signal V IN The voltage level is sampled, and a digital value V is generated. OUT The numerical value V OUT Corresponding to the analog data signal V IN Upsampled voltage level V DATA .

[0039] Figure 3 It shows the control Figure 2 A flowchart of a method 300 for clock delay in a calibrated SAR-ADC circuit 200. Method 300 includes receiving a first clock signal CLOCK having a frequency and a first phase in a clock calibration circuit 204 (block 302). 1ST (Box 304). Method 300 continues in clock calibration circuit 204, generating multiple delayed clock signals DCLK(0)-DCLK(N), each delayed clock signal being based on a delay adjustment signal DEL_ADJ relative to a first clock signal CLOCK. 1ST The corresponding delay is applied (box 306). Method 300 continues, in the SAR-ADC circuit 100 (box 308), in response to the calibrated delayed clock signal CLOCK among the plurality of delayed clock signals DCLK(0)-DCLK(N). CAL For analog data signal V IN voltage level V DATA Sampling is performed (box 310). Method 300 continues in the SAR-ADC circuit 100, generating the voltage level V corresponding to the sampled voltage. DATA The corresponding numerical value V OUT (Box 312). Method 300 continues further, in delay control circuit 202 (Box 314), receiving a plurality of delayed clock signals DCLK(0)-DCLK(N) relative to the first clock signal CLOCK. 1ST The delayed clock signal CLOCK, which is monitored accordingly, is delayed. MON (Box 316). Method 300 further includes receiving a first clock signal CLOCK in the delay control circuit 202. 1ST The frequency and different from the first clock signal CLOCK 1ST The phase-shifted clock signal CLOCK of the first phase and the second phase PS (Box 318). Method 300 in the delay control circuit 202 further includes generating a monitored delay clock signal (CLOCK). MON The phase and phase-shifted clock signal (CLOCK) PS The phase difference between the second phases of the clock signal is indicated by PHASE_DIFF (box 320). In the delay control circuit 202, method 300 continues based on the monitored delay clock signal (CLOCK). MON The phase and phase-shifted clock signal (CLOCK) PS The phase difference between the second phases of the signal is indicated by PHASE_DIFF to generate the delay adjustment signal DEL_ADJ (box 322).

[0040] Figure 4 yes Figure 2A schematic diagram of a clock calibration circuit 204 including a variable delay clock circuit 206 in a calibrated SAR-ADC circuit 200. Figure 4 It also includes the first clock signal CLOCK. 1ST A timing diagram of multiple delayed clock signals DCLK(0)-DCLK(N) with corresponding delays. As described above, in some embodiments, the first clock signal CLOCK is configured to be delayed. 1ST The series-coupled delay buffers BUF(0)-BUF(L) generate multiple delayed clock signals DCLK(0)-DCLK(N) in the variable delay clock circuit 206, and the variable delay clock circuit 206 includes multiple tapped outputs that are coupled to the outputs of the corresponding delay buffers BUF(0)-BUF(L). The monitored delayed clock signal CLOCK MON DCLK(N) can be generated by the last buffer BUF(L) of the series-connected clock buffers, thus relative to the first clock signal CLOCK. 1ST It has a longer delay than any other delayed clock signal DCLK(0)-DCLK(N-1). However, the monitored delayed clock signal CLOCK... MON It does not need to be delayed longer than all other delayed clock signals in the multiple delayed clock signals DCLK(0)-DCLK(N-1).

[0041] like Figure 4 As shown, the delayed clock signals DCLK(0), DCLK(01), DCLK(02), DCLK(N-1), and DCLK(N) are relative to the first clock signal CLOCK. 1ST Delays were applied respectively to D0, D1, D2, and D... N-1 and D N A plurality of selectable delayed clock signals DCLK(0)-DCK(N) from the tapped output of the variable delayed clock circuit 206 are provided to the input of multiplexer 402 in clock calibration circuit 204. Multiplexer 402 is coupled to the tapped output of the variable delayed clock circuit 206 and is configured to receive a plurality of selectable delayed clock signals from the plurality of delayed clock signals DCLK(0)-DCK(N). Multiplexer 402 is configured to select one of the selectable plurality of delayed clock signals DCLK(0)-DCK(N) based on a selection signal CLK_SEL, and generate a calibrated delayed clock signal CLOCK based on the selected delayed clock signal from the plurality of selectable plurality of delayed clock signals DCLK(0)-DCK(N). CAL During calibration, the multiplexer selection signal CLK_SEL is controlled to select the analog data signal V. INThe sampling point is synchronized or most closely synchronized with one of the multiple delayed clock signals DCLK(0)-DCLK(N), and the selected delayed clock signal is provided to the SAR-ADC circuit 100 as the calibrated delayed clock signal CLOCK. CAL .

[0042] Figure 5 yes Figure 2 A schematic diagram of a delay control circuit 202 in a calibrated SAR-ADC circuit 200, which is configured to generate a delay adjustment signal DEL_ADJ to control the clock delay through a variable delay clock circuit 206. Figure 5 A phase difference detection circuit 210 is shown, which is configured to detect the monitored delayed clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases. The phase difference detection circuit 210 is also configured to generate a monitored delayed clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases is indicated by PHASE_DIFF. The phase difference indicator PHASE_DIFF is provided to the delay control modification circuit 502 in the delay control circuit 202. The delay control modification circuit 502 is configured to receive the monitored delay clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases is indicated by PHASE_DIFF, and a delay control signal DEL_CTL is generated to control the delay adjustment circuit 208 to generate a delay adjustment signal DEL_ADJ. The delay adjustment signal DEL_ADJ controls the multiple delayed clock signals DCLK(0)-DCLK(N) relative to the first clock signal CLOCK. 1ST The corresponding delay.

[0043] In other words, the delay control circuit 202 is configured to generate a delay adjustment signal DEL_ADJ to control the monitored delay clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases. In some embodiments, the delay control circuit 202 is configured to generate a delay adjustment signal DEL_ADJ to compensate for the change in phase difference, thereby minimizing the monitored delay clock signal CLOCK. MON Phase and phase shift clock signal CLOCK PS The phase difference between the second phases. In some embodiments, the target phase difference can be the monitored delayed clock signal CLOCK. MONPhase and phase shift clock signal CLOCK PS The zero-degree phase difference between the second phase and the target phase difference can correspond to the zero-degree phase difference relative to the first clock signal CLOCK. 1ST The monitored delayed clock signal CLOCK with a known delay MON In some embodiments, the delay control circuit 202 is configured to indicate the monitored delayed clock signal CLOCK in response to the phase difference indicator PHASE_DIFF. MON The phase leads the phase-shift clock signal CLOCK. PS The second phase adjusts the delay adjustment signal DEL_ADJ to increase the monitored delay clock signal CLOCK. MON Relative to the phase-shifted clock signal CLOCK PS The delay control circuit 202 is also configured to respond to the phase difference indicator PHASE_DIFF indicating the monitored delay clock signal CLOCK. MON The phase lags behind the phase-shifted clock signal CLOCK. PS The second phase adjusts the delay adjustment signal DEL_ADJ to reduce the monitored delay clock signal CLOCK. MON Relative to the phase-shifted clock signal CLOCK PS The delay.

[0044] Figure 5 Includes the monitored delayed clock signal CLOCK MON With phase-shifted clock signal CLOCK PS Timing diagram for cases with phase difference. In the first case, when the delay through the variable delay clock circuit 206 is shorter than expected, the early-monitored delayed clock signal CLOCK... MON_EARLY The rising edge of the phase-shifted clock is greater than the phase-shifted clock CLOCK. PS The rising edge appears early, reaching a phase difference D. EARLY In the second case, when the delay through the variable delay clock circuit 206 is longer than expected, the late-monitored delayed clock signal CLOCK... MON_LATE The rising edge of the phase-shifted clock is greater than the phase-shifted clock CLOCK. PS The rising edge appears late, reaching a phase difference D. LATE .

[0045] Figure 5 The delay control modification circuit 502 is also configured to receive a phase difference indication PHASE_DIFF from the phase difference detection circuit 210, and generate a delay control signal DEL_CTL based on the OVERRIDE signal to control the delay adjustment circuit 208 to set the monitored delay clock signal CLOCK. MON With phase-shifted clock signal CLOCK PSThe phase difference between the phase difference and the phase difference. The delay control modification circuit 502 includes an override input configured to receive the OVERRIDE signal. The delay control modification circuit 502 includes a storage circuit 504 configured to store the value of the OVERRIDE signal. The delay control modification circuit 502 may include a control signal generation circuit 506 configured to generate the OVERRIDE signal based on at least one of the OVERRIDE signal received at the override input, the stored value of the OVERRIDE signal stored in the storage circuit 504, and an indication PHASE_DIFF of the phase difference from the phase difference detection circuit 210. For example, the OVERRIDE signal can be used to add an offset or multiplier to calibrate the delay control signal DEL_CTL. Alternatively, in some cases, the OVERRIDE signal can be used to determine the delay control signal DEL_CTL. For example, a value from a previous calibration process can be stored in the storage circuit 504 or provided via the OVERRIDE signal to set the value of the delay control signal DEL_CTL, thereby reducing the time from reset to a fully calibrated state. In another example, the delay setting can be determined based on measuring harmonic distortion using spectrum analysis. In another example, the OVERRIDE signal or storage circuit 504 can provide correction for incorrectly implemented algorithms used in calibration after a reset. In another example, for analog data signals with four (4) different signal levels, a measurement of the 4-level pulse amplitude modulation (PAM4) eye height can be used as an indicator of the delay setting for adjusting the maximum signal level. In another example, an algorithm can be implemented that produces performance improvements by adjusting the delay setting via the OVERRIDE signal. In another example, the OVERRIDE signal can be used in the IC's power-on sequence to set the delay control signal DEL_CTL, such as before the phase difference detection circuit 210 can send the phase difference indication PHASE_DIFF.

[0046] Figure 6 This is a diagram of a time-interleaved SAR-ADC system 600 comprising multiple calibrated SAR-ADC circuits 602(0)-602(M-1) configured to process analog data signal V. IN The continuous voltage level is sampled, and a digital value V is generated. OUT (0)-V OUT(M-1) is used to convert serial analog data into serial digital data. In the case of a time-interleaved SAR-ADC system 600 that includes M specific components, these components can be collectively referred to as (0)-(M-1), or simply as (N) for individual components within such components. The time-interleaved SAR-ADC system 600 includes multiple clock inputs configured to receive multiple first clock signals CLOCK. 1ST (0)-CLOCK 1ST (M-1), each first clock signal has the same frequency and is consistent with the analog data signal V. IN The corresponding phase synchronized with one of the continuous sampling points. Figure 6 The calibrated SAR-ADC circuits 602(0)-602(M-1) shown are different from those shown. Figure 2 The calibrated SAR-ADC circuits 200 in the time-interleaved SAR-ADC system 600 do not all include a delay control circuit 202. Instead, each of the multiple calibrated SAR-ADC circuits 602(0)-602(M-1) in the time-interleaved SAR-ADC system 600 includes only a clock calibration circuit 204 and a SAR-ADC circuit 100. The clock calibration circuit 204 of each calibrated SAR-ADC circuit 602(0)-602(M-1) is configured to generate multiple delayed clock signals, each clock signal being based on a delay adjustment signal DEL_ADJ(N) relative to a first clock signal CLOCK. 1ST (N) is delayed. In the first embodiment, the delay adjustment signals DEL_ADJ(0)-DEL_ADJ(M-1) are all generated in the delay control circuit 604(0) based on the delay control signal DEL_CTL(0). In an alternative embodiment of the time-interleaved SAR-ADC system 600 (discussed further below), each of the delay adjustment signals DEL_ADJ(1)-DEL_ADJ(M-1) is generated in the corresponding delay control circuit 604(N). The SAR-ADC circuit 100 in each of the calibrated SAR-ADC circuits 602(0)-602(M-1) is configured to sample the voltage level of the analog data signal in response to a calibrated delay clock signal among a plurality of delayed clock signals, and generate a digital value corresponding to the voltage level of the sampled analog data signal, as described above regarding Figure 2 The SAR-ADC circuit 100 described herein.

[0047] The time-interleaved SAR-ADC system 600 also includes a delay control circuit 604(0). The delay control circuit 604(0) includes a phase difference detection circuit 606(0), which is configured to receive a monitored delayed clock signal CLOCK from a calibrated SAR-ADC circuit 602(0). MON (0), receiving a clock signal CLOCK with the same frequency but different from the first clock signal. 1ST The phase-shifted clock signal CLOCK of the second phase of phase (0) PS (0)(First clock signal CLOCK) 1ST (0) is also received in the calibrated SAR-ADC circuit 602(0), and a monitoring delayed clock signal CLOCK is generated. MON (0) phase and phase shift clock signal CLOCK PS The delay control circuit 604(0) further includes a delay control modification circuit 608(0), which is configured to generate a delay control signal DEL_CTL(0) based on the indication PHASE_DIFF(0) from the phase difference detection circuit 606(0). The delay control circuit 604(0) also includes a delay adjustment circuit 610(0), which, in a first embodiment, is configured to generate a first delay adjustment signal DEL_ADJ(0) based on the delay control signal DEL_CTL(0). The first delay adjustment signal DEL_ADJ(0) may be a delay adjustment signal DEL_ADJ(0)-DEL_ADJ(M-1) provided to at least one or all of the plurality of calibrated SAR-ADC circuits 602(0)-602(M-1). The delay control circuit 604(0) is configured to generate a first delay control signal DEL_CTL(0) to control the monitored delay clock signal CLOCK in a plurality of calibrated SAR-ADC circuits 602(0)-602(M-1). MON (0) phase and phase shift clock signal CLOCK PS The phase difference between the second phases of (0).

[0048] Multiple calibrated SAR-ADC circuits 602(0)-602(M-1) receive multiple first clock signals CLOCK. 1ST (0)-CLOCK 1ST (M-1), at consecutive sampling points, the analog data signal V IN The voltage level is sampled, and a digital value V corresponding to the sampled voltage level is generated. OUT (0)-V OUT(M-1) to convert the analog data signal V in each cycle IN The serial analog data transmitted in the process is converted into digital data.

[0049] like Figure 2 The timing diagram in the image shows the analog data signal V. IN Each data clock cycle includes sampling points A and B, where, in this example, the voltage level is sampled at sampling points A and B. Figure 6 In the time-interleaved SAR-ADC system 600, each of the M calibrated SAR-ADC circuits 602(0)-602(M-1) is capable of calibrating analog data signal V. IN The voltage level V will be sampled within M / 2 data clock cycles. DATA Convert to a numerical value V OUT Therefore, the calibrated SAR-ADC circuits 602(0)-602(M-1) are used in a time-interleaved manner (e.g., in an alternating sequence) for the analog data signal V. IN Data is sampled at each sampling point (e.g., A and B) in each cycle, and the analog data is converted into digital data.

[0050] To achieve this interleaving, M first clock signals CLOCK... 1ST (0)-CLOCK 1ST (M-1) is provided to the time-interleaved SAR-ADC system 600. M first clock signals CLOCK... 1ST (0)-CLOCK 1ST (M-1) are synchronized with the sequential sampling points of M / 2 data clock cycles respectively. Each calibrated SAR-ADC circuit in the calibrated SAR-ADC circuits 602(0)-602(M-1) receives the first clock signal CLOCK via the clock trace. 1ST (0)-CLOCK 1ST A first clock signal corresponding to (M-1) has a propagation delay that depends on the position of the calibrated SAR-ADC circuit 602(N) (where "N" is from 0 to M-1) on the IC. Therefore, in the clock calibration process described above, a clock calibration circuit 204 is used in each calibrated SAR-ADC circuit 602(n) to select the calibrated delayed clock signal CLOCK. CAL (N) to synchronize the sampling of the calibrated SAR-ADC circuit 602(N) with the sampling points of the data clock cycles in M / 2 data clock cycles.

[0051] like Figure 6As shown, the delay control circuit 604(0) of the time-interleaved SAR-ADC system 600 may include a single delay control modification circuit 608(0) and a phase difference detection circuit 606(0), which respectively have Figure 5 The functions of the delay control modification circuit 502 and the phase difference detection circuit 210 are described. In this example, the calibrated SAR-ADC circuits 602(0)-602(M-1) can receive their corresponding delay adjustment signals DEL_ADJ(N) from the delay control circuit 604(0). The variable delay clock circuit 206, which experiences the same IC and environmental fluctuations, will be similarly affected. Therefore, the monitored delay clock signal CLOCK... MON The delayed phase of (0) will correspond to the monitored delayed clock signal (i.e., CLOCK) in the calibrated SAR-ADC circuits 602(1)-602(M-1). MON (1)-CLOCK MON The delayed phase of (M-1). Monitored delayed clock signal CLOCK. MON (0) is provided to the phase difference detection circuit 606(0) for use with the phase shift clock signal CLOCK. PS (0) is compared, and the delay adjustment signal DEL_ADJ(0) based on the detected phase difference indication PHASE_DIFF(0) can be used to compensate for or otherwise control the delay of the variable delay clock circuit 206 in each of the calibrated SAR-ADC circuits 602(0)-602(M-1).

[0052] In the alternative embodiments discussed above, the time-interleaved SAR-ADC system 600 includes delay control circuits 608(0)-608(M-1) that generate outputs for each of the corresponding calibrated SAR-ADC circuits 602(0)-602(M-1), thereby providing personalized control. For example, delay control circuits 604(0)-604(M-1) can provide individual control in cases where IC and environmental fluctuations differ on the IC, or where the effect of such differences on the IC is such that the delay through the corresponding variable delay clock circuit is not similarly affected. In this example, the time-interleaved SAR-ADC system 600 includes phase difference detection circuits 606(0)-606(M-1) to provide individual indications PHASE_DIFF(0)-PHASE_DIFF(M-1) of M phase differences to the delay control circuits 604(0)-604(M-1). Therefore, the calibrated SAR-ADC circuits 602(1)-602(M-1) generate the output CLOCK. MON (1) To CLOCKMON (M-1), output CLOCK MON (1) To CLOCK MON (M-1) will be combined with the corresponding phase-shift clock (not shown) to detect individual phase shifts in delay control circuits 604(1)-604(M-1).

[0053] In this respect, each delay control circuit 604(N) includes a phase difference detection circuit 606(N), a delay control modification circuit 608(N), and a delay adjustment circuit 610(N). The second phase difference detection circuit 606(N) is configured to generate a monitored delay clock signal CLOCK for another calibrated SAR-ADC circuit (not among at least one of the calibrated SAR-ADC circuits 602(0)-602(M-1) that receives the first delay adjustment signal DEL_ADJ(0)). MON The phase of the second phase-shifted clock signal CLOCK PS The second indication of the second phase difference between the second phases of (N). The second phase-shift clock signal CLOCK. PS (N) relative to the first clock signal CLOCK 1ST (N) is shifted. A second delay control modification circuit 608(N) is configured to generate a second delay control signal DEL_CTL(N) based on a second indication of the second phase difference from the second phase difference detection circuit, to control the second phase difference in another calibrated SAR-ADC circuit among a plurality of calibrated SAR-ADC circuits 602(N). A second delay adjustment circuit 610(N) is configured to generate a second delay adjustment signal DEL_ADJ(N) based on the second delay control signal DEL_CTL(N). In this alternative embodiment, the second delay adjustment signal DEL_ADJ(N) is the delay adjustment signal DEL_ADJ(N) in the clock calibration circuit 204 of another calibrated SAR-ADC circuit among a plurality of calibrated SAR-ADC circuits 602(N).

[0054] In some embodiments, the delay control modification circuit 608(0) further includes a... Figure 5 The first control signal generation circuit 506(0) corresponds to the control signal generation circuit 506 in the circuit. The delay control modification circuit 608(0) also includes a first control signal generation circuit 506(0) corresponding to the control signal generation circuit 506 in the circuit. Figure 5The storage circuit 504(0) corresponds to the storage circuit 504 in the storage circuit 504. The delay control modification circuit 608(0) also includes an overshoot input configured to receive the overshoot signal OVERRIDE(0). The control signal generation circuit 506(0) is configured to generate a delay control signal DEL_CTL(0) to control the monitored delay clock signal CLOCK of one of the calibrated SAR-ADC circuits 602(0) based on at least one of the overshoot signal OVERRIDE(0), the stored value of the overshoot signal OVERRIDE(0) stored in the storage circuit 504(0), and an indication PHASE_DIFF(0) of the phase difference from the phase difference detection circuit 606 of one of the calibrated SAR-ADC circuits 602(0). MON (0) phase and phase shift clock signal CLOCK PS (0) Phase difference between the second phases. In an alternative embodiment, the second delay control modification circuit 608(N) includes a second control signal generation circuit 506(N) (not shown), which is configured to generate a second delay control signal DEL_CTL(N) based on at least one of the second overdrive signal OVERRIDE(N), a stored value of the second overdrive signal OVERRIDE(N) stored in the second storage circuit 504(N), and a second indication PHASE_DIFF(N) of the second phase difference from the second phase difference detection circuit of the second phase difference detection circuit of the phase difference detection circuit of the other calibrated SAR-ADC circuit of the plurality of calibrated SAR-ADC circuits 602(N), to control the monitored delay clock signal CLOCK of the other calibrated SAR-ADC circuit of the plurality of calibrated SAR-ADC circuits 602(N). MON (0) phase and phase shift clock signal CLOCK PS The second phase difference between the second phases of (0).

[0055] Figure 7 It is shown Figure 6 The time-interleaved SAR-ADC system 600 uses time-interleaved calibrated SAR-ADC circuits 602(0)-602(M-1) to convert the analog data signal V IN A flowchart of a method 700 for converting voltage levels in a continuous period into serial digital data. Method 700 includes receiving a plurality of first clock signals CLOCK in each of a plurality of calibrated SAR-ADC circuits 602(0)-602(M-1) (block 702). 1ST (0)-CLOCK 1STA first clock signal in (M-1), each first clock signal having a frequency and a corresponding phase (block 704), generates multiple delayed clock signals DCLK(0)-DCLK(N) in clock calibration circuit 204, each delayed clock signal being based on a delay adjustment signal DEL_ADJ(N) relative to the multiple first clock signals CLOCK. 1ST (0)-CLOCK 1ST One of the first clock signals in (M-1) is delayed (block 706). Method 700 also includes, in the calibrated SAR-ADC circuits 602(0)-602(M-1), a calibrated delayed clock signal CLOCK in response to one of the plurality of delayed clock signals DCLK(0)-DCLK(N). CAL For analog data signal V IN The voltage level is sampled (box 708), and the analog data signal V is generated in the calibrated SAR-ADC circuits 602(0)-602(M-1). IN The sampled voltage level V DATA The corresponding numerical value V OUT (Box 710)

[0056] Method 700 continues in delay control circuit 604(0) (block 712), receiving the monitored delayed clock signal CLOCK from one of a plurality of calibrated SAR-ADC circuits 602(0)-602(M-1) among a plurality of delayed clock signals DCLK(0)-DCLK(N). MON (0)(Box 714), and receives a phase-shifted clock signal CLOCK with the same frequency and second phase. PS (0), the second phase is different from the first clock signal CLOCK received in one of the calibrated SAR-ADC circuits 602(0)-602(M-1). 1ST (0)-CLOCK 1ST The first phase of (M-1). Method 700 also includes generating a monitored delayed clock signal CLOCK in phase difference detection circuit 606(0). MON (0) phase and phase shift clock signal CLOCK PSThe method includes an indication of the phase difference between the second phases of (0) PHASE_DIFF(0) (block 718), and a delay control signal DEL_CTL(0) generated in the delay control modification circuit 608(0) based on the indication of the phase difference PHASE_DIFF(0) (block 720). The method also includes generating a first delay adjustment signal DEL_ADJ(0) based on the delay control signal DEL_CTL(0) (block 722). In method 700, the delay control signal DEL_CTL(0) as the first delay adjustment signal DEL_ADJ(0) is provided to at least one of the plurality of calibrated SAR-ADC circuits 602(0)-602(M-1).

[0057] Figure 8 This is a block diagram of an exemplary processor-based system 800 including a processor 802 (e.g., a microprocessor), which includes instruction processing circuitry 804. The processor-based system 800 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. The processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. The processor 802 is configured to execute processing logic in instructions for performing the operations and steps discussed herein.

[0058] Processor 802 may include register renaming recovery circuit 814, which is used to restore the state of register renaming map in instruction processing circuit 804 in response to a refresh instruction indicating that some instructions in the instruction pipeline should be refreshed due to a failed instruction.

[0059] Processor 802 and main memory 810 are coupled to system bus 812 and can interconnect peripheral devices included in processor-based system 800. Processor 802 is known to communicate with these other devices by exchanging address, control, and data information on system bus 812. For example, processor 802 can transmit bus transaction requests to memory controller 819 in main memory 810, which is an example of a slave device. Although Figure 8Not shown, but multiple system buses 812 may be provided, each forming a different architecture. In this example, the memory controller 819 is configured to provide memory access requests to the memory array 820 in the main memory 810. The memory array 820 consists of an array of storage bit cells for storing data. As a non-limiting example, the main memory 810 may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0060] Other devices can be connected to system bus 812. For example... Figure 8 As shown, as an example, these devices may include main memory 810, one or more input devices 822, one or more output devices 824, modem 826, and one or more display controllers 828. The input devices 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Figure 6 Time-interlaced SAR-ADC system 600 or Figure 2 The calibrated SAR-ADC circuit 200 is used to receive serial data from an analog data signal via a high-speed data interface. Output device 824 can include any type of output device, including but not limited to audio, video, and other visual indicators. Modem 826 can be any device configured to allow data exchange with network 830. Network 830 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. TM Networks and the Internet. Modem 826 can be configured to support any type of desired communication protocol. Processor 802 can also be configured to access display controller 828 via system bus 812 to control information sent to one or more displays 832. The displays (multiple) 832 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0061] Figure 8The processor-based system 800 may include a set of instructions 834 that will be executed by the processor 802 according to instructions for any desired application. The instructions 834 may be stored in main memory 810, the processor 802, and / or instruction cache 808, as examples of non-transitory computer-readable media 836. The instructions 834 may also reside wholly or at least partially in main memory 810 and / or the processor 802 during their execution. The instructions 834 may also be transmitted or received on network 830 via modem 826, such that network 830 includes computer-readable media 836.

[0062] Although computer-readable medium 836 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store a set or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions executable by a processing device and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Accordingly, the term "computer-readable medium" should include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0063] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or embodied in machine-executable instructions that can be used by a general-purpose or special-purpose processor programmed with those instructions to perform the steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0064] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. Machine-readable media include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.) and so on.

[0065] Unless otherwise specifically stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities within computer system registers into other data similarly represented as physical quantities within computer system memory or registers or other such information storage, transmission, or display devices.

[0066] The algorithms and displays presented herein are not inherently related to any particular computer or other such entity. Various systems can be used with programs based on the teachings herein, or it may be convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will be apparent from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using various programming languages.

[0067] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0068] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or performed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0069] The embodiments disclosed herein can be implemented in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0070] It should also be noted that the operational steps described in any exemplary embodiment herein are described as being for the purpose of example and discussion. The described operations may be performed in a variety of different orders than those shown. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof, which may be referenced in the above description.

[0071] Unless otherwise expressly stated, no method described herein shall be construed as requiring its steps to be performed in a particular order. Accordingly, where a method claim does not actually state the order in which its steps are followed, or where the claims or specification do not specifically state that these steps are limited to a particular order, this shall not imply the inference of any particular order.

[0072] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as encompassing all contents within the scope of the appended claims and their equivalents.

Claims

1. A calibrated successive approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising: Clock calibration circuit, including: A clock input is configured to receive a first clock signal having a first phase and a frequency; and A variable delay clock circuit is configured to generate multiple delayed clock signals, each delayed clock signal being delayed relative to the first clock signal based on a delay adjustment signal. The SAR-ADC circuit is configured as follows: In response to a calibrated delayed clock signal among the plurality of delayed clock signals, the voltage level of the analog data signal is sampled; and Generate digital values ​​corresponding to the voltage levels sampled from the analog data signal; and Delay control circuit, including: The phase difference detection circuit is configured as follows: Receive a monitored delayed clock signal from the plurality of delayed clock signals, wherein the monitored delayed clock signal is delayed by a selected delay relative to the first clock signal; Receive a phase-shifted clock signal, the phase-shifted clock signal having the frequency of the first clock signal and a second phase different from the first phase of the first clock signal; and Generate an indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal; and A delay adjustment circuit is configured to generate the delay adjustment signal based on the indication of the phase difference from the phase difference detection circuit; and A first phase interpolator circuit is used to generate the first clock signal based on multiple root clocks from the phase-locked loop; and A second phase interpolator circuit is used to generate the phase-shifted clock signal based on the plurality of root clocks from the phase-locked loop.

2. The calibrated SAR-ADC circuit according to claim 1, wherein: The delay control circuit is configured to generate the delay adjustment signal to control the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

3. The calibrated SAR-ADC circuit according to claim 1, wherein: The delay control circuit is configured to generate the delay adjustment signal to counteract the change in phase difference, thereby minimizing the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

4. The calibrated SAR-ADC circuit according to claim 1, wherein: The second phase of the phase-shifted clock signal lags behind the first phase of the first clock signal; and The delay control circuit is configured as follows: In response to the indication of the phase difference indicating that the phase of the monitored delayed clock signal leads the second phase of the phase-shifted clock signal, the delay control signal is adjusted to increase the delay of the monitored delayed clock signal relative to the phase-shifted clock signal; as well as In response to the indication of the phase difference indicating that the phase of the monitored delayed clock signal lags behind the second phase of the phase-shifted clock signal, the delay control signal is adjusted to reduce the delay of the monitored delayed clock signal relative to the phase-shifted clock signal.

5. The calibrated SAR-ADC circuit according to claim 1, wherein, The delay control circuit further includes: The delay control modification circuit is configured as follows: Receive the indication of the phase difference from the phase difference detection circuit; and A delay control signal is generated based on the overdrive signal to control the delay adjustment circuit to set the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

6. The calibrated SAR-ADC circuit according to claim 5, wherein: The delay control modification circuit includes a control signal generation circuit configured to generate the overdrive signal based on at least one of the following: The overdrive signal received at the overdrive input; A storage circuit configured to store the value of the overdrive signal; as well as The indication of the phase difference from the phase difference detection circuit.

7. The calibrated SAR-ADC circuit according to claim 1, wherein: The variable delay clock circuit includes: A series-coupled delay buffer is configured to delay the first clock signal; and Multiple tap outputs, coupled to the outputs of corresponding delay buffers; and A multiplexer circuit, coupled to the plurality of tap outputs of the variable delay clock circuit, is configured such that: Receive a selectable plurality of delayed clock signals from the plurality of delayed clock signals; Based on the selection signal, one of the optional multiple delayed clock signals is selected as a delayed clock signal; and The calibrated delay clock signal is generated based on a selected delay clock signal from the plurality of optional delay clock signals.

8. A method in a calibrated successive approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising: In the clock calibration circuit: Receive a first clock signal having a frequency and a first phase; as well as Multiple delayed clock signals are generated, each delayed clock signal being delayed relative to the first clock signal based on a delay adjustment signal; In SAR-ADC circuits: The voltage level on the analog data signal is sampled in response to the calibrated delayed clock signal among the plurality of delayed clock signals; as well as Generate a digital value corresponding to the sampled voltage level; as well as In the delay control circuit: Receive a monitored delayed clock signal from the plurality of delayed clock signals, wherein the monitored delayed clock signal is delayed by a selected delay relative to the first clock signal; Receive a phase-shifted clock signal, the phase-shifted clock signal having the frequency of the first clock signal and a second phase different from the first phase of the first clock signal; An indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal is generated; as well as The delay adjustment signal is generated based on the indication of the phase difference; In the first phase interpolator circuit: The first clock signal is generated based on multiple root clocks from the phase-locked loop; as well as In the second phase interpolator circuit: The phase-shift clock signal is generated based on the plurality of root clocks from the phase-locked loop.

9. The method according to claim 8, further comprising: The delay adjustment signal is generated to control the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

10. The method of claim 8, further comprising: The delay adjustment signal is generated to offset the change in phase difference, thereby minimizing the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

11. The method of claim 8, wherein: The second phase of the phase-shifted clock signal lags behind the first phase of the first clock signal; and Generating the delay adjustment signal further includes: In response to the indication of the phase difference indicating that the phase of the monitored delayed clock signal leads the second phase of the phase-shifted clock signal, the delay control signal is adjusted to increase the delay of the monitored delayed clock signal relative to the phase-shifted clock signal; as well as In response to the indication of the phase difference indicating that the phase of the monitored delayed clock signal lags behind the second phase of the phase-shifted clock signal, the delay control signal is adjusted to reduce the delay of the monitored delayed clock signal relative to the phase-shifted clock signal.

12. The method of claim 8, further comprising: The indication of the phase difference is received from the phase difference detection circuit; as well as A delay control signal is generated based on the overdrive signal to set the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal.

13. The method of claim 12, further comprising generating the overdrive signal based on at least one of the following: The overdrive signal received at the overdrive input; A storage circuit configured to store the value of the overdrive signal; and The indication of the phase difference from the phase difference detection circuit.

14. The method of claim 8, further comprising: The first clock signal is delayed in a series-coupled delay buffer; Receive, from the respective outputs of the series-coupled delay buffer, a selectable plurality of delayed clock signals from the plurality of delayed clock signals; Based on the selection signal, one of the multiple selectable delayed clock signals is selected; as well as The calibrated delay clock signal is generated based on a selected delay clock signal from the plurality of optional delay clock signals.

15. A time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) system, comprising: Multiple clock inputs are configured to receive multiple first clock signals, each first clock signal having a frequency and a corresponding phase; Multiple calibrated SAR-ADC circuits, each calibrated SAR-ADC circuit including: The clock calibration circuit is configured as follows: Generate a plurality of delayed clock signals, each delayed clock signal being based on a delay adjustment signal relative to a first clock signal among the plurality of first clock signals; and The SAR-ADC circuit is configured as follows: In response to a calibrated delayed clock signal among the plurality of delayed clock signals, the voltage level of the analog data signal is sampled; and Generate digital values ​​corresponding to the voltage levels sampled from the analog data signal; and Delay control circuit, including: The phase difference detection circuit is configured as follows: Receive the monitored delayed clock signal from one of the plurality of delayed clock signals from one of the plurality of calibrated SAR-ADC circuits; Receive a phase-shifted clock signal having the same frequency and a second phase, the second phase being different from the first phase of a first clock signal received in one of the plurality of calibrated SAR-ADC circuits; and An indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal is generated; A delay control modification circuit is configured to generate a delay control signal based on the indication of the phase difference from the phase difference detection circuit; and The delay adjustment circuit is configured to generate a first delay adjustment signal based on the delay control signal; and A first phase interpolator circuit is used to generate the first clock signal based on multiple root clocks from the phase-locked loop; and A second phase interpolator circuit is used to generate the phase-shifted clock signal based on the plurality of root clocks from the phase-locked loop, and in: The first delay adjustment signal is a delay adjustment signal in the clock calibration circuit of at least one of the plurality of calibrated SAR-ADC circuits.

16. The time-interleaved SAR-ADC system according to claim 15, wherein: The delay control circuit is configured to generate the first delay adjustment signal to control the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal in at least one of the plurality of calibrated SAR-ADC circuits.

17. The time-interleaved SAR-ADC system of claim 15, wherein the delay control modification circuit comprises: A control signal generation circuit, the control signal generation circuit being configured to generate the delayed control signal based on at least one of the following: The first overdrive signal received at the overdrive input; The stored value of the first overdrive signal stored in the storage circuit; and The indication of the phase difference from the phase difference detection circuit.

18. The time-interleaved SAR-ADC system of claim 17, further comprising a second delay control circuit, the second delay control circuit comprising: The second phase difference detection circuit is configured to generate a second indication of the second phase difference between the phase of the monitored delayed clock signal of another calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits and the second phase of the second phase-shifted clock signal, wherein the other calibrated SAR-ADC circuit is not among the at least one calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits. The second delay control modification circuit is configured to generate a second delay control signal based on the second indication of the second phase difference from the second phase difference detection circuit; as well as The second delay adjustment circuit is configured to generate a second delay adjustment signal based on the second delay control signal; The second delay adjustment signal is the delay adjustment signal in the clock calibration circuit of another calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits.

19. A method in a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) system, comprising: In each of the multiple calibrated SAR-ADC circuits: Receive one of a plurality of first clock signals, each first clock signal having a frequency and a corresponding first phase; In the clock calibration circuit, multiple delayed clock signals are generated, each delayed clock signal being delayed relative to one of the multiple first clock signals based on a delay adjustment signal; In the SAR-ADC circuit, the voltage level of the analog data signal is sampled in response to a calibrated delayed clock signal among the plurality of delayed clock signals; as well as In the SAR-ADC circuit, a digital value corresponding to the voltage level of the sampled analog data signal is generated; as well as In the delay control circuit: Receive the monitored delayed clock signal from one of the plurality of delayed clock signals from one of the plurality of calibrated SAR-ADC circuits; Receive a phase-shifted clock signal having the same frequency and a second phase, the second phase being different from the corresponding first phase of one of the plurality of first clock signals received in one of the plurality of calibrated SAR-ADC circuits; In the phase difference detection circuit, an indication of the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal is generated; In the delay control modification circuit, a delay control signal is generated based on the indication of the phase difference; as well as Based on the delay control signal, a first delay adjustment signal is generated; In the first phase interpolator circuit: The first clock signal is generated based on multiple root clocks from the phase-locked loop; as well as In the second phase interpolator circuit: The phase-shift clock signal is generated based on the plurality of root clocks from the phase-locked loop; in: The first delay adjustment signal is a delay adjustment signal in at least one of the plurality of calibrated SAR-ADC circuits.

20. The method of claim 19, further comprising: The first delay adjustment signal is generated to control the phase difference between the phase of the monitored delayed clock signal and the second phase of the phase-shifted clock signal in at least one of the plurality of calibrated SAR-ADC circuits.

21. The method of claim 19, further comprising: The delay control signal is generated in the first control signal generation circuit of the delay control modification circuit based on at least one of the following: The first overdrive signal received at the overdrive input; The stored value of the first overdrive signal stored in the storage circuit; and The indication of the phase difference from the phase difference detection circuit.

22. The method of claim 21, further comprising: In the second phase difference detection circuit, a second indication is generated of the second phase difference between the phase of the monitored delayed clock signal of another calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits and the second phase of the second phase-shifted clock signal, wherein the other calibrated SAR-ADC circuit is not among the at least one calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits. A second delay control signal is generated in the second delay control modification circuit; as well as In the second delay adjustment circuit, a second delay adjustment signal is generated based on the second delay control signal; The second delay adjustment signal is the delay adjustment signal in another calibrated SAR-ADC circuit among the plurality of calibrated SAR-ADC circuits.

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