Solid-state camera

Abstract

[Problem] In order to suppress the generation of distortion. [Solution] According to the present invention, a solid-state imaging device includes a first substrate and a second substrate, the first substrate includes a pixel array, wherein a plurality of pixels configured to output analog signals through photoelectric conversion are arranged two-dimensionally in columns along a first direction and rows along a second direction intersecting the first direction, and the second substrate is stacked on the first substrate and includes an analog circuit, which is positioned to overlap with the pixel array in a third direction intersecting the first direction and the second direction, and processes the analog signals output from the pixels. The pixel array is divided into a first area and a second area by a pixel dividing portion along the second direction, and each area includes continuous pixels. The analog circuit is connected to pixels belonging to the first area and pixels belonging to the second area, and is divided into adjacent first analog circuits and second analog circuits by a circuit dividing portion arranged to overlap with the pixel dividing portion along the third direction.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device. Background Art

[0002] Conventional sensors such as CMOS (Complementary Metal Oxide Semiconductor) devices including a pixel array in which pixels are arranged obtain signals from predetermined devices in sequence, which disadvantageously reduces the frame rate. A possible configuration for increasing the frame rate includes a pixel array divided into a plurality of regions, and an analog circuit and a logic circuit for receiving signals, the pixel array having a signal line provided for each divided region. This configuration, which has poor compatibility with other circuits and may be complicated, is not suitable for minimization of pixel size and multi-pixelization.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Publication No. 2012-054876 Summary of the invention

[0006] Technical issues

[0007] In order to avoid the above situation, it is possible to consider dividing the pixel array into simple areas. Simple division allows multiple pixels in the pixel array that are adjacent to each other but to be processed by different analog circuits (i.e., pixels that are adjacent to each other with a boundary between regions inserted therebetween) to propagate through signal lines with different signal processing timings. Due to the different timings of signal processing, pixels that are adjacent to each other with a boundary inserted therebetween may have significantly different timings of light reception compared to other pixels that are adjacent to each other. This will cause deformation of the rolling shutter at the boundaries between regions.

[0008] The present disclosure provides a solid-state image pickup device including a plurality of regions in a pixel array and in which the occurrence of deformation is reduced.

[0009] Solution to the problem

[0010] According to one embodiment, a solid-state imaging device includes a first substrate and a second substrate. The first substrate includes a pixel array, wherein a plurality of pixels configured to output analog signals by photoelectric conversion are arranged in two dimensions in columns along a first direction and rows along a second direction intersecting the first direction. The second substrate is stacked on the first substrate and includes an analog circuit positioned to overlap the pixel array in a third direction intersecting the first direction and the second direction, and processes analog signals output from the pixels. The pixel array is divided into a first region and a second region by a pixel separator along the second direction, each region including continuous pixels. The analog circuit is divided into a first analog circuit and a second analog circuit, which are connected to pixels belonging to the first region and pixels belonging to the second region, and the first analog circuit and the second analog circuit are adjacent to each other with a circuit separator interposed therebetween, and the circuit separator is positioned to overlap the pixel separator in the third direction.

[0011] The pixel array may include a plurality of first signal lines arranged along a first direction, and one or more rows in the first direction are selected from rows having pixels continuous in a second direction, and analog signals output from pixels selected by the first signal lines may be processed by an analog circuit. Through the first signal lines, pixels can be specified in units of rows.

[0012] The pixel array may include a plurality of second signal lines arranged along the second direction, and one or more columns in the second direction are selected from columns having pixels continuous in the first direction, analog signals output from pixels selected by the first signal lines are transmitted through the second signal lines and processed by analog circuits, and the second signal lines may be electrically separated at the pixel separators. The second signal lines are kept powered on region by region in the pixel array without being connected to different regions, which enables shortening of their routes.

[0013] The pixel dividing portion and the circuit dividing portion may be located near the middle of the pixel array in the first direction.

[0014] The solid-state imaging device may include a connection portion configured to connect the pixels and the analog circuit in a third direction at the pixel separation portion and the circuit separation portion. Therefore, the second signal line can be separated near the middle of the pixel array, and the first substrate and the second substrate can be connected to each other near the separation.

[0015] The connection portion may include a first connection portion and a second connection portion, the first connection portion being connected to the second signal line and being configured to connect the pixels belonging to the first region and the first analog circuit through the second signal line, and the second connection portion being connected to the second signal line and being configured to connect the pixels belonging to the second region and the second analog circuit through the second signal line. The analog circuit of the second substrate may also be divided like the pixel array.

[0016] The solid-state imaging device may include a first switch configured to switch the connection state between the first connection portion and the second connection portion. By providing the first switch in the second substrate, the potentials of the floating diffusion portions in the first region and the second region in the pixel array can be kept comparable.

[0017] The first switch may switch a connection state between the first connection portion and the second connection portion based on a timing of an analog signal output to the analog circuit through the first connection portion or the second connection portion.

[0018] A plurality of first connection parts, a plurality of second connection parts, and a plurality of first switches may be provided along the second direction, and the plurality of first switches may be operable in a synchronized manner.

[0019] A plurality of first connection parts and a plurality of second connection parts may be provided along the second direction, and the solid-state imaging device may include a second switch configured to switch the connection state between the plurality of first connection parts and a third switch configured to switch the connection state between the plurality of second connection parts. The second switch can keep the potential in the row direction equivalent.

[0020] The second switch may switch the connection state between the first connection parts, and the third switch may switch the connection state between the second connection parts, based on the timing of the analog signal output to the analog circuit through the first connection part or the second connection part.

[0021] The second switch and the third switch can be operated in a synchronized manner.

[0022] A plurality of second switches and a plurality of third switches may be provided along the second direction, and the plurality of second switches and the plurality of third switches may be operable in a synchronized manner.

[0023] The solid-state imaging device may include a first voltage source and a fourth switch, the first voltage source being configured to apply a predetermined voltage to a plurality of first connection portions connected via a second switch, the fourth switch being configured to switch the connection state between the first voltage source and the plurality of first connection portions, and the second switch and the fourth switch being operable in a synchronized manner. Such control makes it possible to raise the potential of the floating diffusion portion to a predetermined potential.

[0024] The solid-state imaging device may include a second voltage source and a fifth switch, wherein the second voltage source is configured to apply a predetermined voltage to a plurality of second connection portions connected by a third switch, and the fifth switch is configured to switch the connection state between the second voltage source and the plurality of second connection portions, and the third switch and the fifth switch can be operated in a synchronized manner. Further, all switches can be operated in a synchronized manner. The synchronization can be performed at a timing based on a reset timing of a pixel or a timing of outputting an analog signal from a pixel.

[0025] The number of the first connecting portions and the number of the second connecting portions may each be at least the same as the number of pixels present in a row.

[0026] The number of the first connection parts and the second connection parts may be at least the same as the product of the number of pixels existing in the row and the predetermined number, respectively. By providing the connection parts as described above, signals output from pixels belonging to the same row can be transmitted to the second substrate in parallel.

[0027] The connection portion may be in the form of a micro-bump, a micro-pad, or a via.

[0028] The first analog circuit and the second analog circuit may process analog signals from different pixels belonging to one or more rows along the second direction at the same timing.

[0029] The first analog circuit and the second analog circuit may change the number of analog signals to be processed at the same timing according to predetermined conditions.

[0030] The second substrate may convert the analog signal into a digital signal, and the solid-state imaging device may include a logic circuit configured to process the digital signal.

[0031] The logic circuit may be positioned to intersect the analog circuit in a first direction.

[0032] The logic circuit may include a first logic circuit configured to process a digital signal output from the first analog circuit and a second logic circuit configured to process a digital signal output from the second analog circuit.

[0033] The solid-state image pickup device may include a plurality of pixel dividing sections and a plurality of circuit dividing sections as well as a pixel array divided into a plurality of regions and an analog circuit corresponding to each region.

[0034] The second substrate may include a signal processing circuit, an image processing circuit, a storage unit, a selector, and an interface. The signal processing circuit performs signal processing on a digital signal. The image processing circuit performs image processing on a digital signal, and the digital signal includes image information. The storage unit stores data freely selected from the digital signal, the data output from the signal processing circuit, and the data output from the image processing circuit. The selector freely selects at least one of the data output from the signal processing circuit, the data output from the image processing circuit, or the data stored in the storage unit. The interface outputs the data or signal selected by the selector to the outside, or receives input of data or signals from the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a block diagram of a solid-state imaging device according to an embodiment.

[0036] Figure 2 is a diagram showing the locations of a pixel array and analog circuits according to an embodiment.

[0037] Figure 3 is a diagram showing a stacked state of a pixel array and an analog circuit according to an embodiment.

[0038] Figure 4 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0039] Figure 5 is a diagram showing an overview of a simulation circuit according to an embodiment.

[0040] Figure 6 is a diagram showing potentials in response to switch control of a second substrate according to an embodiment.

[0041] Figure 7 is a graph showing potentials in response to switch control of the second substrate according to a comparative example.

[0042] Figure 8 is a diagram showing a stacked state of a pixel array and an analog circuit according to an embodiment.

[0043] Fig. 9 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0044] Fig.10 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0045] Fig.11 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0046] Fig.12 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0047] Fig.13 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0048] Fig.14 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0049] Fig.15 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0050] Fig.16 is a diagram showing an example of a connection portion according to an embodiment.

[0051] Fig.17 is a diagram showing an example of a connection portion according to an embodiment.

[0052] Fig.18 is a diagram showing an example of a connection portion according to an embodiment.

[0053] Fig.19 : is a diagram showing an example of the position of the circuit of the second substrate according to one embodiment.

[0054] Fig. 20 : is a diagram showing a stacked state of a solid-state imaging device according to an embodiment.

[0055] Fig.21 : is a diagram showing a stacked state of a solid-state imaging device according to an embodiment.

[0056] Fig. 22 is a diagram illustrating application of voltage to an analog circuit according to an embodiment.

[0057] Fig.23 is a block diagram showing an example of an indirect time-of-flight sensor to which the present technology is applied.

[0058] Fig.24 10230 is a circuit diagram showing an example of the construction of the pixel 10230 in an embodiment of the present technology.

[0059] Fig.25 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0060] Fig.26 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0061] Hereinafter, a solid-state imaging device according to several embodiments will be described with reference to the drawings.

[0062] (First embodiment)

[0063] Figure 1 1 is a block diagram showing the functions of a solid-state imaging device 1 according to an embodiment. The solid-state imaging device 1 includes, for example, a first substrate 10 and a second substrate 20. The first substrate 10 includes an optical system 12 and a pixel array 14. The second substrate 20 includes an analog circuit 22, a logic circuit 24, and an input / output interface (hereinafter referred to as input / output I / F) 26.

[0064] The optical system 12 is a system that corrects an optical path, aberration, etc. in such a manner that the pixel array 14 detects light. The optical system 12 including, for example, a lens (including a virtual lens, etc.) is installed so that the pixel array 14 appropriately receives light.

[0065] The pixel array 14 includes a plurality of pixels that perform photoelectric conversion on received light and output analog signals. The analog signal output from each pixel belonging to the pixel array 14 is transmitted to the second substrate 20 through the connection portion 30 .

[0066] The analog circuit 22 is a circuit that processes an analog signal output from each pixel of the pixel array 14. The analog circuit 22 may include, for example, an ADC (Analog-to-Digital Converter) that converts an analog signal into image data or a digital signal. The analog circuit 22 outputs the digital image data converted from the analog signal to the logic circuit 24.

[0067] The analog circuit 22 may also include, for example, a DAC (digital-to-analog converter) that generates a digital signal for analog-to-digital conversion, a comparator that compares a voltage output from the DAC and an analog signal, a counter that counts outputs from the comparator, and an amplifier that amplifies the output of the counter.

[0068] The logic circuit 24 including circuits for processing various obtained digital signals performs appropriate signal processing on the digital signals output from the analog circuit 22. For example, the logic circuit 24 as a digital circuit may include a signal processing circuit and an image processing circuit. The image processing circuit may include, for example, a circuit for performing motion detection, a circuit for performing neural network processing, etc. The image processing circuit may include, for example, a circuit for performing various filtering processing, deformation processing, etc.

[0069] The input / output I / F 26 is an interface that outputs data output from the logic circuit 24 to the outside as needed and receives data input, requests, etc. from the outside. The solid-state imaging device 1 may further include a selector that selects data output from the logic circuit 24, and the input / output I / F 26 may output a signal selected by the selector to the outside.

[0070] The connection portion 30 connects the first substrate 10 and the second substrate 20. In the present embodiment, in particular, the connection is intended to output analog signals output from pixels belonging to the pixel array 14 located on the first substrate 10 to the analog circuit 22 located on the second substrate 20.

[0071] What has been described above are components related to the propagation paths of analog signals and digital signals according to the present embodiment. Therefore, any other components required for control are omitted. The first substrate 10 is appropriately provided with, for example, wiring that determines which pixel of the pixel array 14 is to receive the output, etc. In addition, the second substrate 20 is appropriately provided with a control circuit responsible for controlling the components of the solid-state imaging device 1, etc. In addition, in addition to the above-mentioned connection portion 30, the connection between the first substrate 10 and the second substrate 20 may be appropriately additionally provided with, for example, a connection circuit for outputting a signal to a wiring that determines which pixel is selected from the pixels belonging to the pixel array 14.

[0072] Therefore, although not shown, elements, wirings, and the like for realizing the operation and effects of the solid-state imaging device 1 are appropriately provided.

[0073] Figure 2is a diagram showing an example of the positions of the pixel array 14 and the analog circuit 22 according to the present embodiment.

[0074] In the first substrate 10, the pixel array 14 includes a plurality of pixels 140 arranged in two dimensions. The pixels 140 are arranged in a first direction and a second direction. The pixels 140, for example, respectively include light receiving devices such as photodiodes (PDs), which receive light through a lens (i.e., the optical system 12) and output analog signals based on the intensity of the received light, etc. In the description, pixels that are continuous in the second direction are sometimes referred to as rows, and pixels that are continuous in the first direction are sometimes referred to as columns. That is, a plurality of rows of pixels that are continuous in the second direction are arranged in the first direction to form an array; in other words, a plurality of columns of pixels that are continuous in the first direction are arranged in the second direction to form an array.

[0075] The pixel array 14 has a first region 141 and a second region 142. The first region 141 and the second region 142 are separated from each other by a pixel separator 143. The pixel separator 143 is provided, for example, near the middle in the first direction in such a manner as to span the pixel array 14 in the second direction.

[0076] The term "near the middle" means that, for example, in the case where the pixel array 14 includes n pixels 140 arranged along the first direction, the pixel separator 143 is arranged between the [n / 2]th pixel and the ([n / 2]+1)th pixel. [·] represents a floor function. It should be noted that this is not restrictive and the pixel separator 143 may be significantly or insignificantly offset to Figure 2 The pixel array 14 may be positioned at one of the upper side and the lower side thereof, rather than being exactly centered; however, “near the middle” is broad in meaning herein.

[0077] In the second substrate 20, the analog circuit 22 is provided, for example, near the middle of the region where the pixel array 14 exists in a stacked state. In the second substrate 20, the dotted line indicates the range of the pixel array 14 provided in the first substrate 10 in a stacked state. Therefore, the analog circuit 22 is provided so as to include the middle portion of the range where the pixel array 14 is provided and its vicinity.

[0078] The analog circuit 22 includes a first analog circuit 221 and a second analog circuit 222, and these circuits are disposed adjacent to each other with a circuit divider 223 interposed therebetween. In a case where the first substrate 10 and the second substrate 20 are stacked, the circuit divider 223 is positioned so that, for example, it overlaps with the pixel divider 143 in the third direction. The position of the circuit divider 223 does not necessarily completely overlap with the pixel divider 143 and may be offset thereby.

[0079] The first analog circuit 221 and the second analog circuit 222 each operate as an analog circuit. For example, the first analog circuit 221 and the second analog circuit 222 each operating as an ADC converts analog signals output from the pixel 140 into digital signals and outputs them.

[0080] For example, in the vicinity of the pixel dividing portion 143 and the circuit dividing portion 223 , the pixel array 14 and the analog circuit 22 are connected by the connecting portion 30 that connects the first substrate 10 and the second substrate 20 .

[0081] Here, "nearby" refers to, for example, between two pixels 140 closest to the pixel separator 143 in the first direction and the pixel separator 143. It should be noted that this is not restrictive, and for example, the connection portion 30 may not be located between the pixel 140 and the pixel separator 143, but may be positioned so that it overlaps with one or more pixels 140 directly below it near the middle.

[0082] Figure 3 Schematically shows the positions of the pixel array 14 and the analog circuit 22 when the first substrate 10 and the second substrate 20 are stacked. Figure 3 As shown, the pixel array 14 and the analog circuit 22 are stacked so that the pixel dividing section 143 and the circuit dividing section 223 overlap each other in the third direction near the middle of the pixel array 14 .

[0083] The connection portion 30 is positioned to connect the vicinity of the pixel dividing portion 143 and the vicinity of the circuit dividing portion 223 to each other along the third direction between the pixel array 14 and the analog circuit 22. The first analog circuit 221 and the second analog circuit 222 receive analog signals from the pixels 140 connected via the connection portion 30 and perform appropriate processing. As described later, for example, a digital circuit (logic circuit) is provided so that it is sandwiched outside the first analog circuit 221 and the second analog circuit 222 in the first direction.

[0084] Next, the connection between the pixel array 14 and the analog circuit 22 will be described in detail.

[0085] Figure 4 1 is a diagram showing an example of wiring of the pixel array 14 according to the present embodiment. The analog signal output from the pixel 140 is transmitted through Figure 4 The wiring in is transmitted to the analog circuit 22. It should be noted that Figure 4 , the distance between pixels above and below the pixel separator 143 is drawn wider than the distance between other pixels; however, this is only for convenience of explanation, and the distance may actually be comparable to the distance between other pixels.

[0086] In the first substrate 10, the pixel array 14 is provided with a plurality of first signal lines 16 and a plurality of second signal lines 181 and 182. The second signal lines 181 and 182 of the same column are electrically separated near the pixel separator 143. In other words, in the first substrate 10, the second signal lines 181 connected to the pixels 140 belonging to the first region 141 and the second signal lines 182 connected to the pixels 140 belonging to the second region 142 are not directly electrically connected to each other.

[0087] Furthermore, the connection portion 30 includes a plurality of first connection portions 301 and a plurality of second connection portions 302 near the pixel dividing portion 143, and the pixels 140 are connected to the analog circuit 22 of the second substrate 20 through the second signal lines 181 and 182 and the connection portions. More specifically, the pixels 140 belonging to the first region 141 are connected to the analog circuit 22 through the second signal line 181 and the first connection portion 301, and the pixels 140 belonging to the second region 142 are connected to the analog circuit 22 through the second signal line 182 and the second connection portion 302.

[0088] The first signal line 16 is a wiring for selecting which row of pixels 140 in the pixel array 14 is to be processed for the analog signal output. For example, at the ends opposite to the connection with the pixels 140, the first signal lines 16 respectively connected to the row selection circuit select the row of the signal to be output to the analog circuit 22 according to the signal from the row selection circuit.

[0089] The pixels 140 in rows selected by the first signal line 16 are transmitted to the first connection section 301 or the second connection section 302 through the second signal lines 181 and 182. Then, the first connection section 301 or the second connection section 302 outputs the analog signal output from the pixel 140 to the analog circuit 22 where analog signal processing is performed.

[0090] In the pixel array 14, the processing of the analog signal output from the pixel 140 is performed, for example, Figure 4 For example, first execute the Figure 4 The processing is performed on the pixels 140 in the bottom row of the image. The respective analog signals output from the pixels 140 are processed in parallel in the analog circuit 22. Next, the upper row (i.e., the second row from the bottom) is processed in the same manner. This processing is performed, for example, by selecting rows in sequence from the bottom from the row selection circuit according to a row-direction synchronization signal.

[0091] This also applies to the case where a pixel separator 143 is inserted between two rows; Figure 4After processing the row directly below the pixel divider 143 in the first region 141, processing is performed on the row directly above the pixel divider 143. In this case, the signal from the pixel 140 belonging to the region 141 is transmitted to the analog circuit 22 through the second signal line 181 and the first connection portion 301, and the signal from the pixel 140 belonging to the second region 142 is transmitted to the analog circuit 22 through the second signal line 182 and the second connection portion 302. Subsequently, scanning is sequentially performed from the lower side to the upper side of the second region 142 based on the synchronization signal in the row direction as well.

[0092] For example, row selection is performed by applying a selection signal to one of the first signal lines 16 corresponding to the row selected by the row selection circuit based on the synchronization signal. The current carrying state of the signal output portion of the pixel 140 belonging to the selected row and the second signal lines 181 and 182 is controlled by the selection signal, so that the analog signal is output to the analog circuit 22. For example, the control of the current carrying state is performed by a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transisto: Metal Oxide Semiconductor Field Effect Transistor) having a gate connected to the first signal line 16 and having a drain and a source (alternatively, a source and a drain) connected to the pixel 140 and the second signal lines 181 and 182, respectively. This is not restrictive, and the current carrying state can be realized by any other technology, for example, by a switch driven by a signal through the first signal line 16.

[0093] As described above, the area of ​​the pixel array 14 provided in the first substrate 10 is divided near the middle portion, and the analog circuit 22 is located near the middle portion in the stacked second substrate 20 to overlap, which makes it possible to shorten the transmission path of the signal output from the pixel 140 in the second signal lines 181 and 182. Due to the shortening of the transmission path, the load on the second signal lines 181 and 182 can be reduced. Therefore, as the solid-state imaging device 1, power reduction and high-speed processing of analog signals can be achieved. Due to the continuous processing of the rows on the pixel array 14 and the high-speed, the deformation of the rolling shutter can also be reduced.

[0094] (Second embodiment)

[0095] In the above embodiment, by additionally providing a switch in the second substrate 20 , the accuracy of analog signal processing can be further improved.

[0096] Figure 5 Schematically shows the connection near the circuit partitioning portion of the analog circuit 22 according to the present embodiment. Figure 5 The aspect ratio is adjusted in Figure 4 The approximate stacking relationship and approximate size relationship of the pixel array 14 in Figure 3 same.

[0097] As described above, the analog circuit 22 includes the first analog circuit 221 and the second analog circuit 222 with the circuit dividing section 220 interposed therebetween.

[0098] For example, the wiring connecting the first connection part 301 from the first substrate 10 is located in the first analog circuit 221. For example, the wiring connecting the second connection part 302 from the first substrate 10 is located in the second analog circuit 222. As shown in the figure, the connection part is respectively connected to the first analog circuit 221 or the second analog circuit 222 through, for example, a multiplexer (or an analog switch) to process the transmitted analog signal. The analog circuit 22 may include a comparison circuit and a counter circuit not shown before the multiplexer so that a digital signal converted based on the output from the DAC is output to the multiplexer, etc.

[0099] In the second substrate 20 , the first switch 281 is provided between the first connection portion 301 and the second connection portion 302 .

[0100] The plurality of first connection parts 301 are connected to each other along the second direction, and the second switch 282 is disposed between the first connection parts 301. The plurality of second connection parts 302 are connected to each other along the second direction, and the third switch 283 is disposed between the second connection parts 302.

[0101] The plurality of first connection parts 301 are connected to a voltage source through a fourth switch 284, for example, at one end of a wiring that connects them to each other through a second switch 282. The plurality of second connection parts 302 are connected to a voltage source through a fifth switch 285, for example, at one end of a wiring that connects them to each other through a third switch 283. The voltage source may be a constant voltage source. In addition, the voltages applied by the voltage sources may be the same.

[0102] The plurality of first switches 281 synchronously switch respective current-carrying states between the first connection portion 301 and the second connection portion 302. In other words, the first connection portion 301 is respectively connected to the second connection portion 302 at a predetermined timing, and the second connection portion is connected to the second signal line 182 belonging to the same column of the second signal line 181 connected to the first connection portion in the pixel array 14. This connection is performed synchronously, which enables the second signal line 181 and the second signal line 182 belonging to the same column in the plurality of columns to be connected at the same timing in the second substrate 20. Therefore, the potential of the first connection portion 301 and the second connection portion 302 are controlled to be the same potential at a predetermined timing, and the potential is output to the first analog circuit 221 and the second analog circuit 222. Due to this control, the potential of the points in the analog circuit 22 to process the pixels in the same column can be made equal.

[0103] The second switch 282 synchronously switches the current carrying state between the first connection parts 301. The third switch 283 synchronously switches the current carrying state between the second connection parts 302. Further, the second switch 282 and the third switch 283 synchronously switch the current carrying state. In other words, the plurality of first connection parts 301 and the plurality of second connection parts 302 are connected to each other in a predetermined timing and are controlled to be the same potential. Due to this control, the potential of the floating diffusion part of the pixel 140 can be equalized.

[0104] Further, the second switch 282 and the third switch 283 may be synchronized to control the fourth switch 284 and the fifth switch 285. Such control makes it possible to increase the potential of the floating diffusion of the pixel 140 to a predetermined potential at a predetermined timing.

[0105] Further, the first switch 281, the second switch 282, the third switch 283, the fourth switch 284, and the fifth switch 285 can be switched in a synchronized manner. For example, from a reset period when an analog signal from the pixel 140 is received and the processing of the analog signal is completed to a next transmission period, the switches can be synchronized to be powered on. This processing makes it possible to raise the potential of the floating diffusion portion of the pixel 140 to a predetermined potential, and further make the potentials of the first analog circuit 221 and the second analog circuit 222 equal.

[0106] Figure 6 An example of a timing diagram of the potentials of the first analog circuit 221 and the second analog circuit 222 when controlled by using the above-mentioned switch provided in the second substrate 20 is shown. The topmost diagram is a row synchronization signal output from the row selection circuit. The analog signals from the pixels 140 belonging to one row are processed in parallel based on the row synchronization signal. The dotted line represents a reset signal, for example, a charge in the reset circuit at this timing. At the moment shown by the dotted line, the row in which the processing is switched from the first analog circuit 221 to the second analog circuit 222 is crossed.

[0107] The second figure from the top is a switch example of a switch. The switch is turned on / off according to a synchronization signal. For example, the states of all switches may be switched according to the synchronization signal, or only the first switch 281 may be switched independently, only the combination of the second switch 282 and the third switch 283 may be switched independently, and only the combination of the second switch 282, the third switch 283, the fourth switch 284, and the fifth switch 285 may be switched independently.

[0108] In the present embodiment, for example, a synchronization signal is issued at the moment when the row scan is completed. This is only an example and is not restrictive. For example, it is only necessary to issue a synchronization signal between the reset signal and the row synchronization signal. This moment can be written into a register or the like provided in the solid-state imaging device 1. In addition, the synchronization signal (i.e., the period when the switch is turned on) can also be set as desired within the range of appropriate signal processing.

[0109] The third and fourth figures from the top are diagrams showing potential transitions in the standby state, respectively. The fifth and sixth figures from the top are diagrams showing potential transitions in the state of receiving analog signals, respectively. The potential transitions show, for example, changes in signals at the first connection portion 301 and the second connection portion 302.

[0110] In the diagram representing the potential state, the solid line represents the actual potential of the connection, and the dotted line represents that the potential state is unknown because the circuit is disconnected.

[0111] In contrast, Figure 7 FIG. 1 is a diagram showing a case where no switch control is performed (ie, all switches are turned off) as a comparative example. Figure 6 and Figure 7 To illustrate the function of the switch.

[0112] In the absence of the first switch 281, the processing of the first area 141 and the processing of the second area 142 are continuously performed in the first analog circuit 221 and the second analog circuit 222. In this case, at the timing of processing the pixels 140 belonging to the rows between which the pixel separators 143 are present (eg, Figure 7 Before the second analog circuit 222 is in the floating state, the potential is unknown. Since the signal processing is performed from the unknown potential, it is likely that a discontinuous signal will appear. The discontinuity of the signal also does not occur in the standby state, but even at the moment of signal processing.

[0113] At the same time, the circuit can be switched at the moment of eliminating the potential difference between the first analog circuit 221 and the second analog circuit 222 by turning on the first switch 281 at the end of the row in response to the synchronization signal. Figure 6 As shown by the arrows in , switching enables processing of analog signals from the pixel 140 while maintaining continuity of the signal potential. Therefore, noise contamination due to discontinuity, excessive transient response, or measured potential lower than the actual situation can be reduced.

[0114] The synchronous switching of the second switch 282 and the third switch 283 can shorten the Figure 7 The dotted lines in the figure show the floating period where the state is unknown. Figure 7In the case of region switching, the process starts from a floating state where the potential is unknown. Figure 6 As shown hashed, a stable analog signal can be obtained from the pixel 140 .

[0115] Furthermore, synchronization of the fourth switch 284 and the fifth switch 285 makes it possible to control the floating potential to a predetermined value. Therefore, a more stable measurement result can be obtained.

[0116] As described above, continuity is ensured by the first switch 281 , and the potential of the floating diffusion can be stabilized by the second switch 282 , the third switch 283 , the fourth switch 284 , and the fifth switch 285 , which enables high-precision processing even when the analog circuit 22 is divided.

[0117] It should be noted that, as described above, only the first switch 281 may be switched, or only the second switch 282 to the fifth switch 285 may be switched. Further, the first switch 281 to the fifth switch 285 may be switched synchronously. Alternatively, in another example, in the case where the second switch 282 to the fifth switch 285 are turned on, control may be performed at a timing thereafter to turn on the first switch 281.

[0118] It should be noted that control can be performed as follows.

[0119] For example, at the time of processing the analog signal from the pixel 140 belonging to the first area 141, the third switch 283 that connects the second connection parts 302 to each other can be always connected. By maintaining the connection state in this way, a relatively floating state can be maintained in the column until the pixel 140 to be processed is transferred from the first area 141 to the second area 142.

[0120] Further, the fifth switch 285 may be in a connected state. By the third switch 283 and the fifth switch 285 thus being in a connected state, the floating state in the column can be maintained at a predetermined potential.

[0121] Likewise, when processing analog signals from the pixels 140 belonging to the second region 142 , the second switch 282 may be always connected, or the second switch 282 and the fourth switch 284 may be always connected.

[0122] (Third Embodiment)

[0123] In the configuration of the above-described embodiment, one pixel dividing section 143 and one corresponding circuit dividing section 223 are provided respectively; however, this is not restrictive. In other words, the pixel array 14, the analog circuit 22, and the logic circuit 24 may be divided into more areas.

[0124] Figure 82 is a diagram showing a stacked state of the pixel array 14 and the analog circuit 22 according to the present embodiment. The pixel array 14 includes three pixel separators 143A, 143B, and 143C, and the second substrate 20 corresponding thereto includes at least circuit separators 223A and 223B, and further includes a circuit separator 223C. It should be noted that the circuit separator 223C is not an essential component.

[0125] The pixel array 14 is divided into two large areas by the pixel divider 143C. These areas are divided into a first area 141A and a second area 142A by the pixel divider 143A, and into a first area 141B and a second area 142B by the pixel divider 143B. Thus, the pixel array 14 is divided into four areas, for example.

[0126] For pixels 140 that are continuous in the second direction, i.e., pixels that belong to the same row, a single first signal line is provided as in the above-described embodiment. Meanwhile, second signal lines connected to pixels 140 that are continuous in the first direction and belong to regions 141A, 142A, 141B, and 142B are divided between the regions as in the above-described embodiment, and are output to the analog circuit 22 through corresponding connection portions. In other words, in Figure 8 In the example of , four second signal lines are set for each column.

[0127] Fig. 9 1 is a diagram showing an overview of the pixel array 14 according to the present embodiment. The pixel array 14 is divided into regions 141A, 142A, 141B, and 142B by pixel dividers 143A, 143B, and 143C. The divided regions are respectively provided with the same number of first signal lines 16 as the number of rows where the pixels 140 are located, for selecting whether to output the pixels 140 belonging to the same row. Figure 4 As shown, the distance between pixels is wider at locations that straddle the pixel dividers; however, this is for ease of illustration only, and in practice, the distance may be comparable to the distance between other pixels.

[0128] In contrast, the second signal lines are arranged so that they are respectively connected to the outputs of the pixels 140 belonging to the same column in each region, while being separated between different regions. For example, a plurality of second signal lines 181A arranged in region 141A connect the pixels 140 belonging to each column. At the same time, the second signal lines 181A are arranged so that they are not electrically connected to the second signal lines 182A, 181B, and 182B in other regions 142A, 141B, and 142B.

[0129] The signal line is connected to the second substrate 20 through the connection portion. For example, the second signal line 181A in the first region 141A is connected to the analog circuit 22A through the first connection portion 301A. The same is true for other signal lines; the second signal line 182A in the second region 142A is connected to the analog circuit 22A through the second connection portion 302A. In addition, the upper side in the figure is the same as the lower side, the second signal line 181B in the first region 141B is connected to the analog circuit 22B through the first connection portion 301B, and the second signal line 182B in the second region 142B is connected to the analog circuit 22B through the second connection portion 302B.

[0130] The pixel array 14 may be divided into a plurality of regions by the plurality of pixel dividers 143 as described above. Fig. 9 As shown, the second signal lines and the connection portions independently provided in each region are respectively connected to the analog circuits 22 of the second substrate 20 .

[0131] Return to Figure 8 , the second substrate 20 is provided. Fig. 9 The area of ​​the connection portion 30 is provided with a corresponding analog circuit. For example, the second substrate 20 includes an analog circuit 22A and an analog circuit 22B.

[0132] As described in the above embodiment, the circuit dividers 223A and 223B exist in each analog circuit 22 so that they overlap with the pixel dividers 143A and 143B in the third direction in a stacked state. The analog circuit 22A is divided into the first analog circuit 221A and the second analog circuit 222A by the circuit divider 223A, and the analog circuit 22B is divided into the first analog circuit 221B and the second analog circuit 222B by the circuit divider 223B. The configuration of each circuit is similar to Figure 5 The structure is equivalent to that in , so its detailed description is omitted.

[0133] For example, the logic circuit may be provided on the lower side of the first analog circuit 221A, between the second analog circuit 222A and the first analog circuit 221B, and on the upper side of the second analog circuit 222B in the drawing.

[0134] As described above, it is possible to increase the number of divisions of the pixel array 14. Such an increase in the number of divisions makes it possible to further reduce the load on the second signal line, thereby achieving further speed-up and reduction in power consumption.

[0135] (Fourth embodiment)

[0136] In the above embodiment, one second signal line is provided for one column; however, this is not restrictive. For example, a plurality of second signal lines may be provided for the pixels 140 belonging to one column. The plurality of second signal lines may be provided with respective connection portions.

[0137] Fig.10 Schematically shows the outline of the pixel array, the second signal line and the connection portion according to the present embodiment. In the accompanying drawings, the pixels, the wiring, the connection portion, etc. are drawn on a plane; however, this is not restrictive. For example, the following structure is also acceptable: the pixels are located on the upper surface, the wiring is provided below it along the third direction, and the wiring and the connection portion are connected within the first substrate 10.

[0138] The pixel array 14 includes a plurality of pixels 140. A plurality of second signal lines 181 and 182 are provided so that outputs from the pixels 140 belonging to the same column are connected thereto respectively. Unlike the above-described embodiment, the plurality of second signal lines 181 and 182 are provided between the columns. It should be noted that the first signal lines omitted from the illustration for the sake of convenience of explanation are shown in FIG. Figure 4 Set up as shown.

[0139] For example, 12 second signal lines 181 and 182 may be provided in each space between the columns of the pixels 140. In this case, analog signals output from 12 or less pixels 140 along the first direction may be output in parallel to the analog circuit 22 of the second substrate 20. In other words, processing of analog signals may be applied in parallel to the pixels 140 belonging to rows less than 12 rows at the same timing.

[0140] The first signal line not shown specifies 12 or fewer rows at the same timing. In the drawings, the positions of the wiring and the second signal line connected from the pixel 140 are indicated by black dots as electrically connected positions, and the positions without black dots are electrically unconnected positions. For example, a switch is set at the intersection of the wiring from the pixel 140 and the second signal line, and the state of the switch is appropriately switched by the first signal line, so that the pixel 140 to be subjected to analog signal processing can be selected.

[0141] As an example, Fig.11 14 is a diagram showing the wiring of an analog circuit having 12 pairs of second signal lines and 12 pairs of connection portions. The left diagram shows the signal distribution when processing an analog signal from a pixel 140 belonging to a first region 141, and the right diagram shows the signal distribution when processing an analog signal from a pixel 140 belonging to a second region 142.

[0142] In the left figure, the first connection portion 301 is represented by a solid line, and the second connection portion 302 is represented by a dotted line. Therefore, for each column, 12 pairs of connection portions are provided from the first substrate 10 to the second substrate 20. The 6 pairs of connection portions on the left allow the transmission of signals processed by the first analog circuit 221, while the 6 pairs of connection portions on the right allow the transmission of signals processed by the second analog circuit 222. The first switch 281, the second switch 282, and the third switch 283, which are not shown, may be provided between the respective connection portions. Further, a fourth switch 284, a fifth switch 285, and a voltage source may be provided.

[0143] As shown in the left figure, when the pixel 140 belonging to the first area 141 becomes the processing object, the analog signal output from the first connection portion 301 is appropriately distributed and output to the first analog circuit 221 and the second analog circuit 222. Then, the analog circuit processes the analog signal in parallel. Therefore, the signals from multiple pixels 140 can be output to multiple analog circuits through a shorter path.

[0144] When the pixel 140 to be subjected to signal processing is changed from a pixel belonging to the first area 141 to a pixel belonging to the second area 142, that is, when the first signal line selected by the row selection circuit exceeds the pixel dividing portion 143, a change occurs as shown in the right figure. In response to this change, the second connection portion 302 is allocated and connected to the first analog circuit 221 and the second analog circuit 222, so that the signals from the plurality of pixels 140 can be appropriately processed in parallel in a similar manner as described above.

[0145] As described above, the present embodiment enables appropriate parallel processing of analog signals output from pixels 140 across multiple rows. Even in the case of such processing, the load on the second signal line can be reduced by providing the analog circuit 22 as described in the above embodiment and appropriately arranging the signal line, thereby enabling high-speed analog signal processing and reduced power consumption.

[0146] Figures 12 to 15 Various processing methods are shown, for example, for wiring so that 12 signals are processed in parallel as described above on a column-by-column basis. Solid lines represent wiring and connections to be used, and dashed lines represent wiring and connections not used at that moment. In this way, instead of processing pixels 140 in 12 rows of a column in parallel, processing can be performed in a switched manner depending on the image desired or settings such as low power consumption mode.

[0147] Fig.12 1 is a diagram showing an example of parallel processing of eight rows of pixels 140 in one column. For example, among the six pairs of first connection portions 301 and second connection portions 302, the connection portions in the middle portion can be used to form wiring. In this case, Fig.12In the embodiment, two of the 12 second signal lines at both ends and two in the middle are not used. By such cooperation of the wirings of the first substrate 10 and the second substrate 20, eight rows of pixels 140 in one column can be processed in parallel.

[0148] Fig.13 1 is a diagram showing an example of parallel processing of, for example, four rows of pixels 140 in one column. In this way, four pixels can be processed in parallel using four connection portions and four wirings.

[0149] Fig.14 1 is a diagram showing an example of parallel processing of two rows of pixels 140 in one column, for example. In this way, two pixels can be processed in parallel using two connection portions and two wirings.

[0150] For the case of 4 pixels or 2 pixels, the power consumption can be further reduced by not using the second analog circuit 222 . Fig.15 2 is a diagram showing a case where two rows of each column are processed without using the second analog circuit 222. In this way, it is also possible to process signals in parallel without using the second analog circuit 222 and using only the first analog circuit 221. In this case, for example, the control of the third switch 283 and the fifth switch 285 can be omitted, or the first switch 281 can be omitted while providing a time sufficient for the floating potential to be sufficiently charged.

[0151] Therefore, the wiring can be switched appropriately according to the situation. The situation may involve a predetermined condition. For example, in the case where it is desired to shoot high-speed video, even if the power consumption increases, it can be achieved by using Fig.11 In contrast, in the case of taking a still image of a still object, the Fig.15 As shown, processing is applied by setting wiring to reduce power consumption.

[0152] It should be noted that in the present embodiment, a case where a single pixel separator and a single circuit separator are provided has been described; however, this is not restrictive. In other words, as described in the present embodiment, even in the case where a plurality of second signal lines are provided in each space between pixels, the pixel array 14 and the analog circuit 22 can be divided smaller. In addition, the number of wirings in one column is not necessarily 12, and may be 11 or less or 13 or more.

[0153] (Example of the connection portion)

[0154] Will Figure 1 The chip structure of the solid-state imaging device 1 in FIG. 1 is described below. As described above, the solid-state imaging device 1 is in the form of a stacked body in which a first substrate 10 and a second substrate 20 are stacked. The first substrate 10 and the second substrate 20 are sometimes referred to as dies, respectively. For example, in Figure 2In the embodiment, the first substrate 10 and the second substrate 20 are respectively rectangular; however, the specific shape and size can be determined as desired. In addition, the sizes of the first substrate 10 and the second substrate 20 can be the same or different.

[0155] Figure 4 The pixel array 14 and the like are shown to be located on the first substrate 10. In addition, at least a portion of the optical system 12 can be implemented in the first substrate 10 in an on-chip manner.

[0156] The second substrate 20 includes another necessary circuit while including at least the analog circuit 22, the logic circuit 24, and the input / output I / F 26. For example, a clock signal generating circuit may be provided that outputs a clock signal for determining the timing of the above-mentioned row selection signal, synchronization signal, etc. In addition, a control circuit that controls each circuit in its entirety or in part may be provided.

[0157] As a specific way of bonding the first substrate 10 and the second substrate 20 together, for example, a technology generally known as CoC (Chip on Chip) can be used; the first substrate 10 and the second substrate 20 are cut out from a wafer and singulated, and then they are bonded to each other while being vertically stacked. Alternatively, a technology generally known as CoW (Chip on Wafer) can be used; one of the first substrate 10 and the second substrate 20 (for example, the first substrate 10) is cut out from a wafer and singulated, and then the singulated first substrate 10 is bonded to the unsingulated second substrate 20. Alternatively, a technology generally known as WoW (Wafer on Wafer) can be used; the first substrate 10 and the second substrate 20 are bonded to each other in a wafer state.

[0158] Various bonding methods may be used to bond the first substrate 10 and the second substrate 20. For example, plasma bonding or the like may be used.

[0159] When bonding the first substrate 10 and the second substrate 20, in particular, the bonding shown in the following figure can be used to electrically connect the connection portion of the first substrate 10 and the second substrate 20. It should be noted that the specific state of the circuit is not shown, and only the connection of the connection portion is shown. Therefore, in the drawings, the illustration of the elements of various circuits, etc. is omitted. In addition, the second signal line 181 will be described, but this also applies to the second signal line 182, etc.

[0160] Fig.16is a diagram showing an example of a connection portion. As shown in the following figure, for example, the analog circuit 22 and the second signal line 181 are connected to the area where the second signal line 181 is located. The pixels 140 that receive the light collected by the optical system 12 are connected to each other through the second signal line 181. The second signal line 181 is connected to the connection portion 30 including, for example, a microbump, and is therefore connected to the analog circuit 22. For example, respective micropads may be formed on both the pixel 140 side and the analog circuit 22 side, and the micropads are connected to each other through the microbump.

[0161] Fig.17 30 can be connected via micro pads as shown in the figure. The first substrate 10 and the second substrate 20 can be directly connected to each other via micro pads without inserting a substrate between the micro pads. Fig.16 The micro bumps in the .

[0162] Fig.18 The connection portion 30 may be in the form of, for example, a through hole, and may connect the pixel 140 and the analog circuit 22 by bringing the through hole into contact with the second signal line 181 and the analog circuit 22 .

[0163] In addition, if necessary, for the pixel 140 , the first substrate 10 and the second substrate 20 connected by the connection part 30 may be provided with additional connection lines for transmitting and receiving other signals.

[0164] (Example of Second Substrate)

[0165] Next, an embodiment of the second substrate 20 will be described. Fig.19 An example of implementing the second substrate 20 is shown. The area indicated by the dotted line in the second substrate 20 is the area in the first substrate 10 where the pixel array 14 exists.

[0166] For example, in the second substrate 20, the first analog circuit 221 and the second analog circuit 222 are positioned so that the circuit dividing portion 223 overlapping the pixel dividing portion in the third direction is sandwiched therebetween. The DAC 23 may be provided adjacent to the analog circuit. For example, the logic circuit 24 is provided so that the analog circuit 22 is sandwiched therebetween. The logic circuit 24 may, for example, include a first logic circuit adjacent to the first analog circuit 221 and a second logic circuit adjacent to the second analog circuit 222. In this case, the first logic circuit may process a signal output from the first analog circuit 221, and the second logic circuit may process a signal output from the second analog circuit 222.

[0167] In addition, if necessary, a CPU (central processing unit) or a control unit may be provided. Further, a memory 25 may be provided as a storage unit. The second substrate 20 as a component independent of the pixel 140 includes a circuit required for the solid-state imaging device 1 as described above. In addition, although not shown, a selector, an input / output I / F 26, etc. may be provided.

[0168] Fig. 20 An example of a two-layer form of the solid-state imaging device 1 is shown. The first substrate 10 includes an optical system and a pixel array 14 having two-dimensionally arranged pixels 140. The first substrate 10 also includes wiring and the like necessary to extract information about the pixels, such as first and second signal lines.

[0169] The second substrate 20 includes various switches for switching connection states between connection portions for connecting to the first substrate 10, an analog circuit 22, a logic circuit 24, a memory 25, and an input / output I / F 26. In addition, the second substrate 20 includes circuits necessary for controlling the solid-state imaging device 1.

[0170] Fig.21 1 is a diagram showing an example of a solid-state imaging device 1 in a three-layer form. The elements of the first substrate 10 and the second substrate 20 are Fig.19 The elements in are substantially the same. However, the second substrate 20 does not include a memory, while the third substrate 40 includes a memory. Fig.21 In the embodiment, the third substrate 40 is located below the second substrate 20; however, this is not restrictive. In other words, the third substrate 40 may be disposed between the first substrate 10 and the second substrate 20.

[0171] Even in the case where the solid-state imaging device 1 has three layers, the connections between the layers are similar to those in the above-described embodiments; for example, the layers are connected by Figures 16 to 18 The connection methods shown are connected to each other.

[0172] Fig. 22 2 is a diagram showing an example of the power supply position in the analog circuit 22 of the second substrate 20. In the drawing, considering visibility, only the case where the power supply is located at the position corresponding to the first analog circuit 221 is drawn; however, the power supply is also located on the second analog circuit 222 side.

[0173] In the drawings, for example, the shaded portion indicated by the oblique lines tilted to the left is the wiring to which the power supply voltage is applied, and the shaded portion indicated by the oblique lines tilted to the right is the wiring connected to the ground voltage. Therefore, the first analog circuit 221 is provided with wiring for the power supply voltage and wiring for the ground voltage at regular intervals. For ease of understanding, the power supply is regarded as being on the surface; however, the power supply is not on the surface but is embedded under the circuit of, for example, the second substrate 20.

[0174] The analog circuit 22 is located in the middle, which extends the power wiring on the chip of the second substrate 20. This reduces the power supply voltage observed at one end of the analog circuit 22 by the amount corresponding to the resistance and consumption current of the wiring. In this case, the unevenness of the arrangement of the power supply wiring further leads to the degradation of the light shielding property in the second direction. In order to avoid this, the power supply wiring is evenly arranged along the second direction, thereby achieving equalization of the power supply in the horizontal direction. Therefore, the shadow in the second direction can be reduced.

[0175] All embodiments are described by taking CMOS sensors as an example; however, this is not restrictive. The present disclosure is applicable to CCD (Charge Coupled Device) and other types of light receiving devices. For example, for CCD, the charges of the rows selected by the channel are propagated in sequence and processed by the analog circuit, so that similar functions and effects can be achieved.

[0176] The present disclosure may be used for indirect ToF sensors.

[0177] Fig.23 is a block diagram showing an example of an indirect time-of-flight sensor to which the present technology is applied.

[0178] [Construction example of an indirect time-of-flight sensor]

[0179] Fig.23 1 is a block diagram showing an example of an indirect time-of-flight sensor 10000 to which an embodiment of the present technology is applied. The indirect time-of-flight sensor 10000 includes a sensor chip 10001 and a circuit chip 10002 stacked on the sensor chip 10001 .

[0180] A pixel region 10020 including a plurality of pixels arranged in a two-dimensional grid pattern is arranged on the sensor chip. The pixel region 10020 can be arranged in rows and columns and can include a plurality of column signal lines. Each column signal line is coupled to each pixel. In addition, a vertical drive circuit 10010, a column signal processing circuit 10040, a timing adjustment circuit 10050, and an output circuit 10060 are arranged on the circuit chip 10002.

[0181] The vertical driving circuit 10010 is configured to drive pixels and output pixel signals to the column signal processing section 10040. The column signal processing section 10040 applies analog-to-digital (AD) conversion processing to the pixel signals and outputs the AD-converted pixel signals to the output circuit. The output circuit 10060 applies CDS (Correlated Double Sampling) processing and the like to the data from the column signal processing section 10040 and outputs the data to the subsequent signal processing circuit 10120.

[0182] The timing control circuit 10050 is configured to control each driving timing of the vertical driving circuit 10010. The column signal processing section and output circuit 10060 operates in synchronization with the vertical synchronization signal.

[0183] The pixel area 10020 includes a plurality of pixels arranged in a two-dimensional grid pattern. Each pixel is configured to receive infrared light and photoelectrically convert the infrared light into a pixel signal.

[0184] In addition, vertical signal lines VSL1 and VSL2 are wired in the vertical direction in each column of pixel 10230. Assuming that the total number of columns in the pixel area 10020 is M (M is an integer), a total of 2×M vertical signal lines are wired. Each pixel has two taps. The vertical signal line VSL1 is connected to Tap A of the pixel 10230, and the vertical signal line VSL2 is connected to Tap B of the pixel 10230. In addition, the vertical signal line VSL1 transmits the pixel signal AINP1, and the vertical signal line VSL2 transmits the pixel signal AINP2.

[0185] The vertical drive circuit 210 sequentially selects and drives the rows of the pixel blocks 221 so that the pixel signals AINP1 and AINP2 are simultaneously output from each pixel block 221 of the row. In other words, the vertical drive circuit 210 simultaneously drives the pixels 230 of the 2kth row and the (2k+1)th row. It should be noted that the vertical drive circuit 210 is an example of the drive circuit described in the claims.

[0186] Fig.24 1 is a circuit diagram showing an example of the construction of a pixel 10230 according to a mode of the present technology. The pixel 10230 includes a photodiode 10231, two transfer transistors 10232 and 10237, two reset transistors 10233 and 10238, two taps (floating diffusion layers 10234 and 10239), two amplification transistors 10235 and 102339, and two selection transistors 10236 and 10239.

[0187] The photodiode 10231 is configured to perform photoelectric conversion on received light to generate electric charge. The photodiode 10231 is arranged on the back side of the semiconductor substrate, opposite to the front side of the semiconductor substrate where the circuit is arranged. This solid-state imaging element is called a back-illuminated solid-state imaging element. It should be noted that instead of the back-illuminated type, a front-illuminated type including the photodiode 10231 arranged on the front side can also be used.

[0188] The transfer transistor 10232 is configured to transfer charges from the photodiode 10231 to Tap A 10239 and Tap B 10234 in sequence according to a transfer signal TRG from the vertical drive circuit 10010. Tap A 10239 and Tap B 10234 are configured to accumulate the transferred charges to generate a voltage according to the accumulated charge amount.

[0189] The overflow transistor 10242 is a transistor configured to sequentially discharge the charge of the photodiode 10231 to VDD, and has a function of resetting the photodiode.

[0190] The reset transistors 10238 and 10233 are configured to extract charges from Tap A 10239 and Tap B 10234, respectively, to initialize the charge amount according to the reset signal RSTp from the vertical drive circuit 210. The amplifier transistors 10240 and 10235 are configured to amplify the voltages of Tap A 10239 and Tap B 10234, respectively. The selection transistors 10236 and 10241 are configured to output the pixel signal as a signal of the amplified voltage to the column signal processing section 10040 through two vertical signal lines (e.g., VSL1 and VSL2) according to the selection signal SELp from the vertical drive circuit 210. VSL1 and VSL2 are connected to the input terminal of the analog-to-digital converter in the column signal processing circuit 10040.

[0191] It should be noted that the circuit configuration of the pixel 230 is not limited to Fig.23 The construction shown by way of example in FIG.

[0192] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as: an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0193] Fig.25 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0194] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.25In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0195] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices and mechanisms: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a drive force for the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force for the vehicle, etc.

[0196] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, rear lights, brake lights, turn signal lights, fog lights, etc. In this case, a radio wave transmitted from a mobile device that replaces the key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, power window device, lights, etc. of the vehicle.

[0197] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing for objects such as people, vehicles, obstacles, signs, or characters on the road surface, or perform detection processing of the distance thereto.

[0198] The imaging unit 12031 is an optical sensor that receives light, and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light or may be invisible light such as infrared light.

[0199] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0200] The microcomputer 12051 calculates the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of the advanced driver assistance system (ADAS), which includes collision avoidance or collision mitigation of the vehicle, following driving based on the following distance, speed maintenance driving, collision warning of the vehicle, and lane departure warning of the vehicle.

[0201] In addition, the microcomputer 12051 can perform collaborative control for automatic driving based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040 by controlling the driving force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation.

[0202] In addition, the microcomputer 12051 can output a control instruction to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights so as to change the high beam to the low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0203] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify information to a passenger of the vehicle or the outside of the vehicle. Fig.25 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0204] Fig.26 This is a diagram illustrating an example of the installation position of the camera unit 12031.

[0205] exist Fig.26 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0206] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the following positions: the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and the upper part of the windshield inside the vehicle. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 arranged on the side mirrors mainly acquire images on the sides of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or rear door mainly acquires images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0207] It should be noted that Fig.26 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 observed from above is obtained.

[0208] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0209] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thus, specifically, the nearest three-dimensional object that appears on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more) can be extracted as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform cooperative control aimed at automatic driving, which allows the vehicle to travel automatically without relying on the driver's operation, etc.

[0210] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk representing the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0211] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the camera units 12101 to 12104. For example, such identification of pedestrians is performed by extracting feature points in the image captured by the camera units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points representing the outline of the object to determine whether there is a pedestrian. If the microcomputer 12051 determines that there is a pedestrian in the image captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square outline for emphasis, thereby superimposing it on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian is displayed at a desired position, etc.

[0212] The above-described embodiment may be arranged in the following manner.

[0213] (1) A solid-state imaging device comprising:

[0214] a first substrate having a pixel array in which a plurality of pixels configured to output analog signals by photoelectric conversion are two-dimensionally arranged in columns along a first direction and in rows along a second direction intersecting the first direction; and

[0215] a second substrate stacked on the first substrate, the second substrate comprising an analog circuit, the analog circuit being configured to overlap the pixel array in a third direction intersecting the first direction and the second direction and processing the analog signal output from the pixel, wherein

[0216] The pixel array is divided into a first area and a second area by a pixel separator along the second direction, each of the areas includes continuous pixels, and

[0217] The analog circuit is divided into a first analog circuit and a second analog circuit, the first analog circuit and the second analog circuit are connected to the pixels belonging to the first area and the pixels belonging to the second area, the first analog circuit and the second analog circuit are adjacent to each other with a circuit dividing portion inserted therebetween, and the circuit dividing portion is configured to overlap with the pixel dividing portion in the third direction.

[0218] (2) The solid-state imaging device according to (1), wherein

[0219] The pixel array includes a plurality of first signal lines arranged along the first direction, and one or more rows in the first direction are selected from rows having the pixels continuous in the second direction, and

[0220] The analog signal output from the pixel selected by the first signal line is processed by the analog circuit.

[0221] (3) The solid-state imaging device according to (2), wherein:

[0222] The pixel array includes a plurality of second signal lines arranged along the second direction, and one or more columns in the second direction are selected from columns having the pixels continuous in the first direction,

[0223] the analog signal output from the pixel selected by the first signal line is transmitted through the second signal line and processed by the analog circuit,

[0224] The second signal line is electrically separated at the pixel dividing portion.

[0225] (4) The solid-state imaging device according to (3), wherein the pixel dividing section and the circuit dividing section are arranged near the middle of the pixel array in the first direction.

[0226] (5) The solid-state imaging device according to (3), comprising:

[0227] A connection portion configured to connect the pixel and the analog circuit in the third direction at the pixel separation portion and the circuit separation portion.

[0228] (6) The solid-state imaging device according to (5), wherein

[0229] The connecting portion includes

[0230] a first connection portion connected to the second signal line and configured to connect the pixels belonging to the first area and the first analog circuit through the second signal line, and

[0231] A second connection section is connected to the second signal line and is configured to connect the pixels belonging to the second area and the second analog circuit through the second signal line.

[0232] (7) The solid-state imaging device according to (6), comprising:

[0233] A first switch is configured to switch a connection state between the first connection portion and the second connection portion.

[0234] (8) The solid-state imaging device according to (7), wherein

[0235] Based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion,

[0236] The first switch switches the connection state between the first connection portion and the second connection portion.

[0237] (9) The solid-state imaging device according to (7) or (8), wherein:

[0238] A plurality of the first connecting parts, a plurality of the second connecting parts, and a plurality of the first switches are arranged along the second direction, and

[0239] The plurality of first switches are operated in a synchronized manner.

[0240] (10) The solid-state imaging device according to any one of (6) to (9), wherein:

[0241] A plurality of the first connecting parts and a plurality of the second connecting parts are arranged along the second direction,

[0242] The solid-state imaging device comprises:

[0243] a second switch configured to switch a connection state between the plurality of first connection portions; and

[0244] A third switch is configured to switch a connection state between the plurality of second connection portions.

[0245] (11) The solid-state imaging device according to (10), wherein

[0246] Based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion,

[0247] The second switch switches the connection state between the first connection parts, and

[0248] The third switch switches the connection state between the second connection parts.

[0249] (12) The solid-state imaging device according to (10) or (11), wherein the second switch and the third switch operate in a synchronized manner.

[0250] (13) The solid-state imaging device according to (10) or (11), wherein:

[0251] A plurality of the second switches and a plurality of the third switches are arranged along the second direction, and

[0252] The plurality of second switches and the plurality of third switches are operated in a synchronized manner.

[0253] (14) The solid-state imaging device according to any one of (10) to (13), comprising:

[0254] a first voltage source configured to apply a predetermined voltage to the plurality of first connection portions connected through the second switch; and

[0255] a fourth switch configured to switch a connection state between the first voltage source and the plurality of first connection portions, wherein:

[0256] The second switch and the fourth switch are operated in a synchronized manner.

[0257] (15) The solid-state imaging device according to any one of (10) to (14), comprising:

[0258] a second voltage source configured to apply a predetermined voltage to the plurality of second connection portions connected through the third switch; and

[0259] a fifth switch configured to switch a connection state between the second voltage source and the plurality of second connection portions, wherein:

[0260] The third switch and the fifth switch are operated in a synchronized manner.

[0261] (16) The solid-state imaging device according to any one of (6) to (15), wherein the number of the first connection portions and the second connection portions is at least the same as the number of the pixels existing in the row.

[0262] (17) The solid-state imaging device according to (16), wherein the number of the first connection portions and the second connection portions are at least the same as the product of the number of the pixels existing in the row and a predetermined number.

[0263] (18) The solid-state imaging device according to any one of (5) to (17), wherein:

[0264] The connecting portion is in the form of a micro bump, a micro pad or a through hole.

[0265] (19) The solid-state imaging device according to any one of (1) to (18), wherein the first analog circuit and the second analog circuit process the analog signals from different pixels belonging to one or more rows along the second direction at the same timing.

[0266] (20) The solid-state imaging device according to (19), wherein the first analog circuit and the second analog circuit change the number of analog signals to be processed at the same timing according to a predetermined condition.

[0267] (21) The solid-state imaging device according to (20), wherein:

[0268] The analog circuit converts the analog signal into a digital signal, and

[0269] The solid-state imaging device includes a logic circuit configured to process the digital signal.

[0270] (22) The solid-state imaging device according to (21), wherein the logic circuit is positioned so as to insert the analog circuit in the first direction.

[0271] (23) The solid-state imaging device according to (21) or (22), wherein:

[0272] The logic circuit includes

[0273] a first logic circuit configured to process the digital signal output from the first analog circuit, and

[0274] A second logic circuit is configured to process the digital signal output from the second analog circuit.

[0275] (24) The solid-state imaging device according to (1), comprising:

[0276] a plurality of the pixel dividing parts and a plurality of the circuit dividing parts; and

[0277] A pixel array is divided into a plurality of regions and the analog circuit corresponds to each of the regions.

[0278] (25) The solid-state imaging device according to any one of (1) to (24), wherein:

[0279] The second substrate includes

[0280] a signal processing circuit configured to perform signal processing on the digital signal,

[0281] an image processing circuit configured to perform image processing on the digital signal, the digital signal including image information,

[0282] a storage section configured to store data freely selected from the digital signal, the data output from the signal processing circuit, and the data output from the image processing circuit,

[0283] a selector configured to freely select at least one of the data output from the signal processing circuit, the data output from the image processing circuit, and the data stored in the storage section, and

[0284] An interface is configured to output the data or signal selected by the selector to the outside, or to receive input of data or signal from the outside.

[0285] (26) The solid-state imaging device according to any one of (7) to (15), wherein all of the switches are operated in a synchronized manner.

[0286] (27) The solid-state imaging device according to (26), wherein synchronization is performed at a timing based on a reset timing of the pixel or a timing at which the analog signal is output from the pixel.

[0287] One aspect of the present disclosure is not limited to the above-described embodiments; it includes various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. If necessary, the components of the embodiments may be used in combination. In other words, various supplements, changes, and partial deletions may be made without departing from the conceptual ideas and scope of the present disclosure as defined by the claims and their equivalents.

[0288] Reference numerals list

[0289] 1: Solid-state camera

[0290] 10: First substrate

[0291] 12: Optical system

[0292] 14: Pixel Array

[0293] 140: Pixels

[0294] 141, 141A, 141B: First area

[0295] 142, 142A, 142B: Second area

[0296] 143, 143A, 143B, 143C: pixel separator

[0297] 16: First signal line

[0298] 181, 182: Second signal line

[0299] 20: Second substrate

[0300] 22, 22A, 22B: Analog circuits

[0301] 221, 221A, 221B: First analog circuit

[0302] 222, 222A, 222B: Second analog circuit

[0303] 223, 223A, 223B, 223C: Circuit separator

[0304] 23: DAC

[0305] 24: Logic Circuit

[0306] 25: Memory

[0307] 26: Input / Output Interface

[0308] 281: First switch

[0309] 282: Second switch

[0310] 283: The third switch

[0311] 284: The fourth switch

[0312] 285: The fifth switch

[0313] 30: Connection

[0314] 301: First connection part

[0315] 302: Second connection portion.

Claims

1. A solid-state imaging device, include: a first substrate having a pixel array in which a plurality of pixels configured to output analog signals by photoelectric conversion are two-dimensionally arranged in columns along a first direction and in rows along a second direction intersecting the first direction; as well as a second substrate stacked on the first substrate, the second substrate comprising an analog circuit, the analog circuit being configured to overlap the pixel array in a third direction intersecting the first direction and the second direction, and the analog circuit processing the analog signal output from the pixel, wherein The pixel array is divided into a first area and a second area by a pixel separator along the second direction, the first area and the second area both including continuous pixels, and The analog circuit is divided into a first analog circuit and a second analog circuit, the first analog circuit and the second analog circuit are connected to the pixels belonging to the first area and the pixels belonging to the second area, the first analog circuit and the second analog circuit are adjacent to each other with a circuit dividing portion inserted therebetween, and the circuit dividing portion is configured to overlap with the pixel dividing portion in the third direction.

2. The solid-state imaging device according to claim 1, in, The pixel array comprises: a plurality of first signal lines arranged along the first direction, and one or more rows in the first direction are selected from rows having the pixels continuous in the second direction; and a plurality of second signal lines, the second signal lines being arranged along the second direction, and one or more columns in the second direction being selected from the columns having the pixels continuous in the first direction, the analog signal output from the pixel selected by the first signal line is transmitted through the second signal line and processed by the analog circuit, The second signal line is electrically cut off at the pixel dividing portion.

3. The solid-state imaging device according to claim 2, in, The pixel dividing section and the circuit dividing section are arranged near the middle of the pixel array in the first direction.

4. The solid-state imaging device according to claim 2, wherein include: A connection portion configured to connect the pixel and the analog circuit in the third direction at the pixel separation portion and the circuit separation portion.

5. The solid-state imaging device according to claim 4, in, The connecting portion comprises: a first connection portion connected to the second signal line and configured to connect the pixels belonging to the first area and the first analog circuit through the second signal line; and A second connection section is connected to the second signal line and is configured to connect the pixels belonging to the second area and the second analog circuit through the second signal line.

6. The solid-state imaging device according to claim 5, wherein include: A first switch is configured to switch a connection state between the first connection portion and the second connection portion.

7. The solid-state imaging device according to claim 6, in, The first switch switches the connection state between the first connection portion and the second connection portion based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion.

8. The solid-state imaging device according to claim 6, in, A plurality of the first connecting parts, a plurality of the second connecting parts, and a plurality of the first switches are arranged along the second direction, and The plurality of first switches are operated synchronously.

9. The solid-state imaging device according to claim 5, in, A plurality of the first connecting parts and a plurality of the second connecting parts are arranged along the second direction, The solid-state imaging device comprises: a second switch configured to switch a connection state between the plurality of first connection portions; and A third switch is configured to switch a connection state between the plurality of second connection parts.

10. The solid-state imaging device according to claim 9, in, Based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion, The second switch switches the connection state between the first connection parts, and The third switch switches the connection state between the second connection parts.

11. The solid-state imaging device according to claim 9, in, The second switch and the third switch are operated synchronously.

12. The solid-state imaging device according to claim 9, in, A plurality of the second switches and a plurality of the third switches are arranged along the second direction, and The plurality of second switches and the plurality of third switches are operated synchronously.

13. The solid-state imaging device according to claim 9, wherein include: a first voltage source configured to apply a predetermined voltage to the plurality of first connection portions connected through the second switch; as well as a fourth switch configured to switch a connection state between the first voltage source and the plurality of first connection portions, wherein: The second switch and the fourth switch are operated synchronously.

14. The solid-state imaging device according to claim 9, wherein include: a second voltage source configured to apply a predetermined voltage to the plurality of second connection portions connected through the third switch; as well as a fifth switch configured to switch a connection state between the second voltage source and the plurality of second connection portions, wherein: The third switch and the fifth switch are operated synchronously.

15. The solid-state imaging device according to any one of claims 1 to 14, in, The first analog circuit and the second analog circuit process the analog signals from different pixels belonging to one or more rows along the second direction at the same timing.

16. The solid-state imaging device according to claim 15, in, The first analog circuit and the second analog circuit change the number of the analog signals to be processed at the same timing according to a predetermined condition.

17. The solid-state imaging device according to claim 16, in, The analog circuit converts the analog signal into a digital signal, and The solid-state imaging device includes a logic circuit configured to process the digital signal.

18. The solid-state imaging device according to claim 17, in, The logic circuit is positioned to sandwich the analog circuit in the first direction.

19. The solid-state imaging device according to any one of claims 1 to 14, include: a plurality of the pixel dividing parts and a plurality of the circuit dividing parts; as well as The pixel array is divided into a plurality of areas and the analog circuit corresponds to each of the divided areas.

20. The solid-state imaging device according to any one of claims 1 to 14, in, The second substrate comprises: a signal processing circuit configured to perform signal processing on the digital signal; an image processing circuit configured to perform image processing on the digital signal, the digital signal including image information; a storage section configured to store data freely selected from the digital signal, the data output from the signal processing circuit, and the data output from the image processing circuit; a selector configured to freely select at least one of the data output from the signal processing circuit, the data output from the image processing circuit, and the data stored in the storage section; and An interface is configured to output the data or signal selected by the selector to the outside, or to receive input of data or signal from the outside.

Images