Error detection method and related apparatus

Abstract

The embodiment of the application discloses an error detection method, and relates to the technical field of computers. The method comprises the following steps: obtaining a scheduling table of a target task, wherein the scheduling table is used for indicating at least one test mode, the at least one test mode is used for detecting errors of a target logic circuit, and the target logic circuit is a logic circuit used for executing the target task; and executing the at least one test mode according to the scheduling table, so as to detect errors of the target logic circuit. By determining the scheduling table of the target task and executing the test mode included in the scheduling table, all test modes in a software test library can be avoided from being executed, so that the load of a processor is reduced, and the working efficiency of the processor is effectively improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an error detection method and related apparatus. Background Technology

[0002] In the field of computers, data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts.

[0003] In certain applications with high safety requirements, such as the automotive industry where safety is paramount, error detection mechanisms can be provided for processors to ensure functional safety, detect hardware errors, and ensure safe operations are performed in the event of a hardware error.

[0004] Currently, related technologies detect errors in logic circuits by having the processor periodically execute test patterns from a Software Test Library (STL). However, since the STL contains a large number of test patterns, the periodic execution of these patterns by the processor leads to a high processor load, meaning the processor needs to spend a significant amount of time detecting errors, thus affecting its efficiency. Summary of the Invention

[0005] This application provides an error detection method and related apparatus. During error detection, a schedule table for the target task is determined, and the test modes included in the schedule table are executed. Since the schedule table only includes test modes for detecting target logic circuits used to execute the target task, error detection based on this schedule table avoids executing all test modes in the software test library, thereby reducing the processor load and effectively improving processor efficiency.

[0006] This application provides a method for error detection applied to terminals in fields with security requirements, such as vehicle-mounted terminals or control terminals in aerospace. The method includes: the terminal acquiring a schedule table of a target task, which may be pre-installed in the terminal or pre-generated by the terminal; the target task may be, for example, a process or a thread. The schedule table includes at least one test mode, based on which errors in the target logic circuit dependent on the execution of the target task can be detected. Finally, the terminal executes at least one test mode according to the schedule table to achieve error detection of the target logic circuit.

[0007] In this solution, during error detection, the terminal determines the target task's scheduling table and executes the test modes included in that table. Since the scheduling table only includes test modes for detecting the target logic circuit used to execute the target task, error detection based on this table avoids executing all test modes in the software test library, thereby reducing the processor's load and effectively improving its efficiency.

[0008] In some possible implementations, the target task is a running task. Since an error occurs in the logic circuits required for the target task during its execution on the terminal, this error could pose a security risk. Therefore, executing test modes based on the target task's schedule table can detect errors in the required logic circuits, preventing security risks. For other logic circuits, since the terminal is not currently executing the corresponding task and therefore does not need to use them, errors in these circuits will not pose a security risk. Thus, detecting errors based on the schedule table of the currently running task allows for checking only the test modes in the schedule table of a single task each time error detection is performed, avoiding the execution of all test modes in the software test library. This reduces processor load and effectively improves processor efficiency. In some possible implementations, the terminal can pre-generate the schedule table for the task to be run before performing error detection. Specifically, the method may further include: the terminal acquiring a set of machine instruction codes for a target task. Since the target task can be a process or a thread, the corresponding set of machine instruction codes can be acquired, for example, based on the executable file of the target task. This set of machine instruction codes includes multiple machine instruction codes (also called machine codes). The terminal determines at least one instruction type corresponding to the set of machine instruction codes according to a preset second mapping relationship. This second mapping relationship includes a mapping relationship between machine instruction codes and instruction types, in which one machine instruction code uniquely corresponds to one instruction type. The terminal determines at least one test mode corresponding to at least one instruction type according to a preset first mapping relationship. This at least one test mode is used to detect errors in the logic circuit corresponding to at least one instruction type. This first mapping relationship includes a mapping relationship between instruction types and test modes, and in this mapping relationship, one instruction type can correspond to one or more test modes. The terminal then generates a scheduling table based on at least one test mode.

[0009] In other words, after the terminal obtains the set of machine instruction codes for the target task, it determines the instruction type corresponding to the set of machine instruction codes based on a preset second mapping relationship, and determines the test mode corresponding to the instruction type based on the first mapping relationship, thereby obtaining the test mode corresponding to the target task.

[0010] In this solution, the terminal can generate a scheduling table corresponding to the task to be run based on the preset mapping relationship. This ensures that the terminal can generate the scheduling table corresponding to the new task when it obtains the new task, thus guaranteeing the feasibility of the solution.

[0011] In some possible implementations, the method may further include: the terminal determining the execution count of at least one instruction type based on the instruction types corresponding to multiple machine instruction codes. Simply put, the terminal can count the number of machine instruction codes corresponding to each instruction type and determine the execution count of that instruction type. Based on this execution count, the terminal can determine the execution order of at least one test mode to generate a scheduling table that also includes the execution order of the test modes. That is, the terminal can sort the test modes in descending order based on the execution count; the higher the execution count of the instruction type corresponding to a test mode, the earlier the execution order of that test mode; conversely, the lower the execution count of the instruction type corresponding to a test mode, the later the execution order of that test mode.

[0012] Since each use of a logic circuit can potentially lead to an error, the more times a logic circuit is used, the higher the probability of an error, assuming the probability of error is the same. That is, the more times the same instruction type is executed, the more times the logic circuit is used, and the higher the probability of error. Therefore, in this embodiment, determining the execution order of test modes in the scheduling table based on the number of times the instruction type corresponding to the machine instruction code of the target task is executed allows the terminal to determine the order of detecting logic circuits based on the probability of error, i.e., detecting logic circuits with a higher probability of error first, thereby shortening error detection time and improving error detection efficiency.

[0013] In this solution, the terminal determines the execution order of the test mode based on the number of times the instruction type corresponding to the task is executed during the process of generating the scheduling table corresponding to the task. This can shorten the error detection time and improve the efficiency of error detection.

[0014] In some possible implementations, the schedule table may be pre-installed in the terminal or pre-generated by the terminal. At least one test mode in the schedule table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes the mapping relationship between instruction types and test modes. At least one instruction type is determined based on a second mapping relationship and a set of machine instruction codes for the target task. The second mapping relationship includes the mapping relationship between machine instruction codes and instruction types. The set of machine instruction codes includes multiple machine instruction codes.

[0015] In some possible implementations, the scheduler also indicates the execution order of at least one test mode, which is determined based on the number of times at least one instruction type corresponding to the machine instruction code set of the target task is executed.

[0016] In some possible implementations, when there are many tasks waiting to be run on the terminal, the terminal can generate a large number of scheduling tables. Therefore, the method can also include: the terminal generating a third mapping relationship, which includes the mapping relationship between the target task and the scheduling table. In this way, when the terminal performs error detection, the scheduling table can be determined according to the target task and the third mapping relationship, ensuring that the terminal can quickly determine the scheduling table corresponding to the target task during the error detection process, thereby improving the efficiency of error detection.

[0017] In some possible implementations, the scheduling table is stored in shared memory, which is configured to store scheduling tables for one or more tasks and can be accessed by multiple processors. When the terminal provides a configuration area for the scheduling table by reserving shared memory, multiple processors in the terminal can access the scheduling table in that shared memory. This allows each processor in the terminal to perform corresponding error detection independently based on its respective task. Providing a configuration area for the scheduling table by reserving shared memory avoids providing a separate configuration area for each processor, saving storage resource overhead.

[0018] In some possible implementations, the terminal executing at least one test mode according to the scheduling table may specifically include: the terminal writing at least one test mode into a sorting register according to the execution order; executing the test modes according to the execution order in the sorting register; and writing the execution result of the test mode into a status register. By implementing the ordered scheduling of test modes in the scheduling table in hardware, the efficiency of test mode scheduling can be improved.

[0019] A second aspect of this application provides a terminal, comprising: a processing unit and an acquisition unit; the acquisition unit is configured to acquire a schedule table of a target task, the schedule table indicating at least one test mode, the at least one test mode being used to detect errors in a target logic circuit, the target logic circuit being a logic circuit used to execute the target task; the processing unit is configured to execute at least one test mode according to the schedule table to detect errors in the target logic circuit.

[0020] In some possible implementations, the target task is a running task.

[0021] In some possible implementations, at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and a set of machine instruction codes for the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The set of machine instruction codes includes multiple machine instruction codes.

[0022] In some possible implementations, the scheduler also indicates the execution order of at least one test mode, which is determined based on the number of times at least one instruction type corresponding to the machine instruction code set of the target task is executed.

[0023] In some possible implementations, the terminal further includes: an acquisition unit; the acquisition unit is configured to acquire a set of machine instruction codes for a target task, the set of machine instruction codes including multiple machine instruction codes; the processing unit is further configured to: determine at least one instruction type corresponding to the set of machine instruction codes according to a second mapping relationship, the second mapping relationship including a mapping relationship between machine instruction codes and instruction types; determine at least one test mode corresponding to at least one instruction type according to a first mapping relationship, the first mapping relationship including a mapping relationship between instruction types and test modes, the at least one test mode being used to detect errors in the logic circuit corresponding to at least one instruction type; and generate a scheduling table according to at least one test mode.

[0024] In some possible implementations, the processing unit is further configured to: determine the number of times an instruction type is executed in at least one instruction type based on the instruction types corresponding to the multiple machine instruction codes; determine the execution order of the test modes in at least one test mode based on the number of executions; and generate a scheduling table based on at least one test mode and the execution order.

[0025] In some possible implementations, the processing unit is also used to: generate a third mapping relationship, which includes the mapping relationship between the target task and the scheduling table; and determine the scheduling table based on the target task and the third mapping relationship.

[0026] In some possible implementations, the scheduling table is stored in shared memory, which is configured to store the scheduling tables for one or more tasks and can be accessed by multiple processors.

[0027] In some possible implementations, the processing unit is also used to: write at least one test mode into a sorting register according to the execution order; execute the test modes according to the execution order in the sorting register, and write the execution result of the test mode into a status register.

[0028] In some possible implementations, the target task includes a process or a thread.

[0029] A third aspect of this application provides a terminal, the terminal comprising: a processor; the processor reading computer-readable instructions from a memory to cause the terminal to implement any of the implementations of the first aspect.

[0030] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform a method as described in any of the implementations of the first aspect.

[0031] The fifth aspect of this application provides a computer program product that, when run on a computer, causes the computer to perform a method as implemented in any of the first aspects.

[0032] A sixth aspect of this application provides a chip including one or more processors. Part or all of the processors are used to read and execute a computer program stored in a memory to perform the methods in any possible implementation of any of the above aspects. Optionally, the chip includes a memory, which is connected to the processor via a circuit or wire. Further optionally, the chip also includes a communication interface, to which the processor is connected. The communication interface is used to receive data and / or information to be processed, the processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. The communication interface can be an input / output interface. The methods provided in this application can be implemented by a single chip or by multiple chips working together. Attached Figure Description

[0033] Figure 1a A schematic diagram of a FETI and FHTI provided for an embodiment of this application;

[0034] Figure 1b This is a schematic diagram of the structure of a terminal 101 provided in an embodiment of this application;

[0035] Figure 2 A flowchart illustrating an error detection method 200 provided in an embodiment of this application;

[0036] Figure 3a A flowchart illustrating a scheduling table generation method 300 provided in an embodiment of this application;

[0037] Figure 3b This is a schematic diagram illustrating another process for generating a scheduling table, as provided in an embodiment of this application.

[0038] Figure 3c This is a schematic diagram illustrating another process for generating a scheduling table, as provided in an embodiment of this application.

[0039] Figure 4A schematic diagram of the structure of a sorting register and a status register provided in an embodiment of this application;

[0040] Figure 5 A comparative schematic diagram illustrating the execution of error detection provided in an embodiment of this application;

[0041] Figure 6 A comparative schematic diagram of FDTI in different schemes provided in the embodiments of this application;

[0042] Figure 7(a) is a comparative diagram of FDTI in different schemes when errors exist, provided in the embodiments of this application;

[0043] Figure 7(b) is a schematic diagram comparing the total time consumption of error detection in different schemes provided in the embodiments of this application;

[0044] Figure 8 This is a schematic diagram of the structure of a terminal 800 provided in an embodiment of this application. Detailed Implementation

[0045] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will recognize, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0046] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved.

[0047] In the field of computers, data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts.

[0048] With the widespread application of data processing devices in numerous fields, the concept of "functional safety" has been proposed to avoid losses caused by hardware failures in these devices. Functional safety refers to the absence of unacceptable risks due to electronic system failures, and its ultimate goal is to prevent personal injury or significant property damage caused by electronic system malfunctions.

[0049] In fields with high safety requirements, such as aerospace, transportation, and healthcare, corresponding safety mechanisms are in place to meet functional safety requirements. These mechanisms must ensure that the system reaches a safe state after detecting an error to prevent harm. For example, in the automotive industry, typical safety risks are often caused by errors in the electronic control units (ECUs) of anti-lock braking systems (ABS) or power steering systems. Errors in these ECUs can lead to fatal collisions. To ensure the system reaches a safe state and prevent safety incidents, it is necessary to detect and address errors promptly.

[0050] In simple terms, when a system error occurs, the safety mechanism must detect the error and handle it promptly to ensure the system reaches a safe state before a dangerous situation arises. Typically, the time interval from the occurrence of an error to its detection is called the Fault Detection Time Interval (FDTI); the interval from error detection to the system reaching a safe state is called the Fault Handling Time Interval (FHTI). For example, see [link to relevant documentation]. Figure 1a , Figure 1a This diagram illustrates an FDTI and FHTI provided in an embodiment of this application. To avoid danger, after a system error occurs, the system must reach a safe state within a certain period; that is, the sum of the FDTI and FHTI must be less than or equal to a certain time threshold. Therefore, to ensure a sufficiently long FHTI to handle errors and guarantee successful error processing, minimizing the FDTI is crucial.

[0051] Currently, one method for error detection in related technologies is Dual-core Lockstep (DCLS). DCLS works by having two processors run the same program and inputting their outputs into a comparison logic to determine if they are identical. If the outputs are the same, no error has occurred; if they are different, an error has occurred. While this method effectively detects errors, it requires two processors to run the same program, resulting in high cost and poor flexibility.

[0052] Therefore, another software-based error detection method has been provided in related technologies. This method detects errors in logic circuits by having the processor periodically execute test modes in the STL. Compared to DCLS, this method is less costly and more flexible. However, since systems often have a large number of logic circuits, the STL typically includes many test modes to detect errors in all of them. Therefore, the processor's periodic execution of these STL test modes leads to a high processor load, meaning the processor needs to spend a significant amount of time detecting errors, thus impacting processor efficiency.

[0053] In view of this, embodiments of this application provide an error detection method that can be applied to a terminal. During error detection, the terminal determines the scheduling table corresponding to the currently running task and executes the test modes included in that scheduling table. Since the scheduling table only includes test modes corresponding to the machine instruction code of the task, the terminal can detect errors based on this scheduling table, avoiding the execution of all test modes in the software test library, thereby reducing the processor load and effectively improving processor efficiency.

[0054] The terminals involved in the embodiments of this application can be devices used for data processing in fields with security requirements. Examples of such terminals include: vehicle-mounted terminals in transportation, control terminals in aerospace, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, and wireless terminals in smart homes.

[0055] Please refer to Figure 1b , Figure 1b This is a schematic diagram of the structure of a terminal 101 provided in an embodiment of this application.

[0056] like Figure 1b As shown, terminal 101 includes a processor 103, which is coupled to a system bus 105. The processor 103 can be one or more processors, each of which can include one or more processor cores. A video adapter 107 drives a display 109, which is coupled to the system bus 105. The system bus 105 is coupled to an input / output (I / O) bus via a bus bridge 111. An I / O interface 115 is coupled to the I / O bus. The I / O interface 115 communicates with various I / O devices, such as an input device 117 (e.g., a touchscreen), a media tray 121 (e.g., a compact disc read-only memory, CD-ROM, multimedia interface, etc.), a transceiver 123 (capable of sending and / or receiving radio communication signals), a camera 155 (capable of capturing still and moving digital video images), and an external USB port 125. Optionally, the interface connected to the I / O interface 115 can be a USB interface.

[0057] The processor 103 can be any conventional processor, including a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, or a combination thereof. Optionally, the processor can be a special-purpose device such as an ASIC.

[0058] Terminal 101 can communicate with software deployment server 149 via network interface 129. Exemplarily, network interface 129 is a hardware network interface, such as a network interface card (NIC). Network 127 can be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (VPN). Optionally, network 127 can also be a wireless network, such as a WiFi network or a cellular network.

[0059] Hard disk drive interface 131 is coupled to system bus 105. Hardware driver interface is connected to hard disk drive 133. System memory 135 is coupled to system bus 105. Data running in system memory 135 may include the operating system (OS) 137, applications 143, and schedules of terminal 101.

[0060] An operating system consists of the Shell 139 and the kernel 141. The Shell 139 is an interface between the user and the operating system kernel. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input for the operating system, and processing various operating system outputs.

[0061] Kernel 141 consists of the parts of the operating system used to manage memory, files, peripherals, and system resources. Kernel 141 interacts directly with the hardware. The operating system kernel typically runs processes and provides inter-process communication, CPU time-slice management, interrupts, memory management, I / O management, and so on.

[0062] For example, when terminal 101 is an in-vehicle terminal, application 143 includes programs related to controlling vehicle driving, such as programs managing the interaction between the autonomous vehicle and obstacles on the road, programs controlling the autonomous vehicle's route or speed, and programs controlling the interaction between the autonomous vehicle and other autonomous vehicles on the road. In one embodiment, when application 143 needs to be executed, terminal 101 can download application 143 from software deployment server 149. In one embodiment, when terminal 101 downloads application 143 from software deployment server 149, terminal 101 may also download a schedule corresponding to application 143 from software deployment server 149.

[0063] Sensor 153 is associated with terminal 101. Sensor 153 is used to detect the environment around terminal 101. For example, sensor 153 can detect animals, cars, obstacles, and pedestrian crossings, etc. Furthermore, sensor 153 can also detect the environment around the aforementioned animals, cars, obstacles, and pedestrian crossings, such as the environment around the animals, for example, other animals around the animals, weather conditions, ambient light levels, etc. Optionally, if terminal 101 is located on an autonomous vehicle, the sensor can be a radar system, etc.

[0064] The above describes the application scenarios of the error detection method provided in the embodiments of this application. The following will describe in detail the execution process of the error detection method.

[0065] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating an error detection method 200 provided in an embodiment of this application. Figure 2 As shown, the error detection method 200 includes the following steps.

[0066] Step 201: Obtain the scheduling table of the target task. The scheduling table is used to indicate at least one test mode. The at least one test mode is used to detect errors in the target logic circuit. The target logic circuit is the logic circuit used to execute the target task.

[0067] In this embodiment, during normal operation of the terminal, the terminal can periodically execute the error detection method 200, for example, every 30 milliseconds or 50 milliseconds, to ensure that errors that have occurred can be detected in a timely manner.

[0068] In one possible embodiment, the target task can be a task currently running on the terminal, such as a process or thread running on the terminal. The terminal can determine the target task by obtaining the identifier (ID) of the currently running task or by determining the target task based on the data structure corresponding to the currently running task, such as determining which thread the currently running task is based on the thread ID. For example, when the target task is a process, it could be a vehicle video inspection process, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock braking system (ABS) process, or a tire pressure monitoring process.

[0069] In this embodiment, each runnable task on the terminal can have a corresponding scheduling table. These scheduling tables can be pre-installed in the terminal or generated by the terminal based on the task's machine instruction code. Therefore, the terminal can determine the scheduling table corresponding to the target task from multiple scheduling tables. For example, if the target task is a process, the terminal can determine the corresponding scheduling table based on the process ID.

[0070] The scheduling table corresponding to the target task may include at least one test mode, which corresponds to the machine instruction code of the target task. This at least one test mode is used to detect errors in the target logic circuit. The correspondence between the at least one test mode and the machine instruction code of the target task means that, based on this at least one test mode, error detection of the target logic circuit upon which the execution of the machine instruction code of the target task depends can be achieved.

[0071] In simple terms, when a terminal executes machine instruction code, it relies on the logic circuits within the terminal; that is, it executes machine instruction code based on the logic circuits. Therefore, given that at least one test mode corresponds to the machine instruction code of the target task, errors can be detected in the logic circuits used by the terminal when executing the machine instruction code of the target task based on that at least one test mode.

[0072] It is understandable that if an error occurs in the logic circuitry required for the target task during its execution on the terminal, security risks may arise due to this error. Therefore, executing a test mode based on the scheduling table corresponding to the target task can detect errors in the required logic circuitry, thus preventing security risks. For other logic circuits, since the terminal is not currently executing the corresponding task and therefore does not need to use them, errors in these circuits will not pose a security risk.

[0073] In one possible embodiment, at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and a set of machine instruction codes for the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The set of machine instruction codes includes multiple machine instruction codes.

[0074] In one possible embodiment, the scheduling table corresponding to the target task may also indicate the execution order of at least one test mode, which is determined based on the number of times the instruction type corresponding to the machine instruction code of the target task is executed.

[0075] A task typically includes multiple machine instruction codes, which may belong to different instruction types or the same instruction type. Machine instruction codes of the same instruction type usually rely on the same logic circuit for execution, while machine instruction codes of different instruction types rely on different logic circuits for execution. Therefore, when a target task includes multiple machine instruction codes of the same instruction type, the terminal needs to use the logic circuit corresponding to that instruction type multiple times during the execution of the target task. That is, since each use of the logic circuit may lead to an error, and the probability of an error is the same, the more times the logic circuit is used, the higher the probability of an error. In other words, the more times the same instruction type is executed, the more times the logic circuit is used, and the higher the probability of an error. Therefore, in this embodiment, the execution order of the test modes in the scheduling table can be determined based on the number of times the instruction type corresponding to the machine instruction code of the target task is executed. That is, the more times an instruction type is executed, the earlier the execution order of the test mode corresponding to that instruction type is. This allows the terminal to determine the order of detecting logic circuits based on the probability of logic circuit errors, thereby shortening the error detection time and improving the efficiency of error detection.

[0076] For example, suppose the target task includes 6 machine instruction codes, of which 3 belong to instruction type 1, 2 belong to instruction type 0, and 1 belongs to instruction type 2. Then, the execution counts for instruction type 0, instruction type 1, and instruction type 2 are 2, 3, and 1, respectively. The scheduling table corresponding to the target task includes test mode A, test mode B, and test mode C, corresponding to instruction type 0, instruction type 1, and instruction type 2, respectively. This scheduling table may also include the execution order of these three test modes, which is determined based on the execution count of the instruction type corresponding to each test mode. That is, the execution order of the test modes is: Test Mode B - Test Mode A - Test Mode C. Thus, during error detection, the terminal can execute test mode B, test mode A, and test mode C sequentially based on this execution order.

[0077] Step 202: According to the schedule, execute at least one test mode to detect errors in the target logic circuit.

[0078] After obtaining the schedule table, the terminal executes one or more test modes indicated by the schedule table in sequence. Furthermore, after completing the execution of the test modes indicated by the schedule table, the terminal can determine that the current error detection cycle has ended, and the terminal can re-execute the error detection method 200 after a certain time interval. Additionally, if the schedule table also includes the execution order of the test modes, the terminal can also execute one or more test modes in the schedule table in sequence according to the execution order indicated by the schedule table.

[0079] In this embodiment, during error detection, the terminal obtains the target task's scheduling table and executes the test modes included in the scheduling table. Since the scheduling table only includes test modes for detecting the target logic circuit, the terminal can detect errors based on this scheduling table, avoiding the execution of all test modes in the software test library, thereby reducing the processor's load and effectively improving its efficiency. Furthermore, when the scheduling table also includes the execution order of test modes determined by the number of times each instruction type is executed, the terminal executes the test modes based on this execution order. This allows the terminal to determine the order of logic circuit detection based on the probability of errors occurring in the logic circuit, thereby shortening error detection time and improving error detection efficiency.

[0080] The above describes the process by which the terminal executes the corresponding test mode based on the scheduling table corresponding to the target task to achieve error detection. The following will describe in detail the process by which the terminal generates the scheduling table.

[0081] Please refer to Figure 3a , Figure 3aThis is a flowchart illustrating a scheduling table generation method 300 provided in an embodiment of this application. Figure 3a As shown, the scheduling table generation method 300 includes the following steps.

[0082] Step 301: Obtain the set of machine instruction codes for the target task. The set of machine instruction codes includes multiple machine instruction codes.

[0083] In this embodiment, before performing error detection, the terminal can pre-generate a scheduling table corresponding to the task to be run in the terminal, so that the terminal can obtain the scheduling table corresponding to the target task during the error detection process.

[0084] It should be understood that before the terminal performs error detection, the aforementioned target task is a task to be run on the terminal. The terminal can obtain the set of machine instruction codes for the target task by obtaining its executable file. For example, when the target task is an application, the application is installed on the terminal. The executable file of the application can be a file of type ".exe", ".sys", ".com", etc. The terminal can obtain the set of machine instruction codes corresponding to the application based on the application's executable file.

[0085] Generally speaking, for a target task, the executable file of the target task usually includes multiple machine instruction codes, that is, the set of machine instruction codes includes multiple machine instruction codes, and the terminal executes these multiple machine instruction codes to run the target task.

[0086] Step 302: Determine at least one instruction type corresponding to the machine instruction code set according to the second mapping relationship, wherein the second mapping relationship includes the mapping relationship between machine instruction codes and instruction types.

[0087] It is understandable that any machine instruction code has a corresponding instruction type, meaning that any machine instruction code can be categorized into a certain instruction type. Instruction types can include, for example, data transfer instructions, fixed-point arithmetic instructions, bitwise operation instructions, and program control instructions. Since different machine instruction codes can correspond to the same instruction type or different instruction types, at least one instruction type can be determined based on each machine instruction code in the set of machine instruction codes.

[0088] A second mapping relationship can be preset in the terminal. This second mapping relationship includes the mapping relationship between machine instruction codes and instruction types. Based on this second mapping relationship, the instruction type corresponding to each machine instruction code in the machine instruction code set can be determined. Specifically, a possible example of this second mapping relationship is shown in Table 1:

[0089] Table 1

[0090] Machine instruction code 1, Machine instruction code 2 Instruction Type 1 … … Machine instruction code M Instruction type N

[0091] As shown in Table 1, each machine instruction code corresponds to a unique instruction type; and each instruction type can correspond to one or more machine instruction codes. Thus, the number of instruction types determined by the terminal based on the set of machine instruction codes is equal to or less than the number of machine instruction codes in the set. When the number of instruction types is less than the number of machine instruction codes, multiple machine instruction codes may correspond to the same instruction type; that is, the number of times an instruction type is executed is equal to the number of its corresponding machine instruction codes.

[0092] Specifically, this second mapping relationship can be established based on the instruction set manual corresponding to the processor in the terminal. Generally speaking, in the computer field, a command that instructs computer hardware to perform a certain operation or processing function is called an instruction, and the way this instruction is represented can be the machine instruction code mentioned above. An instruction is the smallest functional unit of computer operation, and the role of hardware is to complete the function specified by each instruction. The set of all instructions on the terminal is the instruction set of that terminal, which embodies all the functions of the terminal. Usually, the instruction set on a terminal reflects all the functions of that terminal. Different types of terminals may have different instruction sets, and therefore different functions. The setting of the instruction set is closely related to the hardware circuit of the terminal, and the instruction set manual can indicate the set of instructions that the terminal can execute, as well as the relationship between the instruction set and the hardware circuit in the terminal. Based on the instruction set manual, the relationship between instructions and hardware circuits can be determined, as well as the instruction type to which each instruction in the instruction set belongs, thereby establishing a mapping relationship between machine instruction code and instruction type.

[0093] Step 303: Determine at least one test mode corresponding to at least one instruction type according to the first mapping relationship. The first mapping relationship includes the mapping relationship between instruction types and test modes. The at least one test mode is used to detect errors in the logic circuit corresponding to at least one instruction type.

[0094] Since each type of instruction can be executed within a specific logic circuit, and the logic circuit corresponding to each type of instruction is fixed, it can be assumed that once the instruction type corresponding to a given machine instruction code is determined, the logic circuit used to execute that machine instruction code can be uniquely identified. Therefore, after determining at least one instruction type corresponding to the set of machine instruction codes, by determining the test mode corresponding to that at least one instruction type, the logic circuit used by the target task can be tested based on the determined test mode.

[0095] A first mapping relationship can be preset in the terminal. This first mapping relationship includes the mapping relationship between instruction types and test modes. Based on this first mapping relationship, the test mode corresponding to each instruction type can be determined. Specifically, a possible example of this first mapping relationship is shown in Table 2:

[0096] Table 2

[0097] Instruction Type 1 Test mode group 1 … … Instruction type N Test mode group N

[0098] As shown in Table 2, for any instruction type, there is a corresponding test mode group. Each test mode group can include one or more test modes, meaning that any instruction type has one or more corresponding test modes. Furthermore, each test mode is used to test a specific logic circuit. Therefore, after the terminal determines the instruction type of the machine instruction code, it can determine the test mode to be executed based on the instruction type.

[0099] Specifically, this first mapping relationship can be obtained based on the STL design document. For example, based on the STL design document, relevant information about all test modes included in the STL can be determined, such as the logic circuits detected by the test modes. Thus, having determined the logic circuits detected by the test modes and the logic circuits required by the instruction types, a first mapping relationship can be established to create a mapping between instruction types with the same logic circuits and the test modes.

[0100] Step 304: Generate a scheduling table based on at least one test mode.

[0101] In one possible embodiment, the terminal may generate the schedule table based solely on at least one determined test mode, meaning that the obtained schedule table only includes the at least one test mode without specifying the execution order between the test modes.

[0102] In another possible embodiment, the terminal may also determine the execution order of the at least one test mode and generate a schedule table based on the execution order, such that the schedule table may also include the execution order between the test modes.

[0103] For example, after determining the instruction types corresponding to multiple machine instruction codes according to the second mapping relationship, the terminal can determine the execution count of each instruction type in the at least one instruction type based on the instruction types corresponding to the multiple machine instruction codes. Simply put, the terminal can count the number of machine instruction codes corresponding to each instruction type and determine the execution count of that instruction type. Based on the execution count, the terminal can determine the execution order of the test modes in the at least one test mode. Since each test mode has a unique corresponding instruction type, and each instruction type has its corresponding execution count, the terminal can determine the execution order of the test modes based on the execution count of the instruction type corresponding to the test mode. That is, the terminal can sort the test modes in descending order based on the execution count; the higher the execution count of the instruction type corresponding to the test mode, the earlier the execution order of that test mode; conversely, the lower the execution count of the instruction type corresponding to the test mode, the later the execution order of that test mode. Finally, the terminal can generate a schedule table including the execution order of the test modes based on the at least one test mode and the execution order, so that when the terminal performs error detection, it can execute the test modes sequentially according to the execution order indicated in the schedule table.

[0104] Steps 301-304 above describe the process by which the terminal generates a corresponding scheduling table based on the target task. In practical applications, after acquiring multiple tasks to be run, the terminal can determine the scheduling table corresponding to each task based on a similar process, thus allowing the terminal to store the scheduling table corresponding to each task. In this way, when the terminal executes any task, it can look up the scheduling table corresponding to that task to achieve error detection for that task.

[0105] Understandably, when there are many tasks waiting to be run on the terminal, the terminal can generate a large number of scheduling tables. Therefore, in order for the terminal to quickly determine the scheduling table corresponding to the target task during error detection, after generating the scheduling table for each task, the terminal can also establish a mapping relationship between tasks and scheduling tables. For example, the terminal can generate a third mapping relationship, which includes the mapping relationship between tasks waiting to be run and scheduling tables. After generating any new scheduling table, the terminal can update this third mapping relationship to add the mapping relationship between the newly generated scheduling table and tasks, thereby ensuring that the third mapping relationship generated by the terminal can include the mapping relationship between each task waiting to be run on the terminal and its corresponding scheduling table.

[0106] In one possible embodiment, after generating the scheduling table, the terminal can assign a unique ID to each newly generated scheduling table and establish a mapping relationship between task IDs and scheduling table IDs to obtain a third mapping relationship. In this way, the terminal can quickly determine the corresponding scheduling table ID based on the task ID and the third mapping relationship, and then find the corresponding scheduling table based on that scheduling table ID. Specifically, a possible example of this third mapping relationship is shown in Table 3:

[0107] Table 3

[0108] Task 1 Scheduling Table 1 … … Task N Scheduling table N

[0109] Alternatively, after a new scheduling table is generated, the terminal can allocate a corresponding address space for it to obtain the address space for storing the scheduling table. In this way, the terminal can establish a mapping relationship between task IDs and the address spaces of scheduling tables, thus obtaining a third mapping relationship. That is, based on the task ID and this third mapping relationship, the terminal can quickly determine the address space of the corresponding scheduling table, and thus be able to find the corresponding scheduling table in that address space.

[0110] Please refer to Figure 3b , Figure 3b This is a schematic diagram illustrating another process for generating a scheduling table, as provided in an embodiment of this application. Figure 3b As shown, the terminal can acquire N tasks, such as Task 1, Task 2, ..., Task N, located in the terminal. Then, the terminal performs machine instruction code scanning on each of these tasks to determine the machine instruction code corresponding to each task. Based on the machine instruction code of each task, the terminal can select the test mode corresponding to the machine instruction code of each task from the STL, and sort these selected test modes to obtain the scheduling table for each task, namely, scheduling table 1 for Task 1, scheduling table 2 for Task 2, ..., scheduling table N for Task N.

[0111] Please refer to Figure 3c , Figure 3c This is a schematic diagram illustrating another process for generating a scheduling table, as provided in an embodiment of this application. Figure 3c As shown, Figure 3c Taking the Hi1951 Taishan processing chip as an example, the process of generating the scheduling table is introduced. The Hi1951 Taishan is a processing chip from Huawei, which can include multiple processors capable of executing different tasks in parallel. Figure 3cAs shown, firstly, based on the Hi1951 Taishan processor architecture instruction set, the mapping relationship between machine instruction codes and instruction types can be determined, resulting in mapping table A. Secondly, based on the Hi1951 Taishan test mode design scheme, the mapping relationship between instruction types and test modes can be determined, resulting in mapping table B. Then, based on mapping table A and the executable file of the target task, the instruction scanner can determine the instruction type corresponding to each machine instruction code in the executable file, thereby obtaining all instruction types corresponding to the executable file. After obtaining all instruction types corresponding to the executable file, the test modes corresponding to these instruction types can be determined based on mapping table B, and these test modes can be sorted according to the execution count of each instruction type. That is, test modes are selected and sorted in the STL to obtain the scheduling table corresponding to the target task.

[0112] The above describes the process of generating a scheduling table from a task-based machine instruction code set by the terminal. The following section will detail how the terminal configures the scheduling table after it has been generated.

[0113] In one possible embodiment, the terminal can provide a configuration area for the scheduling table by reserving shared memory.

[0114] For example, the terminal can reserve a portion of memory space as shared memory through the device tree binary (DTB) configuration and obtain a reference handle for the shared memory. This reference handle includes configuration information such as the address, size, and access permissions of the shared memory. After generating a scheduling table, the terminal can allocate an address space within the shared memory for the scheduling table and store the scheduling table in that address space. Furthermore, the terminal can generate configuration information for the scheduling table based on this address space, such as generating a mapping between the address space index and the scheduling table ID. This allows the terminal to determine the address space index based on the scheduling table ID when performing error detection, thereby locating the scheduling table within that address space.

[0115] When the terminal provides a configuration area for the scheduling table by reserving shared memory, multiple processors in the terminal can access the scheduling table in that shared memory. This allows each processor to independently perform error detection based on its respective task. Providing a configuration area for the scheduling table by reserving shared memory avoids providing a separate configuration area for each processor, thus saving storage resources.

[0116] In another possible embodiment, the terminal can implement the scheduling of the schedule table in hardware.

[0117] For example, the terminal's processor can be pre-designed with two registers for scheduling the schedule table: a sorting register and a status register. During error detection, after the terminal determines the schedule table corresponding to the target task, it can write the test modes in the schedule table into the sorting register in an orderly manner according to their execution order. Then, the terminal can execute the test modes according to the execution order in the sorting register and write the execution results of the test modes into the status register.

[0118] For example, see Figure 4 , Figure 4 This is a schematic diagram illustrating the structure of a sorting register and a status register provided in an embodiment of this application. Figure 4 As shown, both the sort register and the status register are 64-bit registers. In the sort register, the 64 bits are divided into 16 groups of 4 bits, each group of 4 bits representing the ID of a test mode. The terminal can write the test modes in the schedule table into the sort register in an orderly manner according to their execution order, and execute the test modes in an orderly manner according to the execution order in the sort register during error detection.

[0119] In the status register, the 64 bits are divided into several parts. Bits [2:0] represent the test status: 0 indicates the test has not started; 1 indicates the test has been completed; and 2 indicates the test is in progress. Bits [4:3] represent the test result: 0 indicates the test has passed; and 1 indicates the test has failed. Bits [30:5] are reserved bits, used to reserve a certain number of bits for future expansion. Bits [47:31] represent the test mode ID, used to indicate the ID of the currently executed test mode. Bits [54:48] represent the hardware module being detected by the current test mode, such as indicating a specific logic circuit.

[0120] The above describes how the terminal performs error detection. To facilitate understanding, the following will provide a detailed explanation of the beneficial effects of the terminal performing the above error detection method, using examples.

[0121] Assume that the STL in the terminal includes 20 test modes, namely test mode 1 to test mode 20. The terminal also includes two tasks to be run, task A and task B, and based on the error detection method provided in this embodiment, the test modes corresponding to task A are determined to be test mode 1 to test mode 12, and the test modes corresponding to task B are test mode 10 to test mode 20.

[0122] Please refer to Figure 5 , Figure 5This is a comparative schematic diagram illustrating the execution error detection provided in an embodiment of this application. For example... Figure 5 As shown in (a), the error detection process in the related technology is as follows: During normal terminal operation, the terminal first executes task A, and then executes task B. After a certain time interval between the start of task A execution, the terminal begins executing the 20 test modes included in the STL, namely test mode 1 to test mode 20. After executing these 20 test modes, the terminal continues to execute task A until task A is completed, and then continues to execute task B. During the execution of task B, after a certain time interval between the last execution of a test mode, the terminal continues to execute these 20 test modes. In other words, regardless of what task the terminal is currently executing, the terminal needs to periodically execute all 20 test modes, which requires a significant amount of processor time to execute the test modes.

[0123] like Figure 5 As shown in (b), the error detection process in this scheme is as follows: During normal terminal operation, the terminal first executes task A, and then task B. After a certain time interval between the start of task A execution, the terminal begins executing the 12 test modes corresponding to task A, namely test mode 1 to test mode 12. After executing these 12 test modes, the terminal continues to execute task A until task A is completed, and then continues to execute task B. During the execution of task B, after a certain time interval between the last execution of a test mode, the terminal executes the 10 test modes corresponding to task B, namely test mode 10 to test mode 20. In other words, the terminal can select the test mode to be executed based on the currently executing task, rather than executing all test modes in the STL, thereby shortening the time for the terminal to execute each test mode.

[0124] Furthermore, suppose an error occurs during the execution of task A by the terminal, and the logic circuit causing the error is one that is frequently used during task A. The test mode used to detect this logic circuit is test mode 12. In related technologies, the terminal executes test modes 1-20 sequentially, requiring a total of 12 test modes (i.e., test modes 1-12) to detect the erroneous logic circuit, resulting in a long error detection time. However, in this solution, since the logic circuit corresponding to test mode 12 is one that is frequently used in task A, test mode 12 is executed earlier. Based on the adjusted execution order, the terminal can quickly detect the erroneous logic circuit. For details, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a comparative schematic diagram of FDTI in different schemes provided in the embodiments of this application. Figure 6It can be seen that, compared with related technologies, the test mode based on the adjusted execution order in this solution can effectively shorten the error detection time.

[0125] Furthermore, this embodiment also provides a comparison of FDTI (Fault-to-Time Interaction) when using related techniques and the present solution for error detection in the case of errors in the logic circuit; and a comparison of the total time consumption when using related techniques and the present solution for error detection in the case of no errors in the logic circuit. Referring to Figure 7(a), which is a schematic diagram comparing FDTI in different solutions when errors exist, as provided in this embodiment, when errors exist in the logic circuit, the error detection time using related techniques is close to 0.7 milliseconds, while the error detection time using the present solution is less than 0.4 milliseconds, effectively shortening the error detection time. Referring to Figure 7(b), which is a schematic diagram comparing the total time consumption for error detection in different solutions, as provided in this embodiment, when errors exist in the logic circuit, the total error detection time using related techniques is close to 4.5 milliseconds, while the total error detection time using the present solution is less than 3.5 milliseconds, effectively shortening the error detection time and reducing the processor load.

[0126] Based on the embodiments corresponding to Figures 1 to 7(b), in order to better implement the above-described solutions of this application, related equipment for implementing the above-described solutions is also provided below. For details, please refer to... Figure 8 , Figure 8 This is a schematic diagram of the structure of a terminal 800 provided in an embodiment of this application. The terminal 800 includes a processing unit 801 and an acquisition unit 802. The acquisition unit 802 is used to acquire a scheduling table of a target task. The scheduling table indicates at least one test mode, and the at least one test mode is used to detect errors in a target logic circuit, which is a logic circuit used to execute the target task. The processing unit 801 is used to execute at least one test mode according to the scheduling table to detect errors in the target logic circuit.

[0127] In some possible implementations, the target task is a running task.

[0128] In some possible implementations, at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and a set of machine instruction codes for the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The set of machine instruction codes includes multiple machine instruction codes.

[0129] In some possible implementations, the scheduling table also indicates the execution order of at least one test mode, the execution order being determined based on the number of executions of at least one instruction type corresponding to the machine instruction code set of the target task. In some possible implementations, the terminal further includes: an acquisition unit 802; the acquisition unit 802 is used to acquire the machine instruction code set of the target task, the machine instruction code set including multiple machine instruction codes; the processing unit 801 is further used to: determine at least one instruction type corresponding to the machine instruction code set according to a second mapping relationship, the second mapping relationship including the mapping relationship between machine instruction codes and instruction types; determine at least one test mode corresponding to at least one instruction type according to a first mapping relationship, the first mapping relationship including the mapping relationship between instruction types and test modes, the at least one test mode being used to detect errors in the logic circuit corresponding to at least one instruction type; and generate a scheduling table based on the at least one test mode.

[0130] In some possible implementations, the processing unit 801 is further configured to: determine the number of times an instruction type is executed in at least one instruction type based on the instruction types corresponding to the multiple machine instruction codes; determine the execution order of the test modes in at least one test mode based on the number of executions; and generate a scheduling table based on at least one test mode and the execution order.

[0131] In some possible implementations, the processing unit 801 is further configured to: generate a third mapping relationship, which includes the mapping relationship between the target task and the scheduling table; and determine the scheduling table based on the target task and the third mapping relationship.

[0132] In some possible implementations, the scheduling table is stored in shared memory, which is configured to store the scheduling tables for one or more tasks and can be accessed by multiple processors.

[0133] In some possible implementations, the processing unit 801 is further configured to: write at least one test mode into a sorting register according to the execution order; execute the test modes according to the execution order in the sorting register; and write the execution result of the test modes into a status register.

[0134] In some possible implementations, the target task includes a process or a thread.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

Claims

1. An error detection method, characterized in that, include: Obtain a scheduling table corresponding to the target task. The scheduling table is used to indicate at least one test mode, which is used to detect errors in the target logic circuit. The target logic circuit is a logic circuit used to execute the target task. The scheduling table is pre-generated. The scheduling table only includes at least one of the test modes used to detect errors in the target logic circuit. According to the scheduling table, at least one test mode is executed to detect errors in the target logic circuit.

2. The error detection method according to claim 1, characterized in that, The target task is a running task.

3. The error detection method according to claim 1 or 2, characterized in that, The at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and the machine instruction code set of the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The machine instruction code set includes multiple machine instruction codes.

4. The error detection method according to claim 1, characterized in that, The scheduling table also indicates the execution order of the at least one test mode, which is determined based on the number of times at least one instruction type corresponding to the machine instruction code set of the target task is executed.

5. The error detection method according to claim 1 or 2, characterized in that, The method further includes: Obtain the set of machine instruction codes for the target task, wherein the set of machine instruction codes includes multiple machine instruction codes; At least one instruction type corresponding to the machine instruction code set is determined according to the second mapping relationship, wherein the second mapping relationship includes the mapping relationship between machine instruction codes and instruction types; At least one test mode corresponding to the at least one instruction type is determined according to a first mapping relationship, wherein the first mapping relationship includes a mapping relationship between instruction types and test modes, and the at least one test mode is used to detect errors in the logic circuit corresponding to the at least one instruction type. The scheduling table is generated based on at least one of the test modes.

6. The error detection method according to claim 5, characterized in that, The method further includes: Based on the instruction types corresponding to the plurality of machine instruction codes, determine the number of times an instruction type in the at least one instruction type is executed; Based on the number of executions, determine the execution order of the test modes in the at least one test mode; Generating the scheduling table according to the at least one test mode includes: The scheduling table is generated based on the at least one test mode and the execution order.

7. The error detection method according to any one of claims 1 to 2, characterized in that, The scheduling table is stored in shared memory, which is configured to store the scheduling table of one or more tasks and can be accessed by multiple processors.

8. The error detection method according to claim 4 or 6, characterized in that, The step of executing the at least one test mode according to the scheduling table includes: According to the execution order, the at least one test mode is written into the sort register; The test modes are executed according to the execution order in the sort register, and the execution results of the test modes are written to the status register.

9. The error detection method according to any one of claims 1 to 2, characterized in that, The target task includes a process or a thread.

10. A terminal, characterized in that, Includes a processor; the processor is used for: Obtain a scheduling table corresponding to the target task. The scheduling table is used to indicate at least one test mode, which is used to detect errors in the target logic circuit. The target logic circuit is a logic circuit used to execute the target task. The scheduling table is pre-generated. The scheduling table only includes at least one of the test modes used to detect errors in the target logic circuit. According to the scheduling table, at least one test mode is executed to detect errors in the target logic circuit.

11. The terminal according to claim 10, characterized in that, The target task is a running task.

12. The terminal according to claim 10 or 11, characterized in that, The at least one test mode in the scheduling table is determined based on a first mapping relationship and at least one instruction type. The first mapping relationship includes a mapping relationship between instruction types and test modes. The at least one instruction type is determined based on a second mapping relationship and the machine instruction code set of the target task. The second mapping relationship includes a mapping relationship between machine instruction codes and instruction types. The machine instruction code set includes multiple machine instruction codes.

13. The terminal according to claim 10, characterized in that, The scheduling table also indicates the execution order of the at least one test mode, which is determined based on the number of times at least one instruction type corresponding to the machine instruction code set of the target task is executed.

14. The terminal according to claim 10 or 11, characterized in that, The processor is also used for: Obtain the set of machine instruction codes for the target task, wherein the set of machine instruction codes includes multiple machine instruction codes; At least one instruction type corresponding to the machine instruction code set is determined according to the second mapping relationship, wherein the second mapping relationship includes the mapping relationship between machine instruction codes and instruction types; At least one test mode corresponding to the at least one instruction type is determined according to a first mapping relationship, wherein the first mapping relationship includes a mapping relationship between instruction types and test modes, and the at least one test mode is used to detect errors in the logic circuit corresponding to the at least one instruction type. The scheduling table is generated based on at least one of the test modes.

15. The terminal according to claim 14, characterized in that, The processor is also used for: Based on the instruction types corresponding to the plurality of machine instruction codes, determine the number of times an instruction type in the at least one instruction type is executed; Based on the number of executions, determine the execution order of the test modes in the at least one test mode; The scheduling table is generated based on the at least one test mode and the execution order.

16. The terminal according to any one of claims 10 to 11, characterized in that, The scheduling table is stored in shared memory, which is configured to store the scheduling table of one or more tasks and can be accessed by multiple processors.

17. The terminal according to claim 13 or 15, characterized in that, The processor is also used for: According to the execution order, the at least one test mode is written into the sort register; The test modes are executed according to the execution order in the sort register, and the execution results of the test modes are written to the status register.

18. The terminal according to any one of claims 10 to 11, characterized in that, The target task includes a process or a thread.

19. A computer-readable storage medium, characterized in that, Includes computer-readable instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 9.

20. A computer program product, characterized in that, Includes computer-readable instructions, which, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 9.

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