Semiconductor device having three-dimensional cell structure and method of manufacturing the same

Abstract

This application relates to a semiconductor device and a method for fabricating the same. According to one aspect of this disclosure, the semiconductor device includes a substrate and a plurality of word line structures disposed above the substrate and spaced apart from each other in a first direction perpendicular to the substrate surface. Each of the plurality of word line structures extends in a second direction parallel to the substrate surface. Additionally, the semiconductor device includes: a switching layer disposed on the substrate to contact side surfaces of the plurality of word line structures; and bit line structures disposed on the substrate to extend in the first direction and contact the surface of the switching layer. The switching layer is configured to perform threshold switching operation and has a variable, programmable threshold voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean application No. 10-2020-0142565, filed with the Korean Intellectual Property Office on October 29, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a semiconductor device, and more specifically, to a semiconductor device having a three-dimensional unit structure and a method for manufacturing the same. Background Technology

[0004] Recently, semiconductor devices with three-dimensional structures have emerged compared to those with planar structures. The advantage of three-dimensional semiconductor devices is their ability to effectively respond to industrial demands for reduced design rules and increased integration density. Research on three-dimensional semiconductor devices has been actively ongoing, particularly in the field of memory technology, which requires high integration and high capacity. Summary of the Invention

[0005] A semiconductor device according to one aspect of this disclosure may include a substrate and a plurality of word line structures disposed above the substrate and spaced apart from each other in a first direction perpendicular to the substrate surface. Each of the plurality of word line structures may extend in a second direction parallel to the substrate surface. Furthermore, the semiconductor device may include: a switching layer disposed above the substrate to contact side surfaces of the plurality of word line structures; and bit line structures disposed above the substrate to extend in the first direction and contact the surface of the switching layer. The switching layer may be configured to perform threshold switching operation and have a variable, programmable threshold voltage.

[0006] A method for manufacturing a semiconductor device according to another aspect of this disclosure is disclosed. In this method, a substrate having a base insulating layer can be provided. A plurality of first word line structures extending in a first lateral direction parallel to the surface of the substrate and a first switching functional layer disposed between the plurality of first word line structures can be formed over the base insulating layer. The plurality of first word line structures can be spaced apart from each other over the base insulating layer in a second lateral direction parallel to the surface of the substrate and perpendicular to the first lateral direction. A first interlayer insulating layer can be formed on the plurality of first word line structures and the first switching functional layer. A plurality of second word line structures extending in the first lateral direction and a second switching functional layer disposed between the plurality of second word line structures can be formed on the first interlayer insulating layer. The plurality of second word line structures can be arranged to overlap with the plurality of first word line structures respectively. The second switching functional layer, the first interlayer insulating layer, the first switching functional layer and the base insulating layer can be selectively etched to form bit line contact holes exposing the substrate, such that portions of the first switching functional layer and the second switching functional layer retained on the side surfaces of the plurality of first word line structures and the plurality of second word line structures are left. A conductive material can be provided in the bit line contact holes to form bit line structures. Attached Figure Description

[0007] Figure 1 This is a schematic view of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A This is a schematic view illustrating a first programming operation on a unit cell according to an embodiment of the present disclosure.

[0009] Figure 2B This is a schematic view illustrating a second programming operation on a unit cell according to an embodiment of the present disclosure.

[0010] Figure 2C This is a schematic view illustrating a reading operation of a unit cell according to an embodiment of the present disclosure.

[0011] Figure 3A This is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3B It is along Figure 3A A cross-sectional view of a semiconductor device taken along line I-I'.

[0013] Figure 3C It is along Figure 3A A cross-sectional view of a semiconductor device taken along line II-II'.

[0014] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0015] Figures 5A to 11A This is a plan view schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 5B to 11B It is along Figures 5A to 11A A cross-sectional view of a semiconductor device taken along line A-A'.

[0017] Figures 8C to 11C It is along Figures 8A to 11A A cross-sectional view of a semiconductor device taken along line B-B'. Detailed Implementation

[0018] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components, such as width and thickness, are enlarged to clearly illustrate the parts of each device. The terminology used herein may correspond to words chosen with regard to their function in the embodiments, and these terms may be interpreted in different ways according to those skilled in the art to which the embodiments pertain. Where there is a clear and detailed definition, these terms may be interpreted according to the definition. Unless otherwise defined, the meanings of the terms used herein (including technical and scientific terms) are the same as those commonly understood by those skilled in the art to which the embodiments pertain.

[0019] Furthermore, unless explicitly used otherwise in the context, the singular form of a word should be understood to include the plural form of that word. It is understood that the terms “comprising,” “including,” or “having” are intended to indicate the presence of a feature, number, step, operation, component, element, part, or combination thereof, but do not preclude the presence or possibility of adding one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0020] Furthermore, when performing a method or manufacturing method, each process constituting the method may be performed in a manner different from the prescribed order, unless the specific order is explicitly described in the context. In other words, each process may be performed in the same manner as the prescribed order and may be performed substantially at the same time, or it may be performed in a different order. Additionally, at least a portion of each of the above processes may be performed in reverse order.

[0021] In this specification, the term "predetermined direction" can refer to a direction that includes a direction defined in a coordinate system and directions opposite to that direction. For example, in an xyz coordinate system, the x-direction can include directions parallel to the x-direction. That is, the x-direction can refer to both directions that increase in absolute value along the x-axis in the positive direction from the origin 0 and directions that increase in absolute value along the x-axis in the negative direction from the origin 0. In the xyz coordinate system, the y-direction and z-direction can be described in substantially the same way.

[0022] In this specification, word lines and bit lines can be interpreted as relative concepts. That is, the function of word lines and bit lines can be determined relatively according to the design of the semiconductor device. Accordingly, word lines can function as bit lines according to the design, and bit lines can function as word lines.

[0023] Figure 1 This is a schematic view illustrating a semiconductor device according to one embodiment of the present disclosure. Reference Figure 1 The semiconductor device 1 may include a bit line BL extending in a first direction (i.e., the z-direction) and a plurality of word lines WL1-1, WL1-2, WL2-1, WL2-2, WL3-1, WL3-2, WL4-1, and WL4-2 extending in a second direction perpendicular to the first direction (i.e., the y-direction). Furthermore, the semiconductor device 1 may include a plurality of unit cells C disposed in the region where the bit line BL overlaps with the plurality of word lines WL1-1, WL1-2, WL2-1, WL2-2, WL3-1, WL3-2, WL4-1, and WL4-2.

[0024] Multiple word lines WL1-1, WL1-2, WL2-1, WL2-2, WL3-1, WL3-2, WL4-1, and WL4-2 may include first word lines WL1-1 and WL1-2, second word lines WL2-1 and WL2-2, third word lines WL3-1 and WL3-2, and fourth word lines WL4-1 and WL4-2. These word lines can be arranged along a first direction (i.e., the z-direction). Figure 1 The first to fourth word lines are shown in the figure, but the number of word lines is not necessarily limited to this, and various other numbers are also possible.

[0025] The first word lines WL1-1 and WL1-2 can be configured as a pair of word lines sharing bit line BL. Each of the second word lines WL2-1 and WL2-2, the third word lines WL3-1 and WL3-2, and the fourth word lines WL4-1 and WL4-2 can also be configured as a pair of word lines sharing bit line BL in the same manner.

[0026] The unit cell C according to embodiments of this disclosure may have a switching layer that performs threshold switching operations. This switching layer may have a programmable and variable threshold voltage. That is, by performing different programming operations on the unit cell C, the switching layer may have different threshold voltages. Subsequently, a read operation is performed to identify the difference between the different threshold voltages, thereby allowing the signal information programmed in the unit cell C to be read.

[0027] Figure 2A This is a schematic view illustrating a first programming operation on a unit cell according to an embodiment of the present disclosure. Figure 2B This is a schematic view illustrating a second programming operation on a unit cell according to an embodiment of the present disclosure. Figure 2C This is a schematic view illustrating a read operation on a unit cell according to one embodiment of the present disclosure. In the following, as an embodiment, in Figure 1 In this document, the first programming operation, the second programming operation, and the read operation will be described with respect to a unit cell C disposed between any one of the multiple word lines WL1-1, WL1-2, WL2-1, WL2-2, WL3-1, WL3-2, WL4-1, and WL4-2 and the bit line BL. For ease of description, any word line coupled to the unit cell C will be referred to as the selected word line.

[0028] refer to Figure 2A The first programming operation 11 can be performed by applying a first programming voltage P1 to the unit cell C. In one embodiment, the first programming voltage P1 may be a positive pulse voltage having a first amplitude V1 during a first time interval Δt1. In one implementation, the first programming voltage P1 can be applied to a selected word line, and... Figure 1 The first programming operation 11 is performed by grounding the bit line BL. In this case, no voltage may be applied to word lines other than the selected word line, or a positive pulse voltage with an amplitude less than the first programming voltage P1 may be applied to word lines other than the selected word line.

[0029] refer to Figure 2B The second programming operation 12 can be performed by applying a second programming voltage P2 to the unit cell C. In one embodiment, the second programming voltage P2 can be a negative pulse voltage with a second amplitude V2 during a second time interval Δt2. In one embodiment, in Figure 1 In this case, the second programming operation 12 can be performed by applying the second programming voltage P2 to the selected word line and grounding the bit line BL. In this case, no voltage may be applied to the word lines other than the selected word line, or a negative pulse voltage with a second amplitude V2 less than the second programming voltage P2 may be applied to the word lines other than the selected word line.

[0030] refer to Figure 2C The first switching curve 21 and the second switching curve 22 are used to describe the read operation method of unit cell C, which has performed the first programming operation 11 and the second programming operation 12. The first switching curve 21 and the second switching curve 22 represent the read operation method when a voltage is applied to the selected word line (which sweeps the frequency in the positive direction from 0V) and when the bit line BL is grounded. Figure 1 The current output by the selected unit cell C in the diagram.

[0031] Referring to the first switching curve 21 and the second switching curve 22, when the applied voltage reaches the first threshold voltage Vth1 and the second threshold voltage Vth2, respectively, the current output from unit cell C can rapidly increase to reach the turn-on current Ic. Therefore, when the applied voltage is less than the respective first threshold voltage Vth1 and second threshold voltage Vth2, a relatively low current can be output from unit cell C, while when the applied voltage is equal to or greater than the respective first threshold voltage Vth1 and second threshold voltage Vth2, a relatively high current can be output from unit cell C. However, when the applied voltage drops back to 0V, the output current can decrease to 0A. In this way, unit cell C can perform threshold switching operation by applying voltage along the first switching curve 21 and the second switching curve 22.

[0032] In one embodiment, such as Figure 2A After performing the first programming operation 11 on the unit cell C using a first programming voltage P1 with positive polarity, when a voltage with positive polarity is applied to the unit cell C, and as... Figure 2C During frequency sweep, unit cell C can perform threshold switching operation along the first switching curve 21. That is, unit cell C can have a relatively low first threshold voltage Vth1.

[0033] In another embodiment, such as Figure 2B After performing the second programming operation 12 on the unit cell C using the second programming voltage P2, when a positive voltage is applied to the unit cell C, and as... Figure 2C During frequency sweep, unit cell C can perform threshold switching operation along the second switching curve 22. That is, unit cell C can have a relatively high second threshold voltage Vth2.

[0034] refer to Figure 2CFor a unit cell C that has undergone either the first programming operation 11 or the second programming operation 12, the following read operation can be performed. First, the voltage between the first threshold voltage Vth1 and the second threshold voltage Vth2 can be determined as the read voltage Vread. The determined read voltage Vread can be applied to the unit cell C, and the current output from the unit cell C can be measured. The measured current can be identified as either a high current or a low current; therefore, the signal information stored in the unit cell C can be read. The voltage difference ΔVth between the first threshold voltage Vth1 and the second threshold voltage Vth2 can determine the amplitude or window of the read voltage.

[0035] As described above, when the unit cell C is programmed with a programming voltage having the same polarity as the read voltage, the unit cell C may have a relatively small threshold voltage during the read operation using the read voltage. Conversely, when the unit cell C is programmed with a programming voltage having a different polarity than the read voltage, the unit cell C may have a relatively large threshold voltage during the read operation using the read voltage. Therefore, according to embodiments of this disclosure, after determining the polarity of the read voltage, the polarity of the programming voltage to be applied for the programming operation can be determined based on the determined polarity of the read voltage.

[0036] Figure 3A This is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 3B It is along Figure 3A A cross-sectional view of a semiconductor device taken along line I-I'. Figure 3C It is along Figure 3A A cross-sectional view of a semiconductor device taken along line II-II'.

[0037] refer to Figure 3A , 3B Similar to 3C, semiconductor device 1a may include a substrate 101, a plurality of word line structures 122, 124, 126, and 128 disposed on or above the substrate 101, and a switching layer 150. Furthermore, semiconductor device 1a may include a bit line structure 140 above the substrate 101, adjacent to the surface of the switching layer 150. The switching layer 150 may be arranged between the plurality of word line structures 122, 124, 126, and 128 and the bit line structure 140 to form a plurality of unit cells.

[0038] Substrate 101 may be made of or comprise semiconductor materials. Semiconductor materials may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or combinations of two or more thereof. For example, the semiconductor material may be doped with n-type or p-type dopants. In some other embodiments, substrate 101 may be an insulating substrate or a conductive substrate.

[0039] A substrate insulating layer 110 may be disposed on the substrate 101. The substrate insulating layer 110 may electrically insulate the lowest word line structure 122 of the plurality of word line structures 122, 124, 126 and 128 from the substrate 101. The substrate insulating layer 110 may be made of or comprise an insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides or combinations of two or more thereof.

[0040] Although not shown, an integrated circuit may be disposed between substrate 101 and substrate insulating layer 110. For example, the integrated circuit may include active devices such as transistors, passive devices such as resistors and capacitors, or a combination of active and passive devices. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer for insulating the at least one circuit pattern layer.

[0041] refer to Figure 3B and Figure 3C The first word line structure 122 can be disposed on the substrate insulating layer 110. The first word line structure 122 can extend in a second direction (i.e., the y direction) parallel to the top or bottom surface (i.e., the xy plane) of the substrate 101. The first word line structure 122 can be configured to be spaced apart from another first word line structure in a third direction (i.e., the x direction), wherein the third direction is perpendicular to the second direction.

[0042] The second character line structure 124 can be positioned above the first character line structure 122. The second character line structure 124 can extend in a second direction (i.e., the y-direction). The second character line structure 124 can be positioned spaced apart from another second character line structure in a third direction (i.e., the x-direction). The second character line structure 124 can be positioned parallel to the first character line structure 122 in a different parallel plane.

[0043] The second character line structure 124 and the first character line structure 122 can be configured to overlap each other on different planes. A first interlayer insulating layer 132 can be disposed between the first character line structure 122 and the second character line structure 124. The first interlayer insulating layer 132 can electrically insulate the first character line structure 122 and the second character line structure 124.

[0044] In substantially the same manner, the second interlayer insulation layer 134, the third letter structure 126, the third interlayer insulation layer 136, the fourth letter structure 128, and the fourth interlayer insulation layer 138 can be sequentially disposed above the base insulation layer 110.

[0045] The first to fourth word line structures 122, 124, 126, and 128 may be made of or include conductive materials. Conductive materials may include, for example, doped semiconductors, metals, conductive metal nitrides, conductive metal carbides, conductive metal silicides, or conductive metal oxides. Conductive materials may include, for example, silicon (Si), gallium arsenide (GaAs), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations thereof, doped with n-type or p-type dopants.

[0046] The first to fourth interlayer insulating layers 132, 134, 136, and 138 may be made of or comprise insulating material. The insulating material may include, for example, oxides, nitrides, oxynitrides, or combinations of two or more thereof.

[0047] In some embodiments, when interlayer insulating layers and word line structures are alternately stacked along a first direction (i.e., the z-direction), the number of stacked interlayer insulating layers and the number of stacked word line structures may not necessarily be limited to a certain number. Figure 3A , Figure 3B and Figure 3C The number shown is not the actual number; rather, the number of these structures and layers can vary.

[0048] Each of the switch layers 150 may be configured to be adjacent to the side surface S1 of each of the first to fourth word line structures 122, 124, 126, and 128, respectively. Each of the switch layers 150 may be separated by the unit insulation structure 170 in a second direction (i.e., the y-direction). The surface S2 of each of the switch layers 150 may be in contact with the bit line structure 140.

[0049] For example, the switch layer 150 may be made of or include chalcogenide-based materials. The switching layer 150 may be made of or include the following: for example, germanium-tellurium (Ge-Te), germanium-selenium-tellurium (Ge-Se-Te), indium-selenium (In-Se), antimony-tellurium (Sb-Te), arsenic-tellurium (As-Te), aluminum-tellurium (Al-Te), germanium-antimony-tellurium (Ge-Sb-Te), tellurium-germanium-arsenic (Te-Ge-As), indium-antimony-tellurium (In-Sb-Te), tellurium-tin-selenium (Te-Sn-Se), germanium-selenium-gallium (Ge-Se-Ga), bismuth-selenium-antimony (Bi-Se-Sb), gallium-selenium-tellurium (Ga-Se-Te), tin-antimony-tellurium (Sn-Sb-Te), tellurium-germanium-antimony-sulfur (Te-Ge-Sb-S), tellurium-germanium-tin-oxygen (Te-Ge-Sn-O), tellurium- Germanium-tin-gold (Te-Ge-Sn-Au), palladium-tellurium-germanium-tin (Pd-Te-Ge-Sn), indium-selenium-titanium-cobalt (In-Se-Ti-Co), germanium-antimony-tellurium-palladium (Ge-Sb-Te-Pd), germanium-antimony-tellurium-cobalt (Ge-Sb-Te-Co), antimony-tellurium-bismuth-selenium (Sb-Te-Bi-Se), silver-indium-antimony-tellurium (Ag-In-Sb-Te), germanium-antimony-selenium-tellurium (Ge-Sb-Se-Te), germanium-tin-antimony-tellurium (Ge-Sn-Sb-Te), germanium-tellurium-tin-nickel (Ge-Te-Sn-Ni), germanium-tellurium-tin-palladium (Ge-Te-Sn-Pd), germanium-tellurium-tin-platinum (Ge-Te-Sn-Pt), or combinations of two or more of these.

[0050] Switching layer 150 can perform the functions described above by applying a voltage across it. Figures 2A to 2C The threshold switching operation is described above. The switching layer 150 may have a programmable and variable threshold voltage. In one embodiment, the switching layer 150 may function as a memory layer within a unit cell utilizing the variable threshold voltage characteristic.

[0051] refer to Figure 3A , Figure 3B and Figure 3C The bit line structure 140 can be disposed above the substrate 101 to extend in a first direction (i.e., the z-direction) and contact the surface S2 of each switching layer 150. For example... Figure 3A As shown, bit line structure 140 can be configured to be spaced apart from other adjacent bit line structures in the second direction (i.e., the y direction) by unit insulation structure 170.

[0052] Each of the bit line structures 140 may be configured to contact the substrate 101. Each of the bit line structures 140 may be electrically connected to an integrated circuit within the substrate 101.

[0053] refer to Figure 3B Each bit line structure 140 may have a side surface in contact with the switch layer 150 and the first to fourth interlayer insulating layers 132, 134, 136 and 138 having an inclination angle α1 that may be substantially perpendicular to the surface of the substrate 101.

[0054] Bitline structure 140 may be made of or include conductive materials. Conductive materials may include, for example, silicon (Si), gallium arsenide (GaAs), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more thereof, doped with n-type or p-type dopants.

[0055] The unit insulation structure 170 may be disposed above the base insulation layer 110 to extend in a first direction (i.e., the z-direction). The unit insulation layer 170 may be configured to contact the switch layer 150, the first to fourth interlayer insulation layers 132, 134, 136, and 138, and the bit line structure 140 in a second direction (i.e., the y-direction). The unit insulation layer 170 may be configured to contact the first to fourth word line structures 122, 124, 126, and 128, and the first to fourth interlayer insulation layers 132, 134, 136, and 138 in a third direction (i.e., the x-direction).

[0056] Although not illustrated, in some embodiments, a polymer layer comprising carbon (C) may be disposed at the interface between the switch layer 150 and the bit line structure 140. This polymer layer can serve as a buffer layer between the switch layer 150 and the bit line structure 140. The polymer layer may be formed during the formation of the switch layer 150. The following will be combined with… Figure 10A , Figure 10B and Figure 10C The process of generating polymer layers through a patterning process for switching functional layers 352, 354, 356 and 358 is described in detail.

[0057] The polymer layer can be connected to the switching layer 150, which is connected in series with the bit line structure 140 between the first to fourth word line structures 122, 124, 126, and 128, respectively. The polymer layer can serve as a resistive layer with constant resistance. The polymer layer can prevent the output current from rapidly increasing at the threshold voltage during threshold switching operation of the switching layer 150. That is, the polymer layer can prevent excessive bias voltage from being applied to the switching layer 150 or excessive current from flowing through the switching layer 150 during threshold switching operation, thereby preventing a decrease in the durability of the semiconductor device.

[0058] Furthermore, the polymer layer can help to gradually increase the output current as the applied voltage increases during threshold switching operation of the switching layer 150. Therefore, the range of programmed operations (i.e., the operating window) can be increased by increasing the voltage range capable of driving the switching layer 150.

[0059] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Reference Figure 4 Semiconductor device 1b can be referenced above. Figure 3A , Figure 3B and Figure 3C The semiconductor device 1a described is different in that the tilt angle α2 formed by one side of the bit line structure 240 and the surface of the substrate 101 is different.

[0060] Figure 4 The sectional view can correspond to Figure 3B A cross-sectional view. The semiconductor device 1b may include first to fourth word line structures 222, 224, 226, and 228 spaced apart from each other in a first direction (i.e., the z-direction). The first to fourth word line structures 222, 224, 226, and 228 may be made of substantially the same material as the first to fourth word line structures 122, 124, 126, and 128 of the semiconductor device 1a.

[0061] Semiconductor device 1b may include bit line structures 240 extending in a first direction (i.e., the z-direction). A tilt angle α2 is formed by the side surface of each bit line structure 240 and the substrate 101. The side surface of each bit line structure 240 may also contact the switching layer 250 and the first to fourth interlayer insulating layers 132, 134, 136, and 138. The tilt angle α2 may be an acute angle. The bit line structures 240 may be made of substantially the same material as the bit line structure 140 of semiconductor device 1a.

[0062] refer to Figure 4 In each bitline structure 240, the area of ​​the cross-section perpendicular to the first direction (i.e., the z-direction) (i.e., the cross-section formed by planes parallel to the xy-plane) can be varied along the first direction (i.e., the z-direction). For example, the area of ​​the lower cross-section of each bitline structure 240 can be smaller than the area of ​​the upper cross-section of each bitline structure 240.

[0063] In one embodiment, each of the first to fourth word line structures 222, 224, 226, and 228 may have a different width in the third direction (i.e., the x-direction). In one embodiment, the width in the third direction may decrease sequentially from the first word line structure 222 to the fourth word line structure 228. For example, the width W1 of the first word line structure 222 in the third direction may be the largest, while the width W2 of the fourth word line structure 228 in the third direction may be the smallest.

[0064] In one embodiment, the distance between the first word line structure 222 and the adjacent bit line structure 240 along a third direction (i.e., the x-direction) can vary between a minimum distance d1 and a maximum distance d2. The minimum distance d1 can be obtained at the interface between the first word line structure 222 and the first interlayer insulating layer 132. The maximum distance d2 can be obtained at the interface between the first word line structure 222 and the substrate insulating layer 110.

[0065] Furthermore, the distance in the third direction (i.e., the x-direction) between each of the second to fourth word line structures 224, 226, and 228 and its adjacent bit line structure 240 can be substantially the same as the distance in the third direction (i.e., the x-direction) between the first word line structure 222 and its adjacent bit line structure 240. For example, the distance in the third direction (i.e., the x-direction) between each of the second to fourth word line structures 224, 226, and 228 and its adjacent bit line structure 240 can vary between a minimum distance d1 and a maximum distance d2. The minimum distance d1 can be obtained at the upper surface of each of the second to fourth word line structures 224, 226, and 228, respectively, and the maximum distance d2 can be obtained from the lower surface of each of the second to fourth word line structures 224, 226, and 228, respectively.

[0066] refer to Figure 4 Switch layer 250 may be disposed between each of the first to fourth word line structures 222, 224, 226, and 228 and bit line structure 240. Each switch layer 250 may have a thickness varying from a minimum thickness d1 to a maximum thickness d2 measured from the side surface of each of the first to fourth word line structures 222, 224, 226, and 228 in a third direction (i.e., the x-direction). Switch layer 250 may be constructed using the method described above. Figure 3A , Figure 3B and Figure 3C The described switch layer 150 is made of essentially the same material.

[0067] Figures 5A to 11A This is a plan view schematically illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 5B to 11B It is along Figures 5A to 11A A cross-sectional view of a semiconductor device taken along line A-A'. Figures 8C to 11C It is along Figures 8A to 11A A cross-sectional view of a semiconductor device taken along line B-B'.

[0068] refer to Figure 5A and 5B Substrate 301 can be provided. Substrate 301 can be referenced above. Figure 3A , Figure 3B and Figure 3C The substrate 101 described is substantially the same.

[0069] Next, a substrate insulating layer 310 can be formed on the substrate 301. The substrate insulating layer 310 can be formed using, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.

[0070] Although not illustrated, an integrated circuit can be formed between substrate 301 and substrate insulating layer 310. For example, the integrated circuit may include active devices such as transistors, passive devices such as resistors and capacitors, or a combination of active and passive devices. The integrated circuit may include at least one circuit pattern layer and at least one insulating layer for insulating the at least one circuit pattern layer.

[0071] Next, a conductive material layer can be formed on the substrate insulating layer 310. The conductive material layer can be patterned to form a plurality of first word line structures 322 extending along a first lateral direction (i.e., the y-direction) on the substrate insulating layer 310. For example, the conductive material can include doped semiconductors, metals, conductive metal nitrides, conductive metal carbides, conductive metal silicides, or conductive metal oxides. For example, the conductive material can include silicon (Si), gallium arsenide (GaAs), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more thereof, doped with n-type or p-type dopants. For example, methods for forming the conductive material layer can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. Photolithography and etching methods can be used as methods for patterning the conductive material layer.

[0072] refer to Figure 5A and Figure 5B Each of the plurality of first word line structures 322 can be configured to be spaced apart from each other in a second lateral direction (i.e., the x-direction) perpendicular to the first lateral direction. A groove 3001 can be formed in the space between the plurality of first word line structures 322 in the second lateral direction (i.e., the x-direction). The groove 3001 can extend in the first lateral direction (i.e., the y-direction).

[0073] refer to Figure 6A and Figure 6B A switching material layer can be formed on top of the substrate insulating layer 310 using a sputtering method to fill the gap. Figure 5A and Figure 5BThe trench 3001. In this case, a switching material layer can also be formed on the plurality of first word line structures 322 outside the trench 3001. Subsequently, the switching material layer can be planarized on the substrate insulating layer 310 to form a first switching functional layer 352. The first switching functional layer 352 can be positioned at the same level as the plurality of first word line structures 322 on the substrate insulating layer 310. That is, the first switching functional layer 352 can have the same thickness as each of the plurality of first word line structures 322 on the substrate insulating layer 310.

[0074] The switching material layer may be formed of or comprise a switching material, such as a chalcogenide-based material. For example, the switching material layer may be formed from or include the following: germanium-tellurium (Ge-Te), germanium-selenium-tellurium (Ge-Se-Te), indium-selenium (In-Se), antimony-tellurium (Sb-Te), arsenic-tellurium (As-Te), aluminum-tellurium (Al-Te), germanium-antimony-tellurium (Ge-Sb-Te), tellurium-germanium-arsenic (Te-Ge-As), indium-antimony-tellurium (In-Sb-Te), tellurium-tin-selenium (Te-Sn-Se), germanium-selenium-gallium (Ge-Se-Ga), bismuth-selenium-antimony (Bi-Se-Sb), gallium-selenium-tellurium (Ga-Se-Te), tin-antimony-tellurium (Sn-Sb-Te), tellurium-germanium-antimony-sulfur (Te-Ge-Sb-S), tellurium-germanium-tin-oxygen (Te-Ge-Sn-O), tellurium- Germanium-tin-gold (Te-Ge-Sn-Au), palladium-tellurium-germanium-tin (Pd-Te-Ge-Sn), indium-selenium-titanium-cobalt (In-Se-Ti-Co), germanium-antimony-tellurium-palladium (Ge-Sb-Te-Pd), germanium-antimony-tellurium-cobalt (Ge-Sb-Te-Co), antimony-tellurium-bismuth-selenium (Sb-Te-Bi-Se), silver-indium-antimony-tellurium (Ag-In-Sb-Te), germanium-antimony-selenium-tellurium (Ge-Sb-Se-Te), germanium-tin-antimony-tellurium (Ge-Sn-Sb-Te), germanium-tellurium-tin-nickel (Ge-Te-Sn-Ni), germanium-tellurium-tin-palladium (Ge-Te-Sn-Pd), germanium-tellurium-tin-platinum (Ge-Te-Sn-Pt), or combinations of two or more thereof.

[0075] For example, the switching material layer can be formed by a sputtering method. In one embodiment of this disclosure, the sputtering method can be performed by a process including preparing at least one metal target made of a metal constituting the switching material layer, and a process of bombarding the at least one metal target with a plasma of an inert gas. The switching material layer can be formed by depositing metal escaping from the at least one metal target onto a substrate through the impact of the at least one metal target. The inert gas may include helium (He), nitrogen (N2), argon (Ar), etc.

[0076] In one embodiment, at least one metal target may be made of a single metal constituting the switching material layer. The number of at least one metal target may correspond to the number of metals constituting the switching material layer. In another embodiment, at least one metal target may be made of an alloy of multiple metals constituting the switching material layer.

[0077] In some embodiments, a reactive gas may be additionally provided during the sputtering process to form the switching material layer. For example, the reactive gas may include oxygen (O2).

[0078] For example, the switching material layer can be planarized by applying a chemical mechanical polishing process or an etching process to form the first switching functional layer 352. As a result of planarization, such as... Figure 6A and Figure 6B As shown, the upper surface of the first switch function layer 352 and the upper surface of the multiple word line structures 322 can be positioned on the same plane.

[0079] refer to Figure 7A and Figure 7B The first interlayer insulating layer 332 can be formed on the plurality of word line structures 322 and the first switching function layer 352. The first interlayer insulating layer 332 can be formed of or include an insulating material. For example, the insulating material may include oxides, nitrides, oxynitrides, or combinations of two or more thereof. For example, the first interlayer insulating layer 332 can be formed using physical vapor deposition, chemical vapor deposition, or the like.

[0080] Next, a plurality of second word line structures 324 extending in the first lateral direction (i.e., the y-direction) can be formed on the first interlayer insulating layer 332. The plurality of second word line structures 324 can be formed and arranged to overlap with the plurality of first word line structures 322 in the vertical direction (i.e., the z-direction).

[0081] The plurality of second word line structures 324 may have substantially the same configuration as the plurality of first word line structures 322. Furthermore, the method of forming the plurality of second word line structures 324 may be substantially the same as the method of forming the plurality of first word line structures 322.

[0082] Next, a second switching function layer 354 can be formed among the plurality of second word line structures 324. The second switching function layer 354 can have a configuration substantially the same as the first switching function layer 352. Furthermore, the method of forming the second switching function layer 354 can be substantially the same as the method of forming the first switching function layer 352.

[0083] Next, a second interlayer insulation layer 334, a plurality of third word line structures 326 and a third switch function layer 356, a third interlayer insulation layer 336, a plurality of fourth word line structures 328 and a fourth switch function layer 358, and a fourth interlayer insulation layer 338 can be sequentially formed above the plurality of second word line structures 324 and the second switch function layer 354.

[0084] The configuration and formation methods of the plurality of third word line structures 326 and the plurality of fourth word line structures 328 can be substantially the same as the configuration and formation methods of the plurality of first word line structures 322 and the plurality of second word line structures 324. The configuration and formation methods of the third switch functional layer 356 and the fourth switch functional layer 358 can be substantially the same as the configuration and formation methods of the first switch functional layer 352 and the second switch functional layer 354. The configuration and formation methods of the second interlayer insulating layer 334, the third interlayer insulating layer 336 and the fourth interlayer insulating layer 338 can be substantially the same as the configuration and formation methods of the first interlayer insulating layer 332.

[0085] According to one embodiment of this disclosure, as described above, chemical etching of the switching material layers 352, 354, 356, and 358 can be effectively eliminated during the formation of the first to fourth switching functional layers 352, 354, 356, and 358 from the switching material layer. Therefore, it is possible to prevent damage to the first to fourth switching functional layers 352, 354, 356, and 358 from the chemical etching process. For example, damage from the chemical etching process can refer to the loss of some metal atoms constituting the first to fourth switching functional layers 352, 354, 356, and 358. When the switching material layer contains different types of metal atoms, different types of metal atoms may be lost in different quantities, depending on the etch selectivity of the etchant during the chemical etching of the switching material layer. Therefore, after the chemical etching process is completed, the stoichiometry among the metal atoms constituting the first to fourth switching functional layers 352, 354, 356, and 358 may change, and thus the physical properties of the first to fourth switching functional layers 352, 354, 356, and 358 may change. Conversely, to prevent the loss of metal atoms, according to one of the embodiments of this disclosure that effectively excludes chemical etching, undesirable changes in physical properties can be prevented when the first to fourth switching functional layers 352, 354, 356, and 358 are formed from switching material layers. Therefore, the electrical reliability of the first to fourth switching functional layers 352, 354, 356, and 358 can be improved. As an example of improvement, the interface characteristics between the plurality of first to fourth word line structures 322, 324, 326, and 328 and the first to fourth switching functional layers 352, 354, 356, and 358 can be stabilized.

[0086] refer to Figure 8A , Figure 8B and Figure 8CThe first to fourth interlayer insulating layers 332, 334, 336, and 338, as well as the first to fourth switching functional layers 352, 354, 356, and 358, can be selectively etched to form unit insulating contact holes 3002 that expose the substrate insulating layer 310. The side surface of each unit insulating contact hole 3002 can have an inclination angle β1, which can be substantially perpendicular to the surface of the substrate insulating layer 310. The unit insulating contact holes 3002 can be formed by applying photolithography and anisotropic etching.

[0087] The unit insulating contact hole 3002 can expose the first to fourth switch functional layers 352, 354, 356, and 358, as well as the first to fourth interlayer insulating layers 332, 334, 336, and 338, in the first lateral direction (i.e., the y-direction). The unit insulating contact hole 3002 can also expose the first to fourth word line structures 322, 324, 326, and 328, as well as the first to fourth interlayer insulating layers 332, 334, 336, and 338, in the second lateral direction (i.e., the x-direction).

[0088] refer to Figure 9A , Figure 9B and Figure 9C The unit insulating contact hole 3002 can be filled with an insulating material to form a unit insulating structure 370. For example, the insulating material may include oxides, nitrides, oxynitrides, or combinations of two or more thereof. For example, the unit insulating structure 370 can be formed by applying physical vapor deposition or chemical vapor deposition.

[0089] refer to Figure 10A , Figure 10B and Figure 10C The first to fourth interlayer insulating layers 332, 334, 336 and 338, and the first to fourth switching functional layers can be selectively etched. Figure 9B (352, 354, 356, and 358) and a substrate insulating layer 310 to form bit line contact holes 3003 exposing the substrate 301. Selective etching can be performed to expose the first to fourth switching functional layers ( Figure 9B Each of 352, 354, 356, and 358 has residual thickness on the side surfaces of the plurality of first to fourth word line structures 322, 324, 326, and 328, respectively. That is, after the selective etching that forms the bit line contact hole 3003, the first to fourth switch functional layers ( Figure 9BSome portions of (352, 354, 356, and 358) can be retained on the side surfaces of the multiple first to fourth word line structures 322, 324, 326, and 328. Therefore, the first to fourth switch layers 352a, 354a, 356a, and 358a can be formed from the remaining first to fourth switch functional layers after selective etching. The thickness ts of each of the first to fourth switch layers 352a, 354a, 356a, and 358a in the second lateral direction (i.e., the x-direction) can be substantially the same.

[0090] refer to Figure 10B Each side surface of the bit line contact hole 3003 may have an inclination angle β2, which may be perpendicular to the upper surface of the substrate 301. The bit line contact hole 3003 may be formed by applying photolithography and anisotropic etching.

[0091] In some embodiments, when the bit line contact hole 3003 is formed by anisotropic etching, a carbon (C)-containing polymer layer (not shown) can be formed on the surfaces S352, S354, S356, and S358 (which are exposed along the side surfaces of the bit line contact hole 3003) of the first to fourth switching layers 352a, 354a, 356a, and 358a. In one embodiment, anisotropic etching can be performed using a plasma dry etching method. In this case, a reactive gas including chlorine-based and hydrocarbon-based gases can be applied. This reactive gas can react with the first to fourth switching functional layers containing chalcogenide-based materials ( Figure 9B Reactions 352, 354, 356, and 358 are used to etch the first through fourth switch functional layers. Figure 9B (352, 354, 356, and 358). Simultaneously, switching functions can be implemented in the first to fourth switching layers ( Figure 9B A polymer layer is formed on the side surfaces of (352, 354, 356, and 358), and the polymer layer can be retained after etching is completed. This polymer layer can have the characteristics described in the reference above. Figure 3A , Figure 3B and Figure 3C The constant resistance described.

[0092] The bit line contact hole 3003 can expose the side surface of the unit insulating layer 370 in the first lateral direction (i.e., the y-direction). The bit line contact hole 3003 can expose the side surfaces of the first to fourth switching layers 352a, 354a, 356a and 358a, the side surfaces of the first to fourth interlayer insulating layers 332, 334, 336 and 338, and the side surface of the base insulating layer 310.

[0093] refer to Figure 11A , Figure 11B and Figure 11CConductive material can be provided in the bit line contact hole 3003 to form the bit line structure 380. For example, the conductive material may include doped semiconductors, metals, conductive metal nitrides, conductive metal carbides, conductive metal silicides, or conductive metal oxides. For example, the conductive material may include silicon (Si), gallium arsenide (GaAs), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations thereof, doped with n-type or p-type dopants. For example, the bit line structure 380 can be formed by applying physical vapor deposition, chemical vapor deposition, or the like.

[0094] By performing the above process, a semiconductor device according to embodiments of this disclosure can be manufactured.

[0095] In some embodiments, the side surface of each bit line contact hole 3003 may not have an inclination angle perpendicular to the upper surface of the substrate 301. In this case, the above-described approach can be performed. Figure 11A , Figure 11B and Figure 11C The described process forms the bit line structure 380. In this case, the shape of the bit line structure 380 can be similar to that described above. Figure 4 The shape of the bit line structure 240 of the described semiconductor device 1b is substantially the same.

[0096] In some embodiments, when performing the above reference Figure 11A , 11B Following the process described in 11C for forming the bit line structure 380, the above-mentioned reference can be executed. Figure 8A , 8B The process for forming the unit insulating contact hole 3002 is described in 8C. In this case, the resulting unit insulating contact hole 3002 can expose the first to fourth switch layers 352a, 354a, 356a and 358a, the first to fourth interlayer insulating layers 332, 334, 336 and 338, and the bit line structure 380 in the first lateral direction (i.e., the y-direction), and can expose a plurality of first to fourth word line structures 322, 324, 326 and 328, and the first to fourth interlayer insulating layers 332, 334, 336 and 338 in the second lateral direction (i.e., the x-direction). Thereafter, the unit insulating contact hole 3002 can be filled with insulating material to form the unit insulating structure 370.

[0097] Embodiments of this disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of this disclosure and the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A plurality of word line structures are disposed above the substrate and spaced apart from each other in a first direction perpendicular to the surface of the substrate, each of the plurality of word line structures extending in a second direction parallel to the surface of the substrate; A switching layer is disposed above the substrate to contact the side surfaces of the plurality of word line structures; Bit line structures are disposed above the substrate to extend in the first direction and contact the surface of the switching layer, and A carbon-containing resistive layer is disposed at the interface between the switching layer and the bit line structure. The switching layer is configured to perform threshold switching operations and has a variable, programmable threshold voltage.

2. The semiconductor device of claim 1, wherein, The switching layer comprises a chalcogenide-based material.

3. The semiconductor device of claim 2, wherein, The switching layer includes one selected from the following: germanium-tellurium (Ge-Te), germanium-selenium-tellurium (Ge-Se-Te), indium-selenium (In-Se), antimony-tellurium (Sb-Te), arsenic-tellurium (As-Te), aluminum-tellurium (Al-Te), germanium-antimony-tellurium (Ge-Sb-Te), tellurium-germanium-arsenic (Te- Ge-As, Indium-Antimony-Tellul (In-Sb-Te), Tellurium-Tinum-Selenium (Te-Sn-Se), Germanium-Selenium-Gallium (Ge-Se-Ga), Bismuth-Selenium-Antimony (Bi-Se-Sb), Gallium-Selenium-Tellul (Ga-Se-Te), Tin-Antimony-Tellul (Sn-Sb-Te), Tellurium-Antimony-Sulfur (Te-Ge-Sb-S), Tellurium-Germanium-Tinum-O (Te-Ge-Sn-O), Tellurium-Germanium-Tinum-Gold (Te-Ge-Sn-Au), Palladium-Tellurium-Germanium-Tin (Pd-Te-Ge-Sn), Indium-Selenium-Titanium-Cobalt (In-S) Germanium-antimony-tellurium-palladium (Ge-Sb-Te-Pd), Germanium-antimony-tellurium-cobalt (Ge-Sb-Te-Co), antimony-tellurium-bismuth-selenium (Sb-Te-Bi-Se), silver-indium-antimony-tellurium (Ag-In-Sb-Te), Germanium-antimony-selenium-tellurium (Ge-Sb-Se-Te), Germanium-tin-antimony-tellurium (Ge-Sn-Sb-Te), Germanium-tellurium-tin-nickel (Ge-Te-Sn-Ni), Germanium-tellurium-tin-palladium (Ge-Te-Sn-Pd), and Germanium-tellurium-tin-platinum (Ge-Te-Sn-Pt).

4. The semiconductor device of claim 1, wherein, The switching layer is configured to present different threshold voltages based on a first programming voltage and a second programming voltage with different polarities.

5. The semiconductor device of claim 1, wherein, The area of ​​each bitline structure taken along a cross section perpendicular to the first direction varies along the first direction.

6. The semiconductor device of claim 5, wherein, The area of ​​the lower cross section of each bitline structure is smaller than the area of ​​the upper cross section of each bitline structure.

7. The semiconductor device of claim 1, wherein, The width of the lowest word line structure in the third direction is greater than the width of the highest word line structure, wherein the third direction is parallel to the surface of the substrate and perpendicular to the second direction.

8. A method for manufacturing a semiconductor device, the method comprising: Provide a substrate with a base insulating layer; A plurality of first word line structures extending in a first lateral direction parallel to the surface of the substrate and a first switching function layer disposed between the plurality of first word line structures are formed above the substrate insulating layer. The plurality of first word line structures are spaced apart from each other in a second lateral direction, which is parallel to the surface of the substrate and perpendicular to the first lateral direction. A first interlayer insulating layer is formed on the plurality of first word line structures and the first switch function layer; A plurality of second word line structures extending in the first lateral direction are formed on the first interlayer insulating layer, and a second switching function layer is disposed between the plurality of second word line structures, wherein the plurality of second word line structures are arranged to overlap with the plurality of first word line structures respectively. Selective etching is performed on the second switching functional layer, the first interlayer insulating layer, the first switching functional layer, and the substrate insulating layer to form bit line contact holes that expose the substrate, and to leave some portions of the first switching functional layer and the second switching functional layer on the side surfaces of the plurality of first word line structures and the plurality of second word line structures. and Conductive material is provided in the bit line contact hole to form a bit line structure.

9. The method of claim 8, wherein, The step of forming the bit line contact holes includes: forming the bit line contact holes arranged at intervals from each other along the first transverse direction.

10. The method of claim 8, further comprising: The second switching functional layer, the first interlayer insulating layer, and the first switching functional layer are selectively etched to form unit insulating contact holes that expose the substrate insulating layer; and The unit insulating contact holes are filled with insulating material to form a unit insulating structure.

11. The method of claim 10, wherein, The step of forming the cell insulating contact hole is performed before forming the bit line contact hole, and The unit insulating contact hole is formed to expose the first switch function layer, the second switch function layer, and the first interlayer insulating layer in the first lateral direction, and to expose the plurality of first word line structures, the plurality of second word line structures, and the first interlayer insulating layer in the second lateral direction.

12. The method of claim 10, wherein, After forming the bit line structure, the step of forming the unit insulating contact hole is performed, and The unit insulating contact hole is formed to expose the first switch function layer and the second switch function layer, the first interlayer insulating layer and the bit line structure in the first lateral direction, and to expose the plurality of first word line structures and the plurality of second word line structures and the first interlayer insulating layer in the second lateral direction.

13. The method of claim 8, wherein the step of forming the plurality of first word line structures and the first switch function layer comprises: A conductive material layer is formed on the substrate insulating layer; The conductive material layer is patterned to form the plurality of first word line structures extending along the first lateral direction on the substrate insulating layer; A switching material layer is formed by sputtering to fill the space between the plurality of first word line structures on the substrate insulating layer, the switching material layer comprising a chalcogenide-based material; and The switching material layer above the substrate insulating layer is planarized to form the first switching functional layer at the same level as the plurality of first word line structures.

14. The method of claim 8, wherein the step of forming the plurality of second word line structures and the second switch function layer comprises: A conductive material layer is formed on the first interlayer insulating layer; The conductive material layer is patterned to form the plurality of second word line structures extending along the first lateral direction on the first interlayer insulating layer; and A switching material layer is formed on the first interlayer insulating layer by sputtering to fill the space between the plurality of second word line structures, the switching material layer comprising a chalcogenide-based material; as well as The switching material layer on the first interlayer insulation layer is planarized to form a second switching functional layer at the same level as the plurality of second word line structures.

15. The method of claim 8, wherein, The step of forming the bit line contact hole further includes: forming a first switch layer and a second switch layer from portions of the first switch functional layer and the second switch functional layer that are retained on the sides of the plurality of first word line structures and the plurality of second word line structures after selective etching.

16. The method of claim 15, wherein, When forming the bit line contact hole, the selective etching is performed such that the thicknesses of the first switch layer and the second switch layer are substantially the same in the second lateral direction.

17. The method of claim 8, wherein, The step of forming the bit line contact hole includes: forming a polymer layer containing carbon C on the surfaces of the first switch function layer and the second switch function layer exposed along the side surface of the bit line contact hole.

18. The method of claim 8, wherein, The step of forming the bit line contact hole includes: forming the bit line contact hole such that the side surface of each bit line contact hole forms an acute angle relative to the surface of the substrate.

19. The method of claim 8, further comprising: After forming the plurality of second word line structures and the second switch material layer, a second interlayer insulating layer is formed on the plurality of second word line structures and the second switch material layer. The step of forming the bit line contact hole further includes selectively etching the second interlayer insulating layer.

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