Apparatus and method for changing output pwm control of an inverter

Abstract

The present disclosure provides devices and methods for modified digital output pulse width modulation, SPWM, e.g., sinusoidal pulse width modulation, SPWM, control of inverters comprising at least a first switch (S3) and a second switch (S1). The method comprises generating a first binary control signal (PWM3A) at a system modulation frequency; generating a second binary control signal (PWM1A) at a higher carrier frequency that is M times higher; wherein generating the second binary control signal comprises providing a periodic counter with a higher reset frequency that is K times higher; calculating M off instants; for each off instant, determining a corresponding off counter value and a corresponding counter sequence value; storing each off counter value in a respective memory location corresponding to a respective counter sequence and storing dummy values in the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register (620).

Description

Technical Field

[0001] This disclosure relates to apparatus and methods for controlling inverters. Specifically, this disclosure relates to pulse width modulation (PWM) control for such inverters that can be used in applications such as wireless charging. Background Technology

[0002] An inverter converts DC power to AC power. Its applications are wide-ranging. Controllers used for such inverters typically employ pulse width modulation (PWM) that operates at a frequency much higher than the output frequency. A variant of PWM is the so-called sinusoidal PWM (SPWM), where the pulse width changes sinusoidally over the period of the output. The pulse width may also need to be adjusted "in real time" as the load on the inductor changes. Of course, the AC power may not need to be purely sinusoidal; it can be horseshoe-shaped, a low-harmonic approximation of sinusoidal AC where the voltage peaks are smoothly inverted, or trapezoidal, a linear approximation of sinusoidal AC. The following description will refer to SPWM, but this disclosure extends to other waveforms of varying output PWM.

[0003] In some applications, the AC frequency may be relatively high—in this context, it could be from hundreds of kHz to several MHz. An example of such an application is wireless charging, where AC power is typically transferred from the primary coil on the charger side to the secondary coil on the charging side via inductive coupling. In such wireless charging applications, the frequency of the AC power, also referred to herein as the system modulation frequency, may be as high as 1 or 2 MHz.

[0004] High frequencies pose challenges for SPWM control, especially for digital SPWM control. Summary of the Invention

[0005] According to a first aspect of this disclosure, a method is provided for providing digital output pulse width modulation (PWM) control of an inverter comprising at least a first switch and a second switch, the method comprising: generating a first binary control signal at a system modulation frequency; generating a second binary control signal having a carrier frequency that is an integer multiple of the system modulation frequency and having a periodically changing duty cycle; wherein generating the second binary control signal comprises: providing a periodic counter with a reset frequency that is an integer multiple of the modulation frequency (K); calculating a plurality of, i.e., M, disconnection times of the second control signal in a first module; for each of the disconnection times, determining a corresponding disconnection counter value and a corresponding counter sequence value; providing K memory locations in a second module; storing each disconnection counter value in a corresponding memory location corresponding to the corresponding counter sequence; storing a virtual value in each of the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register; the method further comprising, for half a period corresponding to the system modulation frequency: providing the first binary control signal to the first switch; and providing the second binary control signal to the second switch by reading the at least one PWM value register.

[0006] This could potentially reduce the processing time or effort required to determine the correct moment to disconnect one or more power switches controlling the inverter.

[0007] In one or more embodiments, providing at least K memory locations includes providing 2K memory locations; and the method further includes: calculating a plurality of, i.e., M, turn-on times for the second control signal in the first module; providing an additional K memory locations in the second module; for each of the turn-on times, determining a corresponding turn-on counter value and a corresponding counter sequence value, and storing each turn-on counter value in a corresponding memory location corresponding to the corresponding counter sequence. This may reduce the processing time or effort required to determine the correct time to turn on one or more power switches of the control inverter.

[0008] In one or more embodiments, the K memory locations are part of a Direct Memory Access (DMA) module, or the 2K memory locations are part of a DMA module. Using a DMA module may further improve processing efficiency.

[0009] In one or more embodiments, the altered output PWM is a sinusoidal PWM. This may be particularly applicable because most AC waveforms are sinusoidal or nearly sinusoidal. However, in other embodiments, the altered output of the AC waveform may be different, for example, but not limited to, trapezoidal or triangular.

[0010] In one or more embodiments, the integer K is a power of two, 2^N. This can be particularly simple because, in such embodiments, the mapping of M turn-on times and M turn-off times can correspond one-to-one with K.

[0011] In one or more embodiments, the method further includes: generating a third binary control signal and providing it to a third switch; and generating a fourth binary control signal and providing it to a fourth switch, wherein the third binary control signal is complementary to the first binary control signal, and the fourth binary control signal is complementary to the second binary control signal. This facilitates one implementation of a unipolar sinusoidal SPWM.

[0012] In one or more embodiments, the method further includes, for the other half of the period corresponding to the system modulation frequency: providing the first binary control signal to a first switch; providing the third binary signal to a fourth switch; rapidly providing the second binary control signal to a second switch by reading the at least one PWM value register; and providing the fourth binary signal to the third switch. This facilitates another implementation of unipolar sinusoidal SPWM.

[0013] In one or more embodiments, periodically transferring the contents of the memory locations to at least one PWM value register includes transferring the contents of four memory locations to a corresponding PWM value register of four PWM value registers, and subsequently transferring the contents of four other memory locations to corresponding PWM value registers of the four PWM value registers. Such steps enable efficient use of DMA memory transfers.

[0014] In one or more embodiments, the step of determining the corresponding counter value and the corresponding counter sequence value for each of the switching moments is performed at least in part concurrently with the step of transferring the contents of the four memory locations to a corresponding PWM value register in one of the four PWM value registers.

[0015] In one or more embodiments, the method may further include changing the frequency of the modulation frequency. Changing the frequency of the modulation frequency enables Frequency Shift Keying (FSK) communication between two devices, particularly in applications where AC power is used for wireless charging, such as in automobiles or communication devices, and communication is required between the charger and the device being charged. Embodiments of this disclosure can conveniently achieve this objective. In one or more embodiments, the method may further include changing the frequency of the modulation frequency by frequency shift keying (FSK) encoding the data by changing the maximum counter value at which the counter is reset.

[0016] According to a second aspect of this disclosure, a controller for an inverter is provided, the inverter including a first switch and a second switch and configured to operate under altered output pulse width modulation by means of a first binary control signal at a system modulation frequency and a second binary control signal with a carrier frequency that is an integer multiple of the system modulation frequency and periodically changes with the duty cycle of the second switch; the controller includes: a counter module configured to provide a periodic counter with a reset frequency that is a multiple of the modulation frequency; a first module configured to: calculate a plurality of, i.e., M, disconnection times of the second control signal, and for each of the disconnection times determine a corresponding counter value and a corresponding counter sequence value; a second module including K memory locations and arranged to store each counter value in a corresponding memory location corresponding to a corresponding counter sequence and to store a dummy value in each of the remaining memory locations; at least one PWM value register arranged to periodically receive the contents of the memory locations; and an output terminal arranged to be connected to the first switch and to control the switch by data in the at least one PWM value register.

[0017] In one or more embodiments, the first module is further configured to calculate a plurality of additional K on-times of the second control signal, and for each of the on-times, determine a corresponding on-counter value and a corresponding counter sequence value, and the second module includes an additional K memory locations and is arranged to store each counter value in a corresponding memory location corresponding to the corresponding counter sequence, and to store a virtual value in each of the remaining memory locations of the additional K memory locations.

[0018] In one or more embodiments, the second module is a direct memory access (DMA) module. The integer K can be a power of two, 2^N.

[0019] These and other aspects of the invention will be made clear and illustrated by reference to the embodiments described below. Attached Figure Description

[0020] The embodiments will be described by way of example only with reference to the drawings, in which:

[0021] Figure 1 The wireless charging circuit and controller are shown schematically.

[0022] Figure 2 For example, Figure 1 The basic PWM control operation of the inverter in the circuit;

[0023] Figure 3 For example, Figure 1 SPWM control of the inverter in the circuit;

[0024] Figure 4 Showing for example Figure 1 An alternative configuration for SPWM control of the inverter in the circuit;

[0025] Figure 5 A method for providing SPWM control according to one or more embodiments is illustrated schematically;

[0026] Figure 6 This illustrates the DMA transfer between a memory block and a set of PWM value registers;

[0027] Figure 7 This illustrates another variation of DMA transfer between a memory block and a set of PWM value registers;

[0028] Figure 8 A flowchart illustrating the method for determining the second binary control signal data is shown, and

[0029] Figure 9 A flowchart of one or more methods according to this disclosure is shown.

[0030] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience, the relative dimensions and proportions of the parts in these figures have been shown by enlarging or reducing their size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation

[0031] Figure 1 A wireless charging circuit and controller are schematically shown. Circuit 100 includes a DC power supply 110, an inverter 120, a PI filter 150, and a resonant circuit 130. The inverter includes four switches S1 122, S2 134, S3 126, and S4 128 arranged in a full-bridge configuration. The PI filter includes two induction coils L1 152 and L2 154 and a capacitor Cpar 138. The two input connections on the input side of the full-bridge are connected across the DC power supply 110; the two output connections on the output side of the full-bridge are each connected to each of the two induction coils L1 and L2. One side of the DC power supply 110 is connected to ground 156 and can therefore be referred to as the "low side". The other side can be referred to as the "high side".

[0032] Inverter 120 is connected to drive resonant circuit 130 via L1 or L2, depending on the switching state of the inverter. Resonant circuit 130 includes an inductor in the form of a charging coil Lp 132, which is on or typically embedded in charging plate 134. The resonant circuit is completed by series capacitor Cser 136. Each of the inductors and capacitors mentioned above takes the form of one or more individual inductors or capacitors.

[0033] Switches S1 to S4 are typically transistors, such as FETs. The switches are controlled, for example, by controlling the gate of each FET using four control signals from controller 140. Two of these, PWM1A and PWM3A, control the high-side switch; the other two, PWM1B and PWM3B, control the low-side switch.

[0034] For example Figure 1 The normal PWM control of the inductor shown in the figure is in Figure 2 As shown in the diagram. To ensure that the DC power supply is never short-circuited to ground, under any circumstances, only one of S1 and S2, and only one of S3 and S4, can be "on" or conductive. Therefore, the control signal PWM1A 212 for switch S1 is arranged to be complementary to the control signal PWM1B 214 for switch S2. That is, whenever S2 is not conductive, S1 is conductive, and vice versa. Similarly, the control signal PWM3A 216 for switch S1 is arranged to be complementary to the control signal PWM3B 218 for switch S2. That is, whenever S2 is not conductive, S1 is conductive, and vice versa.

[0035] The controller arranges the switches to switch at a period T (and therefore at a frequency of 1 / T); for the first part of the switching cycle (or “pulse”), S1 is not conductive and S2 is conductive; for the remainder of the switching cycle, S1 is conductive and S2 is not conductive. PWM control is typically achieved by adjusting the width of the first part or pulse while keeping the switching cycle frequency or period constant. Of course, given a fixed frequency of S2 and a defined “on time”, the “pulse” in S2 does not necessarily have to be at the beginning of each cycle, but this is commonly used for conventional PWM control. Alternatively, the “pulse” could be at the end of the cycle. It could even occur during the middle of the cycle, but this would require more complex control and is therefore not typically used in conventional PWM. However, for sinusoidal PWM control, such as that discussed below, the “pulse” in S2 is not always at the beginning of the cycle in order to maintain a longer time scale (e.g., the “modulation period,” as will be discussed below in relation to the modulation frequency and referenced). Figure 3 and 4 The symmetry within (which is obvious from the discussion) is evident.

[0036] As long as the DC power supply 110 supplies a fixed voltage, the power supplied to the output depends on the pulse width. Therefore, by changing the width of one or more pulses in a sinusoidal manner, it is possible to provide an AC output. This is in Figure 3 As shown in the image.

[0037] Figure 3 This diagram illustrates switch control for providing AC output via S-PWM. Specifically, it shows control of switches S1 through S4 to provide a sinusoidal AC output 310, also known as a modulated wave output. As shown, the modulation frequency of the output is 1 / T. In this control, switches S1 and S2 provide a so-called "high-frequency" half-bridge, while switches S3 and S4 provide a "low-frequency" half-bridge.

[0038] First, consider the high-frequency half-bridge. This half-bridge uses fixed-frequency PWM control switching – in the example shown, this frequency is 10 times the modulation frequency, that is, the frequency is 10 / T. The PWM frequency is sometimes also called the "carrier frequency," and this is achieved through a triangular carrier 320. Figure 3 It is shown schematically in the diagram.

[0039] It should be noted that the ratio between the modulation frequency and the carrier frequency is relatively small compared to inverters used in other applications. Typically, inverters providing a master frequency output (e.g., 50Hz or 60Hz) operate with a carrier frequency in the range of 10kHz to several hundred kHz to provide the master frequency output – the ratio is thus typically 200 to 2000. In contrast, in the example shown (which is typical for inverters providing a modulation frequency of 100 to 200kHz), the carrier frequency can be 1 to 2MHz, and therefore only five pulses of PWM control exist for each half-cycle of the modulation frequency.

[0040] As shown in the figure, the power supply to the output (and therefore the height of the modulated wave) is proportional to the width of the conductive pulse in S1. Therefore, the pulse width can be calculated from the sinusoidal modulation curve (based on sin(2πt / T) at time t).

[0041] However, Figure 3 The diagram illustrates a computationally simple method. Triangular carrier overlap, meaning that compared to the modulation curve: PWM1A is configured to change its state whenever the carrier crosses the position curve significantly (i.e., switch S1 switches between conductive and non-conductive states). Furthermore, because another switch (S2) in the half-bridge operates complementaryly to S1 under the control of PWM1B, this other switch switches between non-conductive and conductive states. As a result, the voltage on the supply side of inductor L2 switches according to the SPWM switching to drive the resonant circuit of the wireless charger. These switching control signals are shown in the two middle curves 360°.

[0042] Figure 3 The diagram also shows the control signal PWM3A for the third switch S3 and PWM3B for the fourth switch S4 at the bottom of the two curves 370. These two switches form a second half-bridge, operating at 50% PWM at a relatively low frequency on the modulation curve. The relatively low switching frequency has the effect of periodically switching the voltage on the input side of inductor L1 between the supply voltage and ground, and achieves negative switching on the negative side of the AC curve (that is, in the third quadrant 340 and the fourth quadrant 350).

[0043] Because at any given time, SPWM is applied to only one half-bridge (S1 and S2) and not the other half-bridge (S3 and S4), this type of operation is called unipolar PWM operation.

[0044] Figure 4 This illustrates an alternative drive arrangement for supplying unipolar SPWM. This configuration is similar to... Figure 3 The configuration shown is roughly similar; however, instead of having "relatively high frequency" bridges S1 and S2 and "relatively low frequency" bridges S3 and S4, in this configuration, switches S1 and S2 are considered the "left bridge" and switches S3 and S4 are considered the "right bridge." In this configuration, left bridges S1 and S2 operate under SPWM control for the first two quadrants of the modulation curve, as shown by the two middle curves 460, and right bridges S3 and S4 operate under SPWM control for the third and fourth quadrants of the modulation curve, as shown by the two bottom curves 470. Therefore, it can be seen from the figure that switches S3 and S4 are in low-frequency mode for the first two quadrants, and S1 and S2 are in low-frequency mode for the third and fourth quadrants.

[0045] Figure 3 and Figure 4 The common feature of each of the operating modes shown is that, during any quadrant of the modulation curve, a pair of switches corresponding to the first half-bridge operates in SPWM mode at the carrier frequency, and another pair of switches corresponding to the other half-bridge operates in simple PWM mode at the modulation frequency.

[0046] like Figure 3 and 4As shown, the PWM carrier is a symmetrical triangular wave with a PWM frequency. In practical digital SPWM implementations, this carrier can be implemented digitally using a counter (e.g., an up-down counter) to generate a symmetrical triangular wave (e.g., an inverted triangular wave as shown) or a sawtooth (up or down) counter that counts up or down to a maximum (or minimum) value and then resets from the starting value. In practice, considering factors such as transferring data from memory to the PWM value register, it is much simpler to implement a counter such that the counter reset frequency is a power of 2 (i.e., 2^N) of the modulation frequency. However, limiting the PWM frequency to a value that is 2^N times the modulation frequency is an inappropriate constraint. The inventors have realized an efficient control method that relaxes this constraint.

[0047] Compared to Figure 5 The principle is illustrated.

[0048] The method provides digital sinusoidal pulse width modulation (SPWM) control of an inverter comprising at least a first switch S1 and a second switch S3. The method includes generating a first binary control signal at the system modulation frequency, corresponding to low-frequency PWM control with a fixed 50% duty cycle, and controlling switch S3 for, as Figure 3 The complete modulation cycle shown; or its control switch S3 for the first half of the modulation cycle and control switch S1 for the second half of the modulation cycle, as shown. Figure 4 As shown in the image.

[0049] The method also generates a second binary control signal, such as PMW1A, whose carrier frequency is an integer multiple of the system modulation frequency (M times) and whose duty cycle changes periodically. For Figure 3 The single-pole SPWM shown in the figure uses a binary control signal to control switch S1 for the complete modulation cycle and therefore directly corresponds to... Figure 3 PWM1A in the example. For Figure 3 The single-pole SPWM shown in the figure controls switch S1 during the first half of the modulation cycle, and controls switch S3 for the second half of the modulation cycle, as follows: Figure 4 As shown (therefore, a combination of PWM1A and PWM3A). The integer M can be 10, as shown... Figure 5 As shown; however, this value is unrestricted and can have other values ​​(e.g., 8, 9, 12, etc.). Note that it is unrestricted by multiples of 2^N, such as 8 or 16.

[0050] To generate the second binary control signal, a periodic counter 510 is provided, whose reset frequency is an integer multiple of the modulation frequency (K times). Preferably, the reset frequency of the periodic counter is 2^N times the modulation frequency. Therefore, as... Figure 5 As shown, the integer K can have a value of 16. (As...) Figure 5As shown, the period counter can be a sawtooth (upward) counter; however, in other embodiments, it can be a downward counter or a symmetrical up-down counter.

[0051] Calculate multiple, i.e., M, disconnection times for the second control signal. The calculation can be performed in a first module, which may be part of a microcontroller device. The disconnection times are... Figure 5 The top portion of the curve is shown here: This top portion of the curve overlaps with the upper and lower curves of a symmetrical triangle 530, which has a modulation frequency of sine wave 520 and a frequency corresponding to the PWM frequency. It should be noted that, typically, the PWM frequency does not correspond to the counter's reset frequency. The disconnection points are shown at, for example, points 542, 544, 546, and 548, where the triangle 530 curve intersects the sinusoidally modulated sine wave 520.

[0052] Depending on the circumstances, according to one or more embodiments of this disclosure, a further plurality of, namely M, turn-on times for the second control signal are also calculated. Example turn-on times are shown at 552, 554, and 556, and correspond to the times when the triangle curve 530 intersects the sinusoidal modulated sine wave 510 in the downward trajectory.

[0053] Figure 5 The resulting PWM control signal 550 is also shown, which will be derived from the overall on and off times.

[0054] Now consider Figure 5 In the lower part, the disconnection time and, if applicable, the turn-on time can then be mapped to counter 510. As shown, in this case, the counter has a frequency K times the modulation frequency, where K = 2^4 = 16, and therefore has a sequence of 16 triangular sawtooths, shown as C1, C2, C3, etc. Any individual disconnection time thus corresponds to a specific counter value on a specific sequence number; for example, the first disconnection time 542 corresponds to counter Vb in counter sequence number C3. Similarly, the first turn-on time 552 corresponds to the value Va in counter sequence number C2. Thus, for each of the disconnection times and, if applicable, for each of the turn-on times, a corresponding disconnection counter value and a corresponding counter sequence value are determined.

[0055] The corresponding counter sequence values ​​at each disconnection time are stored in memory, spanning K (that is, 16 in this case) memory locations. For fast retrieval, the memory locations will be largely adjacent blocks. However, as can be seen from... Figure 5 Note that although the PWM frequency is actually only 10 times the modulation frequency and the counter reset frequency is 16 times the modulation frequency, some memory locations will not store valid values ​​from the counter: in other words, the PWM control signal is not disconnected at any point in that particular sawtooth.

[0056] Therefore, a dummy value is stored in each of the remaining memory locations (i.e., (KM) locations) of the K memory locations. Selecting a dummy value is invalid if it exceeds the range of the PWM counter, and therefore will not change the PWM level; for example, it might be negative. Thus, in an embodiment using only disconnect values, now for each value in the counter sequence (1-16 in this example), a counter value corresponding to the disconnect control moment will be stored in memory, and if no disconnect control moment exists during that value period of the counter sequence, a dummy value is stored.

[0057] In embodiments that use both disconnect and on-time moments in addition to disconnect moments, a total of 2K memory locations are provided. In this case, two locations are provided for each value of the counter sequence. Similarly, typically for fast memory retrieval, the 2K relocations will be for adjacent blocks. In such embodiments, disconnect moments are interleaved with on-time moments across 2K memory locations. Likewise, there will be (KM) values ​​for the counter sequence for which no on-time value exists, and dummy values ​​are stored in these locations.

[0058] The result is a block with 2K memory locations, where a pair corresponds to each value of the counter sequence, C1, C2, etc. In each pair of memory locations, there may be an on-value and a dummy value (e.g., C1 shows Va), an on-value and a off-value (e.g., C2 shows Vc and Vb respectively), two dummy values ​​(e.g., the sequence value C3 shown), or a dummy value and an off-value (e.g., C8 shows Vd).

[0059] The contents of the memory location are sequentially and periodically transferred to a pair of PWM value registers, namely a rising register and a falling register.

[0060] Thus, a second binary control signal has been generated, thereby implementing SPWM control. Depending on the specific embodiment, this signal is used to control S1 throughout the entire operation, or to control S1 during the first half of the modulation cycle and S3 during the second half of the modulation cycle, as discussed above. It should be noted that if implemented… Figure 4 The SPWM shown is in Figure 5 The PWM control of S3 during the second half of the modulation cycle shown is a copy of the PWM control supplied to S1 during the first half of the modulation cycle, and therefore, only the first half of the cycle needs to be implemented (for S2 - and then repeated for the other switch S3).

[0061] In operation, the inverter's controller reads the off-time of S1 (or S3, depending on the case) from the PWM value register one PWM cycle at a time. Therefore, for each PWM cycle, the PWM value register is updated sequentially with data from the memory locations. In the example described above for determining the on and off control points as described above, in each PWM cycle, two values ​​(from each of two adjacent memory block locations) are transferred to the PWM value register. At the end of the cycle, the control values ​​for the next cycle (i.e., the next two adjacent points in memory) are loaded into the value register. Thus, the values ​​are sequentially transferred to the control register. Furthermore, the sequence is restarted at the end of the counter sequence (that is, after the transmission of the last power value (C16 in the illustrated case) so that the first power value for C1 (which may have been updated during this time) is transmitted. Therefore, in addition to sequentially transmitting values, values ​​are also transmitted periodically.

[0062] As discussed above, providing control signals to the PWM value register involves moving data from memory, which takes a finite amount of time. For low-frequency inverters, this finite amount of time is only a small fraction of the PWM cycle. However, as the inverter frequency increases, and especially as the PWM frequency increases, this finite amount of time occupies a larger portion of the PWM cycle until the processor becomes overloaded at some point. The method described above can be an improvement over conventional control methods because it allows for the use of fast memory access. Specifically, in one or more embodiments, memory access using a so-called DMA (Direct Memory Access) protocol can be used. In this case, the memory block location can be selected as a specific "DMA" memory, which is particularly fast to access compared to other types of random access memory (RAM).

[0063] Figure 6 The diagram illustrates an example of efficient data processing and transfer. It shows adjacent memory block 610 locations, for each of the counter sequence values ​​C1, C2, ..., C16 (16 in this case), where the on and off times of the control signal PWM1A are stored, along with virtual values ​​or entries for the counter sequence values ​​(for this counter sequence, there are no on or off times), as described above relative to... Figure 5 The aforementioned control points (and dummy entries) of the PWM1A are described below. Figure 6The memory locations are labeled VAL2 and VAL3. Each memory location, such as VAL2 of C1, VAL3 of C1, etc., has the same size, typically 4 bytes, but in other applications, different sizes of memory, such as 2 bytes or 8 bytes, may be used. The figure also shows two additional memory locations, VAL4 and VAL5, for each counter sequence. These are the corresponding on and off times of the control signal PWM1B. As already discussed, the control signal PWM1B is substantially complementary to PWM1A at least during a portion of the modulation cycle in which PWM1A is implementing SPWM control. Therefore, at least for the purposes of this disclosure, VAL5 may be a copy of VAL2, and VAL4 may be a copy of VAL3. Those skilled in the art will understand that, for some embodiments, an offset may be provided between the switching times of PWM1A and PWM1B to account, for example, the switching rate of the FET switches used for on and off; this is referred to as the “failure time.” And thus, even in complementary operation of PWM1A and PWM1B, VAL5 may include an offset from VAL2, and VAL4 may include an offset from VAL3. Alternatively, VAL4 and VAL5 may not be used at all, but VAL2 and VAL3 may be the only PWM value registers used (in which case the offset can be provided in a separate register). Alternatively, PWM1A and PWM1B can be controlled independently, which would require all four registers VAL2, VAL3, VAL4, and VAL5. In this particular example, adjacent memory blocks comprise 16 groups of 4×4 bytes. In summary, complementary mode may require only half the number of registers needed in independent mode.

[0064] In some embodiments, additional registers are required to determine control of PWM3A and PWM3B. Alternatively, the PWM1A and PWM1B signals can be connected to the PWM3A and PWM3B ports via, for example, an internal crossbar, in which case no additional registers are required.

[0065] Figure 6 The diagram also shows a group 620 with four registers, specifically for PWM switches, particularly PWM1A and PWM1B. As just mentioned, this may be suitable for embodiments where the PWM1A and PWM1B signals are connected to the PWM3A and PWM3B ports.

[0066] This memory arrangement is convenient because it allows data to be transferred particularly efficiently to the PWM value register using a so-called Direct Memory Access (DMA) protocol. In a DMA protocol, system interrupt and protection flags are typically set and reset, or not used, during data reading from or writing to memory. As a result, read and write operations can be much faster than reading from RAM to RAM, but there are constraints on what memory can be read / written (e.g., the already mentioned contiguous block limitations / requirements).

[0067] Therefore, in embodiments of this disclosure, the value of each counter sequence C1, C2, etc., is written to the PWM value register one counter sequence at a time. Applying DMA rules, these values ​​are typically written in groups of 32 bits (i.e., 4 bytes), resulting in one value being written at a time: VAL2, then VAL3, then VAL4, and finally VAL5. Another possibility for applying DMA is to write the values ​​into a single block of 16 bytes. At the end of each counter sequence (e.g., C2), the value corresponding to the next counter sequence (e.g., C3) is written back to the PWM value register via DMA. After writing the value from C16 to the value register, the loop restarts by writing the value from C1 to the PWM value register.

[0068] Now consider Figure 7 This represents a particularly simple embodiment, but as will be discussed, this embodiment has limited applicability: the figure shows the locations of adjacent memory blocks 610, for each of the values ​​C1, C2, ... C16 (16 in this case) of the counter sequence, where the off-time of the control signal PWM1A is stored, along with a dummy value or entry for the counter sequence (for this counter sequence, there is no on-time or off-time), as described above relative to... Figure 5 The aforementioned control points (and dummy entries) of the PWM1A are described below. Figure 7 The value is labeled VAL3. Each memory location has the same size, typically 4 bytes, but in other applications, different sizes of memory, such as 2 bytes or 8 bytes, can be used. In this embodiment, no other value registers exist. This is possible due to two limitations: first, PWM1A and PWM1B operate in complementary modes (therefore, VAL4 and VAL5 registers are not needed); second, the turn-on time is at the beginning of the PWM cycle, which constrains M to be equal to K. Because M is constrained to be equal to K according to the embodiment described, its use is relatively limited.

[0069] Now go to Figure 8 It shows a flowchart of a method for determining the value of memory 610 according to one or more embodiments.

[0070] The method begins at the start step 810.

[0071] As shown in step 815, in each PWM cycle, the modulated wave and the carrier wave cross each other (typically for both the rising and falling edges of the control signal).

[0072] At step 820, the crossover points are recorded to obtain the rising and falling edges (of the control signal). In other embodiments, only the falling edge of each PWM cycle may be recorded.

[0073] At step 825, it is determined whether the count CNT is less than the number of recorded points. If yes, control continues; if no, control jumps to step 840 mentioned below.

[0074] At step 830, a calculation is performed (recorded points / (1 / 16 sine wave cycle)). This calculation yields a quotient and a remainder. The quotient corresponds to the value of the counter sequence (i.e., the triangle within it); the remainder corresponds to the counter value in that sequence (i.e., the position, that is, the upward or downward distance of the particular triangle), where an intersection occurs.

[0075] Furthermore, at position 835, the quotient and remainder are recorded, and the count CNT increases.

[0076] At step 840, each remainder value is transferred to a corresponding MCU memory location. Typically, as... Figure 6 As shown, there are 16 such memories available for each of the rising edges and each of the falling edges. In a basic embodiment where M=K, the rising edge may always be the start of the carrier period, which is a fraction of the modulation period 1 / (2^N) (e.g., 1(2^4) = 1 / 16), and only the falling edge is required.

[0077] As needed, at 845, update the sinusoidal data transmission table to change the operating frequency or the amplitude of the sinusoidal modulation wave to adjust the power transmitted from Tx or RX according to the requirements of RX.

[0078] The method ends at step 850.

[0079] Figure 9 An overview of a method for digital sinusoidal pulse width modulation (SPWM) control of an inverter including at least a first switch (S3) and a second switch (S1) according to one or more embodiments of the present disclosure is shown:

[0080] The method begins at step 910.

[0081] The method continues at step 920 by generating a first binary control signal (PWM3A) at the system modulation frequency.

[0082] The method continues at step 930 by generating a second binary control signal (PWM1A) whose carrier frequency is an integer multiple of the system modulation frequency, M times. As discussed above, the second binary control signal has a periodically changing duty cycle.

[0083] This control signal is as follows Figure 8 The image shown is generated through the following operations:

[0084] Provide a periodic counter with a reset frequency that is an integer K times the modulation frequency;

[0085] In the first module, multiple, i.e., M, disconnection times of the second control signal are calculated;

[0086] For each of the disconnection times, determine the corresponding disconnection counter value and the corresponding counter sequence value;

[0087] K memory locations are provided in the second module;

[0088] Each disconnect counter value is stored in the corresponding memory location corresponding to the corresponding counter sequence;

[0089] The virtual value is stored in each of the remaining memory locations;

[0090] The contents of the memory location are sequentially and periodically transferred to at least one PWM value register (620).

[0091] The method continues at step 940, for half of the period corresponding to the system modulation frequency:

[0092] The first binary control signal is provided to the first switch; and

[0093] The second binary control signal is provided to the second switch by reading the at least one PWM value register.

[0094] As discussed above, in one or more embodiments, in addition to the disconnection time, the connection time is also determined, and 2*K memory locations are provided, K for the disconnection time and virtual values, and another K for the connection time and other virtual values.

[0095] The method continues at step 950 for the other half of the modulation period:

[0096] According to one or more embodiments, as shown at 952, continue

[0097] The first binary control signal is provided to the first switch, and

[0098] The second binary control signal is provided to the second switch by reading at least one PWM value register;

[0099] Alternatively, the method may be adapted according to one or more other embodiments, as shown at 954.

[0100] The first binary control signal is provided to the second switch, and

[0101] The second binary control signal is provided to the first switch by reading at least one PWM value register.

[0102] The method ends at step 940.

[0103] By reading this disclosure, those skilled in the art will understand other changes and modifications. Such changes and modifications may involve other features known in the field of digital SPWM control that can be used in place of the features already described herein or in addition to those described herein.

[0104] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalization of such novel feature as expressly or implicitly disclosed herein, regardless of whether such novel feature relates to the same invention as currently claimed in any of the claims or whether such novel feature alleviates any or all of the same technical problems as those alleviated by this invention.

[0105] Features described in a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, multiple features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0106] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude multiple, a single processor or other unit can perform the functions of several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A controller for an inverter including a first switch and a second switch, characterized in that, The controller is configured to operate under altered output pulse width modulation by means of a first binary control signal and a second binary control signal to a second switch; the first binary control signal is at the system modulation frequency, and the carrier frequency of the second binary control signal is an integer multiple M of the system modulation frequency and its duty cycle changes periodically; wherein: The controller includes: A counter module configured to provide a periodic counter with a reset frequency that is an integer K times the modulation frequency; The first module is configured as follows: Calculate the multiple, i.e., M, disconnection times of the second binary control signal, and For each of the disconnection times, determine the corresponding counter value and the corresponding counter sequence value; The second module includes K memory locations, and Arranged as Each counter value is stored in the corresponding memory location corresponding to the corresponding counter sequence, and The virtual value is stored in each of the remaining memory locations; At least one PWM value register is arranged to periodically receive the contents of the memory location; and The output terminal is arranged to be connected to the first switch to provide a first binary control signal to the first switch, and to provide a second binary control signal to the second switch by reading data from the at least one PWM value register to control the second switch.

2. The controller according to claim 1, Its features are, The first module is further configured to calculate a plurality of additional M on-times of the second binary control signal, and for each of the on-times, determine a corresponding counter value and a corresponding counter sequence value. The second module includes an additional K memory locations, and is arranged to store each counter value in a corresponding memory location corresponding to the corresponding counter sequence, and to store virtual values ​​in each of the remaining memory locations in the additional K memory locations.

3. The controller according to claim 1, characterized in that, The second module is a Direct Memory Access (DMA) module.

4. The controller according to claim 3, characterized in that, The first module and the DMA module are configured to transfer the contents of four memory locations to a corresponding PWM value register in one of the four PWM value registers, and subsequently transfer the contents of the other four memory locations to the corresponding PWM value registers in the four PWM value registers.

5. A controller for an inverter including a first switch and a second switch, characterized in that, The controller is configured to operate under altered output pulse width modulation by means of a first binary control signal and a second binary control signal to a second switch, wherein the first binary control signal is at the system modulation frequency, and the carrier frequency of the second binary control signal is an integer multiple M of the system modulation frequency and its duty cycle changes periodically; wherein: The controller includes: A counter module configured to provide a periodic counter with a reset frequency that is 2^N times the modulation frequency; The first module is configured as follows: Calculate the multiple, i.e., M, disconnection times of the second binary control signal, and For each of the disconnection times, determine the corresponding counter value and the corresponding counter sequence value; The second module includes 2*(2^N) memory locations, and Arranged as Each counter value is stored in the corresponding memory location corresponding to the corresponding counter sequence, and The virtual value is stored in each of the remaining memory locations; At least one PWM value register is arranged to periodically receive the contents of the memory location; and The output terminal is arranged to be connected to the first switch to provide a first binary control signal to the first switch, and to provide a second binary control signal to the second switch by reading data from the at least one PWM value register to control the second switch.

6. A method for providing digital output pulse width modulation (PWM) control of changing an inverter comprising at least a first switch and a second switch, characterized in that, The method includes: generating a first binary control signal at a system modulation frequency; Generate a second binary control signal whose carrier frequency is an integer M times the system modulation frequency and has a periodically changing duty cycle; The generation of the second binary control signal includes: Provide a periodic counter with a reset frequency that is an integer K times the modulation frequency; In the first module, multiple, i.e., M, disconnection times of the second binary control signal are calculated; For each of the disconnection times, determine the corresponding disconnection counter value and the corresponding counter sequence value; K memory locations are provided in the second module; Each disconnect counter value is stored in the corresponding memory location corresponding to the corresponding counter sequence; Store the virtual value in each of the remaining memory locations; and The contents of the memory location are sequentially and periodically transferred to at least one PWM value register; The method further includes, for half of the period corresponding to the modulation frequency of the system: The first binary control signal is provided to the first switch; and The second binary control signal is provided to the second switch by reading the at least one PWM value register.

7. The method according to claim 6, Its features are, Providing at least K memory locations includes providing 2K memory locations; The method further includes: In the first module, the multiple, i.e., M, on-times of the second binary control signal are calculated; The second module provides an additional K memory locations; For each of the connection times, determine the corresponding connection counter value and the corresponding counter sequence value, and Each on-counter value is stored in the corresponding memory location corresponding to the corresponding counter sequence.

8. The method according to claim 6, characterized in that, The method further includes: generating a third binary control signal and providing it to a third switch; and generating a fourth binary control signal and providing it to a fourth switch, wherein the third binary control signal is complementary to the first binary control signal, and the fourth binary control signal is complementary to the second binary control signal.

9. The method according to claim 6, characterized in that, Periodically transferring the contents of the memory locations to at least one PWM value register includes transferring the contents of four memory locations to a corresponding PWM value register of four PWM value registers, and subsequently transferring the contents of four other memory locations to the corresponding PWM value registers of the four PWM value registers.

10. The method according to claim 9, characterized in that, The step of determining the corresponding counter value and the corresponding counter sequence value at each of the disconnection times is performed at least in part simultaneously with the step of transferring the contents of the four memory locations to a corresponding PWM value register in one of the four PWM value registers.

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