Control synchronization i / o interface

Abstract

The present invention relates to controlling a synchronous I / O interface. An electronic device includes a first input node configured to receive a clock signal, a second input node configured to receive an activation signal or a deactivation signal, a filter circuit responsive to: (a) the activation signal causing the filter circuit to activate to block the clock signal, or (b) the deactivation signal causing the filter circuit to deactivate to pass the clock signal, and an output node configured to couple to a synchronous I / O interface of an integrated circuit to control operation of the synchronous I / O interface.

Description

Technical Field

[0001] This disclosure generally relates to a circuit, and more specifically, to a circuit capable of disabling or enabling a synchronous input / output interface. Background Technology

[0002] When it comes to device security, exposed synchronous input / output (I / O) interfaces of electronic devices (e.g., debug interfaces) are a fundamental problem. Once an attacker gains access to the interface, they can access any information on the device, including security keys and other device information.

[0003] Expensive, high-end devices may offer the option to disable the interface if needed. However, inexpensive devices typically do not offer this feature. It is important to find a way to disable or enable the interface of such inexpensive chips. Summary of the Invention

[0004] According to some embodiments of this disclosure, an electronic device is provided. The electronic device includes: a first input node configured to receive a clock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal activating the filter circuit to block the clock signal, or (b) the deactivation signal deactivating the filter circuit to transmit the clock signal; and an output node configured to be connected to a synchronous input / output (I / O) interface of an integrated circuit to control the operation of the synchronous I / O interface.

[0005] According to some embodiments of this disclosure, an apparatus is provided. The apparatus includes: an integrated circuit including: a synchronous I / O interface; and general-purpose I / O pins configured to provide an activation signal or a deactivation signal; and a filter circuit: coupled to receive a clock signal from an external clock circuit; coupled to receive the activation signal or the deactivation signal from the integrated circuit; and configured to block the clock signal based on the activation signal or to transmit the clock signal to the integrated circuit based on the deactivation signal.

[0006] According to some embodiments of this disclosure, a method for controlling a synchronous I / O interface included in an integrated circuit is also provided. The method includes: receiving a clock signal from an external clock circuit by a filter circuit; transmitting the activation signal, configured to activate the filter circuit, from the integrated circuit to the filter circuit; and, in response to the activation signal, blocking the clock signal by the filter circuit to disable the synchronous I / O interface. The method may further include: transmitting the deactivation signal, configured to deactivate the filter circuit, from the integrated circuit to the filter circuit; and, in response to the deactivation signal, transmitting the clock signal to the synchronous I / O interface by the filter circuit to enable the synchronous I / O interface. Attached Figure Description

[0007] Figure 1 This is a schematic diagram illustrating an apparatus for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure.

[0008] Figure 2 This is a schematic diagram illustrating an exemplary filter circuit for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure.

[0009] Figure 3 This is a schematic diagram illustrating another exemplary filter circuit for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure.

[0010] Figure 4 This is a schematic diagram illustrating another exemplary filter circuit for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure.

[0011] Figure 5 This is a method for controlling synchronous I / O interfaces included in an integrated circuit, consistent with some embodiments of this disclosure. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein the same numerals in different drawings denote the same or similar elements unless otherwise stated. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with this disclosure. Rather, they are merely examples of systems, apparatuses, and methods consistent with the aspects of this disclosure as described in the appended claims.

[0013] Exposed synchronous I / O interfaces (e.g., debug interfaces) on a System-on-a-Chip (SoC) offer beneficial uses in hardware configuration and control. However, the presence of debug interfaces also increases the risk and vulnerability of the SoC. Attackers could illegally access debug interfaces and obtain confidential information stored in the SoC. Expensive high-end devices can provide solutions for disabling debug interfaces when needed. However, inexpensive devices, such as Internet of Things (IoT) devices, typically do not offer this feature.

[0014] A simple Zener diode, used as an electronic fuse, can provide some protection for a debug interface. For example, a Zener diode can be connected to the clock pin of the debug interface, and sufficient current can flow through the diode to burn it out when the debug interface needs to be disabled. However, this burning process is difficult to control and can potentially damage the printed circuit board (PCB). Therefore, a convenient and inexpensive technique is needed to control the debug interface.

[0015] Embodiments of this disclosure provide an apparatus having a synchronous I / O interface (e.g., a debug interface) that can be disabled or enabled by a filter circuit included in the apparatus. The apparatus includes an integrated circuit configured to transmit an activation signal or a deactivation signal to the filter circuit. The filter circuit is coupled to an external clock circuit (e.g., an external debugger) and configured to receive a clock signal from the debugger. In response to the deactivation signal, the filter circuit is disabled and transmits the clock signal to the debug interface. Conversely, in response to the activation signal, the filter circuit is enabled and blocks the clock signal. When the filter circuit is disabled, operation of the debug interface is enabled. Conversely, when the filter circuit is enabled, operation of the debug interface is disabled.

[0016] The embodiments disclosed in this disclosure have one or more technical advantages. By inserting a filter circuit between the debug interface and the external debugger, the operation of the debug interface can be disabled or enabled using an activation signal or a deactivation signal sent to the filter circuit. This allows for easy control of the built-in debug circuitry within the chip without modifying the chip, resulting in improved chip security at low cost.

[0017] Furthermore, the embodiments disclosed in this disclosure provide a roadmap for a general solution, namely, a technique for disabling or enabling any type of synchronous I / O interface by inserting a filter circuit between the synchronous I / O interface and the external clock circuit and controlling the activation or deactivation of the filter circuit with an activation signal or a deactivation signal, respectively.

[0018] Figure 1 This is a schematic diagram illustrating an apparatus 100 for controlling a synchronous I / O interface (e.g., a debug interface), consistent with some embodiments of this disclosure. Reference Figure 1Device 100 includes an integrated circuit 102 and a filter 104. Integrated circuit 102 includes a debug interface configured to communicate with filter 104. The debug interface includes a clock pin 120 and a data pin (not shown). Integrated circuit 102 is configured to transmit an activation signal or a deactivation signal to filter 104 via path 110. Integrated circuit 102 can transmit the activation signal or deactivation signal to filter 104 via a spare I / O pin 122. The spare I / O pin 122 may be a general purpose input / output (GPIO) pin designed for implementation of device 100 in a third-party device, and therefore available in integrated circuit 102, but not connected to any external pin of the third-party device.

[0019] Filter 104 includes a node 114 configured to receive an activation signal or a deactivation signal transmitted from integrated circuit 102. Filter 104 includes a node 116 configured to receive a clock signal transmitted via path 118 from node 124 of external debugger 106. Filter 104 includes filter circuitry (not shown) that can block or transmit the clock signal received from debugger 106 in response to the activation signal or the deactivation signal, respectively. The filter circuitry can be any circuitry capable of filtering out the clock signal received from debugger 106. For example, the filter circuitry can be at least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, a transistor, or a combination thereof. Figures 2 to 4 Some exemplary embodiments of the filter circuit are illustrated. Filter 104 includes node 112, which is configured to transmit a clock signal to integrated circuit 102 via path 108 when the filter circuit is deactivated in response to a deactivation signal. On the other hand, when the filter circuit is activated in response to an activation signal, the filter circuit filters out the clock signal received from debugger 106. In one embodiment, integrated circuit 102 is external to the filter circuit but implemented on the same module as the filter circuit (e.g., on the same PCB).

[0020] In one implementation, the debug interface included in integrated circuit 102 is a serial line debug (SWD) interface synchronized with two signals (i.e., a data signal and a clock signal). The data pins (not shown) of the debug interface can be used to send data to or receive data from an external debugger 106, allowing the debugger to read / write to the internal memory of integrated circuit 102 via the SWD interface. Filter 104 is coupled to the clock pin 120 of the debug interface and the external debugger 106. Filter 104 receives an activation or deactivation signal transmitted via a spare I / O pin 122 of integrated circuit 102. As described above, the spare I / O pin 122 can be a general purpose input / output (GPIO) pin. Filter 104 also receives the clock signal from debugger 106 at node 116 via path 118. In its unprogrammed default state, the GPIO pin 122 is unconfigured and thus in a floating state, and filter 104 can be used as a high-pass filter, allowing the clock signal to be transmitted at an operable frequency of the debug interface. In this default state, the debug interface can be used to program integrated circuit 102, and this programming enables GPIO pin 122 to transmit a deactivation signal. When the deactivation signal is transmitted from GPIO pin 122, the deactivation signal causes a change in the characteristics of the filter circuit, for example, by electrically connecting an additional capacitor to the filter circuit, so that the filter circuit can block the clock signal operating frequency of the debug interface. Then, when an activation signal is transmitted from GPIO pin 122, the activation signal again changes the characteristics of the filter circuit, for example, by disconnecting the additional capacitor of the filter circuit, so that the filter circuit can transmit the clock signal operating frequency of the debug interface received from debugger 106. In one embodiment, activation of the filter circuit corresponds to a low-activation state of the filter circuit, while deactivation of the filter circuit corresponds to a floating state of the filter circuit.

[0021] Thus, the filter circuit of filter 104 blocks or transmits the clock signal based on the activation signal or the deactivation signal, respectively. When the filter circuit blocks the clock signal in response to the activation signal, the operation of the debug interface in integrated circuit 102 is disabled. On the other hand, when filter 104 transmits the clock signal in response to the deactivation signal, the operation of the debug interface in integrated circuit 102 is enabled.

[0022] Integrated circuit 102 can transmit an activation signal or a deactivation signal to filter 104 based on a trigger event. In one embodiment, the trigger event could be the input of a password to unlock a debug interface. For example, in an inter-integrated circuit (I2C) interface, an authorized user of the interface can use a password to lock the I2C bus. This password can be input into the control logic in integrated circuit 102 via an input channel (e.g., Bluetooth, WiFi, or Universal Asynchronous Receiver / Transmitter (UART)). Detection of the input password can trigger integrated circuit 102 to transmit a deactivation signal to filter 104.

[0023] In another implementation, the triggering event could be a button press event. For example, a button on device 100 could be pressed when access to the debug interface is needed during a service return, quality return, or re-production at the factory. In one implementation, access to the button requires access permission, such as via a passcode.

[0024] In another embodiment, the triggering event can be a sensor-triggered event. The sensor can be an accelerometer sensor or any other motion sensor connected to device 100 and sensing movement of the device. When the device begins to move, it can open its Serial Peripheral Interface (SPI), allowing the sensor to send data through the interface. Conversely, when the device is stationary, the sensor does not send data to the device and the interface is locked.

[0025] In one implementation, device 100 may be a module implemented in a third-party system. In this implementation, the host system may use external control and / or spare I / O pins of integrated circuit 102 to control the debug logic. The host system may be any third-party device or system that implements device 100.

[0026] By inserting a filter 104 between the debug interface of integrated circuit 102 and the external debugger 106, the operation of the debug interface can be disabled or enabled using an activation signal or a deactivation signal transmitted from integrated circuit 102, respectively. This allows control of the built-in debug interface within the chip without modifying the chip, resulting in enhanced chip security at low cost.

[0027] The above embodiments relate to a technique for enabling or disabling an on-chip debug interface to provide protection against unauthorized access to confidential information on the chip by an attacker. However, the application of this technique is not limited to this. This technique can be used to control the operation of any other type of synchronous I / O interface. For example, in some embodiments, instead of a filter circuit implemented in the debug interface that operates in response to an activation or deactivation signal, it can be used to control any other synchronous I / O interface (such as Serial Peripheral Interface (SPI) and its variants (e.g., Queued Serial Peripheral Interface (QSPI), Octal Serial Peripheral Interface (OSPI)), Medium Independent Interface (MII), and inter-IC communication interfaces). In these embodiments, the debugger 106 can be replaced by any other external clock circuit. For example, as follows: Figures 2 to 4 The filter circuit shown can be used to disable or enable these synchronous I / O interfaces.

[0028] Figure 2 This is a schematic diagram illustrating an exemplary filter circuit 200 for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure. (See reference...) Figure 2 The filter circuit 200 includes capacitors 202, 204, and 206. The filter circuit 200 receives a clock signal from an external clock circuit via path 208. The external clock circuit can be any clock circuit capable of reading and writing to the integrated circuit's internal memory via a synchronous I / O interface. In one embodiment, the external clock circuit is a debugger, such as... Figure 1 The debugger 106, and the synchronous I / O interface is the debug interface, such as, Figure 1 The debug interface included in integrated circuit 102.

[0029] Filter circuit 200 receives an activation signal or deactivation signal from an integrated circuit including a synchronous I / O interface via path 212. The activation or deactivation signal is provided to capacitors 204 and 206. When the activation signal is provided to capacitors 204 and 206, it electrically connects the capacitors, activating filter circuit 200 to function as a signal filter and filtering out clock signals received from an external clock circuit, thereby disabling the operation of the synchronous I / O interface. In one embodiment, capacitors 204 and 206 are grounded for effective filtering.

[0030] In another embodiment, a deactivation signal is provided to capacitors 204 and 206. The deactivation signal electrically disconnects the capacitors from the circuit. Then, filter circuit 200 is deactivated, and a clock signal received from an external clock circuit is transmitted, thereby enabling operation of the synchronous I / O interface. In this embodiment, filter circuit 200 can be used as a high-pass filter to allow the operating frequency of the synchronous I / O interface to pass through. The clock signal transmitted from filter circuit 200 is transmitted to the clock pin of the synchronous I / O interface via path 210. In one embodiment, each path of the activation or deactivation signal to capacitors 204 and 206 is coupled to a switch (not shown), and the activation or deactivation signal controls the closed or open state of the switch to connect / disconnect capacitors 204 and 206 to / from the circuit. In one embodiment, filter circuit 200 and the synchronous I / O interface can be included in a module that can be implemented in a third-party device.

[0031] Figure 2 An example of activating or deactivating two capacitors (i.e., capacitors 204 and 206) is shown. However, the capacitor circuit is not limited to this. In some embodiments, only one or more capacitors may be activated or deactivated. For example, in one embodiment, instead of capacitors 204 and 206, only one capacitor (capacitor 204 or 206) may be implemented in the filter circuit, and an activation signal or deactivation signal may be sent to that capacitor.

[0032] The capacitors in the filter circuit 200 can be selected so that their capacitance matches the product's safety level. For example, less expensive capacitors with smaller capacitance can be used for simple short-range connections (e.g., Bluetooth), while more expensive capacitors with larger capacitance can be used for medical and other applications.

[0033] Figure 3 This is a schematic diagram illustrating another exemplary filter circuit 300 for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure. Reference Figure 3 The filter circuit 300 includes a resistor 302 and capacitors 304 and 306 connected in parallel. The filter circuit 300 receives a clock signal from an external clock circuit via path 308. The external clock circuit can be any clock circuit. In one embodiment, the external clock circuit is a debugger, such as... Figure 1 The debugger 106, and the synchronous I / O interface is the debug interface, such as, Figure 1 The debug interface included in integrated circuit 102.

[0034] refer to Figure 3The filter circuit 300 receives an activation signal or a deactivation signal from the integrated circuit including the synchronous I / O interface via path 312. The activation signal or deactivation signal is provided to capacitors 304 and 306 via node 314. In one embodiment, the activation signal is provided to capacitors 304 and 306. The activation signal can alter the characteristics of the filter circuit 300 by electrically connecting the capacitors to the circuit. The filter circuit 300 is then activated to function as a signal filter and filters out clock signals received from an external clock circuit, thereby disabling the operation of the synchronous I / O interface.

[0035] In another embodiment, a deactivation signal is provided to capacitors 304 and 306. The deactivation signal alters the characteristics of filter circuit 300 by electrically disconnecting the capacitors from the circuit. This deactivates filter circuit 300 and transmits a clock signal received from an external clock circuit, thereby enabling operation of the synchronous I / O interface. The clock signal is transmitted to the clock pin of the synchronous I / O interface via path 310.

[0036] In one embodiment, instead of two capacitors, only one capacitor (e.g., capacitor 304 or 306) or more than two capacitors can be implemented in the circuit to receive an activation signal or a deactivation signal. In one embodiment, resistor 302 can be interchanged with one of capacitors 304 and 306, and can provide the activation signal or deactivation signal to node 314. In one embodiment, filter circuitry 300 and synchronous I / O interface can be included in a module that can be implemented in a third-party system or device.

[0037] In one embodiment, integrated circuit 102 is a third-party integrated circuit and is implemented on the same module (e.g., PCB) as filter 104. In this embodiment, integrated circuit 102 and filter 104 are different circuits.

[0038] Figure 4 This is a schematic diagram illustrating another exemplary filter circuit 400 for controlling a synchronous I / O interface, consistent with some embodiments of this disclosure. (See reference) Figure 4 The filter circuit 400 includes a metal-oxide-semiconductor field-effect transistor (MOSFET) 402. However, the transistor is not limited to this, and any type of transistor can be implemented in the filter circuit. The transistor 402 includes a gate 404, a source 406, and a drain 408. The filter circuit 400 receives a clock signal from an external clock circuit via path 414. The received clock signal is provided to the source 406 of the transistor 402. The external clock circuit can be any clock circuit. In one embodiment, the external clock circuit is a debugger, such as... Figure 1 The debugger 106, and the synchronous I / O interface is the debug interface, such as, Figure 1 The debug interface included in integrated circuit 102.

[0039] The filter circuit 400 receives an activation signal or a deactivation signal from the integrated circuit including the synchronous I / O interface via path 412. The activation signal or deactivation signal is provided to the gate 404 of the transistor 402. In one embodiment, the activation signal is provided to the gate 404 such that the filter circuit 400 is activated and filters out the clock signal received from the external clock circuit, thereby disabling the operation of the synchronous I / O interface.

[0040] In another embodiment, a deactivation signal is provided to the gate 404 of transistor 402, causing filter circuit 400 to be deactivated and transmitting a clock signal received from an external clock circuit, thereby enabling the operation of the synchronous I / O interface. The clock signal is transmitted to the synchronous I / O interface via path 410. In one embodiment, filter circuit 400 and synchronous I / O interface can form a module that can be implemented in a third-party system or device.

[0041] Figures 2 to 4 Only a few exemplary embodiments of the filter circuit are shown. However, the construction of the filter circuit is not limited to these. Any type of circuit or combination of circuits capable of filtering out clock signals can be used. For example, the filter circuit can be at least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, one or more transistors, or a combination thereof.

[0042] Figure 5 A method 500 for controlling a debug interface included in an integrated circuit is shown, consistent with some embodiments of this disclosure. Method 500 can be provided by a device (such as...) Figure 1 The device 100) is used to perform this action. (See reference...) Figure 5 Method 500 includes step 510 of identifying a trigger event and determining whether to transmit an activation signal or a deactivation signal. For example, device 100 ( Figure 1 The integrated circuit 102 identifies events that trigger the transmission of activation or deactivation signals.

[0043] Method 500 includes transmitting a clock signal and one of an activation signal and a deactivation signal to a filter circuit (such as, Figure 1 Step 520 of the filter circuit included in filter 104. For example, such as Figure 1The external debugger of debugger 106 transmits the clock signal to the filter circuit. Integrated circuit 102 transmits an activation signal or a deactivation signal based on the determination in step 510. In one embodiment, the clock signal and one of the activation and deactivation signals may be transmitted to the filter circuit substantially simultaneously. In another embodiment, either the activation signal or the deactivation signal is always transmitted to the filter circuit, regardless of the transmission of the clock signal.

[0044] Method 500 includes blocking the clock signal or passing the clock signal to a debug interface (such as, Figure 1 Step 530 (the debug interface included in integrated circuit 102). The blocking or transmission of the clock signal is performed by the filter circuit. For example, in response to an activation signal received from integrated circuit 102, the filter circuit is activated and filters out the clock signal, and in response to a deactivation signal received from integrated circuit 102, the filter circuit is deactivated and transmits the clock signal.

[0045] Method 500 includes step 540 of disabling or enabling the debugging interface. For example, the debugging interface is disabled when the filter circuit is activated by an activation signal and filters out the clock signal. On the other hand, the debugging interface is enabled when the filter circuit is deactivated by a deactivation signal and transmits the clock signal.

[0046] Method 500 is executed to disable or enable debug interfaces included in the integrated circuit. However, the application of this method is not limited to this. In some implementations, method 500 can be used to control any synchronous I / O interface, such as SPI and its variants (e.g., QSPI, OSPI, etc.), MII and its variants (Reduced Medium Independent Interface (RMII), Gigabit Medium Independent Interface (GMII), Reduced Gigabit Medium Independent Interface (RGMII), etc.), and inter-IC communication interfaces. In these implementations, instead of a debugger, any external clock circuit capable of reading and writing to the integrated circuit's internal memory via the synchronous I / O interface can be used.

[0047] The steps of the example methods described herein do not necessarily need to be performed in the order described, and the order of the steps in these methods should be understood as merely illustrative. For example, depending on the functionality involved, two consecutively shown boxes may actually be performed substantially simultaneously, or these boxes may sometimes be performed in reverse order. Similarly, additional steps may be included in these methods, and certain steps may be omitted or combined in methods consistent with various implementations.

[0048] The described implementations are not mutually exclusive, and elements, components, or steps described in conjunction with one exemplary implementation may be combined with or eliminated from other implementations in a suitable manner to achieve desired design goals.

[0049] The terms "some embodiments" or "some exemplary embodiments" used herein mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment. The phrases "one embodiment," "some embodiments," or "another embodiment" appearing in various places in this disclosure do not necessarily refer to the same embodiment, nor are they necessarily separate or alternative embodiments that are mutually exclusive with other embodiments.

[0050] As used herein, the term “exemplary” is used to mean that it is used as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the term is intended to present the concept in a specific manner.

[0051] As used in this disclosure, unless otherwise specifically stated, the term "or" includes all possible combinations, unless impractical. For example, if a statement declares that a database may include A or B, then unless specifically stated or impractical, the database may include A, or B, or A and B. As a second example, if a statement declares that a database may include A, B, or C, then unless specifically stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0052] Furthermore, the articles “a” and “an” used in this disclosure and the appended claims should generally be interpreted as meaning “one or more” unless the singular form is clearly indicated by description or from the context.

[0053] Unless otherwise explicitly stated, each value and range should be interpreted as approximate, as if the words “approximately” or “about” preceded the value or range.

[0054] Although the elements in the following method claims are set in a particular order, if any, the elements are not necessarily limited to being implemented in that particular order unless the statement of the claims otherwise implies a particular order for implementing some or all of these elements.

[0055] It should be understood that, for clarity, certain features of this disclosure described in the context of individual embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of this specification described in the context of a single embodiment may also be provided individually or in any suitable sub-combination or as suitably provided in any other embodiment described in this specification. Certain features described in the context of various embodiments are not essential features of those embodiments unless otherwise indicated.

[0056] It should also be understood that, without departing from the scope of the invention, those skilled in the art can make various modifications, substitutions, and variations to the details, materials, and arrangements of the components described and shown to explain the nature of the described embodiments. Therefore, the following claims encompass all such substitutions, modifications, and variations falling within the terms of the claims.

Claims

1. An electronic device, the electronic device comprising: The first input node is configured to receive a clock signal; The second input node is configured to receive an activation signal or a deactivation signal; A filter circuit that responds to: (a) the activation signal activating the filter circuit to block the clock signal, or (b) the deactivation signal deactivating the filter circuit to transmit the clock signal; as well as Output nodes, configured to connect to the synchronous input / output I / O interface of an integrated circuit to control the operation of the synchronous I / O interface. Wherein, the first input node is configured to be connected to an external clock circuit to receive the clock signal, and the second input node is configured to be connected to the integrated circuit to receive the activation signal or the deactivation signal, and Wherein, the external clock circuit is a debugger, the synchronous I / O interface is a serial line debug SWD interface, and the second input node of the electronic device is configured to be connected to the spare I / O pin of the integrated circuit to receive the activation signal or the deactivation signal.

2. The electronic device according to claim 1, wherein, The output node is configured as follows: When the filter circuit is deactivated, the clock signal is output to the synchronous I / O interface to enable the synchronous I / O interface, and When the filter circuit is activated, it blocks the clock signal to disable the synchronous I / O interface.

3. The electronic device according to claim 1, wherein, The filter circuit includes at least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, or a combination thereof.

4. The electronic device according to claim 3, wherein, The filter circuit includes at least one capacitor, and the activation signal is configured to activate the at least one capacitor, causing the filter circuit to block the clock signal.

5. The electronic device according to claim 1, wherein, The filter circuit includes at least one transistor, and the activation signal or the deactivation signal is configured to activate or deactivate the gate of the at least one transistor, such that the filter circuit blocks or transmits the clock signal, respectively.

6. The electronic device according to claim 1, wherein, The filter circuit includes: At least one transistor, and At least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, or a combination thereof.

7. An apparatus comprising: Integrated circuit, the integrated circuit comprising: Synchronous input / output I / O interface; and General-purpose I / O pins, configured to provide activation or deactivation signals; and The filter circuit, wherein the filter circuit is: Connected to receive a clock signal from an external clock circuit and connected to receive the activation signal or the deactivation signal from the integrated circuit; and It is configured to block the clock signal based on the activation signal or to deliver the clock signal to the integrated circuit based on the deactivation signal. The external clock circuit is a debugger, and the synchronous I / O interface is a serial line debug SWD interface, which receives the clock signal transmitted by the filter circuit through the clock pin of the SWD interface.

8. The apparatus according to claim 7, wherein, When the filter circuit is deactivated by the deactivation signal and the clock signal is transmitted, the operation of the synchronous I / O interface is enabled, or When the filter circuit is activated by the activation signal and blocks the clock signal, the operation of the synchronous I / O interface is disabled.

9. The apparatus according to claim 7, wherein, The filter circuit includes at least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, or a combination thereof.

10. The apparatus according to claim 9, wherein, The filter circuit includes at least one capacitor, and the activation signal or the deactivation signal is configured to activate or deactivate the at least one capacitor, such that the filter circuit blocks or transmits the clock signal, respectively.

11. The apparatus according to claim 7, wherein, The filter circuit includes at least one transistor, and the activation signal or the deactivation signal is configured to activate or deactivate the gate of the at least one transistor, such that the filter circuit blocks or transmits the clock signal, respectively.

12. The apparatus according to claim 7, wherein, The filter circuit includes: At least one transistor, and At least one of the following: a capacitor circuit, a resistor-capacitor (RC) circuit, an inductor-capacitor (LC) circuit, a resistor-inductor (RL) circuit, a resistor-inductor-capacitor (RLC) circuit, or a combination thereof.

13. The apparatus according to claim 7, wherein, The activation signal or the deactivation signal is transmitted through the spare I / O pin of the integrated circuit.

14. The apparatus according to claim 13, wherein, The integrated circuit is also configured to: Based on the triggering event, it is determined whether to transmit the activation signal or the deactivation signal, and Based on the determination, the spare I / O pin is controlled to output the activation signal or the deactivation signal to the filter circuit.

15. A method for controlling a synchronous input / output I / O interface included in an integrated circuit, the method comprising: The filter circuit receives the clock signal from the external clock circuit. An activation signal is transmitted from the integrated circuit to the filter circuit, the activation signal being configured to activate the filter circuit. as well as In response to the activation signal, the filter circuit blocks the clock signal to disable the operation of the synchronous I / O interface. The filter circuit includes a first input node and a second input node. The first input node is configured to be connected to an external clock circuit to receive the clock signal, and the second input node is configured to be connected to the integrated circuit to receive the activation signal or the deactivation signal. The external clock circuit is a debugger, the synchronous I / O interface is a serial line debug SWD interface, and the second input node of the filter circuit is configured to be connected to the spare I / O pin of the integrated circuit to receive the activation signal or the deactivation signal.

16. The method according to claim 15, further comprising: A deactivation signal is transmitted from the integrated circuit to the filter circuit, the deactivation signal being configured to deactivate the filter circuit. as well as In response to the deactivation signal, the filter circuit transmits the clock signal to the synchronous I / O interface to enable the operation of the synchronous I / O interface.

17. The method according to claim 16, further comprising: Identify the triggering event that determines the selection of the activation signal or the deactivation signal; as well as In response to the identified trigger event, the spare I / O pin of the integrated circuit is controlled to transmit the activation signal or the deactivation signal to the filter circuit.

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