Display driving devices and methods

Abstract

This application relates to display driving devices and methods. A display driving device is disclosed, configured to provide signals to a display panel, the display panel being driven to receive an active period of a source signal corresponding to image data and a blanking period during which no source signal is input. The display driving device includes: an output buffer unit configured to output a source signal to the display panel during the active period and to output an edge signal to the display panel during the blanking period; and a low dropout (LDO) unit configured to supply an edge signal to the output buffer unit. The output buffer unit includes a buffer configured to output either the source signal or the edge signal to the display panel, a first switch configured to switch the connection between the LDO unit and the buffer's input lines, and a second switch configured to switch the connection between the LDO unit and the buffer's output lines. The buffer is turned on or off according to the respective on / off states of the first and second switches.

Description

Technical Field

[0001] This specification relates to display driver devices and display driver methods. Background Technology

[0002] Representative examples of display devices configured to display images include liquid crystal displays (LCDs) that use liquid crystals and OLED displays that use organic light-emitting diodes (OLEDs).

[0003] The display device includes: a panel configured to display an image via a pixel array; a panel driver configured to drive the panel; and a timing controller configured to control the panel driver. The panel driver includes: a gating driver configured to drive gating lines of the panel; and a data driver configured to drive data lines of the panel.

[0004] Once image data is received from an external system, the timing controller typically supplies the received image data along with predetermined control information to the data driver. The data driver samples and latches the image data in digital format according to the predetermined control signals received from the timing controller, converts the image data into an analog source signal, and outputs the source signal to the display panel.

[0005] The display panel is driven by a blanking period, which is divided into a valid period for the input source signal and a period between the valid periods as a non-input source signal period. Typically, during the blanking period, the data driver supplies a single voltage to the display panel to prevent leakage current. In this case, an increase in power consumption occurs when driving the display. Summary of the Invention

[0006] This disclosure relates to a display driver device and method that can minimize power consumption.

[0007] This disclosure also relates to a display driving device and method capable of preventing current leakage during blanking periods.

[0008] This disclosure also relates to a display driving device and method capable of rapidly driving a display panel in response to high frame rates.

[0009] This disclosure also relates to a display driving device and method capable of providing flexible porch signals during each blanking period.

[0010] This disclosure also relates to a display driving device and method capable of reducing quiescent current generated in a buffer by turning off the buffer during a blanking period.

[0011] According to one aspect of this disclosure, a display driving device is provided, configured to provide a signal to a display panel, the display panel being driven to input a valid period of a source signal corresponding to image data and a blanking period during which no source signal is input. The display driving device includes an output buffer unit and a low dropout (LDO) unit, the output buffer unit being configured to output the source signal to the display panel during the valid period and to output an edge signal to the display panel during the blanking period, the low dropout (LDO) unit being configured to supply the edge signal to the output buffer unit, wherein the output buffer unit includes a buffer configured to output the source signal or the edge signal to the display panel, a first switch configured to switch the connection between the LDO unit and the input line of the buffer, and a second switch configured to switch the connection between the LDO unit and the output line of the buffer, and the buffer being turned on or off according to the on / off state of each of the first switch and the second switch. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specific embodiments, serve to explain the principles of the disclosure. In the drawings:

[0013] Figure 1 This is a diagram illustrating the configuration of a display system according to one embodiment of the present disclosure;

[0014] Figure 2 This is a schematic block diagram of a data driver according to one embodiment of the present disclosure;

[0015] Figure 3 This is a circuit diagram illustrating a portion of a data driver according to one embodiment of the present disclosure;

[0016] Figure 4 This is a timing diagram illustrating a method for driving a display panel according to one embodiment of the present disclosure;

[0017] Figures 5A to 5C This is a circuit diagram illustrating the operation of a data driver according to one embodiment of the present disclosure;

[0018] Figure 6 This is a timing diagram illustrating a method for driving a display panel according to another embodiment of the present disclosure; and

[0019] Figure 7 This is a timing diagram illustrating a method for driving a display panel according to yet another embodiment of the present disclosure. Detailed Implementation

[0020] In this specification, it should be noted that elements used in other figures are represented by the same reference numerals whenever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art are omitted where they are not essential to the configurations required for this disclosure. The terms described in this specification should be understood as follows.

[0021] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0022] The shapes, dimensions, ratios, angles, and figures disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals consistently denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it would be determined to unnecessarily obscure important points of this disclosure.

[0023] When using the terms "including," "having," and "comprising" as described in this specification, another component may be added unless "only~" is used. Singular terms may include plural forms unless expressed otherwise.

[0024] When interpreting a component, although it is not explicitly described, it is interpreted as including a tolerance range.

[0025] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0026] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0027] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second, and third items" means a combination of all items drawn from two or more of the first, second, and third items, as well as the first, second, or third item.

[0028] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may interoperate differently and be technically driven. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0029] In the following text, reference will be made to Figure 1 A display device according to one embodiment of the present disclosure is described in detail. Figure 1 This is a diagram illustrating the configuration of a display device according to one embodiment of the present disclosure.

[0030] Figure 1 This is a diagram illustrating a display system using a display driver device according to one embodiment of the present disclosure. For example... Figure 1 As shown, the display device 100 includes a display panel 110 and a display driver 115, and the display driver 115 includes a timing controller 120, a data driver 130 and a strobe driver 140.

[0031] The display panel 110 includes: a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, which are arranged to intersect each other and define a plurality of pixel regions; and a pixel P disposed in each of the plurality of pixel regions. The plurality of gate lines GL1 to GLn may be arranged in the horizontal direction and the plurality of data lines DL1 to DLm may be arranged in the vertical direction, but this disclosure is not necessarily limited thereto.

[0032] The display panel 110 may be a liquid crystal display (LCD) panel. When the display panel 110 is an LCD panel, the display panel 110 includes thin film transistors (TFTs) formed in a pixel region defined by multiple gate lines GL1 to GLn and multiple data lines DL1 to DLm, and liquid crystal cells connected to the TFTs.

[0033] The TFT transmits data signals supplied via data lines DL1 to DLm to the liquid crystal cell in response to the scan pulses supplied via the gate lines GL1 to GLn.

[0034] A liquid crystal cell consists of a common electrode containing liquid crystal facing each other and sub-pixel electrodes connected to a TFT, and can therefore be equivalently represented as a liquid crystal capacitor CLc. The liquid crystal cell includes a storage capacitor Cst connected to the gate line of the previous stage to maintain a voltage corresponding to the source signal charged in the liquid crystal capacitor CLc until a voltage corresponding to the next source signal is charged.

[0035] Meanwhile, the pixel area of ​​the display panel 110 may include red (R) subpixels, green (G) subpixels, blue (B) subpixels, and white (W) subpixels. Each subpixel may be formed repeatedly in the row direction or in a 2×2 matrix. In this case, a color filter corresponding to each color is provided in each of the red (R), green (G), and blue (B) subpixels, but no separate color filter is provided in the white (W) subpixels. In one embodiment, the red (R), green (G), blue (B), and white (W) subpixels may be formed with the same area ratio, but they may also be formed with different area ratios.

[0036] Furthermore, although the display panel 110 is described as an LCD panel, the display panel 110 may be an OLED display panel in which an organic light-emitting diode (OLED) is formed in each pixel area.

[0037] The timing controller 120 receives various timing signals from an external system (not shown), including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK, and generates a data control signal DCS for controlling the data driver 130 and a gating control signal GCS for controlling the gating driver 140. Furthermore, the timing controller 120 receives image data RGB from the external system, converts the received image data RGB into image data RGB' that can be processed by the data driver 130, and outputs the converted image data RGB'.

[0038] The data control signal DCS may include the source start pulse SSP, the source sampling clock SSC, the source output enable signal SOE, etc., and the gating control signal GCS may include the gating start pulse GSP, the gating shift clock GSC, the gating output enable signal GOE, etc.

[0039] Here, the source start pulse controls the data sampling start timing of the n source driver integrated circuits (ICs) (not shown) of the configuration data driver 130. The source sampling clock is a clock signal that controls the sampling timing of the data in each source driver IC. The source output enable signal controls the output timing of each source driver IC.

[0040] The timing controller 120 generates a gating control signal GCS, which includes a gating start pulse GSP, a gating shift clock GSC, and a gating output enable signal GOE.

[0041] The strobe start pulse controls the start timing of the operation of m strobe driver ICs (not shown) configured in the strobe driver 140. The strobe shift clock is a clock signal that is input to one or more strobe driver ICs and controls the shift timing of the scan signal (strobe pulse). The strobe output enable signal specifies the timing information for one or more strobe driver ICs.

[0042] The timing controller 120 aligns the RGB values ​​of image data received from an external system. Specifically, the timing controller 120 aligns the RGB' image data to match the structure and characteristics of the display panel 110. The timing controller 120 then transmits the aligned RGB' image data to the data driver 130.

[0043] In one embodiment of this disclosure, the timing controller 120 may output signals for controlling the first switch 135b and the second switch 135c of the output buffer unit 135, as will be described below. The timing controller 120 may output control signals for periodically turning the first switch 135b and the second switch 135c on or off. For example, the timing controller 120 may output signals for controlling the first switch 135b and the second switch 135c based on the data enable signal DE.

[0044] The gating driver 140 outputs a gating signal synchronized with the source signal generated by the data driver 130 to the gating line according to the timing signal generated by the timing controller 120. Specifically, the gating driver 140 outputs a gating signal synchronized with the source signal to the gating line according to the gating start pulse, gating shift clock and gating output enable signal generated by the timing controller 120.

[0045] The gating driver 140 includes a gating shift register circuit, a gating level shifter circuit, etc. Here, the gating shift register circuit can be directly formed on the TFT array substrate of the display panel 110 using a gating in-panel (GIP) process. In this case, the gating driver 140 supplies a gating start pulse and a gating shift clock to the gating shift register formed on the TFT array substrate using the GIP process.

[0046] Data driver 130 converts aligned image data RGB' into a source signal based on a timing signal generated by timing controller 120. Specifically, data driver 130 converts aligned image data RGB' into a source signal based on a source start pulse, a source sampling clock, and a source output enable signal. Data driver 130 outputs a source signal corresponding to one horizontal line to the data line for each horizontal cycle in which a strobe signal is provided to the strobe line. Here, data driver 130 can receive a gamma voltage from a gamma voltage generator (not shown) and use the gamma voltage to convert aligned image data RGB' into a source signal. (Refer to...) Figure 2 and Figure 3 A detailed description of a data driver 130 according to one embodiment of the present disclosure.

[0047] Power supply 150 generates various voltages required by gating driver 140 and data driver 130. For example, power supply 150 generates analog and digital power supplies by boosting or lowering the system voltage. Analog power supplies may include reference voltage, common voltage, gamma voltage, gating high voltage, gating low voltage, etc., and digital power supplies may include digital logic voltages, etc.

[0048] In the following text, reference will be made to Figure 2 and Figure 3 A data driver according to one embodiment of this disclosure is described in detail. Figure 2 This is a schematic block diagram of a data driver according to one embodiment of the present disclosure, and Figure 3 This is a circuit diagram illustrating a low-dropout (LDO) unit and an output buffer unit according to one embodiment of the present disclosure.

[0049] The data driver 130 converts aligned image data RGB' into source signals based on timing signals generated by the timing controller 120.

[0050] Therefore, such as Figure 2 As shown, the data driver 130 includes a shift register unit 131, a latch unit 132, a level shifter unit 133, a digital-to-analog converter unit 134, and an output buffer unit 135.

[0051] The shift register unit 131 receives the source start pulse and the source sampling clock from the timing controller 120, and shifts the source start pulse sequentially according to the source sampling clock to output the sampling signal. The shift register unit 131 sends the sampling signal to the latch unit 132.

[0052] The latch unit 132 samples and latches image data sequentially in predetermined units according to the sampling signal. The latch unit 132 then sends the latched image data to the level shifter unit 133.

[0053] The level shifter unit 133 amplifies the level of the latched image data. Specifically, the level shifter unit 133 amplifies the level of the image data to a level that can drive the digital-to-analog converter unit 134. The level shifter unit 133 then sends its amplified image data to the digital-to-analog converter unit 134.

[0054] The digital-to-analog converter unit 134 converts the image data into a source signal that is an analog signal. The digital-to-analog converter unit 134 then sends the source signal, which has been converted into an analog signal, to the output buffer unit 135.

[0055] According to one embodiment of this disclosure, the output buffer unit 135 outputs a source signal or a porch signal to the data line DL based on the switching operations of the switching units 135b and 135c, which will be described later. Specifically, the output buffer unit 135 can buffer and output a source signal to the data line DL based on a source output enable signal generated by the timing controller 120, or output a porch signal received from the LDO unit 151 of the power supply 150 to the data line DL.

[0056] As described above, the display panel 110 displays an image including periodic frames based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK input to the timing controller 120.

[0057] like Figure 3 As shown, according to one embodiment of the present disclosure, the output buffer unit 135 includes a buffer 135a and switching units 135b and 135c.

[0058] According to one embodiment of this disclosure, the buffer 135a is turned on or off according to the switching operations of the switching units 135b and 135c, which will be described later.

[0059] Depending on the switching states of switching units 135b and 135c, buffer 135a receives the source signal via the input line or the edge signal from LDO unit 151, buffers the received signal, and outputs the buffered signal via the output line.

[0060] Switching units 135b and 135c include a first switch 135b and a second switch 135c connecting the LDO unit 151 and the buffer 135a. Specifically, the first switch 135b controls the connection between the input lines of the LDO unit 151 and the buffer 135a, and the second switch 135c controls the connection between the output lines of the LDO unit 151 and the buffer 135a.

[0061] In one embodiment of this disclosure, when the first switch 135b is turned on and the second switch 135c is turned off, the buffer 135a is activated and the edge signal output from the LDO unit 151 is input to the input line of the buffer 135a. Therefore, the output buffer unit 135 buffers the edge signal V input from the LDO unit 151. P And the buffered edge signal V P Output to data line DL.

[0062] In one embodiment of this disclosure, the switching states of switching units 135b and 135c can be controlled according to a control signal output from the timing controller 120. For example, switching units 135b and 135c receive signals for controlling switching units 135b and 135c according to a data enable signal DE from the timing controller 120, and switching units 135b and 135c can be periodically turned on or off. However, this disclosure is not limited thereto, and switching units 135b and 135c can be periodically turned on or off without a separate control signal.

[0063] According to one embodiment of this disclosure, since the output buffer unit 135 outputs the received edge signal to the data line DL through the buffer 135a, the output buffer unit 135 can quickly drive the display panel in response to a high frame rate.

[0064] In one embodiment of this disclosure, when the first switch 135b is open and the second switch 135c is closed, the buffer 135a is closed and the edge signal V output from the LDO unit 151 is... P The signal is input to the output line of buffer 135a. Therefore, output buffer unit 135 will receive the edge signal V input from LDO unit 151. P Output to data line DL.

[0065] According to one embodiment of this disclosure, since the buffer 135a is turned off during a portion of the blanking period, the power consumed by the output buffer unit 135 in driving the display panel can be reduced.

[0066] According to one embodiment of this disclosure, even when buffer 135a is closed, output buffer unit 135 will still receive the edge signal V input from LDO unit 151. P Output to data line DL to prevent leakage current in display panel 110 and reduce quiescent current in buffer 135a.

[0067] According to one embodiment of this disclosure, the edge signal V P It can have intermediate values ​​within the range of the source signal. Additionally, the edge signal V... P It can vary depending on the amount of leakage current in the display panel 110.

[0068] According to one embodiment of this disclosure, the first switch 135b and the second switch 135c can be switched periodically. For example, the first switch 135b is turned on at the end of the data enable signal DE input to the timing controller 120 and remains on for a period of time up to a horizontal level, and the second switch 135c is turned on at the time the first switch 135b is turned off and remains on until the start of the data enable signal DE input to the timing controller 120. This will be referred to... Figures 4 to 6 Detailed description.

[0069] When both the first switch 135b and the second switch 135c are open, the buffer 135a is turned on, and the source signal is input from the digital-to-analog converter unit 134 to the input line of the buffer 135a. Therefore, the output buffer unit 135 buffers the source signal input from the digital-to-analog converter unit 134 and outputs the buffered source signal to the data line DL.

[0070] According to one embodiment of this disclosure, LDO unit 151 is connected to output buffer unit 135 and supplies edge signals to output buffer unit 135. Specifically, LDO unit 151 is connected to the input line of buffer 135a via a first switch 135b and to the output line of buffer 135a via a second switch 135c. That is, depending on the switching states of the first switch 135b and the second switch 135c, buffer 135a is turned on or off, and LDO unit 151 supplies edge signals to either the input or output line of buffer 135a.

[0071] LDO unit 151 may be included in the aforementioned power supply 150 and may supply edge signals to output buffer unit 135. However, this disclosure is not limited thereto, and LDO unit 151 may be included in output buffer unit 135, may receive voltage supplied from power supply 150 to data driver 130, and may generate edge signals and supply edge signals to output buffer unit 135.

[0072] The following will refer to Figures 4 to 5C The switching operations of the first switch 135b and the second switch 135c, and the corresponding signals output from the output buffer unit 135, are described.

[0073] In the following text, reference will be made to Figures 4 to 6 A method for driving a display according to one embodiment and another embodiment of the present disclosure is described in detail. Figure 4 This is a timing diagram illustrating a method for driving a display panel according to one embodiment of the present disclosure, and Figures 5A to 5C This is a circuit diagram illustrating the operation of an output buffer unit according to one embodiment of the present disclosure. Figure 6This is a timing diagram illustrating a method for driving a display panel according to another embodiment of the present disclosure.

[0074] Display panel 110 displays an image comprising periodic frames based on the vertical synchronization signal Vsync, horizontal synchronization signal Hsync, data enable signal DE, and clock signal CLK input to timing controller 120. Specifically, as Figure 4 As shown, the display panel 110 is driven by dividing the data enable signal DE into an active period (ACTIVE) and a blanking period (BLANK). Specifically, as... Figure 4 As shown, the data driver 130 outputs either the source signal IMG or the edge signal V based on the data enable signal DE. P For example, when the data enable signal DE is high, the data driver 130 can output the source signal IMG to drive the display panel 110 for an active period, and when the data enable signal DE is low, the data driver 130 can output the edge signal V. P The blanking period is defined as the time period for driving the display panel 110. At this time, the blanking period can include a first porch period PT1 driven by a first porch mode PM1 and a second porch period PT2 driven by a second porch mode PM2.

[0075] like Figure 4 and Figure 5A As shown, in the first edge mode PM1, the first switch 135b is turned on and the second switch 135c is turned off, and the output buffer unit 135 outputs the edge signal V buffered by the buffer 135a. p Specifically, the first switch 135b is turned on in the first edge mode PM1, so the LDO unit 151 is connected to the input line of the buffer 135a, and the second switch 135c is turned off, so the LDO unit 151 is not connected to the output line of the buffer 135a. Therefore, the buffer 135a is turned on and receives the edge signal V from the LDO unit 151 through the input line. P It buffers the received edge signals and outputs the buffered edge signals to the data line DL.

[0076] The first switch 135b is turned on at the end of the data enable signal DE. At this time, the data enable signal DE is a periodically output signal, and the first switch 135b is turned on periodically according to the data enable signal DE. For example, the first switch 135b can be turned on at the end of the data enable signal DE, and can be turned off after remaining on for one horizontal cycle.

[0077] According to one embodiment of this disclosure, since the output buffer unit 135 receives the edge signal V through the buffer 135a... P The output is sent to the data line DL, so the output buffer unit 135 can be driven quickly in response to high frame rate images.

[0078] like Figure 4 and Figure 5B As shown, in the second edge mode PM2, the first switch 135b is open and the second switch 135c is closed, and the output buffer unit 135 outputs the edge signal V input from the LDO unit 151. p Specifically, in the second edge mode PM2, the first switch 135b is turned off, so the LDO unit 151 is not connected to the input line of the buffer 135a, and the second switch 135c is turned on, so the LDO unit 151 is connected to the output line of the buffer 135a. Therefore, the buffer 135a is turned off, and the output buffer unit 135 receives the edge signal V from the LDO unit 151 through the output line of the buffer 135a. P and the input edge signal V P Output to data line DL. At this time, the edge signal V... P It can have intermediate values ​​within the range of the source signal IMG, and the edge signal V P The same value is found in the first edge mode PM1 and the second edge mode PM2. Additionally, as... Figure 6 As shown, the edge signal V P The edge signal V can have different values ​​in different first edge modes PM1, or different values ​​in different second edge modes PM2. P This can vary depending on the amount of leakage current in the display panel 110. Therefore, the output buffer unit 135 converts the edge signal V in the first edge mode PM1 and the second edge mode PM2. P The current is supplied to the display panel 110 to prevent leakage current from the display panel 110.

[0079] According to one embodiment of this disclosure, since the buffer 135a is turned off in the second edge mode PM2, the power consumed by the output buffer unit 135 can be reduced.

[0080] like Figure 4As shown, the second switch 135c is turned on according to the switching state of the first switch 135b, and turned off according to the data enable signal DE. Specifically, the second switch 135c is turned on at the time when the first switch 135b is off, and turned off at the time when the data enable signal DE begins. For example, when the first switch 135b is turned on for one horizontal cycle from the time when the data enable signal DE ends and then turns off, the second switch 135c can be turned on, remain on until the time when the data enable signal DE begins, and then be turned off.

[0081] According to one embodiment of this disclosure, even when buffer 135a is closed, output buffer unit 135 will still receive the edge signal V input from LDO unit 151. P The output is sent to the data line DL, thereby preventing leakage current in the display panel 110 and reducing the quiescent current of the buffer 135a.

[0082] According to one embodiment of this disclosure, the data driver 130 operates in active mode AM during the active period when the source signal IMG is input to the display panel 110.

[0083] The data driver 130 operates in active mode AM and buffers the source signal IMG input from the digital-to-analog converter unit 134, and outputs the buffered source signal IMG to the data line DL.

[0084] like Figure 4 and Figure 5C As shown, the first switch 135b and the second switch 135c are open in active mode AM, and the output buffer unit 135 outputs the source signal IMG buffered by the buffer 135a. Specifically, in active mode AM, both the first switch 135b and the second switch 135c are open, so the LDO unit 151 is not connected to the input and output lines of the buffer 135a. Therefore, the buffer 135a is turned on to receive the source signal IMG from the digital-to-analog converter unit 134 through the input line of the buffer 135a, buffers the received source signal IMG, and outputs the buffered source signal IMG to the data line DL.

[0085] In the following text, reference will be made to Figure 7 A method for driving a display according to yet another embodiment of the present disclosure is described in detail. Figure 7 This is a timing diagram illustrating a method for driving a display panel according to yet another embodiment of the present disclosure.

[0086] Reference Figure 7 The display panel 110 receives the source signal IMG or the edge signal V based on the data enable signal DE. PThe display panel 110 is driven by the data enable signal DE to receive the source signal IMG during the effective period ACTIVE and the receive edge signal V between the effective period ACTIVE. P The blanking period is defined as follows. For example, the display panel 110 can receive the source signal IMG when the data enable signal DE is high to be driven as the active period, and can receive the edge signal when the data enable signal DE is low to be driven as the blanking period. To this end, the data driver 130 outputs either the source signal IMG or the edge signal V based on the data enable signal DE. p The data driver 130 outputs the source signal IMG during the active period and the edge signal V during the blanking period. p .

[0087] According to another embodiment of this disclosure, the blanking period (BLANK) may include a first edge period (PT1) driven by a first edge mode (PM1), a second edge period (PT2) driven by a second edge mode (PM2), and a frame skipping period (FST) driven by the second edge mode (PM2). The frame skipping period (FST) is a period in which the same image as the source signal IMG input in the previous active period (ACTIVE) is displayed, and therefore no separate new source signal is input. Therefore, the data driver 130 is driven in the second edge mode (PM2) during the frame skipping period (FST), just as it was driven in the second edge mode (PT2) immediately preceding the frame skipping period (FST). That is, during the frame skipping period (FST), the data driver 130 is driven by maintaining the second edge mode (PM2) immediately preceding the frame skipping period (FST). Furthermore, according to another embodiment of this disclosure, the data driver 130 is driven not only when the second edge mode (PM2) is the frame skipping period (FST), but also until the data enable signal (DE) is input.

[0088] According to this disclosure, the data driver can provide an edge signal to the display panel during the blanking period, thereby preventing current leakage from the display panel.

[0089] Furthermore, according to this disclosure, there is an effect that the display panel can be driven quickly and the image can be displayed even when the frame rate of the image is high.

[0090] Furthermore, according to this disclosure, the edge signal can be changed during each blanking period, thereby preventing leakage current changes in the display panel.

[0091] Furthermore, according to this disclosure, the buffer can be turned off during a portion of the blanking period, thereby reducing the quiescent current of the buffer.

[0092] Therefore, it should be understood that the above embodiments are not restrictive in any respect but illustrative. The scope of this disclosure is defined by the appended claims rather than the specific embodiments, and it should be understood that all substitutions or modifications derived from the meaning and scope of the appended claims and their equivalents fall within the scope of this disclosure.

[0093] Cross-references to related applications

[0094] This application claims the benefit of Korean Patent Application No. 10-2020-0144493, filed on November 2, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display driving device configured to provide a signal to a display panel, the display panel being driven to receive an active period of a source signal corresponding to image data and a blanking period of not receiving the source signal, the display driving device comprising: An output buffer unit is configured to output the source signal to the display panel during the effective time period and to output an edge signal to the display panel during the blanking time period. as well as A low-dropout LDO unit, configured to supply the edge signal to the output buffer unit. The output buffer unit includes a buffer configured to output the source signal or the edge signal to the display panel, a first switch configured to switch the connection between the LDO unit and the input line of the buffer, and a second switch configured to switch the connection between the LDO unit and the output line of the buffer. The buffer is turned on or off according to the switching state of each of the first and second switches, and When the first switch is turned on and the second switch is turned off, the output buffer unit receives the edge signal from the LDO unit, buffers and outputs the received edge signal.

2. The display driver device according to claim 1, wherein, When the first switch is turned on and the second switch is turned off, the buffer is activated, and The buffer is closed when the first switch is open and the second switch is closed.

3. The display driver device according to claim 1, wherein, When one of the first switch and the second switch is turned on, the output buffer unit outputs the edge signal, and When both the first switch and the second switch are open, the output buffer unit outputs the source signal.

4. The display driver device according to claim 1, wherein, When the first switch is open and the second switch is closed, the output buffer unit outputs the edge signal received from the LDO unit.

5. The display driver device according to claim 1, wherein, When the first switch is open and the second switch is open, the buffer is turned on to receive the source signal from the digital-to-analog converter connected to the input line of the buffer, and buffers and outputs the received source signal.

6. The display driving device according to claim 1, wherein, The edge signal has an intermediate value within the range of the source signal.

7. The display driver device according to claim 1, wherein, When the first switch is turned on and the second switch is turned off, the output buffer unit operates in the first edge mode where the buffer is enabled, and outputs the edge signal. When the first switch is open and the second switch is closed, the output buffer unit operates in the second edge mode where the buffer is closed, and outputs the edge signal. The edge signal has the same value in the first edge mode and the second edge mode of the output buffer unit, and has different values ​​in the different first edge modes of the output buffer unit and different values ​​in the different second edge modes of the output buffer unit.

8. The display driving device according to claim 7, wherein, The blanking period includes a first edge period, a second edge period, and a frame skipping period, and The output buffer unit is driven in the first edge mode during the first edge period and in the second edge mode during the frame skipping period and the second edge period.

9. The display driver device according to claim 1, wherein, The first switch is periodically turned on according to a data enable signal that enables the source signal to be input to the display panel.

10. The display driving device according to claim 1, wherein, The second switch is turned on at the time when the first switch is turned off, and turned off at the time when the data enable signal that enables the source signal to be input to the display panel begins.

11. A display driving method for providing signals to a display panel, the display panel being driven to receive an effective period of a source signal corresponding to image data and a blanking period during which the source signal is not received, the display driving method comprising the following operations: The output buffer unit operates in a first edge mode to enable the buffer, and the output buffer unit receives the edge signal from the LDO unit, buffers the received edge signal, and outputs it to the display panel. During the operation of the output buffer unit in the first edge mode, the first switch of the output buffer unit is turned on and the second switch of the output buffer unit is turned off; and The output buffer unit operates in a second edge mode such that the buffer of the output buffer unit is turned off, and the output buffer unit outputs the edge signal to the display panel; as well as The output buffer unit operates in an active mode, which enables the buffer of the output buffer unit and outputs a source signal containing pixel information to the display panel.

12. The display driving method according to claim 11, wherein, During the operation of the output buffer unit in the second edge mode, the first switch is off and the second switch is on, and During the operation of the output buffer unit in the effective mode, the first switch is open and the second switch is open.

13. The display driving method according to claim 12, wherein, The second switch is turned on according to the on / off state of the first switch, and The second switch is periodically turned off according to a data enable signal that allows the source signal to be input to the display panel.

14. The display driving method according to claim 11, wherein, The first switch of the output buffer unit is periodically turned on according to a data enable signal that allows the source signal to be input to the display panel.

15. The display driving method according to claim 11, wherein, The edge signal has an intermediate value within the voltage range of the source signal.

16. The display driving method according to claim 11, wherein, The edge signal has the same value in the first edge mode and the second edge mode of the output buffer unit, and has different values ​​in the different first edge modes of the output buffer unit, and has different values ​​in the different second edge modes of the output buffer unit.

17. The display driving method according to claim 11, wherein, During the operation of the output buffer unit in the first edge mode, the display panel is driven to the first edge period, and During the operation of the output buffer unit in the second edge mode, the display panel is driven for a second edge period and a frame skipping period.

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