Stacked memory and method of manufacturing the same

Abstract

The application discloses a stacked memory and a manufacturing method thereof, comprising: a plurality of memory dies, each memory die having an independent fuse information, the fuse information being obtained by fusing a preset number of fuses arranged in the memory die according to a fuse fusing arrangement mode, and the fuse fusing arrangement mode of the preset number of fuses in each memory die being sequentially determined according to a stacked memory manufacturing process; and each memory die being individually selected and controlled by a signal containing the fuse information. On the basis of removing a logic die, a fuse arrangement mode is sequentially determined for each memory die in the stacked memory manufacturing process, so as to obtain an independent fuse information, thereby each memory die can be individually selected and controlled by a signal containing the fuse information, and a through silicon via is not needed on each memory die to distinguish memory partitions, and the effect of reducing the through silicon via and saving cost can be achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a stacked memory and its manufacturing method. Background Technology

[0002] Currently, in the manufacturing scheme of stacked memory, memory dies including memory arrays and control dies including peripheral circuits are fabricated separately. Multiple memory dies and control dies are then stacked and packaged, and the stacked dies are electrically connected to each other through through silicon vias (TSVs).

[0003] Since through-silicon vias (TSVs) occupy a certain amount of space on the die, and in order to increase the chip density of memory, the number of TSVs needs to be reduced, but the current stacked dies are distinguished by TSVs to differentiate memory partitions. Each stacked memory partition is called a repository, and the repository can be accessed independently for read and write operations. Therefore, these TSVs are indispensable. Summary of the Invention

[0004] The purpose of this application is to provide a stacked memory and a method for manufacturing the same, addressing the shortcomings of the prior art. This purpose is achieved through the following technical solutions.

[0005] The first aspect of this application proposes a stacked memory, comprising:

[0006] Multiple memory dies;

[0007] Each of the plurality of memory dies has independent fuse information. The fuse information is obtained by melting a preset number of fuses set in the memory die according to the fuse melting arrangement and combination method. The fuse melting arrangement and combination method in each memory die is determined sequentially according to the manufacturing process of the stacked memory.

[0008] Each of the aforementioned storage dies is individually selected and controlled by a signal containing fuse information.

[0009] A second aspect of this application discloses a method for manufacturing a stacked memory, the method comprising:

[0010] Provides multiple storage dies;

[0011] Each of the plurality of memory dies is extended vertically and stacked together sequentially through through-silicon vias;

[0012] For each memory die, the fuse arrangement is determined according to the stacking order, and the fuses in the memory die are melted according to the fuse arrangement to obtain the fuse information of the memory die.

[0013] A third aspect of this application provides an electronic device including a stacked memory as described in the first aspect above.

[0014] Based on the aforementioned stacked memory and its manufacturing method, in the prior art, each stacked partition is selected and controlled by logic die signals. That is, the prior art distinguishes and controls along the vertical direction. However, this application, by removing the logic die, sequentially determines a certain number of fuse arrangements for each memory die during the stacked memory manufacturing process. The fuses in the memory die are then melted according to the determined fuse arrangements to obtain independent fuse information. Thus, each memory die can be individually selected and controlled by a signal containing the fuse information. In other words, this application distinguishes and controls along the horizontal direction. Therefore, through-silicon vias (TSVs) are no longer needed to distinguish memory partitions on each memory die, thereby reducing TSVs, saving costs, and facilitating increased memory density. Furthermore, removing the logic die also reduces chip thickness. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 This application illustrates a schematic diagram of a stacked memory structure in a related art.

[0017] Figure 2 This is a schematic diagram illustrating the structure of a stacked memory according to an exemplary embodiment of this application;

[0018] Figure 3 This is a flowchart illustrating an embodiment of a method for manufacturing a stacked memory according to an exemplary embodiment of this application. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0022] See Figure 1 The stacked memory in the prior art shown includes memory dies and logic dies that are sequentially stacked in a vertical direction. The dies are electrically connected to each other through through-silicon vias. The memory dies provide memory processing functions for storing data, and the logic dies provide standard memory access coordination functions, such as page table translation, address mapping, and write combination.

[0023] In some embodiments, such as Figure 1 As shown, the stacked memory also includes processing units and a packaging substrate stacked with the die.

[0024] The processing unit is either a programmable processing unit or a reprogrammable processing unit. In some embodiments, the reprogrammable processing unit includes logic circuitry that can be dynamically programmed to perform various functions or execute certain instructions. In one embodiment, the reprogrammable processing unit may be configured to execute instructions that include memory processing functions controlling the memory die. Furthermore, the reprogrammable processing unit may include, but is not limited to, field-programmable gate arrays, application-specific integrated circuits, programmable array logic, and other similar devices. The package substrate may be configured to communicate with other components or dies and externally throughout the system.

[0025] In terms of storage, Figure 1 Each memory die is divided into n memory partitions, each partition includes several memory banks, and each partition is stacked on top of each other in a vertical direction through through-silicon vias. Each stacked group of partitions can be called a vault. The processing unit can independently access each vault through the logic die for read and write operations.

[0026] However, the current contradiction is that in order to increase the storage density of memory, the number of through-silicon vias (TSVs) needs to be reduced, but the storage partitions of the memory die also need TSVs to distinguish them, so they cannot be reduced.

[0027] It should be noted that the above Figure 1 The example shown only depicts one logic die, but the actual product does not limit the number of logic dies.

[0028] To address the aforementioned technical issues and reduce the number of through-silicon vias (TSVs) on the stacked dies, logic dies are removed, and only memory dies are used, extending vertically and stacked sequentially. For each memory die, a fuse arrangement is determined according to the stacking order, and the fuses in the memory die are blown according to the fuse arrangement to obtain the fuse information of the memory die. Thus, each memory die can be individually selected and controlled by a signal containing fuse information.

[0029] See Figure 2 This application illustrates a stacked memory according to an exemplary embodiment, comprising: n memory dies, each of the n memory dies having independent fuse information.

[0030] The fuse information is obtained by melting a preset number of fuses on the memory die according to a fuse-breaking arrangement. The fuse-breaking arrangement of the preset number of fuses on each memory die is determined sequentially according to the stacked memory manufacturing process, and each memory die can be individually selected and controlled by a signal containing the fuse information. For example, this signal can be generated and controlled by a processing unit.

[0031] To ensure the uniqueness of the fuse information for each memory die, the number of fuses set in the memory die can be determined based on the number of memory dies. For example, if there are 4 memory dies, then each memory die needs at least 2 fuses. That is, there are four possible fuse arrangements: 00, 01, 10, and 11. Each memory die corresponds to one fuse arrangement, where 0 indicates no fuse and 1 indicates fuse.

[0032] In some embodiments, each memory die includes a memory array and a control peripheral circuitry.

[0033] For example, starting from the first memory die at the top, the second memory die, the third memory die, ... the nth memory die are stacked together in sequence along the vertical direction. Thus, according to the stacking order, a circuit breaker arrangement 1 is determined for the first memory die, and circuit breaker information 1 is obtained. A circuit breaker arrangement 2 is determined for the second memory die, and circuit breaker information 2 is obtained. And so on, a circuit breaker arrangement n is determined for the nth memory die, and circuit breaker information 3 is obtained.

[0034] Based on the above description, by comparing the stacked memory conceived in this application with the prior art, the partitions of each stack in the prior art are selected and controlled by logic die signals. That is, the prior art distinguishes and controls along the vertical direction. In contrast, this application, by removing the logic die, sequentially determines a certain number of fuse arrangements for each memory die during the stacked memory manufacturing process. The fuses in the memory die are then fused according to the determined fuse arrangements to obtain an independent fuse information. Thus, each memory die can be individually selected and controlled by a signal containing the fuse information. Therefore, there is no need for through-silicon vias (TSVs) to distinguish memory partitions on each memory die, thereby reducing TSVs, saving costs, and facilitating increased memory density. Furthermore, by removing the logic die, the chip thickness can also be reduced.

[0035] It should be noted that the fuse information for each storage die is obtained by fusing the fuses in a predetermined arrangement during the stacking process.

[0036] For example, the fuse set in the storage die can be an electric fuse, or of course a metal fuse; this application does not limit this.

[0037] In some embodiments, in order to enable communication between n memory dies, through-silicon vias (TSVs) may be provided at the same location on each of the n memory dies.

[0038] The through-silicon vias are used to electrically connect the n memory dies.

[0039] It should be noted that, since this application does not require through-silicon vias (TSVs) to distinguish memory partitions compared to existing technologies, the number of TSVs on each memory die in this application is much smaller than the number of TSVs on stacked dies in existing technologies.

[0040] In one example, both the prior art and this application utilize the same number of memory dies with the same storage capacity for stacking. However, because the prior art requires the use of through-silicon vias (TSVs) to distinguish storage partitions, each memory die after stacking typically requires the fabrication of more than 1000 ea TSVs for electrical connection. In contrast, this application does not require the use of TSVs to distinguish storage partitions, and each memory die after stacking only needs to have 200 ea to 400 ea TSVs fabricated.

[0041] In some embodiments, the stacked memory may further include a switch circuit electrically connected to each memory die for sending a signal to the corresponding memory die based on fuse information of the memory die contained in the signal.

[0042] The signal can be generated by the processing unit according to actual needs and sent to the switch selection circuit, or it can be generated by the processing unit according to the control command generated by the external controller and sent to the switch selection circuit.

[0043] The signal can be a row active command or a column active command.

[0044] For example, the switch selection circuit can be constructed using a pass-gate structure or a logic circuit device.

[0045] Based on the above Figure 2 The stacked memory structure shown below will be described in detail with specific embodiments of the manufacturing method of the stacked memory proposed in this application.

[0046] Figure 3 This is a flowchart illustrating an embodiment of a method for manufacturing a stacked memory according to an exemplary embodiment of this application, as shown below. Figure 3 As shown, the manufacturing method of the stacked memory includes the following steps:

[0047] Step 301: Provide multiple raw memory dies.

[0048] Each memory die includes a memory array and peripheral drive circuitry, and each memory die is a valid die that has passed testing.

[0049] Step 302: Stack each of the plurality of memory dies together in a vertical direction through through-silicon vias.

[0050] Step 303: For each memory die, determine the fuse arrangement and combination for the memory die according to the stacking order, and fuse the fuses in the memory die according to the fuse arrangement and combination to obtain the fuse information of the memory die.

[0051] In this process, the fuse information for each storage die is obtained by fusing the fuses in a predetermined arrangement and combination.

[0052] For the processes of steps 301 to 303 above, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated.

[0053] This completes the above. Figure 3 The illustrated embodiment demonstrates a manufacturing process for a stacked memory, which can form a stacked memory requiring a small number of through-silicon vias, providing a prerequisite for increasing the chip density of the memory.

[0054] This application also proposes an electronic device, which includes the features described above. Figure 2 The stacked memory.

[0055] For example, the stacked memory can be any one of dynamic random access memory (DRAM), thyristor random access memory (TRAM), static random access memory (SRAM), and non-volatile memory (such as read-only memory, flash memory, ferroelectric random access memory, magnetoresistive random access memory, etc.).

[0056] In some embodiments, the electronic device may include a smartphone, computer, tablet, wearable smart device, artificial intelligence device, or power bank.

[0057] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0058] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A stacked memory comprising a plurality of memory dies, characterized in that, Each of the plurality of memory dies has independent fuse information. The fuse information is obtained by melting a preset number of fuses set in the memory die according to the fuse melting arrangement and combination method. The fuse melting arrangement and combination method of the preset number of fuses in each memory die is determined sequentially according to the manufacturing process of the stacked memory. Each of the aforementioned storage dies is individually selected and controlled by a signal containing fuse information; Also includes: A switch selection circuit electrically connected to each memory die is used to send the signal to the memory die corresponding to the fuse information based on the fuse information of the memory die contained in the signal. The switch selection circuit is composed of a gate-conducting structure or a logic circuit. The signal is a row activation command or a column activation command.

2. The memory according to claim 1, characterized in that, The fuse in the storage die is an electric fuse and / or a metal fuse.

3. The memory according to claim 1, characterized in that, A through-silicon via is provided at the same location on each of the plurality of memory dies; The through-silicon vias are used to electrically connect the plurality of memory dies.

4. A method for manufacturing a stacked memory, characterized in that, The method for fabricating the stacked memory as described in any one of claims 1 to 3 comprises: Provides multiple storage dies; Each of the plurality of memory dies is extended vertically and stacked together sequentially through through-silicon vias; For each memory die, the fuse arrangement is determined according to the stacking order, and the fuses in the memory die are melted according to the fuse arrangement to obtain the fuse information of the memory die.

5. An electronic device comprising a stacked memory as described in any one of claims 1 to 3.

6. The electronic device according to claim 5 includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

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