Integrated circuit including a cell array with word line assist cells

Abstract

The present disclosure relates to an integrated circuit including a cell array having word line assist cells. The integrated circuit includes a cell array including a plurality of storage cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column, a plurality of word lines respectively extending over a plurality of first rows of the cell array and connected to the plurality of storage cells and the plurality of word line assist cells, and a row driver configured to drive the plurality of word lines.

Description

[0001] Intersection of related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0143879, filed with the Korean Intellectual Property Office on October 30, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to integrated circuits, and more specifically, to integrated circuits comprising a cell array having word line auxiliary units. Background Technology

[0004] Due to the demand for high integration and advancements in semiconductor manufacturing processes, the width, spacing, and / or height of wiring within integrated circuits can be reduced, while parasitic elements within the wiring can increase. Furthermore, the power supply voltage of integrated circuits can be lowered due to reduced power consumption and higher operating speeds; therefore, parasitic elements in the wiring can have a more significant impact on the integrated circuit. Despite the presence of parasitic elements, depending on the requirements of various applications, a stable, high-performance operating environment may be required for integrated circuit cell arrays with memory cells. Summary of the Invention

[0005] The present invention provides an integrated circuit and a method of operating the integrated circuit, the integrated circuit being configured to provide high or improved operational reliability despite the presence of parasitic elements.

[0006] According to one aspect of the present invention, an integrated circuit is provided, the integrated circuit comprising: a cell array including a plurality of memory cells in a plurality of first columns and a plurality of word line auxiliary cells in at least one second column; a plurality of word lines extending over a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line auxiliary cells; and a row driver configured to drive the plurality of word lines, wherein each of the plurality of word line auxiliary cells is configured to accelerate the activation of a corresponding word line among the plurality of word lines, and includes transistors identical to those of each of the plurality of memory cells, and has a footprint identical to that of each of the plurality of memory cells.

[0007] According to another aspect, an integrated circuit is provided, the integrated circuit comprising: a cell array including a plurality of cells, each of the plurality of cells including the same transistor and having the same occupied area; a plurality of word lines extending on a plurality of first rows of the cell array; and a row driver connected to the plurality of word lines, wherein the plurality of cells includes: a plurality of memory cells connected to the plurality of word lines and arranged in a series of first columns; a plurality of first word line auxiliary units connected to the plurality of word lines and arranged in a second column; and a plurality of second word line auxiliary units connected to the plurality of word lines and arranged in a third column adjacent to the second column, wherein each of the plurality of first word line auxiliary units may have a first layout symmetrical to a second layout of the second word line auxiliary units, the second word line auxiliary units being arranged in the same row as the plurality of first word line auxiliary units relative to an axis parallel to the column direction.

[0008] According to another aspect of the present invention, an integrated circuit is provided, the integrated circuit comprising: a cell array including a plurality of cells, each of the plurality of cells including the same transistor and having the same occupied area; a plurality of word lines extending on a plurality of first rows of the cell array; and a row driver connected to the plurality of word lines, wherein the plurality of cells includes: a plurality of first memory cells connected to the plurality of word lines and arranged in a series of first columns; a plurality of first word line auxiliary cells arranged in at least one second column adjacent to the series of first columns; and a plurality of second memory cells connected to the plurality of word lines and arranged in a series of third columns adjacent to the at least one second column. Attached Figure Description

[0009] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention;

[0011] Figure 2 This is a top view of the layout of a cell array according to an exemplary embodiment of the present invention;

[0012] Figure 3 This is a circuit diagram of an example of a memory cell and a word line auxiliary cell according to an exemplary embodiment of the present invention;

[0013] Figure 4This is a timing diagram illustrating a read operation according to an example embodiment of the present invention;

[0014] Figure 5 This is a circuit diagram of an example of a memory cell and a word line auxiliary cell according to an exemplary embodiment of the present invention;

[0015] Figure 6 This is a timing diagram illustrating a read operation according to an example embodiment of the present invention;

[0016] Figure 7 This is a top view of the layout of a cell array according to an exemplary embodiment of the present invention;

[0017] Figure 8 This is a top view of the layout of a cell array according to an exemplary embodiment of the present invention;

[0018] Figure 9 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention;

[0019] Figure 10 This is a top view of the layout of a cell array according to an exemplary embodiment of the present invention;

[0020] Figure 11 This is a circuit diagram illustrating an example of a storage unit, a word line auxiliary unit, a write auxiliary unit, and a dummy unit according to an exemplary embodiment of the present invention.

[0021] Figure 12 This is a top view of the layout of a cell array according to an exemplary embodiment of the present invention;

[0022] Figure 13A and Figure 13B This is a top view of the layout of an integrated circuit according to an exemplary embodiment of the present invention;

[0023] Figure 14 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention;

[0024] Figure 15 This is a flowchart illustrating a method of operating an integrated circuit according to an exemplary embodiment of the present invention;

[0025] Figure 16 This is a flowchart illustrating a method of operating an integrated circuit according to an exemplary embodiment of the present invention;

[0026] Figure 17 This is a flowchart illustrating a method of operating an integrated circuit according to an exemplary embodiment of the present invention; and

[0027] Figure 18 This is a block diagram of an example embodiment of a system-on-a-chip based on the present invention. Detailed Implementation

[0028] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements, and repeated descriptions of them are omitted. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Note that aspects described with respect to one embodiment may be incorporated into different embodiments, although they are not specifically described therein. That is, features of all embodiments and / or any embodiment may be combined in any manner and / or combination. Figure 1 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention. In detail, Figure 1 This is a block diagram of a memory device 10 included in an integrated circuit. In some embodiments, the integrated circuit may store data based on commands and addresses provided from around or outside the integrated circuit, and the memory device 10 may include a separate memory device. Furthermore, in some embodiments, the integrated circuit may also include other components for writing data to or reading data from the memory device 10, as described later with reference to 18, and the memory device 10 may include an embedded memory device. Figure 1 As shown, the memory device 10 may include a cell array 12, a row driver 14, a column driver 16, and control logic 18. Although in Figure 1 Although not shown in the figure, in some embodiments, the memory device 10 may also include an address buffer, a data buffer, a data input / output circuit, an internal voltage generator, etc.

[0029] The memory device 10 can receive commands (CMD), addresses, and data. For example, the memory device 10 can receive a command (CMD) indicating a write operation (which may be referred to as a write command), an address (which may be referred to as a write address), and data (which may be referred to as write data), and can store the received data in the area corresponding to the address in the cell array 12. Additionally, the memory device 10 can receive a command (CMD) indicating a read operation (which may be referred to as a read command) and an address, and can output the data stored in the area corresponding to the address in the cell array 12 to an external receiver.

[0030] Cell array 12 may include a plurality of memory cells accessed by word lines and bit lines, respectively. In some embodiments, the plurality of memory cells included in cell array 12 may include volatile memory cells, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc. In some embodiments, the plurality of memory cells included in cell array 12 may include non-volatile memory cells, such as flash memory, resistive random access memory (RRAM), etc. Exemplary embodiments will be described primarily with reference to SRAM cells, as will be referred to below. Figure 3Other figures are used to describe this. However, it should be noted that the example embodiments are not limited thereto.

[0031] refer to Figure 1 The cell array 12 may include a plurality of first memory cells MC1 in a series of first columns C1, a plurality of word line auxiliary cells in a series of second columns C2, and a plurality of second memory cells MC2 in a series of third columns C3. Each of the plurality of first memory cells MC1 may be connected to at least one of a plurality of first bit lines BL1 extending on the series of first columns C1, and may be connected to one of a plurality of word lines WL extending on a plurality of rows of the cell array 12. Similarly, each of the plurality of second memory cells MC2 may be connected to at least one of a plurality of second bit lines BL2 extending on a series of third columns C3, and may be connected to one of a plurality of word lines WL extending on a plurality of rows of the cell array 12.

[0032] Each of the plurality of word line auxiliary units arranged in the second column C2 can be connected to a pseudo bit line BLP extending on the second column C2, and can be connected to one of the plurality of word lines WL. The word line auxiliary unit (or word line assistance unit), also called a performance assistance unit (or performance assistance unit), can sense word line activation during write or read operations and can accelerate and regenerate word line activation. Therefore, the effects caused by parasitic elements of the plurality of word lines WL can be compensated, and the memory device 10 can have generally high operating speed and generally high reliability. Reference will be made below. Figure 3 Examples of other word line auxiliary units are described in the diagram. In some embodiments, word line auxiliary units may be arranged in two or more consecutive columns, and multiple pseudo bit lines may extend on the consecutive columns respectively.

[0033] The following will be referenced Figure 2 As described in other figures, each of the plurality of word line auxiliary cells may include transistors and footprints that are the same or similar to those of the memory cells (i.e., each of the plurality of first memory cells MC1 and the plurality of second memory cells MC2). Therefore, the plurality of word line auxiliary cells can be formed using the same process as that used to form the plurality of first memory cells MC1 and the plurality of second memory cells MC2, without affecting the structure of the plurality of first memory cells MC1 and the plurality of second memory cells MC2. Thus, due to the uniform structure of the word line auxiliary cells, the effects of parasitic elements caused by word lines extending in the high-capacity cell array 12 can be effectively eliminated, and a high yield of integrated circuits including the memory device 10 can be achieved.

[0034] Row driver 14 can be connected to cell array 12 via multiple word lines. Row driver 14 can activate one of the multiple word lines WL based on row address A_ROW. Therefore, among the multiple first memory cells MC1 and multiple second memory cells MC2, memory cells to be connected to the activated word line can be selected. Data DAT can be written to the selected memory cell in a write operation, and data DAT can be read from the selected memory cell in a read operation via column driver 16, as described below.

[0035] The column driver 16 can be connected to the cell array 12 via multiple first bit lines BL1, pseudo bit lines BLP, and multiple second bit lines BL2. During a read operation, the column driver 16 can identify the value stored in the memory cell connected to the active word line—that is, the value stored in the selected memory cell—by sensing the current and / or voltage received through the multiple first bit lines BL1 and the multiple second bit lines BL2, and can output data based on the identified value. Furthermore, during a write operation, the column driver 16 can apply current and / or voltage to the multiple first bit lines BL1 and the multiple second bit lines BL2, and can write the value to the memory cell connected to the active word line—that is, write it to the selected memory cell.

[0036] Column driver 16 can activate or deactivate multiple word line auxiliary units via pseudo bit lines BLP. For example, column driver 16 can activate multiple word line auxiliary units arranged in the second column C2 by applying a negative supply voltage VSS to the pseudo bit line BLP, and can deactivate multiple word line auxiliary units arranged in the second column C2 by applying a positive supply voltage VDD to the pseudo bit line BLP. Activated word line auxiliary units can accelerate the activation of word lines connected to them, while deactivated word line auxiliary units can release the acceleration of word line activation. Column driver 16 can activate multiple word line auxiliary units before word lines are activated, and can deactivate multiple word line auxiliary units before word lines are deactivated. In some embodiments, reference will be made to the following. Figure 5 and Figure 6 As described, at least one power line connected to multiple word line auxiliary units can extend on the second column C2, and the column driver 16 can activate or deactivate multiple word line auxiliary units via the power line and the pseudo bit line BLP.

[0037] Control logic 18 can receive a command CMD and generate a first control signal CTR1 and a second control signal CTR2. For example, control logic 18 can identify a read command by decoding the command CMD and can generate the first control signal CTR1 and the second control signal CTR2 to read data DAT from cell array 12. Furthermore, control logic 18 can identify a write command by decoding the command CMD and can generate the first control signal CTR1 and the second control signal CTR2 to write data DAT to cell array 12. In some embodiments, row driver 14 can activate or deactivate word lines at a timing determined based on the first control signal CTR1. Additionally, in some embodiments, at a timing determined based on the second control signal CTR2, column driver 16 can sense current and / or voltage from multiple first bit lines BL1 and multiple second bit lines BL2, or can apply current and / or voltage to multiple first bit lines BL1, pseudo bit lines BLP, and multiple second bit lines BL2.

[0038] Figure 2 This is a top view of the layout of a cell array 20 according to an exemplary embodiment of the present invention. In detail, Figure 2 The top view shown schematically illustrates a portion of the cell array 20 on a plane including the X and Y axes. Here, the plane including the X and Y axes may be referred to as the horizontal plane, and the Z-axis direction may be referred to as the vertical direction. Additionally, a component arranged relative to another component along the +Z direction may be referred to as above or above the other component, while a component arranged relative to another component along the -Z direction may be referred to as below the other component. Furthermore, the area of ​​a component may refer to the size of the portion occupied by the component on a plane parallel to the horizontal plane. In the accompanying drawings, only some layers may be shown for ease of illustration. Moreover, in this document, patterns including conductive materials, such as wiring layers, may be referred to as conductive patterns, or more simply, patterns, and components electrically connected to each other through conductive patterns may be simply referred to as connecting components.

[0039] refer to Figure 2 The cell array 20 may include multiple cells C11 to C46, ​​each having the same occupied area, and the multiple cells C11 to C46 may include memory cells and word line auxiliary cells. For example, as Figure 2 As shown, cell array 20 may include cells C11, C12, C15, C16, etc., which are storage cells in the first column COL1, the second column COL2, the fifth column COL5, and the sixth column COL6. Additionally, cell array 20 may include cells C13, C14, etc., which are word line auxiliary cells in the third column COL3 and the fourth column COL4. The following will refer to... Figure 3 and Figure 5An example of a circuit corresponding to region 21, which includes three units C12, C13, and C14.

[0040] In some embodiments, the layout of memory cells arranged in adjacent columns can be symmetrical about an axis parallel to the Y-axis. For example, cell C11 arranged in the first row ROW1 and the first column COL1 can have a layout obtained by flipping the layout of cell C12 arranged in the first row ROW1 and the second column COL2 about an axis parallel to the Y-axis. Therefore, cell array 20 can have a repeating layout in units of two memory cells, and word line auxiliary cells can also be arranged in two adjacent columns, namely the third column COL3 and the fourth column COL4, as shown. Figure 2 As shown. The following will refer to... Figure 7 The description includes an example of the layout of region 22, which comprises four cells C31, C32, C41, and C42 as storage units, and will be referenced below. Figure 8 The description includes an example of the layout of region 23, which includes four units C33, C34, C43, and C44 as word line auxiliary units.

[0041] Multiple word lines can extend parallel to the X-axis, and multiple bit lines and at least one pseudo bit line can extend parallel to the Y-axis. For example, cells C21 to C26 arranged in the second row ROW2 can be connected to word lines extending parallel to the X-axis in the second row ROW2. Additionally, cells C15, C25, C35, and C45 arranged in the fifth column COL5 can be connected to at least one bit line extending parallel to the Y-axis in the fifth column COL5, and cells C14, C24, C34, and C44 arranged in the fourth column COL4 can be connected to at least one pseudo bit line extending parallel to the Y-axis in the fourth column COL4.

[0042] Figure 3 This is a circuit diagram illustrating an example of a memory cell and a word line auxiliary cell according to an exemplary embodiment of the present invention. In detail, Figure 3 The circuit diagram shown represents and Figure 2 The equivalent circuit 30 corresponding to the three units C12, C13, and C14 included in region 21 is shown above. (Refer to the above.) Figure 2 The above, Figure 3 The storage unit C12', the first word line auxiliary unit C13', and the second word line auxiliary unit C14' shown can be arranged in the same row, i.e. Figure 2 The first row, ROW1, is shown below. (Refer to the following text.) Figure 2 To describe Figure 3 .

[0043] Storage unit C12', first word line auxiliary unit C13', and second word line auxiliary unit C14' arranged in the same row can be connected to word line WL[i] (i is an integer greater than 0). Storage unit C12' can be connected to the second bit line BL2 and the second compensation bit line BLB2 extending on the second column COL2. The first word line auxiliary unit C13' can be connected to the first pseudo bit line BLP1 and the second pseudo bit line BLBP1 extending on the third column COL3. The second word line auxiliary unit C14' can be connected to the third pseudo bit line BLBP2 and the fourth pseudo bit line BLP2 extending on the fourth column COL4. See below for reference. Figure 4 As described, in some embodiments, the negative power supply voltage VSS can be connected to the first pseudo bit line BLP1 and the fourth bit line BLP2. Furthermore, in some embodiments, the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2 can be electrically connected to each other and have the same potential.

[0044] refer to Figure 3 The memory cell C12' may include a first p-channel field-effect transistor (PFET) P11, a second PFET P12, and first n-channel field-effect transistors (NFETs) N11 through NFET N14. The memory cell C12' may be a six-transistor (6T) SRAM cell and may include a cross-coupled inverter pair between a node with a positive power supply voltage VDD and a node with a negative power supply voltage (or ground potential) VSS. In the cross-coupled inverter pair, the first inverter may include a first PFET P11 and a first NFET N11, and the second inverter may include a second PFET P12 and a second NFET N12. Additionally, the third NFET N13 and the fourth NFET N14 may be referred to as channel transistors, which are configured to connect the first inverter and the second inverter to a second bit line BL2 and a second compensation bit line BLB2, respectively, via an activated (i.e., high-level voltage) word line WL[i].

[0045] The first word line auxiliary unit C13' and the second word line auxiliary unit C14' may each include transistors similar to or the same as those in the memory unit C12'. For example, as Figure 3As shown, the first word line auxiliary unit C13' may include a first PFET P21, a second PFET P22, and a first NFET N21 to a fourth NFET N24, respectively, corresponding to the first PFET P11, the second PFET P12, and the first NFET N11 to the fourth NFET N14 of the memory cell C12'. Additionally, the second word line auxiliary unit C14' may include a first PFET P31, a second PFET P32, and a first NFET N31 to a fourth NFET N34, respectively, corresponding to the first PFET P21, the second PFET P22, and the first NFET N21 to the fourth NFET N24 of the memory cell C12'. Therefore, as will be referred to later... Figure 7 and Figure 8 As described, the first word line auxiliary unit C13' and the second word line auxiliary unit C14' may include an active region and a gate electrode corresponding to the layout of the memory unit C12'.

[0046] In this paper, transistors can have arbitrary structures. For example, a transistor may include a fin field-effect transistor (FinFET) formed by an active pattern extending in a fin shape and a gate electrode. A transistor may also include a multi-bridge channel FET (MBCFET) formed by multiple nanosheets extending parallel to each other and a gate electrode. A transistor may also include a forksheet FET (or forkFET) with a structure in which the nanosheets of the PFET and the NFET are separated by dielectric walls and the NFET and PFET are closer to each other. Figure 2 The transistor may also include a vertical FET (VFET), which includes source / drain regions separated from each other in the Z direction and a gate electrode that borders or surrounds the channel region. The transistor may include field-effect transistors (FETs), such as complementary FETs (CFETs), negative CFETs (NCFETs), and carbon nanotube FETs (CNTFETs), and may include bipolar junction transistors or other three-dimensional transistors.

[0047] refer to Figure 3In the first word line auxiliary unit C13', the first PFET P21 can be connected to the node to which a positive power supply voltage VDD is applied and the first node n1, and can include a control terminal (e.g., a gate) connected to the word line WL[i]. The first NFET N21 can be connected between the first node n1 and the second pseudo bit line BLBP1, and can include a control terminal connected to the word line WL[i]. The second PFET P22 can be connected between the node to which a positive power supply voltage VDD is applied and the second node n2, and can include a control terminal connected to the first node n1. The second NFET N22 can be connected between the second node n2 and the node to which a negative power supply voltage VSS is applied (which may be referred to as the second power supply node), and can include a control terminal connected to the first node n1. The third NFET N23 can be connected between the first node n1 and the second pseudo bit line BLBP1, and can include a control terminal connected to the word line WL[i]. The fourth NFET N24 can be connected between the second node n2 and the first pseudo bit line BLP1, and can include a control terminal connected to the word line WL[i]. In the second word line auxiliary unit C14', the first PFET P31, the second PFET P32, and the first NFET N31 to the fourth NFET N34 can be connected in a structure similar to that of the first word line auxiliary unit C13'. (Refer to the following...) Figure 4 Describe an operational example of the first word line auxiliary unit C13' and the second word line auxiliary unit C14'.

[0048] Figure 4 This is a timing diagram of a read operation according to an exemplary embodiment of the present invention. Specifically, as shown in the timing diagram. Figure 4 The timing diagrams shown illustrate examples of read operations without word line auxiliary units and examples of read operations with word line auxiliary units. Figure 3 The signal of the equivalent circuit 30 in the diagram changes over time. In this document, it is assumed that the signal is a high-state active signal with a high level when activated; however, it will be understood that the example embodiment is not limited thereto. Furthermore, although... Figure 4 The diagram illustrates a read operation as an example of an operation to compensate for the effects caused by parasitic elements on the word lines, but it should be understood that, compared to... Figure 4 Similarly, the effects caused by parasitic elements on word lines can be compensated for during write operations. Below, we will refer to... Figure 1 and Figure 3 describe Figure 4 ,exist Figure 4 Repeated descriptions will be omitted in the description.

[0049] refer to Figure 4 The read enable signal REN can be activated at time point t41. For example, Figure 1The first control signal CTR1 and the second control signal CTR2 may include a read enable signal REN, and the control logic 18 may activate the read enable signal REN based on a read command. The row driver 14 may activate the word line WL[i] corresponding to the row address A_ROW in response to the activated read enable signal REN. Therefore, the voltage of the word line WL[i] can be as follows: Figure 4 The voltage of the second bit line BL2 (or the second compensation bit line BLB2) can be gradually decreased based on the value stored in memory cell C12' due to the activation word line WL[i].

[0050] The negative supply voltage VSS can be applied to the first pseudo bit line BLP1 and the fourth pseudo bit line BLP2, and the positive supply voltage VDD can be applied to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2. (Reference) Figure 3 Since word line WL[i] has been activated, the voltage of the first node n1 in the first word line auxiliary unit C13' can approximately rise to the positive supply voltage VDD, and when the second PFET P22 is turned off, the first word line auxiliary unit C13' can remain unaffected by the voltage of word line WL[i]. That is, the first word line auxiliary unit C13' and the second word line auxiliary unit C14', which are deactivated due to the positive supply voltage VDD being applied to the second pseudo-bit line BLBP1 and the third pseudo-bit line BLBP2, can remain unaffected by the activation of word line WL[i]. Therefore, as... Figure 4 As shown, due to the parasitic elements of word line WL[i], the voltage of word line WL[i] can approximately reach the positive supply voltage VDD at time point t42, and the first time period T1 from time point t41 to time point t42 can be longer than the second time period T2 described below. In addition, since the first time period T1 is relatively extended, the voltage of the second bit line BL2 can decrease slowly.

[0051] The read enable signal REN can be disabled at time point t43. The row driver 14 can disable word line WL[i] in response to the already disabled read enable signal REN, and the voltage of word line WL[i] can be reduced, such as... Figure 4 As shown. The column driver 16 can identify the value stored in the memory cell C12' based on the voltage and / or current of the second bit line BL2 and the second compensation bit line BLB2. The voltage of the second bit line BL2, which slowly decreases due to the parasitic elements of the word line WL[i], may cause errors when the column driver 16 identifies the value, and may also reduce the read rate due to the delay in the time when the column driver 16 identifies the value.

[0052] The read enable signal REN can be activated at time point t44. Row driver 14 can activate the word line WL[i] corresponding to row address A_ROW in response to the already activated read enable signal REN. Therefore, as... Figure 4 As shown, the voltage of word line WL[i] can be gradually increased, and the voltage of the second bit line BL2 (or the second compensation bit line BLB2) can be gradually decreased.

[0053] The negative supply voltage VSS can be applied to the first pseudo bit line BLP1, the second pseudo bit line BLBP1, the third pseudo bit line BLBP2, and the fourth pseudo bit line BLP2. (Reference) Figure 3 Since word line WL[i] has been activated and the second pseudo-bit line BLBP1 is given a negative power supply voltage VSS, the voltage of the first node n1 in the first word line auxiliary unit C13' can approximately drop to the negative power supply voltage VSS, and when the second PFET P22 is turned on, the positive power supply voltage VDD can be provided to the second node n2. That is, since the negative power supply voltage VSS is applied to the second pseudo-bit line BLBP1 and the third pseudo-bit line BLBP2, the first word line auxiliary unit C13' and the second word line auxiliary unit C14' can be activated, can sense the activation of word line WL[i], and can accelerate and regenerate the activation of word line WL[i]. Therefore, as Figure 4 As shown, despite the presence of parasitic elements in word line WL[i], the voltage of word line WL[i] can still approximately reach the positive supply voltage VDD at time point t46, and the second time period T2 from time point t44 to time point t46 can be shorter than the first time period T1 mentioned above. In addition, since the second time period T2 is relatively short, the voltage of the second bit line BL2 can decrease in an earlier stage.

[0054] The read enable signal REN can be disabled at time point t47. The row driver 14 can disable word line WL[i] in response to the already disabled read enable signal REN, and the voltage of word line WL[i] can be reduced, such as... Figure 4 As shown. The column driver 16 can apply a positive power supply voltage VDD to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2, thus deactivating the first word line auxiliary unit C13' and the second word line auxiliary unit C14'. The column driver 16 can identify the value stored in the memory cell C12' based on the voltage and / or current of the second bit line BL2 and the second compensation bit line BLB2. Despite the presence of parasitic elements in word line WL[i], the voltage of the second bit line BL2, which still drops in the early stages, allows the column driver 16 to safely identify the value, and read speed can be improved by allowing the column driver 16 to identify the value in the early stages. In some embodiments, the positive power supply voltage VDD can be applied to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2 before the read enable signal REN is deactivated (or before word line WL[i] is deactivated), and accordingly, the first word line auxiliary unit C13' and the second word line auxiliary unit C14' can be deactivated in advance before word line WL[i] is deactivated.

[0055] Figure 5 This is a circuit diagram illustrating an example of a memory cell and a word line auxiliary cell according to an exemplary embodiment of the present invention. In detail, Figure 5 The circuit diagram shown represents and Figure 2 The equivalent circuit 50 corresponding to the three units C12, C13, and C14 included in region 21 is shown above. (Refer to the above.) Figure 2 The storage unit C12”, the first word line auxiliary unit C13”, and the second word line auxiliary unit C14” can be arranged in the same row, that is... Figure 2 In the first row, ROW1, shown below. (Compared to...) Figure 3 Compared to the equivalent circuit 30 in the middle, in Figure 5 In the equivalent circuit 50, the first word line auxiliary unit C13” and the second word line auxiliary unit C14” can be connected to the first power line PL1 and the second power line PL2, respectively. In the following text, reference will be made to... Figure 2 To describe Figure 5 And in Figure 5 In the description, omission and Figure 3 The description is the same as the description.

[0056] refer to Figure 5 The memory cell C12” can be connected to the word line WL[i], the second bit line BL2, and the second compensation bit line BLB2, and can include the first PFET P11, the second PFET P12, and the first NFET N11 to the fourth NFET N14. The first word line auxiliary cell C13” can be connected to the word line WL[i], the first pseudo bit line BLP1, and the second pseudo bit line BLBP1, and can include the first PFET P21, the second PFET P22, and the first NFET N21 to the fourth NFET N24. The second word line auxiliary cell C14” can be connected to the word line WL[i], the third pseudo bit line BLBP2, and the fourth pseudo bit line BLB2, and can include the first PFET P31, the second PFET P32, and the first NFET N31 to the fourth NFET N34.

[0057] The first word line auxiliary unit C13” can be connected to the first power line PL1 extending on the third column COL3, and can receive the positive power supply voltage VDD through the first power line PL1. Additionally, the second word line auxiliary unit C14” can be connected to the second power line PL2 extending on the fourth column COL4, and can receive the positive power supply voltage VDD through the second power line PL2. The first power line PL1 and the second power line PL2 can be connected to the column driver (e.g., ...). Figure 1The column driver 16 in the diagram can be activated or deactivated via the first power line PL1 and the second power line PL2, and via the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2. For example, in the first word line auxiliary unit C13", the voltage of the first power node pn1 connected to the first PFET P21 and the second PFET P22 can be varied according to the control of the column driver. (Refer to the following...) Figure 6 Describe an operational example of the first word line auxiliary unit C13” and the second word line auxiliary unit C14”.

[0058] Figure 6 This is a timing diagram of the read operation according to an example embodiment. In detail, Figure 6 The timing diagrams shown illustrate examples of no power line control during a read operation and examples of power line control during a read operation. Figure 5 The signal of the equivalent circuit 50 in the diagram changes over time. This will be discussed in the following text, with reference to... Figure 1 and Figure 5 To describe Figure 6 And in Figure 6 In the description, omission and Figure 4 Same description.

[0059] refer to Figure 6 The read enable signal REN can be activated at time point t61. Figure 1 The row driver 14 can activate the word line WL[i] corresponding to the row address A_ROW in response to the activated read enable signal REN. A negative power supply voltage VSS can be applied to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2, and a positive power supply voltage VDD can be applied to the first power supply line PL1 and the second power supply line PL2. Therefore, the first word line auxiliary unit C13” and the second word line auxiliary unit C14” can be activated, and the activation of the word line WL[i] can be accelerated.

[0060] At time point t62, the read enable signal REN can be disabled. The row driver 14 can disable word line WL[i] in response to the already disabled read enable signal REN, and the voltage of word line WL[i] can be reduced, such as... Figure 6As shown. The column driver 16 can apply a positive power supply voltage VDD to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2, thus the first word line auxiliary unit C13” and the second word line auxiliary unit C14” can be deactivated. The column driver 16 can maintain the positive power supply voltage VDD applied to the first power line PL1 and the second power line PL2, and the voltage of the word line WL[i] can approximately reach the negative power supply voltage VSS at time point t63, and the third time period T3 from time point t62 to time point t63 can be longer than the fourth time period T4 described below.

[0061] At time t64, the read enable signal REN can be activated. The row driver 14 can activate the word line WL[i] corresponding to the row address A_ROW in response to the activated read enable signal REN. A negative power supply voltage VSS can be applied to the second pseudo-bit line BLBP1 and the third pseudo-bit line BLBP2, and a positive power supply voltage VDD can be applied to the first power supply line PL1 and the second power supply line PL2. Therefore, the first word line auxiliary unit C13” and the second word line auxiliary unit C14” can be activated, and the activation of the word line WL[i] can be accelerated.

[0062] At time point t66, the read enable signal REN can be disabled. The row driver 14 can disable word line WL[i] in response to the already disabled read enable signal REN, and the voltage of word line WL[i] can be reduced, such as... Figure 6 As shown. Column driver 16 can apply the positive power supply voltage VDD to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2, thus deactivating the first word line auxiliary unit C13” and the second word line auxiliary unit C14”. Additionally, column driver 16 can disconnect the positive power supply voltage VDD applied to the first power line PL1 and the second power line PL2, thus, as... Figure 6 As shown by the dashed line, the first power line PL1 and the second power line PL2 (or the first power node pn1) can be floated. Therefore, the voltage of word line WL[i] can drop earlier, and the deactivation of word line WL[i] can be accelerated. The voltage of word line WL[i] can approximately reach the negative power supply voltage VSS at time point t67, and the fourth time period T4 from time point t66 to time point t67 can be shorter than the aforementioned third time period T3.

[0063] Figure 7 This is a top view of the layout of a cell array 70 according to an exemplary embodiment of the present invention. In detail, Figure 7 The top view shown illustrates the relationship with Figure 2 The layout of the four units C31, C32, C41, and C42 included in region 22 is shown. Figure 7 In the diagram, the name written on the pattern indicates the wire electrically connected to the pattern and / or the voltage applied to the pattern.

[0064] refer to Figure 7 The first storage cell C31' and the second storage cell C32' can be arranged in the same row (i.e., Figure 2 In the third row (ROW3), and can be connected together to word line WL[k] (where k is an integer greater than 0). The third storage unit C41' and the fourth storage unit C42' can be arranged in the same row (i.e., Figure 2 In the fourth row (ROW4), and can be connected together to word line WL[k+1]. Additionally, the first memory cell C31' and the third memory cell C41' can be connected in the same column (i.e., Figure 2 The first column (COL1) of the memory cell can be arranged in the same column (i.e., C32' and C42'), and can be jointly connected to the first bit line BL1 and the first compensation bit line BLB1. The second memory cell C32' and the fourth memory cell C42' can be arranged in the same column (i.e., C42'). Figure 2 In the second column (COL2), and can be connected together to the second bit line BL2 and the second compensation bit line BLB2.

[0065] In some embodiments, the memory cells included in the cell array 70 may have a symmetrical layout. For example, the first layout of the first memory cell C31' may be the same as the layout obtained by flipping the second layout of the second memory cell C32' about an axis parallel to the column direction (i.e., an axis parallel to the Y-axis). Additionally, the third layout of the third memory cell C41' may be the same as the layout obtained by flipping the first layout of the first memory cell C31' about an axis parallel to the row direction (i.e., an axis parallel to the X-axis). Furthermore, the fourth layout of the fourth memory cell C42' may be the same as the layout obtained by flipping the third layout of the third memory cell C41' about an axis parallel to the column direction, and the layout obtained by flipping the second layout of the second memory cell C32' about an axis parallel to the row direction. In some embodiments, the first memory cell C31' and the fourth memory cell C42' may have the same or similar layouts, and the second memory cell C32' and the third memory cell C41' may have the same or similar layouts. Reference will be made below. Figure 8 As described, word line auxiliary units may include active regions and gate electrodes with the same layout as memory cells.

[0066] Figure 8 This is a top view of the layout of a cell array 80 according to an exemplary embodiment of the present invention. In detail, Figure 8 The top view shown illustrates the relationship with Figure 2 The layout of the four units C33, C34, C43, and C44 included in region 23. Figure 8 In the diagram, the name on the pattern indicates the wire electrically connected to the pattern and / or the voltage applied to the pattern.

[0067] like Figure 8 As shown, the first word line auxiliary unit C33' and the second word line auxiliary unit C34' can be arranged in the same row (i.e., Figure 2 The third word line auxiliary unit C43' and the fourth word line auxiliary unit C44' can be arranged in the same row (i.e., ...). Figure 4 In the fourth row (ROW4), and can be connected together to word line WL[k+1]. Additionally, the first word line auxiliary unit C33' and the third word line auxiliary unit C43' can be arranged in the same column (i.e., Figure 2 The third column (COL3) in the middle, and can be jointly connected to the first pseudo bit line BLP1 and the second pseudo bit line BLBP1. The second word line auxiliary unit C34' and the fourth word line auxiliary unit C44' can be arranged in the same column (i.e., Figure 2 In the fourth column (COL4), and can be connected together to the third pseudo bit line BLBP2 and the fourth pseudo bit line BLP2.

[0068] In some embodiments, the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2 used to control the activation of the first word line auxiliary unit C33', the second word line auxiliary unit C34', the third word line auxiliary unit C43', and the fourth word line auxiliary unit C44' can have the same potential, and as... Figure 8 As shown, the first word line auxiliary unit C33', the second word line auxiliary unit C34', the third word line auxiliary unit C43', and the fourth word line auxiliary unit C44' can share the pattern W8 connected to the second pseudo bit line BLBP1 and the third pseudo bit line BLBP2. In some embodiments, as referenced above... Figure 3 The positive power supply voltage VDD can also be applied to the first power supply line PL1 and the second power supply line PL2. Additionally, in some embodiments, as referenced above... Figure 5 The first power line PL1 and the second power line PL2 can be connected to the column driver (e.g., Figure 1 The column driver 16 in the column driver is controlled so that the positive power supply voltage VDD can be applied to the first power line PL1 and the second power line PL2, or the first power line PL1 and the second power line PL2 can be floated.

[0069] In some embodiments, the word line auxiliary units included in the cell array 80 may have a symmetrical layout. For example, the layout of the first word line auxiliary unit C33' may be the same as the layout obtained by flipping the layout of the second word line auxiliary unit C34' about an axis parallel to the column direction. Additionally, the layout of the third word line auxiliary unit C43' may be the same as the layout obtained by flipping the layout of the first word line auxiliary unit C33' about an axis parallel to the row direction. Furthermore, the layout of the fourth word line auxiliary unit C44' may be the same as the layout obtained by flipping the layout of the third word line auxiliary unit C43' about an axis parallel to the column direction, and the layout obtained by flipping the layout of the second word line auxiliary unit C34' about an axis parallel to the row direction. In some embodiments, the first word line auxiliary unit C33' and the fourth word line auxiliary unit C44' may have the same or similar layouts, and the second word line auxiliary unit C43' and the third word line auxiliary unit C43' may have the same or similar layouts.

[0070] Word line auxiliary units may include active regions and gate electrodes that have the same or similar layout as memory cells. For example, the first word line auxiliary unit C33' may include active regions and gate electrodes that have the same or similar layout as memory cells. Figure 1 The first layout of the first memory cell C31' includes an active region extending along the Y-axis and a gate electrode that are identical to the active region extending along the X-axis. Similarly, the second word line auxiliary cell C34, the third word line auxiliary cell C43', and the fourth word line auxiliary cell C44' may each include the same active region and gate electrode as the first layout of the first memory cell C31'. Figure 7 The active regions and gate electrodes in the layout of the second memory cell C32', the third memory cell C41, and the fourth memory cell C42' are the same.

[0071] Figure 9 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention. In detail, Figure 9 This is a block diagram showing a memory device 90 included in an integrated circuit. (and...) Figure 1 Compared to the memory device 10, Figure 9 The cell array 92 may include multiple write auxiliary cells arranged in the second row R2. For example... Figure 9 As shown, memory device 90 may include cell array 92, row driver 94, column driver 96, and control logic 98. In the following text, in... Figure 9 In the description, omission and Figure 1 Same description.

[0072] Cell array 92 may include multiple first memory cells MC1 and multiple second memory cells MC2 arranged in a series of first rows R1 and a series of third columns C1 and C3, respectively, and may include multiple third memory cells MC3 and multiple fourth memory cells MC4 arranged in a series of first columns C1 and C3, respectively, in a series of third rows R3. Additionally, cell array 92 may include multiple word line auxiliary cells arranged in a second column C2 and multiple write auxiliary cells arranged in a second row R2. To compensate for the effects of parasitic elements on the bit lines, the write auxiliary cells (or write assist cells) may pre-amplify the voltage of the bit lines during write operations. Figure 9 As shown, the cell array 92 may include at least one dummy cell in the region X where the second column C2 intersects the second row R2. In some embodiments, a plurality of write auxiliary cells may be arranged in two or more consecutive rows, and a plurality of write auxiliary lines may extend on the consecutive rows respectively.

[0073] The row driver 94 can be connected to the cell array 92 via multiple first word lines WL1, write auxiliary lines WAL, and multiple second word lines WL2. Multiple first memory cells MC1 and multiple second memory cells MC2 can be connected to multiple first word lines WL1 extending on a series of first rows R1, multiple write auxiliary cells can be connected to write auxiliary lines WAL extending on second rows R2, and multiple third memory cells MC3 and fourth memory cells MC4 can be connected to multiple second word lines WL2 extending on a series of third rows R3.

[0074] The column driver 96 can be connected to the cell array via multiple first bit lines BL1, pseudo bit lines BLP, and multiple second bit lines BL2. Multiple first memory cells MC1 and multiple third memory cells MC3 can be connected to multiple first bit lines BL1 extending on a series of first columns C1, multiple word line auxiliary cells can be connected to pseudo bit lines BLP extending on second columns C2, and multiple second memory cells MC2 and multiple fourth memory cells MC4 can be connected to multiple second word lines BL2 extending on a series of third columns C3.

[0075] Figure 10 This is a top view of the layout of a cell array 100 according to an exemplary embodiment of the present invention. Figure 10 As shown, the cell array 100 may include multiple cells C11 to C86 having the same occupied area.

[0076] Multiple units C11 to C86 may include storage units, write auxiliary units, word line auxiliary units, first-type dummy units, and second-type dummy units. For example, as... Figure 10As shown, the cell array 100 may include cells C11, C15, C71, C75, etc., as storage cells in the regions where the first row ROW1, the second row ROW2, the seventh row ROW7, and the eighth row ROW8 intersect with the first column COL1, the second column COL2, the fifth column COL5, and the sixth column COL6, respectively. The cell array 100 may also include cells C13, C73, etc., as word line auxiliary cells in the regions where the first row ROW1, the second row ROW2, the seventh row ROW7, and the eighth row ROW8 intersect with the third column COL3 and the fourth column COL4. The cell array 100 may include cells C31, C35, etc., as write auxiliary cells, and cells C32 and C36 as first-type dummy cells in the regions where the third row ROW3 to the sixth row ROW6 intersect with the first column COL1, the second column COL2, the fifth column COL5, and the sixth column COL6. The cell array 100 may include cells C33, etc., as second-type dummy cells, and cells C34, etc., as first-type dummy cells, in the area where the third row ROW3 to the sixth row ROW6 intersect with the third column COL3 and the fourth column COL4. (Refer to the following...) Figure 11 An example of a circuit corresponding to region 101, which includes six units C22, C23, C24, C32, C33, and C34, is described below, and reference will be made to... Figure 12 An example describing the layout corresponding to region 102, which includes four units C53, C54, C63, and C64.

[0077] Figure 11 This is a circuit diagram illustrating examples of a memory cell, word line auxiliary cell, write auxiliary cell, and dummy cell according to an exemplary embodiment of the concept of the present invention. In detail, Figure 11 The circuit diagram shown illustrates the circuit included in Figure 10 The equivalent circuit 110 corresponding to the six units C22, C23, C24, C32, C33, and C34 in region 101. See above for reference. Figure 10 The storage unit C22', the first word line auxiliary unit C23', and the second word line auxiliary unit C24' can be arranged in the same row, i.e. Figure 10 The second line, ROW2, and Figure 11 The write auxiliary unit C32', the first dummy unit C33', and the second dummy unit C34' can be arranged in the same row, that is... Figure 10 The third line, ROW3, ​​is mentioned below. Figure 10 describe Figure 11 And the same descriptions as those described with reference to the accompanying drawings will be omitted.

[0078] refer to Figure 11The memory cell C22' can be connected to the word line WL[j], the second bit line BL2, and the second compensation bit line BLB2, and can include a first PFET P41, a second PFET P42, and a first NFET N41 to a fourth NFET N44. The first word line auxiliary cell C23' can be connected to the word line WL[j], the first pseudo bit line BLP1, the second pseudo bit line BLBP1, and the first power line PL1, and can include a first PFET P51, a second PFET P52, and a first NFET N51 to a fourth NFET N54. The second word line auxiliary cell C24' can be connected to the word line WL[j], the third pseudo bit line BLBP2, the fourth pseudo bit line BLP2, and the second power line PL2, and can include a first PFET P61, a second PFET P62, and a first NFET N61 to a fourth NFET N64. The write auxiliary unit C32' can be connected to the fourth write auxiliary line WAL[4], the second bit line BL2, and the second compensation bit line BLB2, and can include the first PFET P71, the second PFET P72, and the first NFET N71 to the fourth NFET N74. The first dummy unit C33' can be connected to the first pseudo bit line BLP1, the second pseudo bit line BLBP1, the first power line PL1, and the second dummy unit C34', and can include the first PFET P81, the second PFET P82, and the first NFET N81 to the fourth NFET N84. The second dummy unit C34' can be connected to the third pseudo bit line BLBP2, the fourth pseudo bit line BLP2, the first write auxiliary line WAL[1], and the second power line PL2, and can be connected to the first pseudo bit line BLP1 through the first dummy unit C33', and can include the first PFET P91, the second PFET P92, and the first NFET N91 to the fourth NFET N94.

[0079] In a write operation, the line driver (e.g., Figure 9 The row driver 94 in the memory can activate the fourth word line WAL[4] before activating one of the multiple word lines (e.g., word line WL[j]). Therefore, the write auxiliary unit C32' can pre-amplify the voltage of the second bit line BL2 and the second compensation bit line BLB2, thereby enabling data to be safely written to the memory cell C22' at an earlier stage.

[0080] The first dummy unit C33' can correspond to Figure 10 The second type of dummy cell is shown. Since the first dummy bit line BLP1 is subjected to a negative supply voltage VSS, the first dummy cell C33' can not affect the second dummy bit line BLBP1. Furthermore, the second dummy cell C34' can correspond to... Figure 10 The first type of dummy cell is shown. During a write operation, even if the first write auxiliary line WAL[1] is driven by the row driver (e.g., Figure 9 When the row driver 94 in the middle is activated, since the first pseudo bit line BLP1 and the fourth pseudo bit line BLP2 are subjected to the negative power supply voltage VSS, the second dummy unit C34' can not affect the third pseudo bit line BLBP2.

[0081] Figure 12 This is a top view of the layout of a cell array 120 according to an exemplary embodiment of the present invention. In detail, Figure 12 The top view shown illustrates the relationship with Figure 10 The layout of the four units C53, C54, C63, and C64 included in region 102. Figure 12 In the diagram, the name on the pattern indicates the wire electrically connected to the pattern and / or the voltage applied to the pattern.

[0082] like Figure 12 As shown, the first dummy unit C53' and the third dummy unit C63' can be arranged in the same column (i.e., Figure 10 The third column (COL3) can be connected to the first pseudo bit line BLP1, the second pseudo bit line BLBP1, and the first power line PL1. The second dummy unit C54' and the fourth dummy unit C64' can be arranged in the same column (i.e., Figure 10 In the fourth column (COL4), and can be connected together to the third pseudo bit line BLBP2, the fourth pseudo bit line BLP2 and the second power line PL2. The second virtual unit C54' and the third virtual unit C63', which are first type virtual units, can be connected to the first write auxiliary line WAL[1] and the fourth write auxiliary line WAL[4], respectively.

[0083] A dummy cell may include an active region and gate electrode that are the same as or similar to the active region and gate electrode of a memory cell. For example, the first dummy cell C53' may include an active region and gate electrode that are the same as or similar to the active region and gate electrode of a memory cell. Figure 7 The first layout of the first memory cell C31' includes an active region extending along the Y-axis and a gate electrode that are identical to those extending along the X-axis. Similarly, the second dummy cell C54', the third dummy cell C63', and the fourth dummy cell C64' may each include the same active region and gate electrode as the first memory cell C31'. Figure 7 The active regions and gate electrodes in the layout of the second storage cell C32', the third storage cell C41', and the fourth storage cell C42' are the same. In some embodiments, the first dummy cell C53' may have a layout generated by rotating the layout of the fourth dummy cell C64' 180 degrees about a horizontal plane, and the second dummy cell C54' may have a layout generated by rotating the layout of the third dummy cell C63' about a horizontal plane.

[0084] Figure 13A and Figure 13BThis is a top view of the layout of an integrated circuit 130 according to an exemplary embodiment of the present invention. Specifically, Figure 13A and Figure 13B The top views shown in the diagrams depict the patterns formed on the element array. For ease of explanation, Figure 13A and Figure 13B Only some of the wiring layers may be illustrated, and integrated circuit 130 may further include, in addition to Figure 13A and Figure 13B Other patterns besides the one shown. Word lines, write auxiliary lines, bit lines, and pseudo bit lines may extend on the cells included in the cell array, and lines configured to provide positive supply voltage VDD and negative supply voltage VSS may extend to the cells.

[0085] refer to Figure 13A In the first wiring layer (e.g., Figure 7 On a second wiring layer M2 above a first wiring layer M1, multiple patterns W01 to W18 may extend in a direction parallel to the Y-axis. Storage cells, write auxiliary cells, and dummy cells arranged in the same column may be connected to patterns extending in the second wiring layer M2. In some embodiments, patterns W01, W04, W13, and W18 may correspond to bit lines, patterns W03, W06, W15, and W18 may correspond to compensation bit lines, and a positive power supply voltage VDD may be applied to patterns W02, W05, W14, and W17. In some embodiments, each of patterns W02, W05, W14, and W17 to which the positive power supply voltage VDD is applied may have a portion protruding in a direction parallel to the X-axis for a via (i.e., a via in the first via layer) used for connecting to patterns in the first wiring layer M1.

[0086] Word line auxiliary units and dummy units arranged in the same column can be jointly connected to the pattern of the second wiring layer M2 extending on that column. In some embodiments, patterns W07, W09, W10, and W12 can correspond to the first pseudo bit line BLP1, the second pseudo bit line BLBP1, the third pseudo bit line BLBP2, and the fourth pseudo bit line BLP2, respectively, and patterns W08 and W11 can correspond to the first power line PL1 and the second power line P2, respectively. Figure 13A As shown, in the second type of dummy unit, pattern W07 may have a portion protruding in a direction parallel to the X-axis for the via, which is used to connect the pattern of the first wiring layer M1 connected to the first pseudo bit line BLP1 and the pattern of the third wiring layer above the second wiring layer M2 (e.g., Figure 13BThe pattern in the third wiring layer M3). Additionally, in the second type of dummy cell, pattern W12 may have a portion protruding along the X-axis for a via, which is used to connect the pattern of the first wiring layer M1 connected to the fourth pseudo-bit line BLP2 and the pattern for connecting the third pattern layer. Furthermore, integrated circuit 130 may include a pattern (e.g., pattern W20) of the second wiring layer M2 extending in the X-axis direction to connect the second pseudo-bit line BLBP1 and the third pseudo-bit line BLBP2.

[0087] refer to Figure 13B In the third wiring layer M3 above the second wiring layer M2, multiple patterns W21 to W30 can extend in a direction parallel to the X-axis. In some embodiments, a negative power supply voltage VSS can be applied to patterns W21, W23, W24, W25, W26, W28, and W30 extending along the row boundaries. Memory cells and word line auxiliary cells arranged in the same row can be jointly connected to the patterns of the third wiring layer M3 extending on that row. For example, patterns W22 and W29 can correspond to word lines, respectively.

[0088] The patterns of the third wiring layer M3 can extend along a direction parallel to the X-axis on the write auxiliary unit and the second type of dummy unit. For example, patterns W31 and W33 can be connected to the third write auxiliary line WAL3, patterns W33 and W34 can be connected to the fourth write auxiliary line WAL[4], patterns W39 and W40 can be connected to the first write auxiliary line WAL[1], and patterns W41 and W42 can be connected to the second write auxiliary line WAL2. In addition, patterns W35 and W36 can be connected to the first pseudo bit line BLP1, and patterns W37 and W38 can be connected to the fourth pseudo bit line BLP2.

[0089] Figure 14 This is a block diagram of an integrated circuit according to an exemplary embodiment of the present invention. In detail, Figure 14 The block diagram shown illustrates a memory device 10 included in an integrated circuit. (As...) Figure 14 As shown, memory device 140 may include cell array 142, row driver 144, column driver 146, and control logic 148. In the following text, in... Figure 14 In the description, the omission of and Figure 1 and Figure 9 Same description.

[0090] Cell array 142 may include memory cells located in regions where a series of first columns C1, a series of third columns C3, a series of fifth columns C5, and a series of seventh columns C7 intersect with a series of second rows R2, a series of fourth rows R4, a series of sixth rows R6, and a series of eighth rows R8. Additionally, cell array 142 may include word line auxiliary cells arranged in a series of second columns C2, a series of fourth columns C4, and a series of sixth columns C6, and may include write auxiliary cells and dummy cells arranged in a series of first rows R1, a series of third rows R3, a series of fifth rows R5, and a series of seventh rows R7. Cell array 142 may also include dummy cells arranged in region X where a series of second columns C2, a series of fourth columns C4, and a series of sixth columns C6 intersect with a series of first rows R1, a series of third rows R3, a series of fifth rows R5, and a series of seventh rows R7. Figure 14 As shown, when the word line auxiliary units and write auxiliary units are arranged regularly, the effects caused by parasitic elements of word lines and bit lines can be appropriately compensated even when the size of the cell array 142 increases.

[0091] The row driver 144 can be connected to the memory cell and the word line auxiliary cell via multiple word lines WL, and can be connected to the write auxiliary cell via multiple write auxiliary lines WAL. The row driver 144 can activate one of the multiple word lines WL during a read operation or a write operation, and can activate at least one write auxiliary cell by activating some of the multiple write auxiliary lines WAL during a write operation.

[0092] The column driver 146 can be connected to the memory cell, write auxiliary cell, and dummy cell via multiple bit lines BL, and can be connected to the word line auxiliary cell and dummy cell via multiple pseudo bit lines BLP. The column driver 146 can control the word line auxiliary cell via the multiple pseudo bit lines BLP during write or read operations. In some embodiments, the column driver 146 can be connected to the word line auxiliary cell and dummy cell via multiple power lines, and can control the word line auxiliary cell via both the power lines and the multiple pseudo bit lines BLP.

[0093] Figure 15 This is a flowchart illustrating a method for operating an integrated circuit according to an exemplary embodiment. Specifically, Figure 15 The flowchart in the diagram illustrates an example of operations performed by a memory device included in an integrated circuit. For example... Figure 15 As shown, the operation method of the integrated circuit may include multiple operations (S20, S40, S60, and S80). In some embodiments, Figure 15 The operation method in can be provided by Figure 1 The column driver 16 in the text is executed, and will be referenced below. Figure 1 describe Figure 15 .

[0094] refer to Figure 15 In operation S20, word line auxiliary units can be activated. For example, column driver 16 can activate word line auxiliary units via pseudo bit lines (BLP). In some embodiments, column driver 16 can activate word line auxiliary units via power lines and pseudo bit lines (BLP). Reference will be made below. Figure 16 Describe an example of operation S20.

[0095] In operation S40, it can be determined whether the word line is active. For example, Figure 1 The second control signal CTR2 may include a write enable signal and a read enable signal, and the column driver 16 may identify the activation of a word line based on the activated write enable signal or read enable signal. Figure 15 As shown, when the word line is activated, operation S60 can be performed subsequently. Therefore, the word line auxiliary unit can be activated by the column driver 16 before the word line is activated.

[0096] In operation S60, it can be determined whether the activation cycle has ended. For example, column driver 16 can identify the end of the activation cycle based on a disabled write enable signal or read enable signal. In some embodiments, column driver 16 can identify the end of the activation cycle before or at the same time as the word line is disabled to disable the word line auxiliary unit. Figure 15 As shown, when the activation cycle ends, operation S80 can be performed subsequently.

[0097] In operation S80, word line auxiliary units can be disabled. For example, column driver 16 can disable word line auxiliary units via pseudo bit lines (BLP). In some embodiments, column driver 16 can disable word line auxiliary units via power lines and pseudo bit lines (BLP). Reference will be made below. Figure 16 Describe an example of operation S80.

[0098] Figure 16 This is a flowchart of a method for operating an integrated circuit according to an exemplary embodiment of the present invention. In detail, Figure 16 The flowchart shows Figure 15 Example of operation S20. See above for reference. Figure 15 As mentioned above, in Figure 16 In operation S20', the word line auxiliary unit can be activated. For example... Figure 16 As shown, operation S20' may include operations S22 and S24. In some embodiments, operations S22 and S24 may be performed in parallel, or operation S24 may be performed before operation S22. Reference will be made below to... Figure 1 describe Figure 16 .

[0099] refer to Figure 16In operation S22, a positive power supply voltage VDD can be provided to the word line auxiliary unit. For example, the column driver 16 can be connected to the word line auxiliary unit via a power line extending on the cell array 12, and can provide the positive power supply voltage VDD to the word line auxiliary unit by applying the positive power supply voltage VDD to the power line.

[0100] In operation S24, a negative supply voltage VSS can be provided to the pseudo bit line BLP. For example, the column driver 16 can be connected to the word line auxiliary cell via the pseudo bit line BLP extending on the cell array 12, and a negative supply voltage VSS can be provided to the pseudo bit line BLP. Therefore, the word line auxiliary cell can be activated, and the effects caused by parasitic elements of the word line can be compensated by sensing and accelerating the activation of the word line.

[0101] Figure 17 This is a flowchart of a method for operating an integrated circuit according to an exemplary embodiment of the present invention. In detail, Figure 17 The flowchart shown illustrates Figure 15 An example of S80 operation. See above for reference. Figure 15 As mentioned above, in Figure 17 In operation S80', the word line auxiliary unit can be disabled. For example... Figure 17 As shown, operation S80' may include operation S82 and operation S84. In some embodiments, operation S82 and operation S84 may be performed in parallel, or operation S84 may be performed before operation S82. Referring below... Figure 1 describe Figure 17 .

[0102] In operation S82, a positive power supply voltage VDD can be provided to the pseudo bit line BLP. For example, column driver 16 can be connected to word line auxiliary cells via the pseudo bit line BLP extending on cell array 12, and a positive power supply voltage VDD can be provided to the pseudo bit line BLP.

[0103] In operation S84, the positive power supply voltage VDD can be cut off or removed from the word line auxiliary unit. For example, column driver 16 can be connected to the word line auxiliary unit via a power line extending on cell array 12, and the positive power supply voltage VDD from the word line auxiliary unit can be cut off or removed by floating the power line. Therefore, the word line auxiliary unit can be disabled and can be used without affecting voltage changes (e.g., voltage drop) on the word line.

[0104] Figure 18 This is a block diagram of a system-on-a-chip (SoC) 180 according to an exemplary embodiment of the present invention. SoC 180 can refer to an integrated circuit in which components of a computing system or other electrical system are integrated. As an example of SoC 180, an application processor (AP) may include processors and components for other functions. Figure 18 As shown, the SoC 180 may include a core 181, a digital signal processor (DSP) 182, a graphics processing unit (GPU) 183, embedded memory 184, a communication interface 185, and a memory interface 186. The components in the SoC 180 can communicate with each other via a bus 187.

[0105] Core 181 can process instructions and control the operation of components included in SoC 180. For example, core 181 can drive an operating system and execute applications on the operating system by processing a series of instructions. DSP 182 can generate useful data by processing digital signals (e.g., digital signals provided by communication interface 185). GPU 183 can generate data for an image output through a display device from image data provided by embedded memory 184 or memory interface 186, and can also encode the image data. In some embodiments, the memory device described above with reference to the accompanying drawings can be included in core 181, DSP 182, and / or GPU 183 as a cache memory and / or buffer. Therefore, core 181, DSP 182, and / or GPU 183 can also have high or improved reliability and efficiency based on the high or improved reliability and efficiency of the memory device.

[0106] Embedded memory 184 can store data for the operation of core 181, DSP 182, and / or GPU 183. In some embodiments, embedded memory 184 may include the memory device described above with reference to the accompanying drawings. Therefore, embedded memory 184 can provide reliable write operation capabilities, and can have a reduced area and lower power consumption, thereby improving the operational reliability and efficiency of SoC 180.

[0107] Communication interface 185 can provide an interface for communication networks or one-to-one communication. Memory interface 186 can provide an interface for the external memory of SoC 180, such as dynamic random access memory (DRAM), flash memory, etc.

[0108] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, the integrated circuit comprising: A cell array comprising a plurality of storage cells in a plurality of first columns and a plurality of word line auxiliary cells in at least one second column; Multiple word lines, which extend on multiple first rows of the cell array and connect to the multiple memory cells and the multiple word line auxiliary units respectively; At least one pseudo bit line, the at least one pseudo bit line extending on the at least one second column and including a first pseudo bit line; as well as A row driver, configured to drive the plurality of word lines. Each of the plurality of word line auxiliary units is configured to accelerate the activation of a corresponding word line among the plurality of word lines based on the voltage of the at least one pseudo bit line, and includes the same transistor as the transistor of each of the plurality of memory cells, and has the same occupied area as the occupied area of ​​each of the plurality of memory cells.

2. The integrated circuit according to claim 1, wherein, Each of the plurality of word line auxiliary units includes: A first p-channel field-effect transistor is connected between a first power node and a first node and includes a control terminal connected to one of the plurality of word lines. A first n-channel field-effect transistor, the first n-channel field-effect transistor being connected between the first node and the first pseudo bit line and including a control terminal connected to one of the plurality of word lines; and A second p-channel field-effect transistor is connected between the first power node and one of the plurality of word lines and includes a control terminal connected to the first node.

3. The integrated circuit of claim 2, further comprising a column driver configured to apply a negative power supply voltage to the first pseudo bit line before the word line of the plurality of word lines is activated and to apply a positive power supply voltage to the pseudo bit line before the word line of the plurality of word lines is deactivated.

4. The integrated circuit according to claim 2, further comprising: At least one power line, the at least one power line extending over the at least one second column and including a first power line; as well as A column driver, connected to the first power node via the first power line, is configured to apply a positive power supply voltage to the first power line before one of the plurality of word lines is activated, and to float the first power line before one of the activated word lines is deactivated.

5. The integrated circuit according to claim 2, wherein, The at least one pseudo bit line also includes a second pseudo bit line; and Each of the plurality of word line auxiliary units further includes: The second n-channel field-effect transistor is connected between the second node and the second power supply node to which a negative power supply voltage is applied, and includes a control terminal connected to the first node. A third n-channel field-effect transistor, the third n-channel field-effect transistor being connected between the first node and the first pseudo bit line and including a control terminal connected to one of the plurality of word lines; and A fourth n-channel field-effect transistor, the n-channel field-effect transistor being connected between the second pseudo bit line and the second node and including a control terminal connected to one of the plurality of word lines.

6. The integrated circuit according to claim 1, wherein, The cell array further includes: Multiple write auxiliary units in at least one second row; and At least one dummy cell in the region where the at least one second column intersects with the at least one second row, and The plurality of write auxiliary units and the at least one dummy unit each include the same transistor as the transistor of each of the plurality of memory cells and have the same footprint as the footprint of each of the plurality of memory cells.

7. The integrated circuit according to claim 6, in, The cell array further includes a plurality of first dummy cells in the at least one second row, each of the plurality of first dummy cells being arranged adjacent to each of the plurality of write auxiliary cells in a row direction or column direction, and Wherein, the at least one dummy unit includes: A second virtual unit corresponding to the first circuit of each of the plurality of first virtual units; and A third dummy unit corresponding to a second circuit that is different from the first circuit.

8. The integrated circuit of claim 7, further comprising a plurality of pseudo bit lines extending respectively on the at least one second column, and in, The third virtual unit includes: The third p-channel field-effect transistor and the fourth p-channel field-effect transistor each include a control terminal connected to a first pseudo bit line among the plurality of pseudo bit lines and a floating current terminal. A fifth n-channel field-effect transistor and a sixth n-channel field-effect transistor, each of the fifth n-channel field-effect transistor and the sixth n-channel field-effect transistor including a control terminal connected to the first pseudo bit line among the plurality of pseudo bit lines; A seventh n-channel field-effect transistor, the seventh n-channel field-effect transistor being connected between the first pseudo-bit line and the fifth n-channel field-effect transistor, and including a control terminal connected to the first pseudo-bit line among the plurality of pseudo-bit lines; and The eighth n-channel field-effect transistor is connected between the second pseudo bit line in the plurality of pseudo bit lines and the sixth n-channel field-effect transistor, and is also connected to the first pseudo bit line in the plurality of pseudo bit lines.

9. An integrated circuit, the integrated circuit comprising: A cell array, the cell array comprising multiple cells, each of the multiple cells comprising the same transistor and having the same occupied area; Multiple word lines, which extend on multiple first rows of the cell array respectively; as well as A line driver, which is connected to the plurality of word lines, The plurality of units include: Multiple storage cells, the multiple storage cells being connected to the multiple word lines and arranged in a series of first columns; A plurality of first character line auxiliary units, the plurality of first character line auxiliary units being connected to the plurality of character lines and arranged in a second column; and A plurality of second character line auxiliary units, the plurality of second character line auxiliary units being connected to the plurality of character lines and arranged in a third column adjacent to the second column, The first layout of each of the plurality of first character line auxiliary units and the second layout of the second character line auxiliary units arranged in the same row as the first character line auxiliary unit are symmetrical about an axis parallel to the column direction.

10. The integrated circuit according to claim 9, wherein, Each of the plurality of storage cells has one of a plurality of layouts that are symmetrical to each other, and Both the first layout and the second layout include the same active region and gate electrode as one of the plurality of layouts.

11. The integrated circuit according to claim 10, wherein, The active region extends along the column direction, and The gate electrode extends along the row direction.

12. The integrated circuit according to claim 9, further comprising: Multiple bit lines, which extend on the series of first columns and are connected to the multiple memory cells respectively; First pseudo bit line and second pseudo bit line, the first pseudo bit line and the second pseudo bit line extend on the second column and are connected to the plurality of first word line auxiliary units; The third pseudo bit line and the fourth pseudo bit line extend on the third column and connect to the plurality of second word line auxiliary units; as well as A column driver connected to the plurality of bit lines, the second pseudo-bit line, and the third pseudo-bit line. The first pseudo bit line and the fourth pseudo bit line are configured to receive negative power supply voltage.

13. The integrated circuit of claim 12, further comprising a plurality of patterns on the cell array connecting the second pseudo bit line and the third pseudo bit line.

14. The integrated circuit according to claim 13, wherein, The plurality of patterns are formed in a wiring layer in which the first pseudo bit line, the second pseudo bit line, the third pseudo bit line and the fourth pseudo bit line are formed.

15. The integrated circuit according to claim 9, further comprising: A first power line extends on the second column and connects to the plurality of first word line auxiliary units; A second power line extends on the third column and connects to the plurality of second word line auxiliary units; as well as A column driver configured to selectively provide a positive power supply voltage to the plurality of first word line auxiliary units via a first power line and to selectively provide a positive power supply voltage to the plurality of second word line auxiliary units via a second power line.

16. The integrated circuit according to claim 9, wherein, The plurality of units also include: A plurality of write auxiliary units, said plurality of write auxiliary units being arranged in at least one second row of said unit array; and Multiple dummy units are arranged in the area where the at least one second row intersects with the second and third columns.

17. The integrated circuit according to claim 16, wherein, The plurality of dummy units include a first dummy unit and a second dummy unit corresponding to different circuits, and The first dummy unit and the second dummy unit are respectively arranged in the second column of the at least one second row and the third column of the at least one second row.

18. An integrated circuit, the integrated circuit comprising: A cell array, the cell array comprising multiple cells, each of the multiple cells comprising the same transistor and having the same occupied area; Multiple word lines, which extend on multiple first rows of the cell array respectively; as well as A line driver, which is connected to the plurality of word lines, The plurality of units include: A plurality of first storage cells, the plurality of first storage cells being connected to the plurality of word lines and arranged in a series of first columns; A plurality of first character line auxiliary units, the plurality of first character line auxiliary units being connected to the plurality of character lines and arranged in at least one second column adjacent to the series of first columns; and A plurality of second storage cells are connected to the plurality of word lines and are arranged in a series of third columns adjacent to the at least one second column.

19. The integrated circuit of claim 18, further comprising a plurality of second word line auxiliary units, the plurality of second word line auxiliary units being connected to the plurality of word lines and arranged in at least one fourth column adjacent to the series of third columns, and in, The number of the first column in the series is the same as the number of the third column in the series.

20. The integrated circuit according to claim 19, further comprising: Multiple bit lines extend on the series of first columns and the series of third columns and are connected to the plurality of first memory cells and the plurality of second memory cells, respectively; At least one first pseudo bit line, the at least one first pseudo bit line extending on the at least one second column and connected to the plurality of first word line auxiliary units; At least one second pseudo bit line, the at least one second pseudo bit line extending on the at least one fourth column and connected to the plurality of second word line auxiliary units; as well as A column driver connected to the plurality of bit lines and configured to activate or deactivate the plurality of first word line auxiliary units and the plurality of second word line auxiliary units via the at least one first pseudo bit line and the at least one second pseudo bit line.

Images