Nonvolatile memory device performing precharge on a cell string and method of programming the same

Abstract

A non-volatile memory device includes an array of memory cells and a control circuit, the array of memory cells including a plurality of strings of cells, wherein each string of cells of the plurality of strings of cells includes a string select transistor, a plurality of memory cells, and a ground select transistor connected in series between a bit line and a common source line; the control circuit configured to perform a program operation on a selected memory cell among the plurality of memory cells and to pre-charge a selected string of cells including the selected memory cell in a pre-charge phase included in a verify phase, wherein the selected string of cells is pre-charged when a first pre-charge voltage is applied to a selected bit line connected to the selected memory cell.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0147153, filed with the Korean Intellectual Property Office on November 5, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a non-volatile memory, and more specifically, to a pre-charged non-volatile memory device for executing a string of cells and a method for programming the non-volatile memory device. Background Technology

[0004] Examples of programming methods performed by non-volatile storage devices (e.g., NAND flash memory) may include Incremental Step Pulse Programming (ISPP). According to the ISPP method, programming cycles can be executed until programming is complete. Each programming cycle may include programming operations, verification operations, and recovery operations to initialize the channels of the cell string.

[0005] In this situation, the channel of a memory cell adjacent to the channel of the programmed memory cell is negatively boosted, which may cause interference. Furthermore, after the verification operation, a read pass voltage may be applied to the word line of the programmed memory cell, potentially causing read interference in adjacent memory cells. Summary of the Invention

[0006] A nonvolatile memory device for performing precharging of a cell string during a verification phase after a programming operation is provided, as well as a programming method for the nonvolatile memory device.

[0007] According to one aspect of this disclosure, a non-volatile memory device includes: a memory cell array and control circuitry, the memory cell array including a plurality of cell strings, wherein each of the plurality of cell strings includes a string select transistor connected in series between a bit line and a common source line, a plurality of memory cells, and a ground select transistor; the control circuitry is configured to: perform a programming operation on a selected memory cell among the plurality of memory cells, and precharge the selected cell string including the selected memory cell in a precharge phase included in a verification phase, wherein the selected cell string is precharged when a first precharge voltage is applied to a select bit line connected to the selected memory cell.

[0008] According to one aspect of this disclosure, a non-volatile memory device includes a memory cell array and control circuitry. The memory cell array includes a plurality of cell strings, wherein each of the plurality of cell strings includes a string select transistor, a plurality of memory cells, and a ground select transistor connected in series between a bit line and a common source line. The control circuitry is configured to: perform a programming operation on a selected memory cell among the plurality of memory cells, and precharge a selected cell string including the selected memory cell in a precharge phase included in a verification phase, wherein the selected cell string is precharged when a first precharge voltage is applied to a selected common source line connected to the selected memory cell.

[0009] According to one aspect of this disclosure, a programming method for a non-volatile memory device includes a plurality of cell strings, wherein each of the plurality of cell strings includes a string select transistor, a plurality of memory cells, and a ground select transistor connected in series between a bit line and a common source line. The programming method includes: performing a programming operation on selected memory cells among the plurality of memory cells; and performing a programming verification operation on the selected memory cells, wherein the programming verification operation includes: pre-charging the selected cell string including the selected memory cells before a recovery phase, and wherein the selected cell string is pre-charged when a first pre-charge voltage is applied to a selected bit line connected to the selected memory cells, or when a second pre-charge voltage is applied to a selected common source line connected to the selected memory cells. Attached Figure Description

[0010] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram of a storage device according to an example embodiment;

[0012] Figure 2 This is a block diagram of a storage device according to an example embodiment;

[0013] Figure 3 This is an example diagram illustrating a storage cell array according to an example embodiment;

[0014] Figure 4 This is a block diagram of a storage device according to an example embodiment;

[0015] Figure 5 This is a circuit diagram of the page buffer according to an example embodiment;

[0016] Figure 6 This is a timing diagram illustrating the operation of the page buffer according to an example embodiment;

[0017] Figure 7 This is a circuit diagram of the page buffer according to an example embodiment;

[0018] Figure 8 This is a timing diagram illustrating the operation of the page buffer according to an example embodiment;

[0019] Figures 9 to 13 This is a timing diagram illustrating the pre-charge operation according to an example embodiment;

[0020] Figure 14 This is a conceptual diagram of the programming loop based on the example embodiment;

[0021] Figure 15 This is an example diagram illustrating the timing of the pre-charging operation according to an example embodiment;

[0022] Figure 16 This is a flowchart of an operation method of a storage device according to an example embodiment; and

[0023] Figure 17 This is a block diagram of a solid-state drive (SSD) system according to an example embodiment. Detailed Implementation

[0024] In the following, one or more embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of a storage device according to an example embodiment.

[0026] Reference Figure 1 The storage device 10 may include a storage device 100 and a memory controller 200.

[0027] The storage device 100 can perform erase, program, and read operations under the control of the memory controller 200. The storage device 100 receives commands (CMD) and addresses (ADDR) from the memory controller 200 via input / output lines, and sends data (DATA) for read operations to the memory controller 200 or receives data (DATA) for programming operations from the memory controller 200. Furthermore, the storage device 100 can receive control signals (CTRL) via control lines.

[0028] In an embodiment, the storage device 100 may include a memory cell array 1000 and control logic 1500. The accompanying drawings illustrate the storage device 100 including a memory cell array 1000, but one or more embodiments are not limited thereto. For example, the storage device 100 may include multiple memory cell arrays 1000. The memory cell array 1000 may include memory cells arranged in regions where word lines and bit lines intersect, and the memory cells may be non-volatile memory cells.

[0029] The storage device 100 may include, for example, NAND flash memory, vertical NAND (VNAND), NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), etc.

[0030] The storage cell array 1000 can have a two-dimensional array structure or, as shown below, a two-dimensional array structure. Figure 3 The three-dimensional array structure is shown. In the following description, for ease of illustration, memory device 100 may be described as a non-volatile memory device. However, one or more embodiments are not limited thereto.

[0031] A memory cell array 1000 with a three-dimensional array structure is monolithically formed on at least one physical level of the memory cell array 1000. Each memory cell array 1000 includes an active region on a silicon substrate and circuitry formed on or in the substrate for operation of the memory cell. The term "monolithic" may indicate that layers at each level of the array are directly stacked on top of each layer of the next lower level of the array. In embodiments, the memory cell array 1000 with a three-dimensional array structure includes vertically arranged strings of cells such that at least one memory cell is located on top of another memory cell. At least one memory cell may include a charge trapping layer. The disclosures of U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference in their entirety, disclosing three-dimensional memory arrays configured in a hierarchical manner, with word lines and / or bit lines shared between the levels.

[0032] Control logic 1500 can control all operations of memory device 100. For example, control logic 1500 can control memory device 100 to perform memory operations corresponding to the command CMD provided by memory controller 200. For example, control logic 1500 can generate various internal control signals used in memory device 100 in response to the control signal CTRL provided by memory controller 200. For example, control logic 1500 can adjust the voltage levels supplied to word lines and bit lines when performing memory operations such as programming or erasing operations.

[0033] Programming or erasing operations within memory operations can each comprise a loop. This description primarily focuses on programming operations, but one or more embodiments are not limited thereto. For example, programming operations can be performed according to the ISPP method. Each programming loop included in a programming operation can include at least one section. For example, such as... Figure 14As shown, a programming cycle can include a setup phase, a programming and verification phase, and a recovery phase.

[0034] The control logic 1500 may include a precharge manager 1510, which may precharge the cell strings of the memory cell array 1000 at a uniform voltage during a precharge phase included in the verification phase.

[0035] The memory controller 200 can control the storage device 100 in response to requests from the host. For example, the memory controller 200 can control the storage device 100 to read or write data DATA stored in the storage device 100 in response to a read / write request from the host. The memory controller 200 can control write, read, and erase operations on the storage device 100 by providing the address ADDR, command CMD, and control signal CTRL to the storage device 100. Furthermore, the data DATA used for the above operations can be exchanged between the memory controller 200 and the storage device 100. That is, the memory controller 200 can interface and communicate with both the host and the storage device 100.

[0036] The memory controller 200 may include random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM may serve as the working memory of the processing unit, and the processing unit may control the operation of the memory controller 200. The host interface may include protocols for exchanging data between the host and the memory controller 200. For example, the memory controller 200 may communicate with the host using at least one of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), SCSI, Enhanced Small Digital Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0037] Figure 2 This is a block diagram of a storage device according to an example embodiment.

[0038] Reference Figure 2 The storage device 100 may include a storage cell array 1000, a row decoder 1100, a voltage generator 1200, a page buffer circuit 1300, a data input / output circuit 1400, and control logic 1500. The storage device 100 may also include configurations such as column decoders.

[0039] The storage cell array 1000 may include storage blocks (e.g., storage blocks BLK1, BLK2, and BLKn). Each storage block may include storage cells. Each storage cell may be a multi-level cell (MLC) that stores at least two bits of data. For example, each storage cell may be a two-bit MLC that stores two bits of data, a three-bit TLC that stores three bits of data, a four-bit QLC that stores four bits of data, or a multi-level cell that stores five or more bits of data. However, one or more embodiments are not limited thereto. For example, some storage cells may be single-level cells (SLCs) that store one bit of data, while other storage cells may be multi-level cells.

[0040] The memory cell array 1000 can be connected to the row decoder 1100 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to the page buffer circuit 1300 via the bit line BL.

[0041] The memory cell array 1000 may include strings connected to the bit line BL. Each string may include at least one string select transistor SST, a memory cell MC, and at least one ground select transistor GST connected in series between the bit line BL and the common source line CSL. Each string may also include at least one dummy cell located between the string select transistor SST and the memory cell MC, and at least one dummy cell located between the ground select transistor GST and the memory cell MC.

[0042] The row decoder 1100 can select some word lines WL based on the row address X-ADDR. The row decoder 1100 can transmit the applied voltage to the word lines WL. During a data write operation, the row decoder 1100 can apply programming and verification voltages to the selected word lines and apply programming disable voltages to the unselected word lines. During a data read operation, the row decoder 1100 can transmit read voltages to the selected word lines and read disable voltages to the unselected word lines. Furthermore, the row decoder 1100 can select some serial select lines SSL or some ground select lines GSL based on the row address X-ADDR.

[0043] Voltage generator 1200 can generate various types of voltages based on the voltage control signal CTRL_VOL to perform write, read, and erase operations on the memory cell array 1000. For example, voltage generator 1200 can generate a word line drive voltage VWL for driving word lines WL. In this case, the word line drive voltage VWL can be a programming voltage, read voltage, erase voltage, disable voltage, recovery voltage, or programming verification voltage.

[0044] Although not shown, voltage generator 1200 can also generate a series select line drive voltage VSSL for driving the series select line SSL and a ground select line drive voltage VGSL for driving the ground select line GSL.

[0045] Furthermore, the voltage generator 1200 can generate voltages for pre-charging the cell string during the pre-charge phase included in the verification phase. For example, it can generate a bit line pre-charge voltage Vpre_BL for pre-charging the bit line BL, and a CSL pre-charge voltage Vpre_CSL for pre-charging the common source line CSL.

[0046] Voltage generator 1200 can transmit bit line precharge voltage Vpre_BL to page buffer circuit 1300 and CSL precharge voltage Vpre_CSL to row decoder 1100.

[0047] Page buffer circuit 1300 can be connected to memory cell array 1000 via bit line BL, and can perform data write or data read operations in response to page buffer control signal CTRL_PB received from control logic 1500. Page buffer circuit 1300 can be connected to data line DL using decoded column address select bit line BL. The number of data lines DL can be less than the number of bit lines BL.

[0048] The page buffer circuit 1300 may include a page buffer for storing data to be programmed during a data write operation or data to be read during a data read operation.

[0049] Each page buffer can precharge the cell string connected to the bit line BL according to the bit line precharge voltage Vpre_BL.

[0050] The data input / output circuit 1400 can be connected to the page buffer circuit 1300 via the data line DL to provide input data DATA to the page buffer circuit 1300, or to output the data DATA provided by the page buffer circuit 1300 to the outside.

[0051] Control logic 1500 can be based on the memory controller (e.g., Figure 1The memory controller 200 receives the command CMD, address ADDR, and control signal CTRL, and outputs various internal control signals for storing data in or reading data from the memory cell array 1000. These internal control signals output from the control logic 1500 can be provided to the row decoder 1100, voltage generator 1200, page buffer circuit 1300, and data input / output circuit 1400. For example, the control logic 1500 can provide the row address X-ADDR to the row decoder 1100, the voltage control signal CTRL_VOL to the voltage generator 1200, the page buffer control signal CTRL_PB including the first control signal BLSHF to the page buffer circuit 1300, and the input / output control signal CTRL_I / O to the data input / output circuit 1400. The types of control signals are not limited to these; the control logic 1500 can also provide other internal control signals. For example, the control logic 1500 can provide the column address to the column decoder.

[0052] The precharge manager 1510 can control various signals used to precharge the cell string during a portion of the verification phase. This portion can be referred to as the precharge phase. For example, the precharge phase can be formed at the end of the verification phase.

[0053] For example, the precharge manager 1510 can provide the page buffer control signal CTRL_PB, including the first control signal BLSHF, to the page buffer circuit 1300 to provide the bit line precharge voltage Vpre_BL to the bit line BL. As another example, the row address X-ADDR for selecting a specific cell string can be provided to the row decoder 1100 to precharge that specific cell string. That is, the precharge manager 1510 can select the cell string for precharging by sending a control signal to the string selection transistor SST or the ground selection transistor GST.

[0054] Figure 3 This is an example diagram illustrating a storage cell array according to an example embodiment.

[0055] Figure 3 It can be a correspondence according to the embodiment Figure 2 The circuit diagram of the memory block. Figure 3 The storage block is a reference Figure 2 Examples of storage blocks BLK1, BLK2, and BLKn described. Figure 3 The first memory block BLK1 is shown. The first memory block BLK1 is a three-dimensional memory block with a three-dimensional structure on a substrate. The string of memory cells included in the first memory block BLK1 can be formed in a direction D1 perpendicular to the substrate.

[0056] Reference Figure 2and Figure 3 The first storage block BLK1 may include cell strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground select lines GSL1 to GSL3, string select lines SSL1 to SSL3, and common source line CSL. Figure 3 The illustration shows that each of the cell strings NS11 to NS33 includes eight memory cells MC connected to eight word lines WL1 to WL8 respectively, but one or more embodiments are not limited thereto.

[0057] Each cell string NS11 to NS33 may include a series-connected string select transistor SST, a memory cell MC, and a ground select transistor GST. The string select transistor SST can be connected to the corresponding string select line SSL1. The memory cell MC can be connected to the corresponding word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select line GSL1. The string select transistor SST can be connected to the corresponding bit line BL1, and the ground select transistor GST can be connected to the common source line CSL. Although not shown, it is referenced above. Figure 2 As described, at least one dummy cell may be included between the string select transistor SST and the memory cell MC, and at least one dummy cell may also be included between the ground select transistor GST and the memory cell MC.

[0058] Word lines at the same height (e.g., word line WL1) can be commonly connected to cell strings NS11 to NS33, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separate. According to this embodiment, by controlling the ground select lines GSL1 to GSL3 or the string select lines SSL1 to SSL3, only some cell strings can be selected and precharged during the precharge phase.

[0059] When performing programming operations, the storage device 100 according to the embodiment can precharge the cell string at a specific voltage in a precharge phase included in the verification phase.

[0060] During the ISPP programming operation according to the embodiment, the memory cell closest to the common source line CSL (e.g., memory cell MC1) can be programmed first, and then programming can be performed in the D1 direction closer to the string select line SSL. However, the programming direction is not limited to this. The memory cell adjacent to the string select line SSL (e.g., memory cell MC8) can be programmed first, and then programming can be performed in a downward direction. In the following, for convenience, the programming operation of the selected memory cell MC4 is described as being performed in the cell string NS11 connected to the bit line BL1; however, the embodiment is not limited to this.

[0061] The channels of memory cells MC5 to MC8, located above the selected memory cell MC4 which has been programmed, can be in a floating state, and the voltage of the floating channels can be reduced to a negative level due to the influence of the selected memory cell MC4. This reduction can be called a negative boost. Due to the negative boost, the voltage difference between the channels of memory cells MC1 to MC3 located below the selected memory cell MC4 and the channels of memory cells MC5 to MC8 increases, and therefore, memory cell MC may be degraded due to hot carrier injection.

[0062] According to an embodiment, programming operations for the selected memory cell MC4 can be completed, and the voltage of the channel of the cell string including the selected memory cell MC4 can be pre-charged in the latter part of the verification phase before performing the recovery operation. For convenience, the cell string including the selected memory cell MC4 can be referred to as the selected cell string NS11. For example, the selected cell string NS11 can be pre-charged, but one or more embodiments are not limited thereto. Other cell strings NS21 and NS31 connected to the bit line BL1 connected to the selected cell string NS11 can also be pre-charged. In addition, all cell strings NS11 to NS33 connected to the common source line CSL can also be pre-charged.

[0063] Therefore, since the next operation can be performed while the voltage of the channel above the selected word line WL4 is increased, negative boost can be limited, thereby preventing memory cell degradation.

[0064] Furthermore, according to the embodiment, during the verification phase after the programming operation of the selected memory cell MC4 is completed, a read pass voltage Vread can be applied to the word line of the selected memory cell MC4 and the word lines of the unselected memory cells MC1 to MC3 and MC5 to MC8. The read pass voltage Vread applied to the selected word line WL4 for a specific period of time after the programming operation is completed can be referred to as the post pulse.

[0065] In this situation, read interference may occur in the word lines adjacent to the selected word line WL4 (e.g., word lines WL3 and WL5) among the unselected word lines WL1 to WL3 and WL5 to WL8 due to coupling caused by the afterpulse.

[0066] According to this embodiment, while pre-charging the cell string, a specific voltage can be applied to the selected word line WL4 and its adjacent word lines WL3 and WL5 to prevent coupling caused by the post-pulse. This is exemplified by having two adjacent word lines, but one or more embodiments are not limited to this. The number of word lines is not necessarily symmetrical about the selected word line.

[0067] Figure 4This is a block diagram of a storage device according to an example embodiment.

[0068] Reference Figure 2 and Figure 4 The page buffer circuit 1300 may include page buffers PB1, PB2, and PBn. Page buffers PB1, PB2, and PBn may all be connected to some bit lines BL. Page buffers PB1, PB2, and PBn may each include latches such as sense latches, data latches, and cache latches, and may also include precharge circuitry and bit line selection circuitry.

[0069] According to this embodiment, the page buffer circuit 1300 can receive a page buffer control signal CTRL_PB from the control logic 1500. The page buffer control signal CTRL_PB can control all operations of the page buffer circuit 1300. For example, the page buffer control signal CTRL_PB may include a first control signal BLSHF, and the precharge circuit of the page buffer circuit 1300 can precharge the bit lines with a specific voltage according to the first control signal BLSHF. The specific voltage may be, for example, the bit line precharge voltage Vpre_BL received from the voltage generator 1200.

[0070] Control logic 1500 can generate control signals for controlling the transistors constituting the precharge circuit included in page buffer circuit 1300, and can provide control signals to page buffer circuit 1300. Therefore, the time taken to apply the bit line precharge voltage Vpre_BL to the connected bit line and the level of the bit line precharge voltage Vpre_BL can be determined.

[0071] During the pre-charge phase, the page buffer circuit 1300 according to this embodiment can provide a bit line pre-charge voltage Vpre_BL to all connected bit lines, thereby enabling pre-charging of the cell string connected to the bit lines.

[0072] The method by which the page buffer circuit 1300 provides the bit line precharge voltage Vpre_BL to the bit line can vary. (Refer to...) Figures 5 to 8 Descriptions of two methods are provided, but one or more embodiments are not limited thereto.

[0073] Figure 5 This is a circuit diagram of the page buffer according to an example embodiment.

[0074] Reference Figure 4 and Figure 5 The page buffer 1310, which corresponds to the page buffer PB1, may include a precharge circuit, a bit line selection circuit, a sense latch, a data latch, etc., but only the precharge circuit is described in this document.

[0075] The precharge circuit of the page buffer 1310 may include first to fourth transistors N1 to N3 and P1. Transistors N1 to N3 and P1 may be turned on or off in response to their respective control signals. According to this embodiment, the page buffer 1310 may include a first transistor N1 turned on according to a first control signal BLSHF, a second transistor N2 turned on according to a second control signal CLBLK, a third transistor N3 turned on according to a third control signal BLCLAMP, and a fourth transistor P1 turned on according to a fourth control signal BLSETUP. One end of the fourth transistor P1 and one end of the second transistor N2 may be connected to the sense output node SO_NODE.

[0076] The first to third transistors N1 to N3 can be NMOS transistors. The first to third transistors N1 to N3 can be turned on when a logic high control signal is transmitted and turned off when a logic low control signal is transmitted. The fourth transistor P1 can be a PMOS transistor. The fourth transistor P1 can be turned off when a logic high control signal is transmitted and turned on when a logic low control signal is transmitted.

[0077] For example, the precharge circuit can turn on the first transistor N1, the second transistor N2, and the fourth transistor P1, and turn off the third transistor N3 to provide the bit line precharge voltage Vpre_BL from the voltage generator to the bit line BL. In order to turn on the fourth transistor P1, the data stored in the latch circuit connected to the fourth transistor P1 can have a specific value (e.g., "1").

[0078] The timing of each transistor's turn-on or the level of the turn-on voltage provided to each transistor can be determined based on the page buffer control signal CTRL_PB provided from the control logic.

[0079] Figure 6 This is a timing diagram illustrating the operation of the page buffer according to an example embodiment.

[0080] As shown above (refer to the reference) Figure 1 As described, a programming cycle may include a setup phase, a programming and verification phase, and a recovery phase. For convenience, the description of the programming phase may be omitted, and the verification phase VFYNOM, the recovery phase VFYRCV, and the setup phase BLSETUP may be shown sequentially for time points t1, t2, and t3, which can be considered as points in time. The timings in the timing diagram may not be represented at a fixed ratio.

[0081] The pre-charge phase can correspond to time points t1 and t2. For ease of illustration, the verification phase VFYNOM can be a phase that does not include the pre-charge phases t1 to t2, and can only indicate the phase up to time point t1.

[0082] Reference Figure 5 and Figure 6 During the precharge phases t1 to t2, the level of the first control signal BLSHF can change from an off level to an on level, as shown by the solid line. As another example, the level of the first control signal BLSHF can change to an on level immediately at time t1 instead of being off, as shown by the dashed line. The level of the second control signal CLBLK can change to an on level (e.g., power supply voltage Vdd). The level of the fourth control signal BLSETUP can change to an on level (e.g., ground voltage Vss). The third control signal BLCLAMP can remain off. Therefore, during the precharge phases t1 to t2, the first transistor N1, the second transistor N2, and the fourth transistor P1 can be turned on, so the bit line precharge voltage Vpre_BL can be provided to the connected bit line.

[0083] At time t2, when the recovery phase VFYRCV begins, the level of the first control signal BLSHF can be changed to the off level. The second control signal CLBLK, the third control signal BLCLAMP, and the fourth control signal BLSETUP can maintain their respective states.

[0084] The start time tl and end time t2 of the pre-charge phase can be determined by the pre-charge manager.

[0085] Figure 7 This is a circuit diagram of the page buffer according to an example embodiment.

[0086] References can be omitted Figure 5 The provided description is duplicated.

[0087] Reference Figure 4 and Figure 7 Page buffer 1310 can be used with reference Figure 5 and Figure 6 The described methods provide a bit line precharge voltage Vpre_BL to the connected bit lines. That is, the precharge circuit can turn on the first transistor N1 and the third transistor N3, and can turn off the second transistor N2 and the fourth transistor P1.

[0088] Figure 8 This is a timing diagram illustrating the operation of the page buffer according to an example embodiment.

[0089] Reference Figure 7 and Figure 8During the pre-charge phases t1 to t2, the level of the first control signal BLSHF can change from an off level to an on level, as shown by the solid line. As another example, the level of the first control signal BLSHF can change to an on level immediately at time t1 instead of an off level, as shown by the dashed line. The level of the third control signal BLCLAMP can change to an on level (e.g., the supply voltage Vdd). The second control signal CLBLK can remain at an off level, and the fourth control signal BLSETUP can remain at an on level.

[0090] Therefore, the first transistor N1 and the third transistor N3 can be turned on, while the second transistor N2 and the fourth transistor P1 can be turned off. Thus, the bit line precharge voltage Vpre_BL can be provided through the connected bit lines.

[0091] Simultaneously, time points t1 and / or t2 can be determined as sufficient to precharge the cell string connected to the bit lines during the precharge phases t1 to t2. For example, sufficient duration can indicate the time taken to precharge all bit lines at the same voltage level (e.g., using the bit line precharge voltage Vpre_BL).

[0092] Furthermore, when the pre-charging operation of the cell string affects the performance of the storage device, the length of the pre-charging phase t1 to t2 can be determined based on the performance of the storage device.

[0093] The following describes the operation of precharging the cell string connected to the bit line during the precharge phases t1 to t2, while simultaneously controlling the word line WL, the string select line SSL, the ground select line GSL, or the common source line CSL.

[0094] Figures 9 to 13 This is a timing diagram illustrating the pre-charge operation according to an example embodiment.

[0095] In the following text, see also reference Figure 3 This describes an example where the selected word line is word line WL4 and the selected memory cell is memory cell MC4.

[0096] Reference Figure 3 and Figure 9 During the pre-charge phase t1 to t2, the level of the control signal BLSHF can be off and then on, as shown by the solid line. As shown by the dashed line, the level of the control signal BLSHF during the pre-charge phase may not be off, but can change to on immediately at time t1.

[0097] During the precharge phases t1 to t2, the bit lines and cell strings can be precharged via the precharge circuitry of the page buffer. When the precharge circuitry is connected to all bit lines BL1 to BL3, the bit line precharge voltage Vpre_BL can be provided to the bit lines BL1 to BL3, thus allowing all cell strings NS1 to NS33 connected to the bit lines BL1 to BL3 to be precharged.

[0098] During the precharge phases t1 to t2, a first voltage V1 can be applied to the selected word line sel_WL, while a negative voltage is applied to it. For example, the first voltage V1 can be the read pass voltage Vread or the power supply voltage Vdd. A second voltage V2 can be maintained for the unselected word lines unsel_WL (e.g., word lines WL1 to WL3 and WL5 to WL8). For example, the second voltage V2 can be the read pass voltage Vread and can be the same as or have a different value than the first voltage V1. During the precharge phases t1 to t2, a third voltage V3 can be applied to the serial select line SSL. Due to the application of the third voltage V3, the serial select transistor SST connected to the serial select line SSL can be turned on.

[0099] For example, when the string selection transistor SST is turned on, the bit line precharge voltage Vpre_BL applied to bit line BL1 can be used to precharge the selected cell string NS11 connected to bit line BL1.

[0100] Then, in the recovery phase VFYRCV, the recovery voltage Vrcv can be applied to the selected word line sel_WL and the unselected word line unsel_WL.

[0101] Although not shown, during the pre-charge phases t1 to t2, an on-state or off-state voltage can be applied to the ground select line GSL. Depending on whether the ground select transistor GST is on, the voltage on the common source line CSL can have a specific voltage level or can be in a floating state.

[0102] For example, when a turn-on voltage is applied to the ground select line GSL, the ground select transistor GST can turn on, and the charge of the pre-charged cell string can flow into the common source line CSL, thus pre-charging the common source line CSL.

[0103] As another example, when a turn-off voltage is applied to the ground select line GSL, the ground select transistor GST can be turned off, and the charge of the pre-charged cell string will not flow into the common source line. Therefore, the common source line CSL can have a constant voltage (e.g., 0V) regardless of whether the cell string is pre-charged.

[0104] Reference Figure 9In the initial part of the verification phase of VFYNOM, a read-through voltage (Vread) or turn-on voltage can be continuously applied to the serial select lines SSL1 to SSL3 for a first time, and a ground voltage (Vss) or turn-off voltage can be continuously applied to the serial select lines SSL1 to SSL3 for a second time. In this case, the voltage applied continuously for the first time can be referred to as the pre-pulse.

[0105] Reference Figures 3 to 10 ,and Figure 9 The difference shown is that, in the initial part of the verification phase of VFYNOM, a pre-pulse may not be applied to the string select lines SSL1 through SSL3. Apart from not applying a pre-pulse to the string select lines SSL1 through SSL3, the other conditions are the same as the reference. Figure 9 The conditions described are the same, so the description will not be repeated.

[0106] In the initial part of the verification phase VFYNOM, a turn-on voltage can be applied to the selected string selection line sel_SSL (e.g., SSL1), and the turn-on voltage can be maintained in the pre-charge phase t1 to t2 and the recovery phase VFYRCV.

[0107] A turn-on voltage can be applied to the unselected string select lines unsel_SSL (e.g., SSL2 and SSL3) for a specific time period during the initial part of the verification phase of VFYNOM, and then a turn-off voltage can be applied to them. During the pre-charge phases t1 to t2, the turn-on voltage can be applied to the unselected string select lines SSL2 and SSL3 again.

[0108] Therefore, even without a pre-pulse applied, all string select lines SSL1 to SSL3 can be turned on, and all connected unit strings NS11 to NS31 can be pre-charged.

[0109] Reference Figure 3 and Figure 11 During the pre-charge phases t1 to t2, a voltage different from the voltage applied to the unselected word line unsel_WL can be applied to adjacent word lines N-1_WL and N+1_WL adjacent to the selected word line sel_WL. (See reference...) Figure 11 The preceding pulse can be applied to the string select lines SSL1 to SSL3, but one or more embodiments are not limited thereto.

[0110] When the selected word line sel_WL is the nth word line, the adjacent word lines N-1_WL and N+1_WL can be the word line N-1_WL below the selected word line sel_WL and the word line N+1_WL above the selected word line sel_WL. For example, when N equals 4, the adjacent word lines N-1_WL and N+1_WL can be word lines WL3 and WL5. The number of adjacent word lines N-1_WL and N+1_WL does not need to be symmetrical about the selected word line sel_WL. For example, when N equals 4, the adjacent word lines N-1_WL and N+1_WL of the selected word line sel_WL can be word lines WL2, WL3, WL5, WL6, and WL7 or word lines WL1, WL2, WL3, WL5, and WL6. (See reference...) Figure 11 The number of adjacent word lines N-1_WL and N+1_WL can be two, and the reference is omitted. Figure 9 and Figure 10 The provided description is redundant. Additionally, unselected word line unsel_WL refers to all word lines except for selected word line sel_WL and adjacent word lines N-1_WL and N+1_WL.

[0111] During the verification phase of VFYNOM, a fourth voltage V4 can be applied to adjacent word lines N-1_WL and N+1_WL. The fourth voltage V4 has a different level than the second voltage V2 applied to the unselected word line unsel_WL. For example, the level of the fourth voltage V4 can be higher than the level of the second voltage V2.

[0112] During the pre-charge phases t1 to t2, a first voltage V1 can be applied to adjacent word lines N-1_WL and N+1_WL, the same as the voltage applied to the selected word line sel_WL. The first voltage V1 can be the supply voltage Vdd (e.g., 2V). As another example, a voltage with a different level than the first voltage V1 applied to the selected word line sel_WL can be applied to adjacent word lines N-1_WL and N+1_WL. A second voltage V2 can be maintained in the unselected word line unsel_WL. For example, the level of the second voltage V2 can be higher than the level of the first voltage V1.

[0113] Then, in the recovery phase VFYRCV, the recovery voltage Vrcv can be applied to word lines N-1_WL, sel_WL, N+1_WL, and unsel_WL.

[0114] According to an embodiment, during the verification phase of VFYNOM, a back pulse can be applied to a selected word line sel_WL within a specific time period. In this case, read interference (Disturbance) may occur in adjacent word lines N-1_WL and N+1_WL due to coupling caused by the back pulse.

[0115] According to this embodiment, a specific voltage can be applied to adjacent word lines N-1_WL and N+1_WL as well as the selected word line sel_WL instead of the read pass voltage Vread, to prevent coupling caused by applying the read pass voltage Vread to the unselected word line unsel_WL.

[0116] Reference Figure 2 , Figure 3 and Figure 12 To precharge cell strings NS11 to NS33, a bit line precharge voltage Vpre_BL can be applied to each of the connected bit lines BL1 to BL3, or the common source line CSL connected to cell strings NS11 to NS33 can be precharged at a specific voltage level.

[0117] As an exemplary method of pre-charging the common source line CSL at a specific voltage level, the common source line CSL can be pre-charged due to the cell current flowing in cell strings NS11 to NS31 when bit line BL1 is pre-charged. In this case, cell strings NS12 to NS33, which are not connected to the pre-charged bit line BL1, can be pre-charged because the common source line CSL is pre-charged.

[0118] As another example, the CSL precharge voltage Vpre_CSL can be applied to the common source line CSL regardless of whether the bit line BL1 is precharged.

[0119] First, the following situation is described: When bit line BL1 is precharged using the bit line precharge voltage Vpre_BL, the common source line CSL is precharged due to the cell current flowing in cell strings NS11 to NS31. (Reference omitted) Figures 9 to 11 The provided description is duplicated.

[0120] During the pre-charge phases t1 to t2, a fifth voltage V5 can be applied to the ground select line GSL1. The fifth voltage V5 can be the turn-on voltage of the ground select transistor GST. Therefore, when the ground select transistor GST is turned on, and when the cell strings NS11 to NS31 connected to bit line BL1 are pre-charged using the bit line pre-charge voltage Vpre_BL, the voltage on the common source line CSL connected to cell strings NS11 to NS31 can increase. Therefore, cell strings NS12 to NS33 connected to bit lines BL2 and BL3, which are not subject to the applied bit line pre-charge voltage Vpre_BL, can be pre-charged.

[0121] Reference Figure 3 and Figure 13Regardless of whether bit line BL1 is precharged, the CSL precharge voltage Vpre_CSL can be applied to the common source line CSL. Therefore, all cell strings NS11 to NS33 can be precharged. The CSL precharge voltage Vpre_CSL can be generated by a voltage generator and applied to the common source line CSL.

[0122] During the pre-charge phases t1 to t2, the off-level of the control signal BLSHF can be maintained. In this case, a sixth voltage V6 can be applied to the common source line CSL.

[0123] As referenced above Figure 12 As described, during the pre-charge phases t1 to t2, a fifth voltage V5 can be applied to the ground selection line GSL1, and the ground selection transistor GST can be turned on. Therefore, when a sixth voltage V6, which is pre-charged in the common source line CSL, is applied to the connected cell strings NS11 to NS33, the cell strings NS11 to NS33 can be pre-charged.

[0124] During the verification phase of VFYNOM, a pre-pulse may not be applied to the serial select lines SSL1 to SSL3 and the ground select lines GSL1 to GSL3. That is, during the pre-charge phases t1 to t2, when the current pulse is applied to at least one of the unselected serial select line unsel_SSL and the unselected ground select line unsel_GSL, a voltage of a specific level may be applied again to the connection line to which the pre-pulse was applied.

[0125] The voltage levels applied to the selected string select line sel_SSL and the selected ground select line sel_GSL (which have been applied with a specific voltage level in the verification phase VFYNOM) during the precharge phase t1 to t2 and the recovery phase VFYRCV can be maintained.

[0126] Figure 14 This is a conceptual diagram of the programming loop based on the example embodiment.

[0127] Reference Figure 14 The Nth programming loop (LOOP(N)) may include a verification phase (VERIFY) and a programming phase (PROGRAM). The verification phase (VERIFY) may include a normal verification phase (VFYNOM), a recovery phase (VFYRCV), and a setup phase (BLSETUP), and the programming phase (PROGRAM) may include a programming execution phase (PGMEX). A precharge operation of the cell string may be performed after the normal verification phase (VFYNOM) before the recovery phase (VFYRCV) begins.

[0128] Figure 15 This is an example diagram illustrating the timing of the pre-charge operation according to an example embodiment.

[0129] Reference Figure 15 The programming loops LOOP1, LOOP2, LOOP3, and LOOPn can be executed sequentially according to the ISPP programming method.

[0130] The pre-charging of the unit string according to this embodiment is not limited to pre-charging performed in every programming loop. That is, the unit string can be pre-charged at least once in at least one of the n programming loops. Furthermore, the pre-charging operation of the unit string does not need to be repeated in consecutive programming loops. For example, the unit string can be pre-charged in the first programming loop and the unit string can be pre-charged in the third programming loop.

[0131] The number of times or intervals in which the unit string is precharged can be determined by the precharge manager. For example, the number of times or intervals can be determined based on the count of the programming loop being executed.

[0132] Figure 16 This is a flowchart of an operation method of a storage device according to an example embodiment.

[0133] Reference Figure 2 and Figure 16 In operation S110, the storage device 100 can perform programming operations on selected memory cells. For example, a programming cycle can be executed according to the ISPP method, and each programming cycle can include a setup phase, a programming and verification phase, and a recovery phase. When the programming operation on the selected memory cell is completed, the verification phase can begin.

[0134] During the verification phase, in operation S120, the storage device 100 may precharge a cell string including selected memory cells. According to one or more embodiments, the storage device 100 may precharge the bit lines connected to the cell string and precharge the common source line CSL to precharge the cell string.

[0135] The cell strings or all cell strings of the memory cell array 1000 connected to a cell string and a bit line can be precharged by the precharge manager 1510.

[0136] The voltage level for precharging the cell string or the time required for precharging the cell string can be determined by the precharge manager 1510.

[0137] The precharge operation of the unit string can be performed in any programming loop. In all programming loops, the precharge operation of the unit string can be performed at least once.

[0138] Once the precharge operation of the cell string is complete, the storage device 100 can perform a recovery operation.

[0139] Figure 17This is a block diagram of a solid-state drive (SSD) system according to an example embodiment.

[0140] Reference Figure 17 The SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 receives a signal SGL from the host 2100 via a signal connector and receives power PWR via a power connector. The SSD 2200 may include an SSD controller 2210, an auxiliary power supply 2220, and storage devices 2230, 2240, and 2250. Storage devices 2230, 2240, and 2250 may be connected to the SSD controller 2210 via channels Ch1, Ch2, and Chn, respectively. Storage devices 2230, 2240, and 2250 may be vertically stacked NAND flash memory devices. In this case, at least one of storage devices 2230 to 2250 may be implemented as described in reference... Figures 1 to 16 The described process involves precharging the cell string and performing a recovery operation.

[0141] Although embodiments have been specifically shown and described with reference to their examples, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile storage device, comprising: A memory cell array comprising multiple cell strings, wherein each cell string includes a string select transistor connected in series between a bit line and a common source line, multiple memory cells, and a ground select transistor; and A control circuit configured to: perform a programming operation on a selected memory cell among the plurality of memory cells, and precharge a selected cell string including the selected memory cell in a precharge phase included in the verification phase. Specifically, when a first pre-charge voltage is applied to the selection line connected to the selected memory cell, the selected cell string is pre-charged. The control circuit is further configured to: apply a first voltage to the selected word line of the selected memory cell during the pre-charge phase, and apply a second voltage to multiple unselected word lines of the remaining memory cells of the plurality of memory cells, wherein the level of the first voltage is lower than the level of the second voltage.

2. The non-volatile memory device of claim 1, further comprising a page buffer connected to the select line and including a plurality of transistors configured to apply the first precharge voltage to the select line.

3. The non-volatile storage device according to claim 2, wherein, The page buffer is configured to: during the pre-charge phase, change the level of a first control signal to an on level, change the level of a second control signal from an off level to the on level, and change the level of a third control signal from the off level to the on level.

4. The non-volatile storage device according to claim 2, wherein, The page buffer is configured to: during the precharge phase, change the level of a first control signal to an on level and change the level of a second control signal from an off level to the on level.

5. The non-volatile storage device according to claim 1, wherein, The control circuit is further configured to apply a third voltage to one of the adjacent word lines that are adjacent to the selected word line among the plurality of unselected word lines during the pre-charging phase.

6. The non-volatile storage device according to claim 5, wherein, The level of the third voltage is equal to the level of the first voltage.

7. The non-volatile storage device according to claim 1, wherein, The control circuit is further configured to: apply a pre-pulse voltage to a plurality of string select transistors of the memory cell array for a first time during the verification phase other than the pre-charge phase, apply a turn-off voltage to the plurality of string select transistors for a second time, and apply a turn-on voltage to the plurality of string select transistors during the pre-charge phase.

8. The non-volatile storage device according to claim 1, wherein, The control circuit is further configured to: apply a pre-pulse voltage to the selected string selection transistor connected to the selected memory cell for a first time during the verification phase other than the pre-charge phase, apply a turn-off voltage to the selected string selection transistor for a second time during the pre-charge phase, and apply a turn-on voltage to the selected string selection transistor during the pre-charge phase.

9. The non-volatile storage device according to claim 1, wherein, Depending on whether the ground selection transistor is turned on, the voltage of the common source line includes either a first voltage or a floating voltage.

10. A non-volatile storage device, comprising: A memory cell array comprising multiple cell strings, wherein each cell string includes a string select transistor connected in series between a bit line and a common source line, multiple memory cells, and a ground select transistor; and A control circuit configured to: perform a programming operation on a selected memory cell among the plurality of memory cells, and precharge a selected cell string including the selected memory cell in a precharge phase included in the verification phase. Specifically, when a first pre-charge voltage is applied to a selected common source line connected to the selected memory cell, the selected cell string is pre-charged. The control circuit is further configured to: apply a first voltage to the selected word line of the selected memory cell during the pre-charge phase, and apply a second voltage to multiple unselected word lines of the remaining memory cells of the plurality of memory cells, wherein the level of the first voltage is lower than the level of the second voltage.

11. The non-volatile storage device according to claim 10, wherein, The first pre-charge voltage is applied by a voltage generator.

12. The non-volatile memory device of claim 10, further comprising a page buffer connected to a select line connected to the selected memory cell and including a plurality of transistors configured to apply a second pre-charge voltage to the select line. in, The first pre-charge voltage is generated from the cell current, which flows in the plurality of cell strings connected to the selected positioning line based on the second pre-charge voltage.

13. The non-volatile storage device according to claim 10, wherein, The control circuit is also configured to: In the verification phase, excluding the pre-charge phase, a pre-pulse voltage is continuously applied to the plurality of ground selection transistors of the memory cell array for a first time, and a turn-off voltage is continuously applied to the plurality of ground selection transistors for a second time. During the pre-charge phase, an on-state voltage is applied to the plurality of ground selection transistors.

14. The non-volatile storage device according to claim 10, wherein, The control circuit is further configured to: apply a pre-pulse voltage to the selected ground selection transistor connected to the selected memory cell for a first time during the verification phase other than the pre-charge phase, apply a turn-off voltage to the selected ground selection transistor for a second time during the pre-charge phase, and apply a turn-on voltage to the selected ground selection transistor during the pre-charge phase.

15. A programming method for a non-volatile memory device, wherein the non-volatile memory device comprises a plurality of cell strings, wherein, Each of the plurality of cell strings includes a string select transistor connected in series between a bit line and a common source line, a plurality of memory cells, and a ground select transistor, and the programming method includes: Perform programming operations on selected memory cells among the plurality of memory cells; and Perform a programming verification operation on the selected memory cell. The programming verification operation includes: pre-charging a selected cell string, including the selected memory cell, before the recovery phase, and Specifically, the selected cell string is precharged when a first precharge voltage is applied to the selected positioning line connected to the selected memory cell, or when a second precharge voltage is applied to the selected common source line connected to the selected memory cell. The pre-charging of the selected cell string, including the selected memory cell, before the recovery phase includes: applying a first voltage to the selected word line of the selected memory cell and applying a second voltage to multiple unselected word lines of the remaining memory cells of the plurality of memory cells, wherein the level of the first voltage is lower than the level of the second voltage.

16. The programming method according to claim 15, wherein, The second pre-charge voltage is applied by a voltage generator or by a cell current generated based on the first pre-charge voltage.

17. The programming method according to claim 15, wherein, In at least one of a plurality of programming loops, the programming operation and the programming verification operation are performed sequentially to program the selected memory cell.

18. The programming method according to claim 15, wherein, The string selection transistor or the ground selection transistor of each of the cell strings is controlled to select the cell string to be precharged.

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