Memory devices and memory systems

Abstract

A memory device includes a multiphase clock generator that generates a plurality of divided clock signals, a first error correction block that receives a first divided clock signal of the plurality of divided clock signals, a first data multiplexer that sends first least significant bit data corresponding to the first divided clock signal, a second error correction block that receives the first divided clock signal, and a second data multiplexer that sends first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a switching time of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a switching time of the first most significant bit data.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0142873, filed on October 30, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to memory devices and memory systems. Background Technology

[0004] In a system comprising multiple semiconductor devices and employing multi-level signaling, a semiconductor memory device can store data. In response to a data processing device, such as a central processing unit (CPU), requesting data, the semiconductor memory device can output data corresponding to an address input from the data processing device, or it can store data at the input address.

[0005] With the increasing operating speed of systems including semiconductor devices and the further development of technologies related to semiconductor integrated circuits (ICs), it is expected that semiconductor memory devices can output and store data at increasingly higher speeds. As a result, synchronous memory devices capable of inputting / outputting data synchronously with the system clock for high-speed input / output data, as well as double data rate (DDR) synchronous memory devices that input / output data on both the rising and falling edges of the system clock, have been developed. Summary of the Invention

[0006] Embodiments of this disclosure provide a memory device that uses multi-level signaling and removes one or more errors in a multiphase clock.

[0007] Embodiments of this disclosure also provide a memory system that removes one or more errors in a multiphase clock in a memory device using multi-level signaling.

[0008] According to embodiments of this disclosure, a memory device is provided, comprising: a multiphase clock generator configured to generate a plurality of frequency-divided clock signals; a first error correction block configured to receive a first frequency-divided clock signal from the plurality of frequency-divided clock signals; a first data multiplexer configured to transmit a first least significant bit data corresponding to the first frequency-divided clock signal; a second error correction block configured to receive the first frequency-divided clock signal; and a second data multiplexer configured to transmit a first most significant bit data corresponding to the first frequency-divided clock signal. The first error correction block receives the first least significant bit data and corrects the switching time of the first least significant bit data, and the second error correction block receives the first most significant bit data and corrects the switching time of the first most significant bit data.

[0009] According to embodiments of this disclosure, a memory device is provided, comprising a memory interface, control logic circuitry for receiving commands from the memory interface, and a memory cell array controlled by the control logic circuitry for storing data. The memory interface generates multiple frequency-divided clock signals via a multiphase clock generator, receives a first frequency-divided clock signal from the multiple frequency-divided clock signals via a first error correction block, and transmits a first least significant bit data corresponding to the first frequency-divided clock signal via a first data multiplexer; it also receives the first frequency-divided clock signal via a second error correction block, and transmits a first most significant bit data corresponding to the first frequency-divided clock signal via a second data multiplexer. The first error correction block receives the first least significant bit data and corrects the switching time of the first least significant bit data, and the second error correction block receives the first most significant bit data and corrects the switching time of the first most significant bit data.

[0010] According to embodiments of this disclosure, a memory system is provided, comprising: a memory controller including a controller interface circuit; and a memory device including a memory interface receiving signals from the memory controller, control logic circuitry receiving commands from the memory interface, and a memory cell array storing data and connected to the control logic circuitry. The memory interface includes: a multiphase clock generator generating multiple frequency-divided clock signals; a first error correction block receiving a first frequency-divided clock signal from the multiple frequency-divided clock signals; a first data multiplexer transmitting a first least significant bit of data corresponding to the first frequency-divided clock signal; a second error correction block receiving the first frequency-divided clock signal; and a second data multiplexer transmitting a first most significant bit of data corresponding to the first frequency-divided clock signal. The first error correction block receives the first least significant bit of data and corrects the switching time of the first least significant bit of data, and the second error correction block receives the first most significant bit of data and corrects the switching time of the first most significant bit of data. Attached Figure Description

[0011] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 and Figure 2 A memory system according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A memory system according to some embodiments of the present disclosure is shown.

[0014] Figure 4 This is a block diagram of a memory interface of a memory device according to some embodiments of the present disclosure.

[0015] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 3Timing diagram of read operations for memory devices.

[0016] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 3 A flowchart of the operation of the memory device.

[0017] Figure 7 and Figure 8 This is a block diagram of the interface of a memory device according to some embodiments of the present disclosure.

[0018] Figure 9 This illustrates some embodiments according to the present disclosure. Figure 8 Timing diagram of read operations for memory devices.

[0019] Figure 10 This illustrates some embodiments according to the present disclosure. Figure 8 A flowchart of the operation of the memory device.

[0020] Figure 11 This is a block diagram of a memory interface of a memory device according to some embodiments of the present disclosure.

[0021] Figure 12 This is a block diagram of a memory system that applies a memory device according to some embodiments of the present disclosure.

[0022] Figure 13 This is a block diagram of a Universal Flash Memory (UFS) system that applies some embodiments of the memory device according to this disclosure. Detailed Implementation

[0023] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. The same reference numerals throughout the drawings may denote the same elements.

[0024] It should be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0025] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects in each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments.

[0026] Unless the context explicitly indicates otherwise, the singular forms “a,” “one,” and “the” used herein are intended to also include the plural forms.

[0027] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that these elements or values ​​are the same, equal to each other within measurement error, or, if not equal in measurement, sufficiently close in value to be functionally equal, as will be understood by one of ordinary skill in the art. For example, taking into account the measurement in question and the error associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term “approximately” as used herein includes a specified value and means within an acceptable deviation for a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations as understood by one of ordinary skill in the art. Furthermore, it should be understood that while a parameter may be described herein as having a “approximately” specific value, according to embodiments, a parameter may be precisely that specific value or approximately that specific value within measurement error, as will be understood by one of ordinary skill in the art. Other uses of these terms and similar terms used to describe relationships between components should be interpreted in a similar manner.

[0028] Figure 1 and Figure 2 A memory system according to some embodiments of the present disclosure is shown.

[0029] Reference Figure 1 The memory system 10 includes a memory controller 20 and a memory device 30. The memory controller 20 includes a clock signal generator (“CK generator”) 21, a command / address generator (“CA generator”) 22, a clock signal transmitter (“CA transmitter”) 23, a command / address register (“CA register”) 24, a command / address comparator (“CA comparator”) 26, a command / address phase / timing controller (“CA phase / timing controller”) 25, and a data input / output unit 27.

[0030] The memory controller 20 can provide the memory device 30 with a clock signal CK generated by the clock signal generator 21 via the clock signal line 11. The command / address generator 22 can generate an initial command / address signal CA0 and can provide the initial command / address signal CA0 to the command / address transmitter 23.

[0031] Command / address transmitter 23 can receive initial command / address signal CA0 and can generate first command / address signal CA1 by controlling the phase or timing of initial command / address signal CA0 in response to control signal CTRL from command / address phase / timing controller 25.

[0032] The first command / address signal CA1 can be provided to and stored in the command / address register 24. The first command / address signal CA1 can be provided to the memory device 30 via the command / address bus 12. The first command / address signal CA1 can be provided to the memory device 30 together with the clock signal CK.

[0033] Command / address register 24 stores the first command / address signal CA1. Command / address comparator 26 compares the first command / address signal CA1 stored in command / address register 24 with the third command / address signal CA3 output from data input / output unit 27. Command / address comparator 26 can compare the first command / address signal CA1 with the third command / address signal CA3 and can output a pass / fail signal P / F based on the comparison result.

[0034] For reference Figure 2 The command / address register 24 and the command / address comparator 26 can store and compare the first command / address signal CA1 and the third command / address signal CA3 at the rising and falling edges of the clock signal CK.

[0035] Reference Figure 2 The command / address register 24 may include a first register 24a that stores the first command / address signal CA1 on the rising edge of the clock signal CK, and a second register 24b that stores the first command / address signal CA1 on the falling edge of the clock signal CK. The command / address comparator 26 may include a first comparator 26a that compares the first command / address signal CA1 with the third command / address signal CA3 on the rising edge of the clock signal CK, and a second comparator 26b that compares the first command / address signal CA1 with the third command / address signal CA3 on the falling edge of the clock signal CK.

[0036] The first comparator 26a generates a first pass / fail signal by comparing the first command / address signal CA1 with the third command / address signal CA3 on the rising edge of the clock signal CK. The second comparator 26b generates a second pass / fail signal by comparing the first command / address signal CA1 with the third command / address signal CA3 on the falling edge of the clock signal CK. The command / address comparator 26 generates a pass / fail signal P / F by performing a logical OR operation on the first pass / fail signal and the second pass / fail signal.

[0037] Refer again Figure 1The command / address phase / timing controller 25 generates a control signal CTRL based on the pass / fail signal P / F from the command / address comparator 26. This control signal CTRL instructs the phase of the first command / address signal CA1 to be shifted. The control signal CTRL is provided to the command / address transmitter 23, and the command / address transmitter 23 generates the first command / address signal CA1 by controlling the phase or timing of the initial command / address signal CA0.

[0038] In normal mode, data input / output unit 27 receives read data R_Data1 from memory device 30 via data bus (“DQ”) 13 or sends write data W_Data1 to memory device 30 via DQ bus 13. In calibration mode, data input / output unit 27 receives a second command / address signal CA2 corresponding to the first command / address signal CA1 received by memory device 30 via DQ bus 13.

[0039] The data input / output unit 27 includes an input buffer 27a, a selector 27b, and an output buffer 27c. The input buffer 27a receives data and a second command / address signal CA2 via the DQ bus 13. In normal mode, the selector 27b, in response to a first select signal SEL1, sends the data received by the input buffer 27a as read data R_Data1 to the internal circuit block of the memory controller 20; or in calibration mode, in response to the first select signal SEL1, it sends the second command / address signal CA2 received by the input buffer 27a as a third command / address signal CA3 to the command / address comparator 26. The output buffer 27c sends write data W_Data1 to the memory device 30 via the DQ bus 13.

[0040] Memory device 30 includes a clock buffer 32, a command / address receiver (“CA receiver”) 34, and a data input / output unit 31. Memory device 30 may include dynamic random access memory (DRAM) cells. Clock buffer 32 receives a clock signal via clock signal line 11 and generates an internal clock signal ICK. Command / address receiver 34, in response to the internal clock signal ICK, generates a second command / address signal CA2 based on a chip select signal / CS, a clock enable signal CKE, and a first command / address signal CA1 transmitted via command / address bus 12. The chip select signal / CS and the clock enable signal CKE may be separate from command / address bus 12, such as... Figure 1 As shown, or it can be sent to the memory device 30 by being included in the command / address bus 12. The command / address bus 12 may also be referred to as the command / address signal line.

[0041] The clock enable signal CKE can be used as a pseudo-command, acting as a read command for the first command / address signal CA1 sent via the command / address bus 12. The command / address receiver 34 generates a second command / address signal CA2 based on the first command / address signal CA1 received when the clock enable signal CKE is active. The second command / address signal CA2 is provided to the data input / output unit 31.

[0042] In normal read mode, data input / output unit 31 receives read data R_Data2 from the internal circuitry of memory device 30 and sends read data R_Data2 to DQ bus 13 in response to the second selection signal SEL2; or in calibration mode, it sends a second command / address signal CA2 to DQ bus 13 in response to the second selection signal SEL2. In normal write mode, data input / output unit 31 receives write data W_Data1 via DQ bus 13 and sends write data W_Data1 to the internal circuitry of memory device 30. Data input / output unit 31 includes selector 31c, output buffer 31a, and input buffer 31b. In normal / calibration mode, selector 31c selects one of the second command / address signal CA2 output from command / address receiver 34 and read data R_Data2 provided by the internal circuitry of memory device 30 in response to the second selection signal SEL2, and sends either the second command / address signal CA2 or read data R_Data2 to output buffer 31a.

[0043] Output buffer 31a sends the second command / address signal CA2 or read data R_Data2 output from selector 31c to DQ bus 13. Input buffer 31b receives data sent via DQ bus 13 and sends the received data as write data W_Data2 to the internal circuit block of memory device 30.

[0044] An example has been described whereby a second command / address signal CA2 output from the output buffer 31a of the memory device 30 is provided to the memory controller 20 via the DQ bus 13. Alternatively, the second command / address signal CA2 output from the output buffer 31a of the memory device 30 may be provided to the memory controller 20 via the data strobe bus (“DQS”) and the DQ bus 13. The data input / output unit 27 of the memory controller 20 and the data input / output unit 31 of the memory device 30 may be connected via the data strobe bus and the DQ bus 13.

[0045] Figure 3 A memory system according to some embodiments of the present disclosure is shown.

[0046] Reference Figure 3The memory system 1 may include a memory device 100 and a memory controller 300. The memory device 100 may be a non-volatile memory device that communicates with the memory controller 300 via one of a plurality of channels.

[0047] The memory device 100 may include first pins P11 to eighth pins P18, a memory interface (“Memory I / F”) 200, control logic circuitry 110, and a memory cell array 120.

[0048] The memory interface 200 can receive a chip enable signal nCE from the memory controller 300 via the first pin P11. The memory interface 200 can send signals to or receive signals from the memory controller 300 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., with a low level), the memory interface 200 can send signals to or receive signals from the memory controller 300 via the second pin P12 to the eighth pin P18.

[0049] For example, memory interface 200 can receive command latch enable signal CLE, address latch enable signal ALE, and write enable signal nWE from memory controller 300 via pins P12 to P14. Memory interface 200 can receive data signal DQ from memory controller 300 via pin P17 or send data signal DQ to memory controller 300 via pin P17. Command CMD, address ADDR, and data “DATA” can be sent via data signal DQ. For example, data signal DQ can be sent via multiple data signal lines. In this example, pin P17 may include multiple pins corresponding to multiple data signals.

[0050] Based on the switching timing of the write enable signal nWE, the memory interface 200 can obtain the command CMD from the data signal DQ received during the enable period (e.g., high level period) of the command latch enable signal CLE. Based on the switching timing of the write enable signal nWE, the memory interface 200 can obtain the address ADDR from the data signal DQ received during the enable period (e.g., high level period) of the address latch enable signal ALE.

[0051] The write enable signal nWE can remain static (e.g., high or low) and then toggle between high and low. For example, the write enable signal nWE can toggle during the transmission of command CMD or address ADDR. Therefore, the memory interface 200 can obtain command CMD or address ADDR based on the toggle timing of the write enable signal nWE.

[0052] The memory interface 200 can receive the read enable signal nRE from the memory controller 300 via pin 5 P15. The memory interface 200 can receive the data strobe signal DQS from the memory controller 300 via pin 6 P16, or can send the data strobe signal DQS to the memory controller 300 via pin 6 P16.

[0053] During the output of data "DATA" by memory device 100, memory interface 200 may receive a switched read enable signal nRE via pin 5 P15 before the output of data "DATA". Memory interface 200 may generate a data strobe signal DQS that switches according to the switching of the read enable signal nRE. For example, memory interface 200 may generate a data strobe signal DQS that begins switching after a predetermined delay following the start of the switching of the read enable signal nRE. Memory interface 200 may transmit a data signal DQ including data "DATA" based on the switching timing of the data strobe signal DQS. Therefore, data "DATA" can be aligned with the switching timing of the data strobe signal DQS and thus be transmitted to memory controller 300.

[0054] During the input of data "DATA" to memory device 100, upon receiving a data signal DQ including "DATA" from memory controller 300, memory interface 200 can receive a switching data strobe signal DQS along with the data "DATA". Memory interface 200 can acquire the data "DATA" from data signal DQ based on the switching timing of data strobe signal DQS. For example, memory interface 200 can acquire the data "DATA" by sampling data signal DQ at the rising and falling edges of data strobe signal DQS.

[0055] The memory interface 200 can send a ready / busy output signal nR / B to the memory controller 300 via pin 8, P18. The memory interface 200 can also send status information of the memory device 100 to the memory controller 300 via the ready / busy output signal nR / B. When the memory device 100 is in a busy state (e.g., performing internal operations), the memory interface 200 can send the ready / busy output signal nR / B to the memory controller 300 indicating that the memory device 100 is in a busy state. When the memory device 100 is in a ready state (e.g., internal operations of the memory device 100 have not been performed or have been completed), the memory interface 200 can send the ready / busy output signal nR / B to the memory controller 300 indicating that the memory device 100 is in a ready state. For example, when memory device 100 is reading data "DATA" from memory cell array 120 in response to a page read command, memory interface 200 may send a ready / busy output signal nR / B (e.g., a low-level ready / busy output signal nR / B) to memory controller 300 indicating that memory device 100 is in a busy state. For example, when memory device 100 is programming data "DATA" into memory cell array 120, memory interface 200 may send a ready / busy output signal nR / B (e.g., a low-level ready / busy output signal nR / B) to memory controller 300 indicating that memory device 100 is in a busy state.

[0056] Control logic circuit 110 can control various operations of memory device 100. Control logic circuit 110 can receive commands CMD or addresses ADDR obtained from memory interface 200. Control logic circuit 110 can generate control signals for controlling other parts of memory device 100 based on commands CMD or addresses ADDR obtained from memory interface 200. For example, control logic circuit 110 can program data "DATA" into memory cell array 120 or generate various control signals for reading data "DATA" from memory cell array 120.

[0057] The memory cell array 120 can store the data "DATA" acquired from the memory interface 200 under the control of the control logic circuit 110. The memory cell array 120 can also output the stored data "DATA" to the memory interface 200 under the control of the control logic circuit 110.

[0058] The memory cell array 120 may include a plurality of memory cells. For example, the memory cells may be flash memory cells, but embodiments of the present disclosure are not limited thereto. Optionally, according to some embodiments, the memory cells may be, for example, resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase-change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, magnetic random access memory (MRAM) cells, DRAM cells, double data rate 4 (DDR4) synchronous DRAM (SDRAM) cells, low-power DDR4 (LPDDR4) SDRAM cells, or low-power DDR4 (LPDDR5) SDRAM cells.

[0059] The memory controller 300 may include first pins P21 to eighth pins P28 and a controller interface circuit (“Controller I / F”) 310. The first pins P21 to eighth pins P28 may correspond to the first pins P11 to eighth pins P18 of the memory device 100, respectively.

[0060] The controller interface 310 can send a chip enable signal nCE to the memory device 100 via the first pin P21. The controller interface 310 can send signals to or receive signals from the memory device 100 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0061] For example, controller interface 310 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to memory device 100 via pins P22 to P24. Controller interface 310 can send the data signal DQ to memory device 100 or receive the data signal DQ from memory device 100 via pin P27.

[0062] The controller interface 310 can send a data signal DQ including a command CMD or an address ADDR together with a switchable write enable signal nWE to the memory device 100. For example, the controller interface 310 can send the data signal DQ including a command CMD according to the transmission of an enabled command latch enable signal CLE, and can send the data signal DQ including an address ADDR to the memory device 100 according to the transmission of an enabled address latch enable signal ALE.

[0063] The controller interface 310 can send a read enable signal nRE to the memory device 100 via pin 5 P25. The controller interface 310 can receive a data strobe signal DQS from the memory device 100, or send a data strobe signal DQS to the memory device 100, via pin 6 P26.

[0064] During the output of data "DATA" by memory device 100, controller interface 310 can generate and send a switching read enable signal nRE to memory device 100. For example, controller interface 310 can generate a read enable signal nRE that transitions from a static state (e.g., high or low) to a switching state before the data "DATA" is output. Therefore, memory device 100 can generate a switching data strobe signal DQS based on the read enable signal nRE. Controller interface 310 can receive the switching data strobe signal DQS and a data signal DQ including the data "DATA" from memory device 100. Controller interface 310 can retrieve the data "DATA" from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0065] During the input of data "DATA" to memory device 100, controller interface 310 may generate a switching data strobe signal DQS. For example, controller interface 310 may generate a data strobe signal DQS that transitions from a static state (e.g., high or low) to a switching state before data "DATA" is transmitted. Controller interface 310 may send a data signal DQ including data "DATA" to memory device 100 based on the switching timing of the data strobe signal DQS.

[0066] The controller interface 310 can receive a ready / busy output signal nR / B from the memory device 100 via pin 8 P28. The controller interface 310 can determine the state of the memory device 100 based on the ready / busy output signal nR / B.

[0067] Memory device 100 can transmit data through multiple channels via multi-level signaling. Multi-level signaling can be configured to increase the speed of data transmission without increasing the frequency and / or power of the transmitted data. An example of multi-level signaling can be pulse amplitude modulation (PAM), and the unique symbol of the multi-level signal can be configured to represent multiple bits of data. Assume that the multi-level signaling used by memory device 100 is PAM. Memory device 100 can use PAM, such as PAM4, PAM8, or PAMN (where N is a natural number greater than 2).

[0068] Memory device 100 can transmit more than two data entries per cycle. For example, memory device 100 can be a four-times data rate (QDR) synchronous memory device capable of inputting / outputting four data entries per cycle of the system clock. Memory device 100 will be described below as a QDR synchronous memory device.

[0069] According to a comparative example, in order to input / output data on both the rising and falling edges of the system clock, a double data rate (DDR) synchronous memory device can process two data entries in each cycle of the system clock. That is, according to the comparative example, the timing of the data output by the DDR memory device is precisely synchronized with the rising or falling edge of the system clock. However, the system clock applicable to semiconductor memory devices according to this comparative example may be delayed, phase-shifted, or distorted by the clock input buffer or transmit line (used to transmit the clock signal) in the semiconductor memory device. To address this issue, the semiconductor memory device according to embodiments of this disclosure may implement an error correction block to transmit accurate data based on multiple divided clock signals of the system clock.

[0070] The memory device 100 according to embodiments of this disclosure can transmit up to twice the number of data packets that a DDR synchronous memory device can transmit. The memory device 100, such as a QDR synchronous memory device 100, can use two clocks. One of these clocks can be used as a reference for sending commands and addresses for reading or writing data, and the other clock can be used as a reference for sending data. Therefore, the read and write operations of the memory device 100 can be made faster.

[0071] According to some embodiments, in order to accurately input or output four data entries within each cycle of the system clock, the memory device 100 precisely synchronizes the data with the 0°, 90°, 180°, and 270° phase of the system clock. That is, the memory device 100 outputs one data entry every 90 degrees. Therefore, according to some embodiments, more precise phase synchronization between the data and the system clock ensures a more effective window for the operation of the memory device 100 and improves the reliability of its operation. To improve the reliability of the memory device 100's operation, error correction blocks can be arranged on the log₂N data paths that can be generated using PAMN (where N is a natural number greater than 2). For example, error correction blocks can be arranged on the log₂N data paths in the memory interface 200, as will be described below.

[0072] Figure 4 This is a block diagram of a memory interface of a memory device according to some embodiments of the present disclosure.

[0073] Reference Figure 4The memory interface 200a may include a multiphase clock generator 210 (also referred to as a multiphase clock generator circuit), a clock multiplexer (“clock MUX”) 220 (also referred to as a clock multiplexer circuit), error correction blocks 230a and 230b (also referred to as error correction circuits) arranged at the data path, data multiplexers (“data MUX”) 240a and 240b (also referred to as data multiplexer circuits), buffers 250a and 250b (also referred to as buffer circuits), pre-drivers 260a and 260b (also referred to as pre-driver circuits), driver circuits 270a and 270b, and input / output pads 280. The memory interface 200a will be described below using, for example, PAM4.

[0074] Error correction blocks 230a and 230b, buffers 250a and 250b, pre-drivers 260a and 260b, and driver circuits 270a and 270b can be arranged on their respective data paths, but embodiments of this disclosure are not limited thereto. For example, according to some embodiments, different configurations of the memory interface 200a can be utilized as long as data can be appropriately fed back to each of the error correction blocks 230a and 230b via each data path.

[0075] The multiphase CK generator 210 can receive a reference clock signal and can generate multiple frequency-divided clock signals with a 90-degree phase difference from each other by dividing the reference clock signal (e.g., the first frequency-divided clock signal "CLK 0", the second frequency-divided clock signal "CLK 90", the third frequency-divided clock signal "CLK 180" and the fourth frequency-divided clock signal "CLK 270").

[0076] Clock multiplexer 220 can receive a first divided clock signal "CLK 0", a second divided clock signal "CLK 90", a third divided clock signal "CLK 180", and a fourth divided clock signal "CLK 270" from multiphase clock generator 210. Clock multiplexer 220 can select at least one of the first divided clock signal "CLK 0", the second divided clock signal "CLK 90", the third divided clock signal "CLK 180", and the fourth divided clock signal "CLK 270", and can send the selected divided clock signal to the first error correction block 230a and the second error correction block 230b. For ease of explanation, it is assumed that clock multiplexer 220 sends the first divided clock signal "CLK 0" to the first error correction block 230a and the second error correction block 230b.

[0077] The first error correction block 230a may include a duty cycle correction (DCC) circuit for correcting any duty cycle distortion caused by phase changes or distortion in the first divided clock signal "CLK0". The DCC circuit may be used to correct the duty cycle of the clock signal input to or output from the first error correction block 230a, or to be transmitted to, for example... Figure 3 The duty cycle of the internal or external clock signal of the memory device 100.

[0078] The first error correction block 230a may also include a quadrature error correction (QEC) circuit. The QEC circuit can receive multiple least significant bit (LSB) data (e.g., first LSB data "LSBData1", second LSB data "LSB Data2", third LSB data "LSB Data3", and fourth LSB data "LSB Data4") transmitted via a first data path including the first error correction block 230a, the first data multiplexer 240a, the first buffer 250a, the first pre-driver 260a, and the first driver circuit 270a), can correct the switching time of the multiple LSB data, and can ensure that the eye diagram or window size of the multiple LSB data is the same as that of the multiple most significant bit (MSB) data (e.g., first MSB data "MSB Data1", second MSB data "MSB Data2", third MSB data "MSB Data3", and fourth MSB data "MSB Data4") transmitted via a second data path. This will be described in detail below.

[0079] The first data multiplexer 240a can receive the first divided clock signal "CLK0" from the first error correction block 230a, and can send the LSB data corresponding to the first divided clock signal "CLK0" to the first buffer 250a. Assume that the LSB data sent from the first data multiplexer 240a to the first buffer 250a is the first LSB data "LSB Data1".

[0080] The first buffer 250a may include, for example, a first-in, first-out (FIFO) component. For instance, multiple LSB data entries (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3", and fourth LSB data "LSB Data 4") sent from the first data multiplexer 240a to the first buffer 250a can be routed via the first buffer 250a. The first buffer 250a can process data based on the number of times and priority of the multiple LSB data entries (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3", and fourth LSB data "LSB Data 4"). For example, the first buffer 250a can process the data that appears first (e.g., in a FIFO manner).

[0081] The first LSB data “LSB Data 1” can be sent to the first pre-driver 260a via the first buffer 250a. The first pre-driver 260a can be, for example, a bias circuit for generating a low-power signal.

[0082] The first LSB data "LSB Data 1" can be sent to the first driver circuit 270a via the first pre-driver 260a. The first driver circuit 270a may include, for example, a pull-up circuit or a pull-down circuit. That is, the first LSB data "LSB Data 1" can be pulled up or pulled down to a desired amplitude level via the first pre-driver 260a, and can then be output to the input / output pad 280.

[0083] The first LSB data "LSB Data 1" can be sent to the outside of the memory interface 200a via the input / output pad 280 (e.g., Figure 3 (Controller interface 310).

[0084] In memory interface 200a, first error correction block 230a can receive first LSB data "LSB Data 1". Then, first error correction block 230a can correct the switching time of the first LSB data "LSB Data 1", and thus make the eye diagram and window size of the first LSB data "LSB Data 1" and the MSB data (e.g., the first MSB data "MSB Data 1") switched in response to the first divider clock signal "CLK 0" the same. This will be described in detail below.

[0085] The above description of the first data path can be directly applied to the second data path, along which MSB data is transmitted via the second error correction block 230b, the second data multiplexer 240b, the second buffer 250b, the second pre-driver 260b, and the second driver circuit 270b. Therefore, for ease of explanation, a detailed description of the second data path will be omitted.

[0086] The following description uses the switching time of multiple data entries as an example, and the embodiments of this disclosure are not limited thereto.

[0087] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 3 Timing diagram of read operations for memory devices.

[0088] Figures 3 to 5 The diagram shows control signals provided within the memory device 100 for the controller interface 310 to read data from the memory device 100 (e.g., a first divided clock signal "CLK 0", a second divided clock signal "CLK 90", a third divided clock signal "CLK 180", and a fourth divided clock signal "CLK 270"), as well as multiple data lines output by the memory device 100 (e.g., a first LSB data "LSB Data 1", a second LSB data "LSB Data 2", a third LSB data "LSB Data 3", and a fourth LSB data "LSB Data 4", and a first MSB data "MSB Data 1", a second MSB data "MSB Data 2", a third MSB data "MSB Data 3", and a fourth MSB data "MSB Data 4").

[0089] Memory device 100 can output data read from memory cell array 120 within time period t to an external location (e.g., to memory controller 300). Controller interface 310 can toggle a read enable signal. The read enable signal can correspond to... Figure 3 The read enable signal nRE is used. When the read enable signal switches, data can be read from the memory cell array 120.

[0090] For example, after the rising edge p1 of the first divided clock signal "CLK 0", the first LSB data "LSB Data 1" and the first MSB data "MSB Data 1" corresponding to the first divided clock signal "CLK 0" can be extracted from the memory cell array 120. After the falling edge p2 of the second divided clock signal "CLK 90", the second LSB data "LSB Data 2" and the second MSB data "MSB Data 2" corresponding to the second divided clock signal "CLK 90" can be extracted from the memory cell array 120. After the rising edge p3 of the third divided clock signal "CLK 180", the third LSB data "LSB Data 3" and the third MSB data "MSB Data 3" corresponding to the third divided clock signal "CLK 180" can be extracted from the memory cell array 120. After the rising edge p4 of the fourth divided clock signal "CLK 270", the fourth LSB data "LSB Data 4" and the fourth MSB data "MSB Data 4" corresponding to the fourth divided clock signal "CLK 270" can be extracted from the memory cell array 120.

[0091] That is, the switching time of multiple LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" and fourth LSB data "LSB Data 4") sent via the first data path and multiple MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" and fourth MSB data "MSB Data 4") sent via the second data path can be adjusted by the first error correction block 230a and the second error correction block 230b respectively arranged on the first data path and the second data path. As a result, the eye diagram or window size of the multiple LSB data and the multiple MSB data can become the same as the maximum size. For example, since the first error correction block 230a arranged on the first data path receives the first LSB data "LSB Data 1" and corrects the timing of sending the first LSB data "LSB Data 1", and the second error correction block 230b arranged on the second data path receives the first MSB data "MSB Data 4", the switching time of multiple LSB data "LSB Data 1" and the second error correction block 230b arranged on the second data path can adjust the switching time of multiple MSB data "LSB Data 1" and the second MSB data "MSB Data 2" and the second MSB data "MSB Data 3" and the second MSB data "MSB Data 4 ... 1” and correct the timing of sending the first MSB data “MSB Data 1”, so that the eye diagram or window size of the first LSB data “LSB Data 1” and the first MSB data “MSB Data 1” corresponding to the first frequency divider clock signal “CLK 0” can become the same as the maximum size.

[0092] Since the first error correction block 230a, arranged on the first data path, receives the second LSB data "LSB Data 2" and corrects the timing of transmitting the second LSB data "LSB Data 2", and the second error correction block 230b, arranged on the second data path, receives the second MSB data "MSB Data 2" and corrects the timing of transmitting the second MSB data "MSB Data 2", the eye diagram or window size of the second LSB data "LSB Data 2" and the second MSB data "MSB Data 2" corresponding to the second frequency division clock signal "CLK 90" can become the same as the maximum size.

[0093] Since the first error correction block 230a, arranged on the first data path, receives the third LSB data "LSB Data 3" and corrects the timing of transmitting the third LSB data "LSB Data 3", and the second error correction block 230b, arranged on the second data path, receives the third MSB data "MSB Data 3" and corrects the timing of transmitting the third MSB data "MSB Data 3", the eye diagram or window size of the third LSB data "LSB Data 3" and the third MSB data "MSB Data 3" corresponding to the third frequency division clock signal "CLK 180" can become the same as the maximum size.

[0094] Since the first error correction block 230a, arranged on the first data path, receives the fourth LSB data "LSB Data 4" and corrects the timing of transmitting the fourth LSB data "LSB Data 4", and the second error correction block 230b, arranged on the second data path, receives the fourth MSB data "MSB Data 4" and corrects the timing of transmitting the fourth MSB data "MSB Data 4", the eye diagram or window size of the fourth LSB data "LSB Data 4" and the fourth MSB data "MSB Data 4" corresponding to the fourth frequency divider clock signal "CLK 270" can become the same as the maximum size.

[0095] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 3 A flowchart of the operation of the memory device.

[0096] Reference Figure 3 , Figure 4 and Figure 6In each of the first error correction block 230a and the second error correction block 230b of the memory device 1, error correction is performed on LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4") and MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") (S100).

[0097] Error correction can be DCC and / or QEC.

[0098] In each of the first error correction block 230a and the second error correction block 230b, the error-corrected LSB data (e.g., the first LSB data "LSB Data 1", the second LSB data "LSB Data 2", the third LSB data "LSB Data 3" or the fourth LSB data "LSB Data 4") and the error-corrected MSB data (e.g., the first MSB data "MSB Data 1", the second MSB data "MSB Data 2", the third MSB data "MSB Data 3" or the fourth MSB data "MSB Data 4") are transmitted via their respective data paths (S200).

[0099] Subsequently, it is determined whether the eye window size of the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4") and MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") corrected by the first error correction block 230a and the second error correction block 230b, combined at the input / output pad 280 and output from the input / output pad 280 has reached the maximum size (S300).

[0100] If it is determined that the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4") and MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") corrected by the first error correction block 230a and the second error correction block 230b, combined at the input / output pad 280 and output from the input / output pad 280, have reached their maximum size ("Yes"), then the feedback of LSB data and MSB data is stopped, and the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") sent via the input / output pad 280 is at its maximum size ("Yes"), then the feedback of LSB data and MSB data is stopped, and the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth MSB data "MSB Data 4") is sent via the input / output pad 280. 4”) and MSB data (e.g., first MSB data “MSB Data 1”, second MSB data “MSB Data 2”, third MSB data “MSB Data 3” or fourth MSB data “MSB Data 4”).

[0101] Conversely, if it is determined that the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4") and MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") corrected by the first error correction block 230a and the second error correction block 230b respectively and combined at the input / output pad 280 and output from the input / output pad 280 have not reached the maximum size ("No"), then the first error correction block 230a and the second error correction block 230b can respectively correct the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth MSB data "LSB Data 4") and output from the input / output pad 280, respectively. Error correction is performed again on the MSB data (e.g., the first MSB data "MSB Data 1", the second MSB data "MSB Data 2", the third MSB data "MSB Data 3" or the fourth MSB data "MSB Data 4").

[0102] Figure 7and Figure 8 This is a block diagram of the interface of a memory device according to some embodiments of the present disclosure. For ease of explanation, [the following is a simplified description of the interface]. Figure 7 and Figure 8 The description of the embodiments will focus primarily on the... Figure 4 The embodiments differ from those described above, and further descriptions of the previously described components and technical aspects may be omitted.

[0103] Reference Figure 7 ,and Figure 4 Unlike memory interface 200a, memory interface 200b may also include a third error correction block 235 connected between multiphase clock generator 210 and clock multiplexer 220.

[0104] The third error correction block 235 may include DCC circuitry for correcting any duty cycle distortion caused by phase transitions or distortions in each divided clock signal received from the multiphase clock generator 210 (e.g., the first divided clock signal "CLK 0", the second divided clock signal "CLK 90", the third divided clock signal "CLK 180", or the fourth divided clock signal "CLK 270"). The DCC circuitry may be used to correct the duty cycle of the clock signal input to the clock multiplexer 220 or to be transmitted to, for example... Figure 3 The duty cycle of the internal or external clock signal of the memory device 100.

[0105] Reference Figure 8 ,and Figure 4 The memory interface 200c differs from the memory interface 200a; it can use PAM8.

[0106] That is, with Figure 4 Unlike memory interface 200a, memory interface 200c may include an additional data path.

[0107] This additional data path may include a third error correction block 230c, a third data multiplexer 240c, a third buffer 250c, a third pre-driver 260c, a third driver circuit 270c, and input / output pads 280. This additional data path is related to... Figure 4 The data paths are basically the same, so further detailed descriptions will be omitted.

[0108] Figure 8 Other features of the memory device and Figure 4 The corresponding parts of the memory devices are basically the same, so further detailed descriptions of them will be omitted.

[0109] Figure 9 This illustrates some embodiments according to the present disclosure. Figure 8 Timing diagram of read operations for memory devices.

[0110] Reference Figure 8 and Figure 9 The switching times of multiple LSB data (e.g., first LSB data "LSBData 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" and fourth LSB data "LSB Data 4") sent via the first data path, multiple MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" and fourth MSB data "MSB Data 4") sent via the second data path, and multiple center significant bit (CSB) data (e.g., first CSB data "CSB Data 1", second CSB data "CSB Data 2", third CSB data "CSB Data 3" and fourth CSB data "CSB Data 4") sent via the third data path can be adjusted by first error correction blocks 230a, second error correction blocks 230b and third error correction blocks 230c respectively arranged on the first data path, the second data path and the third data path. As a result, the eye diagram or window size for multiple LSB data, multiple MSB data, and multiple CSB data can become the same as the maximum size.

[0111] For example, since the first error correction block 230a arranged on the first data path receives the first LSB data "LSB Data1" and corrects the timing of transmitting the first LSB data "LSB Data 1", the second error correction block 230b arranged on the second data path receives the first MSB data "MSB Data 1" and corrects the timing of transmitting the first MSB data "MSB Data 1", and the third error correction block 230c arranged on the third data path receives the first CSB data "CSB Data 1" and corrects the timing of transmitting the first CSB data "CSB Data 1", the eye diagram or window size of the first LSB data "LSB Data 1", the first MSB data "MSB Data 1", and the first CSB data "CSB Data 1" corresponding to the first frequency division clock signal "CLK 0" can become the same as the maximum size.

[0112] Since the first error correction block 230a, arranged on the first data path, receives the second LSB data "LSB Data 2" and corrects the timing of transmitting the second LSB data "LSB Data 2", the second error correction block 230b, arranged on the second data path, receives the second MSB data "MSB Data 2" and corrects the timing of transmitting the second MSB data "MSB Data 2", and the third error correction block 230c, arranged on the third data path, receives the second CSB data "CSB Data 2" and corrects the timing of transmitting the second CSB data "CSB Data 2", the eye diagram or window size of the second LSB data "LSB Data 2", the second MSB data "MSB Data 2", and the second CSB data "CSB Data 2" corresponding to the second frequency division clock signal "CLK 90" can become the same as the maximum size.

[0113] Since the first error correction block 230a, arranged on the first data path, receives the third LSB data "LSB Data 3" and corrects the timing of transmitting the third LSB data "LSB Data 3", the second error correction block 230b, arranged on the second data path, receives the third MSB data "MSB Data 3" and corrects the timing of transmitting the third MSB data "MSB Data 3", and the third error correction block 230c, arranged on the third data path, receives the third CSB data "CSB Data 3" and corrects the timing of transmitting the third CSB data "CSB Data 3", the eye diagram or window size of the third LSB data "LSB Data 3", the third MSB data "MSB Data 3", and the third CSB data "CSB Data 3" corresponding to the third frequency division clock signal "CLK 180" can become the same as the maximum size.

[0114] Since the first error correction block 230a, arranged on the first data path, receives the fourth LSB data "LSB Data 4" and corrects the timing of transmitting the fourth LSB data "LSB Data 4", the second error correction block 230b, arranged on the second data path, receives the fourth MSB data "MSB Data 4" and corrects the timing of transmitting the fourth MSB data "MSB Data 4", and the third error correction block 230c, arranged on the third data path, receives the fourth CSB data "CSB Data 4" and corrects the timing of transmitting the fourth CSB data "CSB Data 4", the eye diagram or window size of the fourth LSB data "LSB Data 4", the fourth MSB data "MSB Data 4", and the fourth CSB data "CSB Data 4" corresponding to the fourth frequency division clock signal "CLK 270" can become the same as the maximum size.

[0115] Figure 8 Other features of the read operation of the memory device and Figure 4 The corresponding parts of the read operation of the memory device are basically the same, so further detailed description of it will be omitted.

[0116] Figure 10 This illustrates some embodiments according to the present disclosure. Figure 8 A flowchart of the operation of the memory device.

[0117] Figure 10 Implementation examples and Figure 6 The difference in the embodiment is that it is determined whether the eye window size of the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4"), MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4") and CSB data (e.g., first CSB data "CSB Data 1", second CSB data "CSB Data 2", third CSB data "CSB Data 3" or fourth CSB data "CSB Data 4") corrected by the first error correction block 230a, the second error correction block 230 and the third error correction block 230c and combined at the input / output pad 280 and output from the input / output pad 280 has reached the maximum size (S310).

[0118] Reference Figure 10If it is determined that the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4"), MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4"), and CSB data (e.g., first CSB data "CSB Data 1", second CSB data "CSB Data 2", third CSB data "CSB Data 3" or fourth CSB data "CSB Data 4") are respectively corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c and combined at the input / output pad 280 and output from the input / output pad 280, then the LSB data is corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c and combined at the input / output pad 280, then the LSB data is corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c and output from the input / output pad 280, then the LSB data is corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c, ... If the eye window size of Data4” reaches the maximum size (“Yes”), then the feedback of LSB data, MSB data and CSB data is stopped, and LSB data (e.g., first LSB data “LSB Data 1”, second LSB data “LSB Data 2”, third LSB data “LSB Data 3” or fourth LSB data “LSB Data 4”), MSB data (e.g., first MSB data “MSB Data 1”, second MSB data “MSB Data 2”, third MSB data “MSB Data 3” or fourth MSB data “MSB Data 4”) and CSB data (e.g., first CSB data “CSB Data 1”, second CSB data “CSB Data 2”, third CSB data “CSB Data 3” or fourth CSB data “CSB Data 4”) are sent via input / output pad 280.

[0119] Conversely, if it is determined that the LSB data (e.g., first LSB data "LSB Data 1", second LSB data "LSB Data 2", third LSB data "LSB Data 3" or fourth LSB data "LSB Data 4"), MSB data (e.g., first MSB data "MSB Data 1", second MSB data "MSB Data 2", third MSB data "MSB Data 3" or fourth MSB data "MSB Data 4"), and CSB data (e.g., first CSB data "CSB Data 1", second CSB data "CSB Data 2", third CSB data "CSB Data 3" or fourth CSB data "CSB Data 4") are respectively corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c and combined at the input / output pad 280 and output from the input / output pad 280, then the LSB data is corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c and combined at the input / output pad 280, and output from the input / output pad 280, then the LSB data is corrected by the first error correction block 230a, the second error correction block 230b, and the third error correction block 230c ... If the eye window size of 4”) does not reach the maximum size (“No”), then the first error correction block 230a, the second error correction block 230b and the third error correction block 230c can respectively perform error correction on LSB data (e.g., first LSB data “LSB Data 1”, second LSB data “LSB Data 2”, third LSB data “LSB Data 3” or fourth LSB data “LSB Data 4”), MSB data (e.g., first MSB data “MSB Data 1”, second MSB data “MSB Data 2”, third MSB data “MSB Data 3” or fourth MSB data “MSB Data 4”) and CSB data (e.g., first CSB data “CSB Data 1”, second CSB data “CSB Data 2”, third CSB data “CSB Data 3” or fourth CSB data “CSB Data 4”) again (S100).

[0120] Figure 11 This is a block diagram of a memory interface of a memory device according to some embodiments of the present disclosure.

[0121] Reference Figure 11 ,and Figure 7 Similar to memory interface 200b, memory interface 200d may also include a third error correction block 235 connected between multiphase clock generator 210 and clock multiplexer 220.

[0122] Figure 11 Other features of the embodiments and Figure 7 and Figure 8 The corresponding parts of the embodiments are substantially the same, therefore, for ease of explanation, further detailed descriptions of components and technical aspects will be omitted.

[0123] Figure 12 This is a block diagram of a memory system that applies a memory device according to some embodiments of the present disclosure.

[0124] Reference Figure 12 The memory system 1000 can be a mobile system, such as a mobile communication terminal (e.g., a mobile phone, smartphone, or tablet PC), wearable device, healthcare device, or Internet of Things (IoT) device, but embodiments of this disclosure are not limited thereto. Optionally, the memory system 1000 can be a PC, laptop computer, server, media player, or automotive device such as a navigation device.

[0125] The memory system 1000 may include a main processor (“CPU core”) 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may also include an optical input device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0126] The main processor 1100 can control the general operation of the memory system 1000, particularly the operation of the components of the memory system 1000. The main processor 1100 can be implemented as, for example, a general-purpose processor, a special-purpose processor, or an application processor.

[0127] The main processor 1100 may include one or more CPU cores 1110 and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator block (“accelerator”) 1130, which may be implemented to perform high-speed data operations such as artificial intelligence (AI) data operations. The accelerator block 1130 may include, for example, a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separate from other components of the main processor 1100.

[0128] Memory 1200a and 1200b can be used as the main memory of memory system 1000 and may include non-volatile memory such as static random access memory (SRAM) and / or dynamic random access memory (DRAM). Optionally, memory 1200a and 1200b may include non-volatile memory such as flash memory, phase-change random access memory (PRAM), and / or resistive random access memory (RRAM). Memory 1200a and 1200b can be implemented in the same package as main processor 1100.

[0129] Storage devices 1300a and 1300b can be used as non-volatile storage devices to store data regardless of whether power is supplied, and can have a larger storage capacity than storage devices 1200a and 1200b. Storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memory (NVM) storage devices 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b. NVM storage devices 1320a and 1320b may include, for example, two-dimensional (2D) or three-dimensional (3D) V-NAND flash memory, or other non-volatile memories such as PRAM and / or RRAM.

[0130] Storage devices 1300a and 1300b may be included in the memory system 1000 as separate components from the main processor 1100, or they may be implemented in the same package as the main processor 1100. Storage devices 1300a and 1300b may be in the form of memory cards and therefore may be detachably coupled to other components of the memory system 1000 via an interface such as connection interface 1480. Storage devices 1300a and 1300b may be devices employing standards such as Universal Flash Memory (UFS), but embodiments of this disclosure are not limited thereto.

[0131] The optical input device 1410 can capture still or moving images and can be, for example, a camera, a portable video camera, and / or a webcam.

[0132] User input device 1420 can receive various types of data from the user and may be, for example, a touchpad, keypad, keyboard, mouse, and / or microphone.

[0133] Sensor 1430 can detect various types of physical quantities that can be measured externally to memory system 1000, and can convert the detected physical quantities into electrical signals. Sensor 1430 may be, for example, a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope.

[0134] Communication device 1440 can send signals to or receive signals from other devices outside the memory system 1000 according to various communication standards. Communication device 1440 can be implemented as, for example, an antenna, a transceiver, and / or a modem.

[0135] The display 1450 and the speaker 1460 can be used as output devices for outputting visual and auditory information to a user.

[0136] The power supply device 1470 can appropriately convert power from a battery embedded in the memory system 1000 or from an external power source, and can provide power to other components of the memory system 1000.

[0137] Connection interface 1480 provides a connection between the memory system 1000 and an external device, which can be connected to the memory system 1000 to exchange data with it. Connection interface 1480 can be implemented as, for example, an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an external SATA (e-SATA) interface, a Small Computer Small Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnect (PCI) interface, a PCIe (PCIe) interface, an NVMe (NVMe) interface, an IEEE 1394 interface, a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) card interface, a Multimedia Card (MMC) interface, an Embedded Multimedia Card (eMMC) interface, a UFS interface, an Embedded UFS (eUFS) interface, or a Compact Flash (CF) interface. Connection interface 1480 can be any of the above-mentioned references. Figures 1 to 11 Any of the described memory interfaces.

[0138] Figure 13 This is a block diagram of a UFS system that applies some embodiments of a memory device according to the present disclosure.

[0139] Figure 13 A UFS system 2000 conforming to the UFS standard published by the Joint Electronic Devices Engineering Committee (JEDEC) is shown. The UFS system 2000 may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. The above refers to... Figure 12 The description of the memory system 1000 can be directly applied to the UFS system 2000 without conflicting with the following description of the UFS system 2000.

[0140] Reference Figure 13 The UFS host 2100 and UFS device 2200 can be connected via the UFS interface 2300. Figure 12 When the main processor 1100 is an application processor, the UFS host 2100 can be implemented as part of the application processor. The UFS host controller 2110 and host memory 2140 can respectively correspond to… Figure 12 The main processor 1100 includes a controller 1120 and memory 1200a and 1200b. The UFS device 2200 can correspond to... Figure 12 Storage devices 1300a and 1300b. The UFS device controller 2210 and non-volatile storage device 2220 can respectively correspond to... Figure 12Storage controllers 1310a and 1310b and NVM storage devices 1320a and 1320b.

[0141] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, non-volatile storage device 2220, storage interface 2230, device memory 2240, UIC layer 2250, and regulator 2260. Non-volatile storage device 2220 may include multiple storage cells 2221, and storage cells 2221 may include 2D or 3D V-NAND flash memory or other flash memory, such as PRAM and / or RRAM. UFS device controller 2210 and non-volatile storage device 2220 may be connected via storage interface 2230. Storage interface 2230 may be configured to conform to standards such as TOGGLE or ONFI.

[0142] Application 2120 may be a program that communicates with UFS device 2200 to use the functionality of UFS device 2200. Application 2120 may send Input / Output Request (IOR) requests to UFS drive 2130 to input data to or output data from UFS device 2200. Input / Output Request (IOR) requests may be, for example, read requests, write requests, and / or discard requests, but embodiments of this disclosure are not limited thereto.

[0143] UFS drive 2130 can manage UFS host controller 2110 via UFS-Host Controller Interface (HCI). UFS drive 2130 can translate Input / Output Request (IOR) provided by application 2120 into one or more UFS commands defined by the UFS standard, and can send one or more UFS commands to UFS host controller 2110. IOR can be translated into multiple UFS commands. UFS commands can be from Small Computer System Interface (SCSI) or commands defined by the UFS standard.

[0144] The UFS host controller 2110 can send UFS commands provided by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can be used as a command queue (CQ).

[0145] The UIC layer 2150 of the UFS host 2100 may include MIPI M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 of the UFS device 2200 may include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0146] The UFS interface 2300 may include a line for transmitting a reference clock signal REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 2200, a pair of lines for transmitting a pair of differential input signals DIN_t and DIN_c, and a pair of lines for transmitting a pair of differential output signals DOUT_t and DOUT_c.

[0147] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of approximately 19.2 MHz, approximately 26 MHz, approximately 38.4 MHz, and approximately 52 MHz, but embodiments of this disclosure are not limited thereto. During operation of the UFS host 2100, such as during data transfer between the UFS host 2100 and the UFS device 2200, the frequency of the reference clock signal REF_CLK can be changed. The UFS device 2200 can use a phase-locked loop (PLL) to generate clock signals with various frequencies from the reference clock signal REF_CLK provided by the UFS host 2100. The UFS host 2100 can set the data rate between the UFS host 2100 and the UFS device 2200 based on the frequency of the reference clock signal REF_CLK. That is, the data rate between the UFS host 2100 and the UFS device 2200 can be determined based on the frequency of the reference clock signal REF_CLK.

[0148] The UFS interface 2300 can support multiple channels, and each channel can include one or more differential pairs. For example, the UFS interface 2300 can include one or more receive (RX) channels and one or more transmit (TX) channels. (See reference...) Figure 13 A pair of lines used to send differential input signals DIN_t and DIN_c can form an RX channel, and a pair of lines used to send differential output signals DOUT_t and DOUT_c can form a TX channel. Figure 13 One TX channel and one RX channel are shown, but the number of TX channels and RX channels can vary depending on embodiments of this disclosure. The UFS interface 2300 can be... Figures 1 to 11 Any of the memory interfaces.

[0149] The RX and TX channels can transmit data serially. The RX and TX channels are separate, and the UFS host 2100 and UFS device 2200 can communicate in full-duplex mode. That is, the UFS device 2200 can send data to the UFS host 2100 via the TX channel and simultaneously receive data from the UFS host 2100 via the RX channel. Control data, such as commands sent from the UFS host 2100 to the UFS device 2200, or user data to be stored in or read from the non-volatile storage device 2220 of the UFS device 2200 by the UFS host 2100, can be transmitted via the same channels. Therefore, according to some embodiments, in addition to a pair of RX channels and a pair of TX channels, a separate channel for transmitting data between the UFS host 2100 and the UFS device 2200 is not required.

[0150] The UFS device controller 2210 of the UFS device 2200 can control the overall operation of the UFS device 2200. The UFS device controller 2210 can manage the non-volatile storage device 2220 via logic units 2211, which are units where logical data is stored. The UFS device controller 2210 may include eight logic units 2211, but embodiments of this disclosure are not limited thereto. The UFS device controller 2210 may include a flash translation layer (FTL) and can use the address mapping information of the FTL to translate logical data addresses (e.g., logical block addresses (LBAs)) received from the UFS host 2100 into physical data addresses (e.g., physical block addresses (PBAs)). In the UFS system 2000, the logical block used to store user data can have a predetermined size. For example, the size of the logical block can be set to a minimum of 4KB.

[0151] In response to a command from UFS host 2100 input to UFS device 2200 via UIC layer 2250, UFS device controller 2210 can perform an operation corresponding to the input command, and can send a completion response to UFS host 2100 when the operation is completed.

[0152] For example, to facilitate the storage of user data in the UFS device 2200 by the UFS host 2100, the UFS host 2100 can send a command to the UFS device 2200 to store the data. In response to receiving a ready-to-transfer response from the UFS device 2200, the UFS host 2100 can send the user data to the UFS device 2200. The UFS device controller 2210 can temporarily store the user data in the device memory 2240, and can store the temporarily stored user data in a selected location in the non-volatile storage device 2220 based on the FTL address mapping information.

[0153] In another example, to facilitate UFS host 2100 reading user data from UFS device 2200, UFS host 2100 can send a read data command to UFS device 2200. Then, UFS device controller 2210 can read the user data from non-volatile storage device 2220 based on the read data command, and can temporarily store the user data in device memory 2240. During this process, UFS device controller 2210 can use error correction code (ECC) circuitry to detect and correct errors in the user data. UFS device controller 2210 can then send the temporarily stored user data to UFS host 2100. UFS device controller 2210 may also include Advanced Encryption Standard (AES) circuitry. The AES circuitry can use a symmetric key algorithm to encrypt or decrypt data input to UFS device controller 2210.

[0154] UFS host 2100 can store commands to be sent to UFS device 2200 in a predetermined order into UFS host register 2111, which can be used as a command queue, and can send the commands to UFS device 2200 in this predetermined order. Even when commands previously sent to UFS device 2200 are still being processed by UFS device 2200, that is, even when a completion notification indicating that the processing of previously sent commands has been completed by UFS device 2200 has not yet been received, UFS host 2100 can still continue to send subsequent commands waiting in the command queue to UFS device 2200, and as a result, UFS device 2200 can receive subsequent commands from UFS host 2100 while processing previously sent commands. The maximum number of commands that can be stored in the command queue (e.g., the queue depth of the command queue) can be 32. Furthermore, the command queue can be implemented as a circular queue that uses head pointers and tail pointers to indicate the start and end of the array of commands stored in the command queue.

[0155] Each of the memory cells 2221 may include a memory cell array and control circuitry for controlling the operation of the memory cell array. The memory cell array may include a 2D or 3D memory cell array. The memory cell array may include multiple memory cells, and the memory cells may be single-level cells (SLCs) capable of storing one bit of data or cells capable of storing two or more bits of data, such as multi-level cells (MLCs), three-level cells (TLCs), or four-level cells (QLCs). A 3D memory cell array may include vertically oriented V-NAND strings such that at least one memory cell is positioned above another memory cell.

[0156] Power supply voltages VCC, VCCQ1, and VCCQ2 can be input to the UFS device 2200. The power supply voltage VCC, serving as the main power supply voltage for the UFS device 2200, can range from approximately 2.4V to approximately 3.6V. Power supply voltage VCCQ1 is a low-voltage power supply used to provide a certain range, primarily for the UFS device controller 2210, and its range can be from approximately 1.14V to approximately 1.26V. Power supply voltage VCCQ2 is a voltage range lower than VCC but higher than VCCQ1, used for input / output interfaces such as the MIPI M-PHY 2251, and its range can be from approximately 1.7V to approximately 1.95V. Power supply voltages VCC, VCCQ1, and VCCQ2 can be supplied to the UFS device 2200 via regulator 2260. Regulator 2260 can be implemented as a set of unit regulators connected to different power supply voltages among VCC, VCCQ1, and VCCQ2.

[0157] As is common practice in the art of this disclosure, these blocks, units, and / or modules are described and embodiments are illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0158] In embodiments of this disclosure, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of a memory cell array having active regions disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within the substrate. The term "monolithic" means that each level of the array is deposited directly on the layers of each lower level of the array. In embodiments of this disclosure, the 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is situated above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents (incorporated herein by reference) describe suitable configurations for three-dimensional memory arrays in which the three-dimensional memory array is configured as multiple levels and shares word lines and / or bit lines between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0159] While this disclosure has been specifically shown and described with reference to its embodiments, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A memory device, comprising: A multiphase clock generator produces multiple frequency-divided clock signals; The first error correction block receives the first frequency-divided clock signal from the plurality of frequency-divided clock signals; The first data multiplexer transmits the first least significant bit data corresponding to the first frequency-divided clock signal; The second error correction block receives the first frequency-divided clock signal; as well as The second data multiplexer transmits the first most significant bit of data corresponding to the first frequency-divided clock signal. in, The first error correction block receives the first least significant bit data and corrects the switching time of the first least significant bit data, and The second error correction block receives the first most significant bit data and corrects the switching time of the first most significant bit data.

2. The memory device according to claim 1, wherein, At least one of the first error correction block and the second error correction block includes a quadrature error correction (QEC) circuit.

3. The memory device according to claim 1, wherein, At least one of the first error correction block and the second error correction block includes a duty cycle correction DCC circuit.

4. The memory device according to claim 1, further comprising: A pre-correction block is connected to the multiphase clock generator, and the pre-correction block receives the multiple frequency-divided clock signals from the multiphase clock generator.

5. The memory device according to claim 4, wherein, The pre-correction block corrects duty cycle errors in at least some of the plurality of frequency-divided clock signals.

6. The memory device according to claim 1, further comprising: The third error correction block receives the first frequency-divided clock signal; as well as The third data multiplexer transmits the first central effective bit data corresponding to the first frequency division clock signal.

7. The memory device according to claim 6, wherein, The third error correction block receives the first central significant bit data and corrects the switching time of the first central significant bit data.

8. A memory device, comprising: Memory interface; The control logic circuit receives commands from the memory interface; The memory cell array is controlled by the control logic circuit and stores data. in, The memory interface generates multiple frequency-divided clock signals via a multi-phase clock generator. A first error correction block receives the first frequency-divided clock signal from these signals and transmits the first least significant bit data corresponding to the first frequency-divided clock signal via a first data multiplexer. A second error correction block receives the first frequency-divided clock signal and transmits the first most significant bit data corresponding to the first frequency-divided clock signal via a second data multiplexer. The first error correction block receives the first least significant bit data and corrects the switching time of the first least significant bit data, and The second error correction block receives the first most significant bit data and corrects the switching time of the first most significant bit data.

9. The memory device according to claim 8, wherein, At least one of the first error correction block and the second error correction block includes a quadrature error correction (QEC) circuit.

10. The memory device according to claim 8, wherein, At least one of the first error correction block and the second error correction block includes a duty cycle correction DCC circuit.

11. The memory device of claim 8, further comprising: A pre-correction block is connected to the multiphase clock generator, and the pre-correction block receives the multiple frequency-divided clock signals from the multiphase clock generator.

12. The memory device according to claim 11, wherein, The pre-correction block corrects duty cycle errors in at least some of the plurality of frequency-divided clock signals.

13. The memory device of claim 8, further comprising: The third error correction block receives the first frequency-divided clock signal; as well as The third data multiplexer transmits the first central effective bit data corresponding to the first frequency division clock signal.

14. The memory device according to claim 13, wherein, The third error correction block receives the first central significant bit data and corrects the switching time of the first central significant bit data.

15. A memory system, comprising: Memory controller, including controller interface circuitry; as well as Memory devices, including: A memory interface that receives signals from the memory controller; The control logic circuit receives commands from the memory interface; and The memory cell array stores data and is connected to the control logic circuit. The memory interface includes: A multiphase clock generator produces multiple frequency-divided clock signals; The first error correction block receives the first frequency-divided clock signal from the plurality of frequency-divided clock signals; The first data multiplexer transmits the first least significant bit data corresponding to the first frequency-divided clock signal; The second error correction block receives the first frequency-divided clock signal; and The second data multiplexer transmits the first most significant bit of data corresponding to the first frequency-divided clock signal. The first error correction block receives the first least significant bit data and corrects the switching time of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects the switching time of the first most significant bit data.

16. The memory system according to claim 15, wherein, At least one of the first error correction block and the second error correction block includes a quadrature error correction (QEC) circuit.

17. The memory system according to claim 15, wherein, At least one of the first error correction block and the second error correction block includes a duty cycle correction DCC circuit.

18. The memory system of claim 15, further comprising: A pre-correction block is connected to the multiphase clock generator, and the pre-correction block receives the multiple frequency-divided clock signals from the multiphase clock generator.

19. The memory system according to claim 18, wherein, The pre-correction block corrects duty cycle errors in at least some of the plurality of frequency-divided clock signals.

20. The memory system of claim 15, further comprising: The third error correction block receives the first frequency-divided clock signal; as well as The third data multiplexer transmits the first center effective bit data corresponding to the first frequency-divided clock signal. The third error correction block receives the first central valid bit data and corrects the switching time of the first central valid bit data.

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