Multilayer capacitor

Abstract

A multilayer capacitor is provided. The multilayer capacitor includes a main body including a multilayer structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes are stacked with the dielectric layers interposed between the plurality of internal electrodes, and an external electrode provided outside the main body and connected to the internal electrodes. At least one of the plurality of dielectric layers includes a plurality of grains, and a proportion of grains having dislocations among the plurality of grains is 20% or more.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0142695, filed on October 30, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer capacitor. Background Technology

[0003] A capacitor is a device that stores electrical energy. In a capacitor, when a voltage is applied, charge typically accumulates in each of the two facing electrodes. When a direct current (DC) voltage is applied, current flows in the capacitor while charge accumulates, and when accumulation is complete, no current flows. Conversely, when an alternating current (AC) voltage is applied, AC current flows while the polarities of the electrodes alternate.

[0004] Capacitors can be classified into various types, such as aluminum electrolytic capacitors in which the electrodes are formed using aluminum and a thin oxide film is placed between the aluminum electrodes, tantalum capacitors using tantalum as the electrode material, ceramic capacitors using high-k dielectric materials such as titanium oxide and barium oxide between the electrodes, multilayer ceramic capacitors (MLCCs) using a multilayer structure of high-k ceramic as the dielectric material placed between the electrodes, and thin film capacitors using polystyrene film as the dielectric material between the electrodes, etc.

[0005] Among these capacitors, MLCCs (Multilayer Ceramic Capacitors) have the advantage of excellent temperature and frequency characteristics and can be implemented in small sizes, thus they have been widely used in various fields such as high-frequency circuits. In recent years, there has been an effort to achieve even smaller multilayer ceramic capacitors, and for this purpose, the dielectric layer and internal electrodes have been formed to be thinner. As the dielectric layer becomes thinner, the electric field applied to the dielectric layer at the same driving voltage increases. Therefore, when a DC electric field is applied, it is necessary to sufficiently ensure the DC bias capacitance (effective capacitance) of the MLCC. Furthermore, given the trend towards integration and miniaturization in electronic devices using MLCCs, it is necessary to design MLCCs to minimize the reduction in effective capacitance due to heat at high temperatures.

[0006] Specifically, DC bias capacitance typically decreases with increasing dielectric grain size. Therefore, it is necessary to reduce the grain size to ensure DC bias capacitance. Furthermore, to mitigate high-temperature capacitance reduction, dielectric grain growth should be suppressed to maintain a high core-to-shell ratio. However, reducing grain size by suppressing dielectric grain growth leads to a decrease in dielectric constant, making it difficult to ensure high levels of capacitance. Therefore, there is a need in the art for a technique that can ensure both DC bias capacitance and effective high-temperature capacitance without suppressing dielectric grain growth. Summary of the Invention

[0007] One aspect of this disclosure is to provide a multilayer capacitor that improves DC bias capacitance and minimizes the reduction in effective capacitance at high temperatures by controlling the dislocation density of the dielectric layer.

[0008] According to one aspect of this disclosure, a multilayer capacitor may include: a body comprising a multilayer structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes are stacked, wherein the plurality of dielectric layers are disposed between the plurality of internal electrodes; and an external electrode disposed outside the body and connected to the internal electrodes. At least one of the plurality of dielectric layers comprises a plurality of grains, and the proportion of grains having dislocations in the plurality of grains is 20% or greater.

[0009] The dislocations can be separated from the grain boundaries between the plurality of grains.

[0010] A dislocation in one of the plurality of grains may contact only one grain boundary between that one grain and the other grains in the plurality of grains.

[0011] Dislocations within one of the plurality of grains can be located between a phase with a tetragonal crystal structure and a phase with a cubic crystal structure.

[0012] Some of the multiple grains may have multiple dislocations.

[0013] The proportion of grains with dislocations in a plurality of grains can be obtained by averaging the values ​​measured in at least four unit areas on the cut surface of the dielectric layer.

[0014] Among the plurality of grains, the proportion of grains with dislocations may be 40% or less.

[0015] Each of the dislocations may be spaced apart from the grain boundaries between the plurality of grains, or may contact only one of the grain boundaries of the plurality of grains.

[0016] According to one aspect of this disclosure, a multilayer capacitor may include: a body comprising a multilayer structure in which a plurality of dielectric layers having grains are stacked and a plurality of internal electrodes are stacked, the plurality of dielectric layers being interposed between the plurality of internal electrodes; and an external electrode disposed outside the body and connected to the internal electrodes. In the grains within a region of the body, the proportion of grains having dislocations is 20% or greater.

[0017] According to one aspect of this disclosure, a multilayer capacitor may include: a body comprising a multilayer structure in which a plurality of dielectric layers having grains are stacked and a plurality of internal electrodes are stacked, the plurality of dielectric layers being interposed between the plurality of internal electrodes; and an external electrode disposed outside the body and connected to the internal electrodes. The average proportion of grains having dislocations in a plurality of unit areas obtained in a cut surface of the body is 20% or greater. Attached Figure Description

[0018] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a perspective view schematically illustrating the appearance of a multilayer capacitor according to an exemplary embodiment of the present disclosure;

[0020] Figure 2 yes Figure 1 A cross-sectional view of a multilayer capacitor taken along line I-I';

[0021] Figure 3 yes Figure 1 A cross-sectional view of a multilayer capacitor taken along line II-II';

[0022] Figure 4 yes Figure 2 An enlarged view of region A in the image, which schematically shows the grains of the dielectric layer;

[0023] Figure 5 and Figure 6 These are images of the microstructure of a multilayer ceramic capacitor (MLCC) captured using annular dark-field scanning TEM (ADF-STEM).

[0024] Figure 7 and Figure 8 These are images of the grain microstructure captured from samples of the comparative example and the example, respectively;

[0025] Figures 9 to 11 The comparison example and the example piezoelectric microscopy (PFM) are shown respectively. 33 The results of the analysis; and

[0026] Figure 12 The results of measuring the temperature coefficient of capacitance (TCC) of the high-temperature portion are shown in the comparative example and the example. Detailed Implementation

[0027] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] Figure 1This is a perspective view schematically illustrating the appearance of a multilayer capacitor according to an exemplary embodiment of the present disclosure. Figure 2 yes Figure 1 A cross-sectional view of a multilayer capacitor taken along line I-I'. Figure 3 yes Figure 1 A cross-sectional view of a multilayer capacitor taken along line II-II'. Figure 4 yes Figure 2 An enlarged view of region A in the image, which schematically shows the grains of the dielectric layer.

[0029] Reference Figures 1 to 4 A multilayer capacitor 100 according to an exemplary embodiment of the present disclosure includes a body 110 and external electrodes 131 and 132. The body 110 includes a dielectric layer 111 and a plurality of internal electrodes 121 and 122, the plurality of internal electrodes 121 and 122 being alternately stacked and the dielectric layer 111 being disposed between the internal electrodes 121 and 122. At least one of the plurality of dielectric layers 111 includes a plurality of grains G, and a portion of the plurality of grains G has dislocations D. Here, the proportion of the plurality of grains G including dislocations D is 20% or greater, and when this condition is met, the DC bias capacitance of the multilayer capacitor 100 can be improved while minimizing the reduction in effective capacitance at high temperatures.

[0030] The body 110 includes a multilayer structure in which multiple dielectric layers 111 are stacked in a first direction (X direction), and the body 110 can be obtained, for example, by stacking multiple green sheets and then sintering the multiple green sheets. Through a sintering process, the multiple dielectric layers 111 can have a monolithic form. Figure 1 As shown, the body 110 may have a shape similar to a cuboid. The dielectric layer 111 included in the body 110 may comprise a ceramic material with a high dielectric constant, such as BT-based, i.e., barium titanate (BaTiO3)-based ceramic, but other materials known in the art may also be used, provided sufficient capacitance is obtained. If desired, the dielectric layer 111 may also include additives, organic solvents, plasticizers, binders, and dispersants together with the ceramic material as a main component. Here, the additives may include metallic components and may be added during the manufacturing process in the form of metal oxides. Examples of such metal oxide additives may include at least one of MnO2, Dy2O3, BaO, MgO, Al2O3, and Cr2O3. In addition, the additives may also include SiO2, CaCO3, etc.

[0031] Multiple internal electrodes 121 and 122 can be obtained by printing a paste containing conductive metal of a predetermined thickness onto one surface of a ceramic green sheet, and then sintering the paste. In this case, as... Figure 2As shown, a plurality of inner electrodes 121 and 122 may include a first inner electrode 121 and a second inner electrode 122 facing each other in a first direction (X direction), and the plurality of inner electrodes 121 and 122 may be exposed on the outer surfaces of the body 110 facing each other in a third direction (Z direction). Here, the third direction (Z direction) may be a direction perpendicular to the first direction (X direction) and the second direction (Y direction). The first inner electrode 121 and the second inner electrode 122 may be connected to different outer electrodes 131 and 132 having opposite polarities when driven, and may be electrically separated from each other by a dielectric layer 111 disposed between the first inner electrode 121 and the second inner electrode 122. However, the number of outer electrodes 131 and 132 or the method for connecting the outer electrodes to the inner electrodes 121 and 122 may vary according to exemplary embodiments. The main component materials of the inner electrodes 121 and 122 may include nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), etc., and alloys thereof may also be used.

[0032] External electrodes 131 and 132 may be formed on the exterior of the body 110 and may include a first external electrode 131 and a second external electrode 132 respectively connected to the first internal electrode 121 and the second internal electrode 122. External electrodes 131 and 132 may be formed by preparing a paste containing a conductive metal and then applying the paste to the body 110. Examples of conductive metals include nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or alloys thereof. Here, external electrodes 131 and 132 may also include a plating containing Ni, Sn, etc.

[0033] As described above, in this exemplary embodiment, at least one of the plurality of dielectric layers 111 comprises a plurality of grains G, and the proportion of grains G including dislocations D among the plurality of grains G may be 20% or greater. Generally, it is known that grains G preferably have fewer dislocations, but the inventors' research has shown that the presence of dislocations D in grains G improves properties such as DC bias. As described above, the dielectric layer 111 may include barium titanate components and additive components added thereto, and in the grains G, a ferroelectric phase having a tetragonal crystal structure and a relaxation phase having a cubic crystal structure coexist. When these two phases are aligned in the c-axis direction, the DC bias capacitance can be improved. In other words, the DC bias capacitance is, in principle, the capacitance when the domains are aligned in the c-axis direction when a DC electric field is applied. Therefore, if the domains within the dielectric material are manufactured to be aligned in the c-axis direction, the capacitance reduction due to domain wall pinning can be minimized.

[0034] In this way, when the ferroelectric and relaxor phases are aligned in one direction, multiple dislocations may occur to stabilize the two phases and align them in one direction. This is because the stress in the c-axis direction increases. As a result, the increase in the density of dislocation D in dielectric layer 111 can lead to an increase in DC bias capacitance. Furthermore, the increase in the density of dislocation D can reduce the contribution of extrinsic capacitance due to domain wall vibrations with large temperature effects, thus reducing the high-temperature effective capacitance reduction. However, excessively high density of dislocation D may degrade the performance and reliability of dielectric layer 111. Specifically, when cracks propagate, dislocation D, as line defects, may become crack propagation paths; therefore, dislocations may be regions with weak mechanical strength. In addition, dislocation D can become charge transfer paths due to the high concentration of chemical charge, which can act as conduction paths for leakage current. Considering these side effects, it is necessary to determine an upper limit for the density of dislocation D, and the proportion of grains with dislocation D in multiple grains G can be set to 40% or less.

[0035] Referring to the shape of dislocation D, measurement methods, and methods for achieving high dislocation density, firstly, as Figure 4 As shown, dislocation D may not contact the grain boundaries between multiple grains G, or a portion of dislocation D may form to contact only one grain boundary and not completely penetrate grain G. In this case, as described above, dislocation D may form between a phase with a tetragonal crystal structure and a phase with a cubic crystal structure in grain G. Furthermore, a portion of the multiple grains G may have multiple dislocations D.

[0036] In the case of methods for determining and measuring dislocation D, for example, at least four points (e.g., four, five, six or more points) can be set on a cut surface of dielectric layer 111, and the proportion of grains G with dislocation D per unit area can be calculated based on the set points. The proportion of grains G with dislocation D at the at least four points can be averaged to obtain the proportion of grains G with dislocation D.

[0037] In one example, the cutting surface may include a cutting surface that cuts the body 110 in a first direction (X direction) - third direction (Z direction) plane, or a cutting surface that cuts the body 110 in a first direction (X direction) - second direction (Y direction) plane. When the cutting surface includes a surface that cuts the body 110 in the first direction (X direction) - third direction (Z direction) plane, the cutting surface may cut the central portion of the body 110 in the second direction (Y direction), and when the cutting surface includes a surface that cuts the body 110 in the first direction (X direction) - second direction (Y direction) plane, the cutting surface may cut the central portion of the body 110 in the third direction (Z direction). The location of the cutting surface is not limited to these examples, and those skilled in the art can select other locations within the body 110 if desired. For example, when multiple measurements are performed at different cutting surfaces, the position of the cutting surface on the first direction (X direction) - the third direction (Z direction) plane and in the second direction (Y direction) can be set by a person skilled in the art, or the position of the cutting surface on the first direction (X direction) - the second direction (Y direction) plane and in the third direction (Z direction) can be set by a person skilled in the art.

[0038] The unit area may have a square shape and may have dimensions such as 5μm × 5μm, 4μm × 4μm, 3μm × 3μm, 2μm × 2μm, or 1μm × 1μm. The unit area is not limited to a square shape. For example, the unit area may have a rectangular shape with one side length of 1μm to 5μm and the other side width of 1μm to 5μm. As another example, the unit area may have a circular shape with a diameter of 1μm to 5μm. The size and shape of the unit area are not limited to these examples, and other sizes or shapes may be chosen by those skilled in the art if desired.

[0039] For example, the unit area in the measurement may be located at the center of the cut surface. In the case of performing multiple measurements at different locations on the same cut surface, one measurement may be performed at the center of the cut surface, and the remaining measurements may be performed at locations at intervals from the center, as defined by those skilled in the art. The location of the unit area is not limited to this and may be selected differently by those skilled in the art if desired.

[0040] It should be understood that when determining the proportion of dislocation-containing grains relative to the total number of grains in a measured unit area, the same criteria can be applied to determine whether grains associated with the measured unit area are counted. For example, grains counted in the measurement may include grains entirely within the selected unit area, as well as grains tangent to or in contact with the boundary of the selected unit area but not intersecting it. Alternatively, grains counted in the measurement may include grains entirely within the selected unit area, as well as grains in contact with or intersecting the boundary of the selected unit area.

[0041] In one example, the unit area in the measurement may be within one of a plurality of dielectric layers 111. Those skilled in the art will recognize that when the thickness of the dielectric layer 111 is less than the length, width, or diameter of the unit area, the unit area may include one or more portions of one or more inner electrodes, but such one or more portions do not have dielectric grains and therefore may not be counted in the measurement. In one example, when the sum of the thickness of the dielectric layer 111 and the thickness of the adjacent inner electrode is less than the length, width, or diameter of the unit area, the unit area in the measurement may include the grains of such dielectric layer within the unit area, and also the grains of one or more dielectric layers adjacent to such dielectric layer within the unit area.

[0042] Dislocation D can be determined by observing its microstructure using annular dark-field scanning transmission electron microscopy (ADF-STEM). Other methods and / or tools, as understood by those skilled in the art, may be used even if not described in this disclosure. Figure 5 and Figure 6 These are images of the microstructure of MLCCs captured by ADF-STEM, obtained using an Osiris-type FEI at an accelerating voltage of 200 kV, a camera length of 110 nm, a magnification of 40,000x, and in dark-field imaging conditions. Figure 5 As can be seen, dislocations appear as white lines that do not completely penetrate the grain. However, in the case of ADF-STEM imaging, the color of the observed dislocations may change depending on the camera length (the distance between the sample and the image frame), but dislocations can be distinguished from other defects by setting the measurement conditions to specify the camera length (e.g., less than 150 nm). That is, the shape of the dislocation can be distinguished from other results (such as... Figure 6 The twin boundaries or domain boundaries shown in the microstructure are clearly distinguishable. Furthermore, when imaging using ADF-STEM, the accelerating voltage can be adjusted from 80kV to 300kV.

[0043] Methods and experimental examples for controlling dislocation density will be described below. According to the inventors' research, dislocation density increases when a relatively high reducing atmosphere (hereinafter referred to as a "heavy reducing atmosphere") is formed during the sintering of the dielectric layer. Here, a heavy reducing atmosphere is an atmosphere with a relatively high partial pressure of H2 during sintering, and this exemplary embodiment is based on an H2 to N2 concentration ratio of 0.2% to 1.0%. In contrast, a weak reducing atmosphere is based on an H2 to N2 ratio of less than 0.2% during sintering. In this disclosure, the reducing atmosphere is set based on the H2 concentration rather than the oxygen partial pressure, and this is based on research findings on the effect of H2 concentration on cation diffusion behavior. Within an H2 concentration ratio of 0.2% to 1.0%, 0.2% is set as the lower limit required for diffusion control, and 1.0% is set as the upper limit, based on the side effect (IR drop) of forming oxygen vacancies. In a heavy reducing atmosphere set according to the above-described basis, additive components (e.g., Mg) permeate into the BT phase to form a second phase, thus reducing the rate at which rare earth elements permeate into the BT phase. Therefore, it should be understood that the proportion of cubic phases can be adjusted by the infiltration of rare earth elements, and finally, the amounts of tetragonal and cubic phases can be balanced to allow for the sufficient formation of dislocations.

[0044] The inventors prepared samples as comparative and example examples and analyzed the dislocations present in the grains of the dielectric layer using the following measurement methods.

[0045] The comparative example was fired in an atmosphere of 0.1% H2 compared to N2, while the example was sintered in an atmosphere of 0.56% H2 compared to N2.

[0046] - 4 points were measured for each sample.

[0047] - Measurement magnification: ×40000

[0048] - Measurement area: approximately 3μm × 3μm (preferably including more than 150 grains)

[0049] - Measure the number of grains including dislocations and the total number of grains in each measurement region.

[0050] Figure 7 and Figure 8 Images of the grain microstructure captured from samples of the comparative example and the example, respectively. Figure 7 and Figure 8 In the diagram, arrows indicate the portions of the sample that correspond to four points defined on the cut surface and are identified as dislocations. Table 1 below summarizes the proportion of grains with dislocations in the comparative and sample examples.

[0051] [Table 1]

[0052]

[0053] Based on the experimental results, the proportion of grains with dislocations in multiple grains was measured to be 0.11 (11%) in the comparative example and 0.20 (20%) in the example.

[0054] Figures 9 to 11 The comparison example and the example piezoelectric microscopy (PFM) are shown respectively. 33 The results of the analysis show that this analytical method analyzes d 33 Phase deviation and amplitude determine domain alignment and polarization magnitude. In this experiment, PFM analysis was performed at a frequency of 1 Hz in a 1 μm × 1 μm region using an NX10 piezoelectric microscope (PFM) from Park System and a Multi75E-G probe from Budget Sensors. Figure 9 and Figure 10 It is shown in d 33 The results of the up-mapping, where the alignment angle of domains in the vertical direction of the applied voltage is represented by color, and the smaller the color deviation, the better the alignment in one direction. As an experimental result, in an example with a relatively high dislocation density ( Figure 10 In the case of ), the color deviation is smaller than that of the comparison example ( Figure 9 The color deviation means that the domains within the dielectric material are better aligned in the c-axis direction. Figure 11 It shows d 33 Amplitude curve, Figure 11 The magnitude of the displacement caused by the applied voltage is shown, where it can be seen that the displacement increases further in the example. This can be understood as the increase in the magnitude of the total polarization when the domains are well aligned in one direction. The above results demonstrate that by increasing the dislocation density in the dielectric layer, the domains can be better aligned in the direction of the applied electric field.

[0055] Table 2 below shows the results of measuring DC bias capacity (C), capacity reduction rate (ΔC), and loss factor (Df) in the comparative and example examples.

[0056] [Table 2]

[0057]

[0058] The results above show that, based on the DC bias capacitance measurements of the two samples using DC voltage, the reduction rate of DC bias capacitance in the example with high dislocation density is lower than that in the comparative example under all DC voltages. In the case of the example, it can be seen that, since the DC bias capacitance is not increased by suppressing grain growth, the nominal capacitance value remains almost the same, allowing the DC bias capacitance to be increased without reducing the capacitance.

[0059] in addition, Figure 12The results of measuring the temperature coefficient of capacitance (TCC) of the high-temperature portion in the comparative and example examples are shown. It can be seen that in the example with high dislocation density, the effective high-temperature capacitance increases, resulting in a 36.7% improvement in the reduction of the capacitance of the high-temperature portion based on 85°C.

[0060] As described above, the experimental results show that DC bias capacitance and high-temperature effective capacitance can be increased by controlling domain alignment, and the contribution of intrinsic capacitance can be increased by increasing the dislocation density in the grains of the dielectric material.

[0061] As described above, in the case of a multilayer capacitor according to the exemplary embodiments of this disclosure, the reduction in effective capacitance at high temperatures can be minimized, while DC bias capacitance can be improved.

[0062] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer capacitor, comprising: The main body includes a multilayer structure in which multiple dielectric layers are stacked and multiple internal electrodes are stacked, with the multiple dielectric layers located between the multiple internal electrodes; as well as An outer electrode is disposed outside the main body and connected to the inner electrode. Wherein, at least one of the plurality of dielectric layers comprises a plurality of grains, and the proportion of grains having dislocations in the plurality of grains is 20% or greater and 40% or less.

2. The multilayer capacitor according to claim 1, wherein, The dislocations are separated from the grain boundaries between the plurality of grains.

3. The multilayer capacitor according to claim 1, wherein, A dislocation in one of the plurality of grains contacts only one grain boundary between that grain and the other grains in the plurality of grains.

4. The multilayer capacitor according to claim 1, wherein, Dislocations within one of the plurality of grains are located between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure.

5. The multilayer capacitor according to claim 1, wherein, Some of the grains have multiple dislocations.

6. The multilayer capacitor according to claim 1, wherein, The proportion of grains with dislocations in a plurality of grains is obtained by averaging the values ​​measured in at least four unit areas on the cut surface of the dielectric layer.

7. The multilayer capacitor according to any one of claims 1 to 6, wherein, The dielectric layer comprises barium titanate-based ceramic.

8. The multilayer capacitor according to claim 1, wherein, Each of the dislocations is spaced apart from the grain boundaries between the plurality of grains, or contacts only one of the grain boundaries of the plurality of grains.

9. A multilayer capacitor, comprising: The main body includes a multilayer structure in which multiple dielectric layers with grains are stacked and multiple internal electrodes are stacked, with the multiple dielectric layers interposed between the multiple internal electrodes; and An outer electrode is disposed outside the main body and connected to the inner electrode. Among the plurality of grains in the dielectric layer in the region of the main body, the proportion of grains having dislocations is 20% or greater and 40% or less.

10. The multilayer capacitor according to claim 9, wherein, In the region of the body, each dislocation is spaced apart from the grain boundaries between the plurality of grains, or contacts only one of the grain boundaries of the plurality of grains.

11. The multilayer capacitor according to claim 9, wherein, Dislocations within one of the plurality of grains are located between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure.

12. The multilayer capacitor according to claim 9, wherein, In the region of the main body, a portion of the plurality of grains have a plurality of dislocations.

13. The multilayer capacitor according to any one of claims 9 to 12, wherein, The dielectric layer comprises barium titanate-based ceramic.

14. A multilayer capacitor, comprising: The main body includes a multilayer structure in which multiple dielectric layers with grains are stacked and multiple internal electrodes are stacked, with the multiple dielectric layers located between the multiple internal electrodes. as well as An outer electrode is disposed outside the main body and connected to the inner electrode. Among the multiple grains obtained in the dielectric layer in multiple unit areas of the cut surface of the main body, the average proportion of grains with dislocations is 20% or greater and 40% or less.

15. The multilayer capacitor according to claim 14, wherein, In each of the plurality of unit areas, each of the dislocations is spaced apart from the grain boundaries between the plurality of grains, or is in contact with only one of the grain boundaries of the plurality of grains.

16. The multilayer capacitor according to claim 14, wherein, Dislocations within one of the plurality of grains are located between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure.

17. The multilayer capacitor according to claim 14, wherein, In each of the plurality of unit areas, a portion of the plurality of grains has a plurality of dislocations.

18. The multilayer capacitor according to any one of claims 14 to 17, wherein, The dielectric layer comprises barium titanate-based ceramic.

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