Semiconductor device and method of forming the same

Abstract

This application relates to semiconductor devices and methods of forming the same. A method for forming a multilayer conductive structure includes forming a first conductive portion, forming a second conductive portion containing ruthenium (Ru) therein over the first conductive portion, forming a third conductive portion over the second conductive portion, and performing a silicidation process on the second conductive portion.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods of forming the same. Background Technology

[0002] In hybrid bonding processes used to join wafers together, copper (Cu) plugs are typically used. However, if copper is used in layers close to silicon, device performance can be degraded in some cases due to copper contamination. Furthermore, for hybrid bonding, the plug height needs to be approximately 500 nm because the expansion of Cu is used to join the copper plugs together. For this reason, handling fine contacts is more difficult.

[0003] In some cases, tungsten (W) is used for digital lines in dynamic random access memory (DRAM). In these cases, if further miniaturization is pursued, it is anticipated that the necessary low resistance may not be achievable using tungsten due to the fine-line effect. Therefore, the use of ruthenium (Ru), which has lower resistance and a smaller fine-line effect than tungsten, is being investigated. However, because heat treatment is performed after drilling holes for the contacts to reduce the resistance of the contacts on the silicon substrate formed simultaneously with the contacts on the digital lines, ruthenium accumulates within the contact space before the contact material is embedded, potentially leading to discontinuities of ruthenium near the contacts in some cases. Summary of the Invention

[0004] In one aspect, this application provides a method for forming a multilayer conductive structure, comprising: forming a first conductive portion; forming a second conductive portion on the first conductive portion, wherein the second conductive portion contains ruthenium (Ru); forming a third conductive portion on the second conductive portion; and performing a silicide process on the second conductive portion.

[0005] In another aspect, this application provides a method comprising: forming a first conductive portion therein containing ruthenium (Ru); forming an insulating film covering the first conductive portion; forming a contact hole exposing a portion of the first conductive portion; and performing a silicide process on the first conductive portion through the contact hole.

[0006] In another aspect, this application provides an apparatus comprising: a first portion containing a conductive material; a second portion containing a conductive material; and a third portion between the first portion and the second portion, wherein the third portion contains ruthenium silicide, the ruthenium silicide being formed by depositing ruthenium and then at least partially silicideizing the ruthenium therein. Attached Figure Description

[0007] Figure 1 This is a diagram used to illustrate a semiconductor device according to the first, second, and third embodiments, and is a longitudinal section showing an example of a schematic configuration of a complementary metal-oxide-semiconductor (CMOS) device having a hybrid bonding structure. Figure 2 and 3 Each is shown Figure 1 A longitudinal section of an example of a schematic configuration of the first and second conductive portions before the bonding of the semiconductor device shown.

[0008] Figures 4 to 9 This is a diagram illustrating a schematic configuration of a semiconductor device according to a first embodiment and a method of forming the device therein. Figures 4 to 9 This is a diagram illustrating examples of schematic configurations in exemplary process stages in sequence. Figure 4 It's a floor plan. Figures 5 to 9 It shows along Figure 4 The longitudinal section is an example of a schematic configuration of the line BB portion in the diagram.

[0009] Figures 10 to 13 This is a diagram illustrating a schematic configuration of a semiconductor device according to a second embodiment and a method for forming the device therein. Figures 10 to 13 This is a diagram illustrating instances of schematic configurations in exemplary process stages in sequence, and it shows the sequence along... Figure 4 The longitudinal section is an example of a schematic configuration of the line BB portion in the diagram.

[0010] Figures 14 to 17 This is a diagram illustrating a schematic configuration of a semiconductor device according to a third embodiment and a method for forming the device therein. Figures 14 to 17 This is a diagram illustrating instances of schematic configurations in exemplary process stages in sequence, and it shows the sequence along... Figure 4 The longitudinal section is an example of a schematic configuration of the line BB portion in the diagram.

[0011] Figure 18 This is a diagram used to illustrate a semiconductor device according to the fourth, fifth, and sixth embodiments, and is a longitudinal section showing an example of a schematic configuration of a DRAM having a hybrid bonding structure.

[0012] Figures 19 to 22 This is a diagram illustrating a schematic configuration of a semiconductor device according to a fourth embodiment and a method for forming the device therein. Figures 19 to 22 This is a diagram illustrating examples of schematic configurations in exemplary process stages in sequence.

[0013] Figures 23 to 25 This is a diagram illustrating a schematic configuration of a semiconductor device according to a fifth embodiment and a method for forming the device therein. Figures 23 to 25 This is a diagram illustrating examples of schematic configurations in exemplary process stages in sequence.

[0014] Figure 26 and 27 This is a diagram illustrating a schematic configuration of a semiconductor device according to a sixth embodiment and a method for forming the device therein. Figure 26 and 27This is a diagram illustrating examples of schematic configurations in exemplary process stages in sequence.

[0015] Figure 28 This is a diagram used to illustrate a semiconductor device according to the seventh and eighth embodiments, and is a plan view layout showing an example of a schematic configuration of a portion of DRAM.

[0016] Figures 29 to 31 This is a diagram illustrating a schematic configuration of a semiconductor device according to the seventh embodiment and a method for forming the device therein. Figures 29 to 31 This is a diagram illustrating instances of schematic configurations in exemplary process stages in sequence, and it shows the sequence along... Figure 28 The longitudinal section of a schematic configuration of the line JJ portion in the diagram.

[0017] Figure 32 and 33 This is a diagram illustrating a schematic configuration of a semiconductor device according to the eighth embodiment and a method for forming the device therein. Figure 32 and 33 This is a diagram illustrating instances of schematic configurations in exemplary process stages in sequence, and it shows the sequence along... Figure 28 The longitudinal section of a schematic configuration of the line JJ portion in the diagram. Detailed Implementation

[0018] Various embodiments of the invention will now be described in detail with reference to the accompanying drawings. The detailed description below refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that other embodiments may be used and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0019] In a semiconductor device according to various embodiments, a third conductive portion disposed between a first conductive portion and a second conductive portion has a structure that comprises ruthenium silicide (RuSi) wholly or partially. A portion of the third conductive portion connecting the first and second conductive portions may be ruthenium silicide, or the entire third conductive portion may be ruthenium silicide. The third conductive portion may be a wire, a contact, a plug electrode, or some other type of conductive portion.

[0020] The third conductive portion connecting the first and second conductive portions may further comprise silicon (Si), titanium (Ti), titanium nitride (TiN), or other conductive materials. Similarly, the third conductive portion may be a wire, contact, plug electrode, or some other type of conductive portion. Additionally, a wire, contact, plug electrode, or some other type of conductive portion may be considered as the first and second conductive portions, and all or part of the gap between them may be configured to contain ruthenium silicide. Furthermore, a portion of a wire may be considered as the first conductive portion, and a contact, plug electrode, or some other type of conductive portion connected to the wire may be considered as the second conductive portion, and all or part of the gap between them may be configured to contain ruthenium silicide.

[0021] Additionally, during silicide formation, ruthenium (Ru) reacts with silicon, and its volume expands as ruthenium silicide is formed. By utilizing this expansion to fill the gaps, electrical connections can be established. In the stages preceding ruthenium silicide formation, wires, contacts, plug electrodes, or some other type of conductive portion may have gaps, and in cases where electrical discontinuities arise due to these gaps, silicide formation can be performed to create ruthenium silicide and fill the gaps.

[0022] When applied to hybrid bonding, after wafer positioning, the components forming electrodes or wires expand due to annealing heat treatment, and using this arrangement, the electrodes or wires can be designed to pass through gaps and contact each other, allowing the silicide reaction to continue. It can also be designed so that the gaps are connected by expansion due to the formation of ruthenium silicide.

[0023] Furthermore, the electrodes or wires can be formed of ruthenium and configured such that ruthenium silicide is pre-formed relative to a gapless structure. By pre-forming ruthenium silicide, aggregation caused by heat treatment can be suppressed, and breaks in the wires can be prevented.

[0024] When forming ruthenium silicide, ruthenium and silicon can be pre-formed into contact with each other, and ruthenium silicide can be formed by performing heat treatment on ruthenium and silicon. Alternatively, ruthenium can be formed on one side of the gap, while silicon can be formed on the other side of the gap, and ruthenium and silicon can be brought into contact during heat treatment through the expansion of ruthenium, thereby forming ruthenium silicide. Furthermore, ruthenium silicide can be formed by supplying ruthenium with a gas containing silane, disilane, dichlorosilane, monochlorosilane, trichlorosilane, or some other type of silicon.

[0025] (First to Third Embodiments)

[0026] Reference Figures 1 to 3 The semiconductor device 1A using the first to third embodiments is described. In the following description, Figure 1 This is a longitudinal section illustrating an example of a schematic configuration of a semiconductor device 1A comprising a CMOS circuit formed by combining NMOS transistors and PMOS transistors.

[0027] Figure 1 A schematic configuration of a portion of semiconductor device 1A is shown. The bonding is achieved through hybrid bonding. Figure 2 and 3 The first conductive portion 10 and the second conductive portion 30 shown herein form a semiconductor device 1A.

[0028] For example, wafers are joined by hybrid bonding using a fusion bonding method. In a fusion bonding method, a process is first performed to adhere a large number of hydroxyl groups to the contact surface, or in other words, a hydrophilization treatment is performed.

[0029] Next, the hydrophilicated contact surfaces are stacked and bonded together. Bonding according to the fusion bonding method is formed through hydrogen bonds between hydroxyl groups on the hydrophilic surfaces. Bonding according to the fusion bonding method can be performed at room temperature. In the following description, the fusion bonding method is used to achieve bonding via hybrid bonding.

[0030] like Figure 1 , 2 As shown in Figure 3, semiconductor device 1A has a first conductive portion 10 and a second conductive portion 30. For example, the first conductive portion 10 is a portion containing an NMOS transistor. For example, the second conductive portion 30 is a portion containing a PMOS transistor.

[0031] The first conductive portion 10 has a semiconductor substrate 11, an isolator 12 disposed in the semiconductor substrate 11, a gate electrode 13, contacts 15, 16 and 17, wires 18 and 19, and plugs 20 and 21 disposed on the semiconductor substrate 11. The gate electrode 13, contacts 15, 16 and 17, wires 18 and 19, and plugs 20 and 21 are covered by an insulating film 14 disposed on the semiconductor substrate 11.

[0032] For example, the semiconductor substrate 11 comprises p-type single-crystal silicon. For example, the separator 12 and the insulating film 14 comprise insulating materials such as silicon dioxide (SiO2). For example, the gate electrode 13 comprises conductive materials such as polysilicon (poly-Si), tungsten nitride (WN), or tungsten (W). An n-type source and drain, not shown, are disposed on either side of the gate electrode 13 within the semiconductor substrate 11, and the gate electrode 13 serves as the gate electrode of an NMOS transistor.

[0033] The second conductive portion 30 has a semiconductor substrate 31, an isolator 32 disposed in the semiconductor substrate 31, a gate electrode 33, contacts 35, 36 and 37, wires 38 and 39, and plugs 40 and 41 disposed on the semiconductor substrate 31. The gate electrode 33, contacts 35, 36 and 37, wires 38 and 39, and plugs 40 and 41 are covered by an insulating film 34 disposed on the semiconductor substrate 31.

[0034] For example, the semiconductor substrate 31 comprises n-type single-crystal silicon. For example, the separator 32 and the insulating film 34 comprise insulating materials such as silicon dioxide. The gate electrode 33 comprises conductive materials such as polycrystalline silicon, tungsten nitride, or tungsten. Source and drain electrodes (not shown) are disposed on either side of the gate electrode 33 within the semiconductor substrate 31, and the gate electrode 33 serves as the gate electrode of a PMOS transistor.

[0035] The first conductive portion 10 and the second conductive portion 30 are joined together by a mixed bonding contact, such that the top surfaces of the insulating films 14 and 34, the end faces of the plugs 20 and 41, and the end faces of the plugs 21 and 40 are abutted against each other. Figure 1 In the middle, the second conductive part 30 is relative to Figure 3 The state shown is displayed in an inverted state.

[0036] exist Figure 1 In this structure, an insulating film 42 is disposed on top of the semiconductor substrate 31 and the insulating member 32. A wire 44 is disposed on top of the insulating film 42, and the bottom surface of the wire 44 and the top surface of the insulating film 34 are connected through a through-hole 43.

[0037] For example, contacts 15, 16, 17, 35, 36, and 37 are formed to contain a conductive material such as titanium nitride (TiN) or tungsten. For example, wires 18, 19, 38, and 39 contain a conductive material such as tungsten nitride or tungsten. Plugs 20, 21, 41, and 40 are formed to contain at least ruthenium silicide (RuSi), as described in the first to fourth embodiments below.

[0038] Figures 4 to 17 The semiconductor devices 1A, 1B, 1C, and 1D shown are Figure 1 , 2 Partial illustrations of plugs 20, 21, 40, and 41 shown in Figure 3, and the plug assembly portions corresponding to the wires 18, 19, 38, and 39 to which the plugs are connected. Referring below... Figures 4 to 17 The semiconductor devices 1A, 1B, 1C and 1D according to the first to fourth embodiments and the methods for forming them are described.

[0039] The semiconductor device 1B and its method of formation according to the first embodiment will be described with reference to 4 to 9. Figure 4 A plan view layout of semiconductor device 1B is shown. Figure 5 It is along Figure 4 The longitudinal section of line BB in the diagram is shown below. This forms the semiconductor device 1B.

[0040] First, the first conductive portion 100 will be described. First, as... Figure 4 and 5As shown, a first insulating film 102 is formed on the first wiring layer 101, and a contact hole 104 having a circular shape in the plan view is formed in the first insulating film 102. For example, the first conductive portion 100 includes an NMOS circuit. The first wiring layer 101 corresponds to, for example... Figure 1 The figure shows wire 18. For example, the first wiring layer 101 contains a conductive material such as tungsten nitride or tungsten.

[0041] For example, tungsten nitride or tungsten is deposited via chemical vapor deposition (CVD). Subsequently, photolithography and dry etching are performed to pattern the tungsten nitride or tungsten, thereby forming the first wiring layer 101.

[0042] For example, the insulating film 102 contains an insulating material such as silicon dioxide. For example, the first insulating film 102 is formed via CVD. Subsequently, photolithography and anisotropic dry etching are performed on the first wiring layer 101 to form contact holes 104 reaching the surface of the first wiring layer 101. The contact holes 104 have a hollow cylindrical shape with an open top.

[0043] Next, as Figure 6 As shown, a first conductive material 106 and a second conductive material 108 are embedded in the contact hole 104. The first conductive material 106 is configured to contact the first wiring layer 101. The first conductive material 106 and the second conductive material 108 have a multilayer conductive structure that is vertically stacked in the contact hole 104, wherein the first conductive material 106 is disposed at the bottom and the second conductive material 108 is disposed to cover the top surface of the first conductive material 106.

[0044] For example, the first conductive material 106 comprises a conductive material such as ruthenium. For example, the second conductive material 108 comprises a conductive material such as silicon. For example, ruthenium and silicon are deposited via CVD. The first conductive material 106 and the second conductive material 108 are embedded within the contact hole 104 as described below. First, the first conductive material 106 is deposited inside the contact hole 104 and on the first insulating film 102, and then an etch-back process is performed to form the first conductive material 106 in the lower portion of the contact hole 104. Sufficient etch-back is performed to remove the first conductive material 106 from the first insulating film 102, and a slight depression is formed in the upper portion of the contact hole 104.

[0045] Next, a second conductive material 108 is deposited inside the contact hole 104 and on the first insulating film 102, followed by sufficient back etching to expose the top surface of the first insulating film 102. Through the above steps, the first conductive portion 100 is formed.

[0046] In addition, such as Figure 7As shown, a second conductive portion 200 is formed according to steps similar to those described above, having a configuration similar to that of the first conductive portion 100. For example, the second conductive portion 200 includes a PMOS circuit. The second conductive portion 200 has a second wiring layer 201, a second insulating film 202, a contact hole 204 disposed in the second insulating film 202, and a third conductive material 206 and a fourth conductive material 208 embedded in the contact hole 204. These elements correspond to the first wiring layer 101, the first insulating film 102, the contact hole 104, the first conductive material 106, and the second conductive material 108 of the first conductive portion 100, and have a similar configuration.

[0047] Next, as Figure 8 As shown, the first conductive portion 100 and the second conductive portion 200 are stacked. Figure 8 The second conductive portion 200 in the middle is relative to Figure 7 The second conductive portion 200 is shown in an inverted state. The first conductive portion 100 and the second conductive portion 200 are in contact with each other at the bonding surface C and are bonded together by a hybrid bonding. At the bonding surface C, the first insulating film 102 and the second insulating film 202 face each other and are in contact. The second conductive material 108 and the fourth conductive material 208 face each other but are not in contact, and a gap 109 is formed between them.

[0048] Next, silicide formation is performed by annealing. During annealing, the second conductive material 108 and the first conductive material 106, as well as the fourth conductive material 208 and the third conductive material 206, react with each other to form ruthenium silicide, as shown below. Figure 9 As shown. For example, annealing is performed at a temperature of approximately 400 degrees Celsius or higher. During annealing, ruthenium and silicon react, and the material expands in volume when ruthenium silicide is formed. For this reason, ruthenium silicide produced by the reaction between the second conductive material 108 and the first conductive material 106, and ruthenium silicide produced by the reaction between the fourth conductive material 208 and the third conductive material 206, fill the gap 109 and bond together to form the fifth conductive material 209.

[0049] The first conductive material 106, the fifth conductive material 209, and the third conductive material 206 serve as plug electrodes connecting the first wiring layer 101 and the second wiring layer 201. Through the above steps, a semiconductor device 1B according to the first embodiment is formed. The fifth conductive material 209, containing ruthenium silicide, is inserted between the first conductive material 106 and the third conductive material 206. Ruthenium silicide is contained in at least a portion of the material between the first wiring layer 101 and the second wiring layer 201.

[0050] Next, we will refer to Figure 4 , Figure 5 and Figures 10 to 13The semiconductor device 1C and its formation method according to the second embodiment will be described. The semiconductor device 1C is formed as follows. The method for depositing each film of the semiconductor device 1C is similar to that in the first embodiment. In the second embodiment, a first conductive portion 110 and a second conductive portion 210 are formed. First, for the first conductive portion 110, the following steps are performed: Figure 4 and 5 The steps described in the document.

[0051] Next, as Figure 10 As shown, a first conductive material 116 is formed along the inner wall of the contact hole 104. The first conductive material 116 contains ruthenium. For example, ruthenium is deposited via CVD, but its thickness is insufficient to fill the contact hole 104. In this case, ruthenium is deposited on the inner wall of the contact hole 104 and on the top surface of the first insulating film 102.

[0052] Next, ruthenium is etched back to expose at least the surface of the first insulating film 102. With this arrangement, a first conductive material 116 containing ruthenium is formed only on the inner wall of the contact hole 104. The upper end of the first conductive material 116 is located slightly below the top surface of the first insulating film 102, and the first conductive material 116 is not formed at the uppermost part of the inner wall of the contact hole 104. With this arrangement, the sides and bottom of the contact hole 104 are covered by the first conductive material 116, and the first conductive material 116 is formed in a cup shape.

[0053] Next, a second conductive material 118 is formed within the contact hole 104. The second conductive material 118 comprises silicon. Silicon is embedded within the contact hole 104 to cover the inner and top surfaces of the cup-shaped first conductive material 116, and silicon is also formed on the top surface of the first insulating film 102. Next, the silicon is sufficiently etched back to expose at least the surface of the first insulating film 102. The etch-back is adjusted to end before the top surface of the first conductive material 116 is exposed. With this arrangement, a cup-shaped first conductive material 116 and a second conductive material 118 covering the sides and top surface of the first conductive material 116 are formed within the contact hole 104.

[0054] exist Figure 10 In the longitudinal section shown, the first conductive material 116 is U-shaped, while the second conductive material 118 is T-shaped. In the contact hole 104, the first conductive material 116 and the second conductive material 118 have a combined structure obtained by nesting the T-shape into the U-shape. In the contact hole 104, the first conductive material 116 and the second conductive material 118 contact each other on their sides extending vertically through the contact hole 104, and the contact area is large. For example, the second conductive material 118 and the first conductive material 116, as well as the fourth conductive material 218 and the third conductive material 216, are set to be approximately equal to each other in volume ratio.

[0055] In addition, such as Figure 11As shown, a second conductive portion 210 with a configuration similar to the first conductive portion 110 is formed according to steps similar to those described above. For example, the second conductive portion 210 includes a PMOS circuit. The second conductive portion 210 has a second wiring layer 201, a second insulating film 202, a contact hole 204 disposed in the second insulating film 202, and a third conductive material 216 and a fourth conductive material 218 embedded in the contact hole 204. These elements correspond to the first wiring layer 101, the first insulating film 102, the contact hole 104, the first conductive material 116, and the second conductive material 118 of the first conductive portion 110, and have a similar configuration.

[0056] Next, as Figure 12 As shown, the first conductive portion 110 and the second conductive portion 210 are stacked. Figure 12 The second conductive portion 210 in the middle is relative to Figure 11 The second conductive portion 210 is shown in an inverted state. The first conductive portion 110 and the second conductive portion 210 are in contact with each other at the bonding surface D and are bonded together by a hybrid bonding process. At the bonding surface D, the first insulating film 102 and the second insulating film 202 face each other and are in contact. The second conductive material 118 and the fourth conductive material 218 face each other but are not in contact, and a gap 119 is formed between them.

[0057] Next, through annealing, the second conductive material 118 and the first conductive material 116, as well as the fourth conductive material 218 and the third conductive material 216 in the contact hole 104, react completely with each other to form ruthenium silicide, as shown below. Figure 13 As shown, ruthenium and silicon react, and the material expands in volume when ruthenium silicide is formed. In contact hole 104, a first conductive material 116 and a second conductive material 118 are formed to contact each other on their sides extending vertically through contact hole 104. With this arrangement, all the ruthenium and silicon in contact hole 104 react when silicide is performed.

[0058] For this reason, ruthenium silicide generated by the reaction between the second conductive material 118 and the first conductive material 116, and ruthenium silicide generated by the reaction between the fourth conductive material 218 and the third conductive material 216 fill the gap 119 and combine to form a fifth conductive material 219. With this arrangement, the contact hole 104 is filled with the fifth conductive material 219 containing ruthenium silicide. In this way, the fifth conductive material 219 has a cylindrical shape and serves as a plug electrode connecting the first wiring layer 101 and the second wiring layer 201.

[0059] Through the above steps, a semiconductor device 1C according to the second embodiment is formed. A fifth conductive material 219 containing ruthenium silicide is inserted between the first wiring layer 101 and the second wiring layer 201, and connects the first wiring layer 101 and the second wiring layer 201.

[0060] Next, we will refer to Figure 4 , Figure 5 and Figures 14 to 17 A semiconductor device 1D and a method for forming the same according to a third embodiment will be described. The semiconductor device 1D is formed as follows. The method for depositing each film of the semiconductor device 1D is similar to that in the first embodiment. In the third embodiment, a first conductive portion 120 and a second conductive portion 220 are formed. First, for the first conductive portion 120, the following steps are performed: Figure 4 and 5 The steps described in the document.

[0061] Next, as Figure 14 As shown, a barrier metal 124 and a first conductive material 125 are formed in the contact hole 104. The barrier metal 124 comprises titanium nitride. The first conductive material 125 comprises tungsten. The barrier metal 124 is formed in a cup shape along the inner wall of the contact hole 104. The first conductive material 125 is formed to fill the interior of the cup-shaped barrier metal 124.

[0062] The top surfaces of the barrier metal 124 and the first conductive material 125 are recessed downwards from the top surface of the first insulating film 102. The barrier metal 124 is formed by CVD deposition along the inner wall of the contact hole 104 followed by etching back. The first conductive material 125 is formed by CVD deposition followed by etching back.

[0063] A second conductive material 126 and a third conductive material 127 are stacked and formed on top of the barrier metal 124 and the first conductive material 125. The second conductive material 126 contains ruthenium. The third conductive material 127 contains silicon. The second conductive material 126 is formed by CVD deposition of ruthenium followed by etch-back of the ruthenium. The third conductive material 127 is formed by CVD formation of silicon followed by etch-back of the silicon.

[0064] In addition, such as Figure 15 As shown, the second conductive portion 220 is formed according to steps similar to those described above. For example, the second conductive portion 220 includes a PMOS circuit. The second conductive portion 220 has a second wiring layer 201, a second insulating film 202, a contact hole 204 disposed in the second insulating film 202, and a barrier metal 224, a fifth conductive material 225, a sixth conductive material 226, and a seventh conductive material 227 embedded in the contact hole 204. These components have a configuration similar to that of the first wiring layer 101, the first insulating film 102, the barrier metal 124, the first conductive material 125, the second conductive material 126, and the third conductive material 127 of the first conductive portion 120.

[0065] Next, as Figure 16 As shown, the first conductive portion 120 and the second conductive portion 220 are stacked. Figure 16 The second conductive portion 220 in the middle is relative to Figure 15 The second conductive portion 220 is shown in an inverted state. The first conductive portion 120 and the second conductive portion 220 are in contact with each other at the bonding surface E and are bonded together by a hybrid bonding. At the bonding surface E, the first insulating film 102 and the second insulating film 202 face each other and are in contact. The third conductive material 127 and the seventh conductive material 227 face each other but are not in contact, and a gap 129 is formed between them.

[0066] Next, silicide formation is performed by annealing. During annealing, the second conductive material 126 and the third conductive material 127, as well as the sixth conductive material 226 and the seventh conductive material 227 in the contact hole 104, react with each other to form ruthenium silicide, as shown below. Figure 17 As shown.

[0067] For example, annealing is performed at a temperature of approximately 400 degrees Celsius or higher. During annealing, ruthenium and silicon react, and the material expands in volume as ruthenium silicide is formed. For this reason, ruthenium silicide produced by the reaction between the second conductive material 126 and the third conductive material 127, and ruthenium silicide produced by the reaction between the sixth conductive material 226 and the seventh conductive material 227, fill the gap 129 and bond to form the eighth conductive material 229.

[0068] The blocking metal 124, the first conductive material 125, the blocking metal 224, the fifth conductive material 225, and the eighth conductive material 229 serve as plug electrodes connecting the first wiring layer 101 and the second wiring layer 201. Through the above steps, a semiconductor device 1D according to the third embodiment is formed. The eighth conductive material 229, containing ruthenium silicide, is inserted between the first wiring layer 101 and the second wiring layer 201, connecting the first wiring layer 101 and the second wiring layer 201.

[0069] (Fourth to Sixth Embodiments)

[0070] Next, we will refer to Figure 18 The semiconductor device 2A, which applies the fourth to sixth embodiments, is described below. Hereinafter, a dynamic random access memory (DRAM) will be described as an example of the semiconductor device 2A. Figure 18 This is a longitudinal section showing an example of a schematic configuration of semiconductor device 2A.

[0071] like Figure 18As shown, semiconductor device 2A has a transistor portion 50 and a capacitor portion 60. The transistor portion 50 has a semiconductor substrate 51, a gate electrode 52, an isolator 53, a capacitive contact 54, a bit line 55, an insulating film 56, and a plug 57. For example, the semiconductor substrate 51 comprises monocrystalline silicon. The gate electrode 52 serves as a DRAM word line, and the gate electrode 52, together with the source and drain disposed on either side, forms the access transistor of a DRAM memory cell. Figure 18 As shown, gate electrode 52 is exemplified as the gate electrode of an embedded gate transistor.

[0072] The capacitor portion 60 has an insulating film 62, a capacitor 64, and a plate electrode 72. The capacitor 64 is formed within a hole disposed in the insulating film 62, and each capacitor has a capacitive insulating film 66, an upper electrode 68, and a lower electrode 70. The upper electrode 68 and the capacitive insulating film 66 are stacked and generally have an inverted cup shape, while the lower electrode 70 is provided to fill the interior of the cup shape. The lower end of the lower electrode 70 contacts a plug 57 at a contact portion 58. The upper electrode 68 contacts the plate electrode 72.

[0073] By fabricating separately formed transistor portion 50 and capacitor portion 60, rotating and inverting either transistor portion 50 or capacitor portion 60, and bringing the surfaces of transistor portion 50 and capacitor portion 60 into contact to connect them to each other through hybrid bonding, a semiconductor device 2A is formed. The fourth to sixth embodiments described below relate to connecting the plug 57 of transistor portion 50 to capacitor 64 of capacitor portion 60.

[0074] The fourth to sixth embodiments described below focus particularly on the connection between plug 57 and capacitor 64, and are described using diagrams showing portions corresponding to the connection between plug 57 and capacitor 64 in transistor portion 50 and capacitor portion 60. In the following description, plug 167 corresponds to plug 57, and capacitors 234, 244, and 254 correspond to capacitor 64.

[0075] The semiconductor device 2B according to the fourth embodiment and its formation method will be described with reference to pp. 19 to 22. The semiconductor device 2B is formed as follows. First, the capacitor portion 230 will be described. Figure 19 As shown, an insulating film 232 is formed on the plate electrode 231, and a hole 233 is formed in the insulating film 232. The plate electrode 231 corresponds to Figure 18 The plate electrode 72 is shown. Note that the hole 233 is circular in the plan view.

[0076] For example, plate electrode 231 comprises a conductive material such as tungsten nitride or tungsten. For example, tungsten nitride or tungsten is deposited via CVD. Photolithography and dry etching are performed to pattern the tungsten nitride or tungsten, thereby forming plate electrode 231.

[0077] For example, the insulating film 232 contains an insulating material such as silicon dioxide. Holes 233 are formed by performing photolithography and anisotropic dry etching on the insulating film 232. Holes 233 penetrate from the top surface of the insulating film 232 to the top surface of the plate electrode 231.

[0078] An upper electrode 235 is formed in a cup shape along the inner wall of the hole 233. Furthermore, as... Figure 19 As shown, the upper electrode 235 has a U-shaped cross-section. For example, the upper electrode 235 comprises a conductive film such as titanium nitride. The upper electrode 235 is formed, for example, by CVD deposition followed by etching back. At this time, etching back is performed such that the upper end of the upper electrode 235 is recessed downward from the top surface of the insulating film 232.

[0079] Next, following the shape of the upper electrode 235 formed on the inner wall of the hole 233, a capacitive insulating film 236 is formed inside the hole 233. At this time, the thicknesses of the upper electrode 235 and the capacitive insulating film 236 are set such that the internal space in the hole 233 is not completely filled by the upper electrode 235 and the capacitive insulating film 236. The capacitive insulating film 236 comprises a high-k insulating material with a high relative permittivity and includes metal oxide materials such as HfO2, ZrO2, or Al2O3.

[0080] The capacitive insulating film 236 is formed, for example, by CVD deposition followed by etching back. The capacitive insulating film 236 has a shoulder 236a formed along the upper portion of the upper electrode 235. With this arrangement, the capacitive insulating film 236 has a cup shape, its upper portion slightly widened by the shoulder 236a. The upper end of the capacitive insulating film 236 is substantially aligned with the top surface of the insulating film 232.

[0081] Next, a first lower electrode 237 is inserted into the central portion of the hole 233. The first lower electrode 237 comprises silicon (Si). The plug-shaped first lower electrode 237 is formed by depositing silicon via CVD and then etching back the silicon until the top surface of the silicon is substantially aligned with the shoulder 236a. A recessed portion 237a is formed above the first lower electrode 237, recessed from the top surface of the insulating film 232.

[0082] Next, as Figure 20 As shown, a metal portion 238 is formed in the recessed portion 237a. The metal portion 238 is a metal and contains ruthenium. The metal portion 238 is formed by CVD deposition of ruthenium to fill the recessed portion 237a and then etching back the ruthenium. The metal portion 238 and the first lower electrode 237 are in contact with each other. Through the above steps, a capacitor portion 230 is formed.

[0083] Next, as Figure 21As shown, capacitor portion 230 is stacked onto plug portion 160. Plug portion 160 and capacitor portion 230 are joined together by a hybrid engagement. Figure 21 The capacitor section 230 in the middle is relative to Figure 20 The capacitor portion 230 is shown in an inverted state. In the plug portion 160, the capacitive contact 161 corresponds to... Figure 18 The capacitive contact 54 in the middle, and the plug 167 corresponds to Figure 18 Plug 57 in the middle.

[0084] A contact hole 164 leading to the capacitive contact 161 is formed by performing photolithography and anisotropic dry etching on the insulating film 162, and then the contact hole 164 is filled with barrier metal 165 and metal 166 to form a plug portion 160. For example, the capacitive contact 161 contains tungsten. For example, the insulating film 162 contains silicon dioxide. For example, the barrier metal 165 contains titanium nitride, and for example, the metal 166 contains tungsten.

[0085] The plug portion 160 and the capacitor portion 230 contact each other at the mating surface G and are joined together by a hybrid engagement. At the mating surface G, the insulating film 162 and the insulating film 232 face each other and are in contact. The metal portion 238 and the metal 166 face each other but are not in contact, and a gap 169 is formed between them.

[0086] Next, through annealing, the first lower electrode 237 of capacitor 234 reacts with the metal portion 238 to form a metal silicide portion 239 containing ruthenium silicide, as shown below. Figure 22 As shown, ruthenium reacts with silicon, and the material expands in volume when ruthenium silicide is formed. For this reason, the resulting ruthenium silicide fills the gap 169 to contact the plug 167, thereby allowing the first lower electrode 237 of the capacitor 234 and the plug 167 to contact each other using the metal silicide portion 239 therebetween and forming an electrical connection.

[0087] Through the above steps, a semiconductor device 2B according to the fourth embodiment is formed. A metal silicide portion 239 containing ruthenium silicide is inserted between the plate electrode 231 and the capacitive contact 161, and connects the plate electrode 231 and the capacitive contact 161. Ruthenium silicide is contained in at least a portion of the material between the plate electrode 231 and the capacitive contact 161.

[0088] Next, the semiconductor device 2C and its method of formation according to the fifth embodiment will be described with reference to 23 to 25.

[0089] First, the capacitor section 240 will be described. For example... Figure 23As shown, the capacitor portion 240 differs from the capacitor portion 230 according to the fourth embodiment in that a second lower electrode 247 is formed instead of a first lower electrode 237, and a silicon portion 248 is formed instead of a metal portion 238. The second lower electrode 247 comprises a metal, and for example, ruthenium. The silicon portion 248 comprises silicon. The plug-shaped second lower electrode 247 is formed by CVD deposition of ruthenium followed by ruthenium etching back.

[0090] The silicon portion 248 is formed by CVD deposition of silicon followed by etching back. The silicon portion 248 and the second lower electrode 247 are in contact with each other. Through the above steps, the capacitor portion 240 is formed. The remaining configuration is similar to that of the capacitor portion 230 according to the fourth embodiment.

[0091] Next, as Figure 24 As shown, capacitor portion 240 is stacked onto plug portion 160. Plug portion 160 and capacitor portion 240 are joined together by a hybrid engagement. Figure 24 The capacitor section 240 in the middle is relative to Figure 23 The capacitor portion 240 shown is in an inverted state. The plug portion 160 has a similar configuration to the plug portion 160 in the fourth embodiment.

[0092] The plug portion 160 and the capacitor portion 240 are in contact with each other at the bonding surface H and are bonded together by a hybrid bonding. At the bonding surface H, the silicon portion 248 and the metal 166 face each other but are not in contact, and a gap 169 is formed between them.

[0093] Next, through annealing, the second lower electrode 247 of capacitor 244 reacts with the silicon portion 248 to form a metal silicide portion 249 containing ruthenium silicide, as shown below. Figure 25 As shown. Ruthenium reacts with silicon, and the material expands in volume when ruthenium silicide is formed. For this reason, the resulting ruthenium silicide fills the gap 169 to contact the plug 167, thereby allowing the second lower electrode 247 of the capacitor 244 and the plug 167 to contact each other using the metal silicide portion 249 therebetween and forming an electrical connection.

[0094] Through the above steps, a semiconductor device 2C according to the fifth embodiment is formed. A metal silicide portion 249 containing ruthenium silicide is inserted between the plate electrode 231 and the capacitive contact 161, and connects the plate electrode 231 and the capacitive contact 161. Ruthenium silicide is contained in at least a portion of the material between the plate electrode 231 and the capacitive contact 161.

[0095] Next, the semiconductor device 2D and its formation method according to the sixth embodiment will be described with reference to 26 and 27.

[0096] In a sixth embodiment, the semiconductor device 2D includes a plug portion 170 and a capacitor portion 250. The plug portion 170 and the capacitor portion 250 are stacked and bonded together by hybrid bonding to form the semiconductor device 2D.

[0097] The plug portion 170 according to the sixth embodiment differs from the plug portion 160 according to the fifth embodiment in that a silicon portion 176 containing silicon is formed instead of a metal 166 containing ruthenium. The remaining configuration is the same as that of the plug portion 160 according to the fifth embodiment. The silicon portion 176 is formed by CVD deposition of silicon followed by silicon etching back.

[0098] Furthermore, the capacitor portion 250 according to the sixth embodiment differs from the capacitor portion 240 according to the fifth embodiment in that a ruthenium-containing metal portion 257 is provided, instead of a second lower electrode 247 and a silicon portion 248 disposed in the capacitor portion 240. The remaining configuration is the same as that of the capacitor portion 240 according to the fifth embodiment. The metal portion 257 is formed by CVD deposition of ruthenium followed by ruthenium etching back.

[0099] like Figure 26 As shown, the plug portion 170 and the capacitor portion 250 contact each other at the mating surface I and are joined together by a hybrid bonding process. At the mating surface I, the metal portion 257 and the silicon portion 176 face each other but do not contact each other, and a gap is formed between the bottom surface 258 of the metal portion 257 and the top surface 178 of the silicon portion 176. It should be noted that the size of this gap is set such that the metal portion 257 and the silicon portion 176 can contact each other through the expansion of the metal portion 257.

[0100] Next, through annealing, the metal portion 257 of capacitor 254 and the silicon portion 176 of plug portion 170 react to form a metal silicide portion 259 containing ruthenium silicide, as shown below. Figure 27 As shown. It should be noted that ruthenium has a higher coefficient of thermal expansion than silicon. The temperature rise caused by annealing causes the ruthenium contained in the metal portion 257 to expand, thereby bringing the metal portion 257 into contact with the silicon portion 176 and generating a silicide reaction between the ruthenium and silicon.

[0101] As ruthenium silicide forms, ruthenium reacts with silicon and expands, increasing the volume of the material. For this reason, the resulting metal silicide portion 259 fills the gap and bonds with the plug 177. Through this arrangement, the metal portion 257 of the capacitor 254 and the plug 177 contact each other using the metal silicide portion 259 therebetween, forming an electrical connection.

[0102] Through the above steps, a semiconductor device 2D according to the sixth embodiment is formed. A metal silicide portion 259 containing ruthenium silicide is disposed between the plug 177 and the capacitor 254. Ruthenium silicide is contained in at least a portion of the material between the plate electrode 231 and the capacitive contact 161.

[0103] (Seventh and Eighth Embodiments)

[0104] Next, we will refer to Figures 28 to 33 The semiconductor device 500 using the seventh and eighth embodiments is described. In the following description, DRAM is given as an example of the semiconductor device 500.

[0105] Figure 28 This is a schematic plan view showing the configuration of one end of a memory cell region in a DRAM. Note that the other end of the memory cell region has a... Figure 28 The layout shown is a linearly symmetrical configuration. Figures 29 to 33 The configuration described in [the document] also applies to [other applications]. Figures 29 to 33 The configuration shown is linearly symmetrical at the other end.

[0106] Figure 28 Examples of planar layouts of semiconductor device 3A according to the seventh embodiment and semiconductor device 3B according to the eighth embodiment, described later, are shown. Figure 28 As shown, the semiconductor device 500 has a memory cell portion R and a peripheral circuit portion S. In the peripheral circuit portion S, a silicon deep trench 501 is provided along the boundary with the memory cell portion R. The silicon deep trench 501 is provided to prevent crystal defects in the silicon.

[0107] In the memory cell section R, multiple word lines 504 and multiple digital lines 506 are arranged orthogonally with equal spacing. Memory cell 502, forming a DRAM memory cell, is located at the intersection between the word lines 504 and the digital lines 506. Memory cell 502 is demarcated by isolators 524.

[0108] The vertical direction of memory cell 502 is tilted at a predetermined angle relative to digital line 506. Each word line 504 serves as the gate electrode of the access transistor of the memory cell within memory cell 502. Digital line 506 is connected to the central portion of memory cell 502 via digital line contact K. In each memory cell 502, capacitive contact M is disposed on the opposite side of word line 504 relative to digital line contact K. The lower electrode of a capacitor (not shown), which will be described later, is connected to each capacitive contact M.

[0109] Digital lines 506 are led out from the peripheral circuit section S, and a contact 508 is provided on every other digital line 506, electrically connected to one of the digital lines 506. The portion of the digital line 506 near the contact 508 is a ruthenium silicide portion 510. The ruthenium silicide portion 510 is connected to the digital line 506.

[0110] A ruthenium silicide portion 510 is inserted between the digital line 506 and the contact 508. The ruthenium silicide portion 510 serves as part of the digital lines of the semiconductor device 3A. These digital lines 506 and the ruthenium silicide portion 510 are disposed on the isolator 522 in the peripheral circuit section S.

[0111] Next, we will refer to Figures 29 to 31 The semiconductor device 3A and its formation method according to the seventh embodiment will be described. Figures 29 to 31 It is along Figure 28 The diagram shows a longitudinal section of line JJ and is an example of a schematic configuration in an exemplary process stage of semiconductor device 3A.

[0112] like Figure 29 As shown, isolation members 522 and 524 are formed on a semiconductor substrate 520. A silicon deep trench 501 and a memory cell 502 are demarcated by isolation members 522 and 524. The semiconductor substrate 520 comprises monocrystalline silicon. For example, isolation members 522 and 524 comprise an insulating material such as silicon dioxide. Isolation members 522 and 524 are formed by forming trenches in the semiconductor substrate 520, forming silicon dioxide via CVD, and then planarizing the surface via chemical mechanical polishing (CMP) to, for example, embed silicon dioxide into the trenches.

[0113] Furthermore, word lines 504 are formed by forming grooves in memory cells 502 and embedding gate insulating film 528, gate conductive material 530, and insulating portions 532 into the grooves. The gate insulating film 528 comprises a SiO film or a SiON film. For example, the gate conductive material 530 provided in each word line 504 comprises a conductive material such as polysilicon, titanium nitride, or tungsten. For example, the insulating portion 532 comprises an insulating material such as silicon nitride. The gate insulating film 528, gate conductive material 530, and insulating portion 532 are embedded in the grooves formed in the memory cells 502 via CVD deposition followed by etching back.

[0114] Furthermore, a digital line contact K is formed in the central portion of the memory cell 502, and a digital line 506 with a multilayer structure comprising a barrier metal 536 and a conductive material 538 is formed. For example, the digital line contact K comprises polysilicon. For example, the polysilicon is embedded in the contact hole via CVD deposition followed by etching back.

[0115] For example, the barrier metal 536 comprises titanium nitride. For example, the conductive material 538 comprises ruthenium. Additionally, an interlayer insulating film 540 is formed to cover the barrier metal 536 and the conductive material 538. The interlayer insulating film 540 may also have a multilayer structure comprising multiple insulating films. The barrier metal 536 and the conductive material 538 are deposited via physical vapor deposition (PVD) and then patterned by performing photolithography and anisotropic dry etching.

[0116] For example, the interlayer insulating film 540 comprises silicon dioxide and is deposited via CVD. Next, a contact hole 542 is formed extending from the top surface of the interlayer insulating film 540 to the surface of the digital line 506. In the contact hole 542, the top surface of the conductive material 538 of the digital line 506 is exposed, or in other words, the top surface of ruthenium is exposed.

[0117] Next, as Figure 30 As shown, semiconductor device 3A is placed in a reaction chamber (not shown), dichlorosilane is introduced into the reaction chamber, and the temperature is set to approximately 500 degrees Celsius or higher, or approximately 550 degrees Celsius or higher. For example, nitrogen (N2) is used as the carrier gas for the dichlorosilane. With this arrangement, the dichlorosilane acts on ruthenium contained in the conductive material 538 exposed in the contact hole 542, transforming the conductive material 538 into ruthenium silicide and forming a ruthenium silicide portion 544. It should be noted that in the silicide formation of ruthenium, a gas containing silane, disilane, monochlorosilane, trichlorosilane, or some other type of silicon can be used instead of dichlorosilane.

[0118] Next, as Figure 31 As shown, conductive material is embedded in contact hole 542 to form contact 508. For example, contact 508 contains a conductive material such as tungsten. For example, contact 508 is formed by CVD deposition of tungsten followed by etch-back of the tungsten. Through the above steps, semiconductor device 3A is formed.

[0119] Based on the semiconductor device 3A according to the seventh embodiment, the digital line 506 is connected to a ruthenium silicide portion 544. The ruthenium silicide portion 544 is inserted between the contact 508 and the digital line 506. By causing the ruthenium exposed in the contact hole 542 to be converted to ruthenium silicide in advance, the accumulation of ruthenium during the heat treatment performed after the formation of the contact hole 542 can be avoided, thereby preventing gaps and discontinuities from forming in the digital line 506.

[0120] Next, we will refer to Figure 29 , 32 The semiconductor device 3B and its method of formation according to the eighth embodiment are described in sections 3 and 33. Figure 29 , 32 The floor plan configuration is similar to that of 33. Figure 28 The layout shown. Figure 29 , 32 And 33 is along Figure 28 The diagram shows a longitudinal section of line JJ and is an example of a schematic configuration in an exemplary process stage of semiconductor device 3B.

[0121] First, the execution is performed according to the seventh embodiment in Figure 29 The steps performed are similar to those in the process.

[0122] Next, as Figure 32 As shown, annealing is performed, for example, by rapid thermal annealing (RTA). Ruthenium accumulates in the exposed portion 506a of the digital line 506 exposed in the contact hole 542, and a gap 550 is formed near the exposed portion 506a. The stress generated by the accumulation of the ruthenium-containing conductive material 538 causes the gap 550 to form even in the blocking metal 536. Therefore, a discontinuity appears in the digital line 506 at the gap 550. In the contact hole 542, the top surface of the conductive material 538 exposing the digital line 506, or in other words, the top surface exposing the ruthenium.

[0123] Next, as Figure 33 As shown, semiconductor device 3B is placed in a reaction chamber (not shown), dichlorosilane is introduced into the reaction chamber, and the temperature is set to approximately 500 degrees Celsius or higher, or approximately 550 degrees Celsius or higher. For example, nitrogen is used as the carrier gas for the dichlorosilane. With this arrangement, the dichlorosilane acts on ruthenium contained in the conductive material 538 exposed in the contact hole 542, causing the conductive material 538 to transform into ruthenium silicide and forming ruthenium silicide portions 544. Because the conductive material 538 expands as it transforms into ruthenium silicide and its volume increases, the gap 550 is filled with ruthenium silicide, and discontinuities in the digital lines 506 are reconnected. It should be noted that in the silicide formation of ruthenium, a gas containing silane, disilane, monochlorosilane, trichlorosilane, or some other type of silicon can be used instead of dichlorosilane.

[0124] Next, a conductive material is embedded in the contact hole 542 to form a contact 508. For example, the contact 508 contains a conductive material such as tungsten. Through the above steps, a semiconductor device 3B is formed. The semiconductor device 3B according to the eighth embodiment has a configuration substantially similar to that of the semiconductor device 3A according to the seventh embodiment.

[0125] Based on the semiconductor device 3B according to the eighth embodiment, effects similar to those of the seventh embodiment are obtained. Furthermore, even if a discontinuity occurs in the digital line 506 due to a gap 550 formed near the exposed portion 506a of the digital line 506 exposed in the contact hole 542, the discontinuity can be reconnected using a relatively simple process.

[0126] As described above, DRAM is presented as an example of a semiconductor device according to various embodiments, but the above description is merely an example and is not intended to limit the application to DRAM. For example, memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase-change memory, can also be used as semiconductor devices. Furthermore, for example, devices other than memory, logic ICs including, for example, microprocessors and application-specific integrated circuits (ASICs), are also suitable as semiconductor devices according to the foregoing embodiments.

[0127] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments can be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined or substituted with each other to form variations of the invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A method for forming a multilayer conductive structure, comprising: Forming the first conductive portion; A second conductive portion containing ruthenium (Ru) is formed on the first conductive portion; A third conductive portion is formed on the second conductive portion; A gap is provided between the second conductive portion and the third conductive portion; A silicide process is performed on the second conductive portion; as well as The gap is filled by expanding the ruthenium silicide formed during the silicide process.

2. The method according to claim 1, further comprising: A silicon portion is formed that contacts the ruthenium in the second conductive portion.

3. The method according to claim 1, further comprising: The second conductive portion and the third conductive portion are connected by filling the gap with ruthenium silicide formed during the silicide process.

4. The method of claim 1, further comprising: During the siliconization process, heat treatment is performed at a temperature of approximately 400 degrees Celsius or higher.

5. The method according to claim 1, The siliconization process involves introducing a silicon-containing gas and performing heat treatment at a temperature of about 500 degrees Celsius or higher.

6. The method according to claim 1, The silanization process involves introducing dichlorosilane gas and performing heat treatment at a temperature of about 500 degrees Celsius or higher.

7. A method for forming a multilayer conductive structure, comprising: Forming the first conductive portion; A second conductive portion containing ruthenium (Ru) is formed on the first conductive portion; A third conductive portion is formed on the second conductive portion; A silicon portion is formed in the third conductive portion; A gap is provided between the second conductive portion and the silicon portion in the third conductive portion; A silicide process is performed on the second conductive portion; as well as The gap is filled by expanding the ruthenium silicide formed during the silicide process.

8. The method of claim 7, further comprising: During the siliconization process, heat treatment is performed at a temperature of approximately 400 degrees Celsius or higher.

9. A method of forming a semiconductor device, comprising: This forms the first conductive portion containing ruthenium (Ru); An insulating film is formed covering the first conductive portion; Forming a contact hole that exposes a portion of the first conductive portion; A gap is formed in the first conductive portion near the contact hole; The first conductive portion is siliconized through the contact hole; as well as The gap is filled by expanding the ruthenium silicide formed during the silicide process.

10. The method according to claim 9, The siliconization process involves introducing a silicon-containing gas.

11. The method according to claim 9, The silanization process involves the introduction of dichlorosilane gas.

12. The method according to claim 9, The siliconization process involves performing heat treatment at a temperature of about 500 degrees Celsius or higher.

13. The method according to claim 9, The gap is formed by annealing performed after the contact hole is formed.

14. A semiconductor device comprising: The first part contains conductive material; The second part contains conductive material; as well as The third part between the first part and the second part The third portion comprises ruthenium silicide, which is formed by depositing ruthenium and then at least partially silicideting the ruthenium therein. The third part includes a first portion and a second portion disposed on the first portion, wherein the first lateral width of the first portion is greater than the second lateral width of the second portion.

15. The semiconductor device according to claim 14, The entire third part contains ruthenium silicide.

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