Methods of forming semiconductor structures, structures, and memories

Abstract

The application discloses a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having an array region and a peripheral region; forming a protective layer on the surface of the array region and a first polysilicon layer on the surface of the peripheral region; opening a contact hole in the array region, the contact hole penetrating through the protective layer and extending to the inside of the substrate; forming a second polysilicon layer within the range limited by the contact hole, and forming a bit line contact structure on the second polysilicon layer. The method can reduce the parasitic capacitance by reducing the height of the bit line contact structure and then reducing the area of the bit line contact structure.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor integrated circuits, and more particularly to a method for forming a semiconductor structure, the structure, and a memory. Background Technology

[0002] In semiconductor devices, dielectric material is formed between conductive structures. As semiconductor devices become highly integrated, the distance between conductive structures gradually decreases, which increases the generation of parasitic capacitance. As parasitic capacitance increases, the performance of semiconductor devices degrades.

[0003] One possible way to reduce the parasitic capacitance of highly integrated semiconductor devices is to choose dielectric materials with lower dielectric constants. However, for other reasons, the dielectric materials used in the manufacture of highly integrated semiconductor devices have relatively high dielectric constants, thus limiting the reduction of parasitic capacitance. Summary of the Invention

[0004] The purpose of this application is to provide a method for forming a semiconductor structure, the structure itself, and a memory that can reduce parasitic capacitance.

[0005] The first aspect of this application provides a method for forming a semiconductor structure, characterized in that it includes:

[0006] A substrate is provided, the substrate having an array region and a peripheral region;

[0007] A protective layer is formed on the surface of the array region, and a first polysilicon layer is formed on the surface of the peripheral region;

[0008] Contact holes are formed in the array region, and the contact holes penetrate the protective layer and extend into the interior of the substrate;

[0009] A second polysilicon layer is formed within the formed contact hole, and a bit line contact structure is formed on the second polysilicon layer.

[0010] In some optional embodiments of this application, forming a protective layer on the surface of the array region and forming a first polysilicon layer on the surface of the peripheral region includes:

[0011] A protective layer is formed on the surface of the array region, and a first polysilicon layer is formed on the protective layer and the surface of the peripheral region.

[0012] A first oxide layer is coated on the first polysilicon layer in the array region and the peripheral region;

[0013] A first photoresist layer is formed on the first oxide layer in the peripheral region, and the first oxide layer and the first polysilicon layer on the surface of the array region are removed.

[0014] Remove the first oxide layer and the first photoresist layer located on the first polysilicon layer in the peripheral region.

[0015] In some optional embodiments of this application, a contact hole is formed in the array region, the contact hole penetrating the protective layer and extending into the substrate, including:

[0016] A second oxide layer is formed on the protective layer and the first polysilicon layer, and a mask layer defining the location of the contact holes is formed on the second oxide layer of the array region.

[0017] The second oxide layer and protective layer are etched to form contact holes extending into the substrate;

[0018] After the contact hole is formed, the mask layer located on the second oxide layer is removed.

[0019] In some alternative embodiments of this application, forming a second polysilicon layer within the formed contact hole includes:

[0020] A second polysilicon layer is filled into the contact hole and extends to the top surface covering the second oxide layer;

[0021] Remove the second polysilicon layer located on the second oxide layer, and retain the second polysilicon layer located inside the contact hole.

[0022] In some optional embodiments of this application, the method further includes the following steps before forming the bit line contact structure on the second polysilicon layer:

[0023] Remove the protective layer and the second oxide layer on the surface of the first polysilicon layer.

[0024] In some optional embodiments of this application, forming a bit line contact structure on the second polysilicon layer includes:

[0025] A conductive layer is covered on the protective layer and the second polysilicon layer, so that the conductive layer covers the protective layer and the second polysilicon layer.

[0026] An insulating layer is placed over the conductive layer;

[0027] The insulating layer, the conductive layer, and the second polysilicon layer located on the sidewall of the contact hole are etched to form a bit line contact structure with a gap and equal width to the sidewall of the contact hole.

[0028] In some optional embodiments of this application, forming a protective layer on the surface of the array region and forming a first polysilicon layer on the surface of the peripheral region includes:

[0029] A protective layer and a first polysilicon layer are stacked on the surface of the array region, and a first polysilicon layer is formed on the surface of the peripheral region.

[0030] A first oxide layer is covered on the first polysilicon layer above the array region and the peripheral region, and a first photoresist layer is formed on the surface of the first oxide layer in the peripheral region.

[0031] Remove the first oxide layer from the area not covered by the first photoresist layer;

[0032] The first photoresist layer located on the peripheral area is removed using the first process;

[0033] The first polysilicon layer on the protective layer is removed using a second process.

[0034] In some optional embodiments of this application, removing the first photoresist layer located on the peripheral region using a first process includes,

[0035] The first photoresist layer located on the peripheral area is removed by cleaning with the first cleaning solution;

[0036] Remove the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region during cleaning with the first cleaning solution until the first polysilicon layer is exposed.

[0037] In some optional embodiments of this application, removing the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region during cleaning with the first cleaning solution to expose the first polysilicon layer includes,

[0038] The oxygen-containing silica layer is oxidized with ozone to form silica, and the silica is removed by a second cleaning solution.

[0039] In some alternative embodiments of this application, removing the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region by SPM cleaning to expose the first polysilicon layer includes:

[0040] The oxygen-containing silicide layer was etched using a chemical dry etching method, with a flow rate of 3600 sccm for N2, a flow rate ratio of 8 sccm:300 sccm for H2 and NF3, and an etching power of 200 W.

[0041] In some optional embodiments of this application, the temperature is maintained at or above 100°C when chemically dry etching the oxygen-containing silicide layer.

[0042] In some alternative embodiments of this application, removing the first polysilicon layer on the protective layer using a second process includes,

[0043] The first polysilicon layer on the protective layer is chemically removed using a third cleaning solution until the protective layer is exposed.

[0044] In some optional embodiments of this application, the first cleaning solution is an SPM solution.

[0045] In some optional embodiments of this application, the second cleaning solution is a mixture of HF, H2O2 and H2O.

[0046] In some optional embodiments of this application, the third cleaning solution is a mixture of NH4OH and H2O.

[0047] According to a second aspect of the embodiments of this application, a semiconductor structure is provided, comprising manufacturing using the method for forming the semiconductor structure described above.

[0048] According to a third aspect of the embodiments of this application, a memory is provided, including the aforementioned semiconductor structure.

[0049] The method described in this application has at least the following advantages:

[0050] When forming the bit line contact structure, a protective layer is formed on the array region of the substrate, and a first polysilicon layer is formed on the peripheral region. The protective layer of the array region and the substrate located below the protective layer are etched to form a contact hole that penetrates the protective layer and extends into the interior of the substrate. After the contact hole is formed, a second polysilicon layer is filled into the bottom and sidewalls of the contact hole. The filling of the second polysilicon layer is based on the range limited by the contact hole, thereby reducing the height of the second polysilicon layer in the contact hole. At the same time, the bit line contact structure continues to be formed on the second polysilicon layer. Therefore, the overall height of the bit line contact structure and the second polysilicon layer can be reduced. According to the capacitance calculation formula, when the dielectric constant of the material and the electrode spacing are constant, the capacitance value can be reduced by reducing the area of ​​the electrode. Therefore, by reducing the height of the bit line contact structure, and thus reducing its area, the purpose of reducing parasitic capacitance can be achieved. Attached Figure Description

[0051] Figures 1-12 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure in the specific embodiments of this application;

[0052] Figures 13-18 This is a schematic diagram of the main process cross-sections in other embodiments of this application during the formation of the array region covered with a protective layer and the peripheral region with a first polysilicon layer.

[0053] Figure label:

[0054] 1. Substrate; 11. Protective layer; 12. First polysilicon layer; 121. First oxide layer; 13. Deep trench; 2. Isolation region; 3. First photoresist layer; 4. Second oxide layer; 5. Mask layer; 6. Contact window; 7. Contact hole; 8. Second polysilicon layer; 91. Conductive layer; 92. Insulating layer; 101. Bit line; 102. Bit line hard mask; 103. Bit line contact plug; 104. Gap; 201. Oxygen-containing silicide layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application.

[0056] As is known from the background art, semiconductor devices in related technologies are highly integrated, and the distance between conductive structures gradually decreases, leading to a need to reduce the parasitic capacitance of the semiconductor structure. Research has shown that, under the condition of a fixed electrode spacing, improving the electrode area can effectively reduce parasitic capacitance. Therefore, this application provides a method for forming a semiconductor structure, a structure, and a memory.

[0057] Figures 1-12 This is a schematic diagram of the main process cross-sections during the formation of the semiconductor structure in the specific embodiments of this application;

[0058] like Figure 1 As shown in the embodiments of this application, a method for forming a semiconductor structure is provided, which may include:

[0059] S110: Provides substrate 1;

[0060] S120: A protective layer 11 is formed on the surface of the array region, and a first polysilicon layer 121 is formed on the surface of the peripheral region;

[0061] S130: A contact hole 6 is formed in the array region, the contact hole 6 penetrating the protective layer 11 and extending into the interior of the substrate 1;

[0062] S140: A second polysilicon layer 8 is formed within the formed contact hole 6, and a bit line contact structure is formed on the second polysilicon layer 8.

[0063] In this embodiment, the second polysilicon layer is limited by the contact hole, thereby reducing the height of the second polysilicon layer within the contact hole. At the same time, bit line contact structures are formed on the second polysilicon layer, thus reducing the overall height of the bit line contact structures and the second polysilicon layer. According to the capacitance calculation formula, given a fixed dielectric constant of the material and a fixed electrode spacing, the capacitance value can be reduced by reducing the electrode area. Therefore, by reducing the height of the bit line contact structure, its area can be reduced, thereby reducing parasitic capacitance.

[0064] To illustrate this more clearly, the steps described above will be explained separately below:

[0065] The first step is S110: providing substrate 1.

[0066] In this step, the substrate 1 has an array region AA and a peripheral region BB. Multiple deep trenches 13 are formed on the surface region AA of the substrate 1. Isolation material is filled within the deep trenches 13 to form isolation regions 2. These isolation regions 2 isolate several active regions 14 from the substrate 1. The isolation regions 2 can isolate several active regions 14 in an array or other distribution type from the substrate 1. The active regions 14 can be formed by implanting impurities into the substrate 1, for example, by an ion implantation process.

[0067] In one example, the insulating material may include silicon oxide, silicon nitride, tetraethyl silicate, or borosilicate glass, etc.

[0068] In this embodiment, the semiconductor structure can be a memory. The substrate 1 has structures such as bit lines, word lines and capacitive contact windows. The peripheral region BB is located around the array region AA. The peripheral region BB is used to realize the electrical connection between the input and output circuits of the memory and other electrical components. The array region AA is used to realize the electrical connection between different conductive structures in the memory.

[0069] Substrate 1 may include a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single-crystal metal oxide substrate, etc. Optionally, substrate 1 may include a ceramic substrate or a glass substrate having a semiconductor layer thereon. In an exemplary embodiment, substrate 1 may include a silicon-containing substrate, such as a silicon substrate, a silicon-germanium substrate, etc.

[0070] The next step is step S120: forming a protective layer 11 on the surface of the array region and forming a first polysilicon layer 12 on the surface of the peripheral region.

[0071] like Figure 1 and Figure 2 As shown, forming a protective layer 11 on the surface of the array region AA and forming a first polysilicon layer 12 on the surface of the peripheral region BB may specifically include: covering the array region AA of the substrate 1 with a protective layer 11, which may be formed on the substrate 1 using oxides, nitrides, oxynitrides, etc.

[0072] In one example, the protective layer 11 may include silicon oxide, silicon nitride, silicon oxynitride, etc. A first polysilicon layer 12 is deposited on the protective layer 11 of the array region AA and the peripheral region BB.

[0073] like Figure 2 As shown, a first oxide layer 121 is covered on the first polysilicon layer 12 located above the array region AA and the peripheral region BB. The thickness of the first oxide layer 121 is controlled between 15 and 30 nm.

[0074] like Figure 3 and Figure 4 As shown, a first patterned first photoresist layer 3 is coated on the surface region of the first oxide layer 121 in the peripheral region BB. The first patterned first photoresist layer 3 is photoresist after mask exposure and development. The first etching is performed to remove the first oxide layer 121 in the area not covered by the first patterned first photoresist layer 3 and the first polysilicon layer 12 located below the first oxide layer 121, forming an array region AA covered by a protective layer 11.

[0075] like Figure 4 and Figure 5 As shown, the first photoresist layer 3 is ashed to remove the first photoresist layer 3 and the first oxide layer 121 on the peripheral region BB. Specifically, the ashing process removes the first photoresist layer 3 and the first oxide layer 121 on the peripheral region BB, thus retaining the first polysilicon layer 12 on the surface of the peripheral region BB without affecting the protective layer 11 on the array region AA. The first polysilicon layer 12 on the surface of the peripheral region BB is retained for fabricating the gate of the subsequent peripheral region BB.

[0076] like Figure 4 and Figure 6 As shown, a second oxide layer 4 is covered on the protective layer 11 of the array region AA and the first polysilicon layer 12 of the peripheral region BB. It should be noted that the materials of the second oxide layer 4 and the first oxide layer 121 can be the same or different. In this embodiment, the materials of the second oxide layer 4 and the first oxide layer 121 can be the same. In other embodiments, the materials of the first oxide layer 121 and the second oxide layer 4 can be different.

[0077] The next step is step S130: a contact hole 6 is formed in the array region, the contact hole 6 penetrates the protective layer 11 and extends into the interior of the substrate 1.

[0078] In this step, a mask layer 5 is formed on the second oxide layer 4 on the array region AA and the peripheral region BB. The mask layer 5 on the array region AA is used to define the position of the contact hole. The second oxide layer 4 of the array region AA is etched to form a contact window 6. The contact window 6 penetrates through the second oxide layer 4 to the bottom exposed protective layer 11. The sidewalls of the contact window 6 are vertically arranged, that is, the contact windows 6 are set with equal width.

[0079] like Figure 6 and Figure 7 As shown, the mask layer 5 located on the array region AA and the peripheral region BB is removed, so that the second oxide layer 4 with contact window 6 is exposed on the array region AA, and the second oxide layer 4 with planarization treatment is exposed on the peripheral region BB.

[0080] like Figure 1 and Figure 7 As shown, the protective layer 11 at the bottom of the contact window 6 is etched a second time to expose the active region 14 and the isolation region 2 located in the substrate 1. The active region 14 and the isolation region 2 at the bottom of the contact window 6 are etched simultaneously to form an inverted trapezoidal contact hole 7. Specifically, the density of the isolation material on the sidewall of the contact hole 7 gradually decreases in the direction from the substrate 1 to the protective layer 11, so that the etching rate of the isolation material in subsequent etching processes gradually increases. A third etching is performed to etch the isolation material on the sidewall of the contact hole 7 to form the contact hole 7. The opening size of the contact hole 7 gradually increases in the direction from the substrate 1 to the protective layer 11. Since the etching rate of the isolation material gradually increases in the direction from the substrate 1 to the protective layer 11, the width of the isolation material removed by the third etching gradually decreases from the top to the bottom of the contact hole 7 to form a contact hole 7 with an inverted trapezoidal shape.

[0081] In this embodiment, the third etching is performed using wet etching. Since the density of the isolation material on the sidewall of the contact hole 7 gradually decreases in the direction from the substrate 1 to the isolation material, the wet etching process can be used to achieve the purpose of gradually increasing the opening size of the contact hole 7 in the direction from the substrate 1 to the protective layer 11 by taking advantage of the characteristic that the smaller the density of the material, the higher the etching rate.

[0082] The etching solution used in wet etching includes phosphoric acid solution or hydrofluoric acid solution. In this embodiment, the material of the isolation material is silicon nitride, so when wet etching the isolation material on the sidewall of contact hole 7, the etching solution is phosphoric acid solution; in other embodiments, the material of the isolation material can also be silicon oxide, so when wet etching the isolation material on the sidewall of contact hole 7, the etching solution is hydrofluoric acid solution.

[0083] Finally, step S140: a second polysilicon layer 8 is formed within the formed contact hole 6, and a bit line contact structure is formed on the second polysilicon layer 8.

[0084] like Figure 7 and Figure 8 As shown, this step of forming the second polysilicon layer 8 within the area limited by the contact hole 7 may specifically include the following:

[0085] The second polysilicon layer 8 fills the bottom and sidewalls of the contact holes 7 and contact windows 6, and covers the top surface area of ​​the second oxide layer 4. The coverage thickness of the filled second polysilicon layer 8 is controlled between 80 and 130 nm. The second polysilicon layer 8 fills the second oxide layer 4 in the peripheral region BB. The second polysilicon layer 8 on the array region AA and the peripheral region BB is flush, that is, the top surface of the second polysilicon layer 8 above the peripheral region BB and the top surface of the second polysilicon layer 8 above the array region AA are kept at the same horizontal plane.

[0086] like Figure 8 , Figure 9 and Figure 10 As shown, the second polysilicon layer 8 located on the peripheral region BB and the array region AA is removed, the second polysilicon layer 8 within the limit of the contact window 6 is removed, and the second polysilicon layer 8 within the limit of the contact hole 7 is retained. The second polysilicon layer 8 located in the contact hole 7 is flush with the protective layer 11. The second oxide layer 4 located on the protective layer 11 and the second oxide layer 4 on the surface of the peripheral region BB are etched using hydrofluoric acid.

[0087] like Figure 10 and Figure 11 As shown, forming a bit line contact structure on the second polysilicon layer 8 may specifically include: stacking a conductive layer 91 and an insulating layer 92 on the protective layer 11 of the array region AA. The conductive layer 91 covers the surface of the second polysilicon layer 8 on the protective layer 11 and within the contact hole 7. The conductive layer 91 and the insulating layer 92 may be sequentially stacked on the protective layer 11. The conductive layer 91 may be formed of or include a metal-containing material. The conductive layer 91 may be formed of or include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of this application, the conductive layer 91 may be formed of or include tungsten (W). According to another embodiment of this application, the conductive layer 91 may be formed of or include a stack of titanium nitride and tungsten (TiN / W). Here, titanium nitride may be used as a barrier layer. The insulating layer 92 may be formed of a dielectric material having etching selectivity relative to the conductive layer 91 and the protective layer 11. The insulating layer 92 may be formed of or comprise silicon oxide or silicon nitride. According to one embodiment of this application, the insulating layer 92 may be formed of silicon nitride.

[0088] A bitline mask layer may be formed on the insulating layer 92. The bitline mask layer may include a photoresist pattern. The bitline mask layer may be formed by a patterning method such as spaced patterning (SPT) or dual patterning (DPT). From a planar view, the bitline mask layer may have the form of lines extending in one direction.

[0089] refer to Figure 11 and12 As shown, bit line 101 and bit line contact plug 103 are formed. Bit line 101 and bit line contact plug 103 can be formed simultaneously. Bit line 101 and bit line contact plug 103 can be formed using an etching process employing a bit line mask layer. Insulating layer 92 and conductive layer 91 can be etched using the bit line mask layer as an etching barrier layer. This allows the formation of bit line 101 and bit line hard mask 102. Bit line 101 can be formed by etching conductive layer 91, and bit line hard mask 102 can be formed by etching insulating layer 92. A second polysilicon layer 8 can be etched with the same linewidth as bit line 101 to form bit line contact plug 103. Bit line contact plug 103 can be formed on active region 14. Bit line contact plug 103 can couple active region 14 to bit line 101. Bit line contact plug 103 can be formed in contact hole 7. The line width of the bit line contact plug 103 can be shorter than the diameter of the contact hole 7. Therefore, a gap 104 can be defined around the bit line contact plug 103. As described above, as the bit line contact plug 103 is formed, a gap 104 can be formed in the contact hole 7, that is, a gap is left between the formed bit line contact plug 103 and the sidewall of the contact hole 7.

[0090] The stacked structure of bitline 101 and bitline hard mask 102 in the above order can be called a "bitline structure".

[0091] By forming a protective layer on the surface of the array region and a first polysilicon layer on the surface of the peripheral region, the protective layer is free of excess first polysilicon. A second polysilicon layer is used to fill the contact holes and contact windows. When removing the second polysilicon layer, the second polysilicon layer within the contact hole's restricted area is retained, ensuring that the retained second polysilicon layer within the contact hole is flush with the protective layer. The second polysilicon layer is etched using the same linewidth as the bit line to form a bit line contact plug, thereby reducing the height of the bit line contact plug within the contact hole. Bit line contact structures are then formed on the bit line contact plug, thus reducing the overall height of the bit line contact structure. According to the capacitance calculation formula, given a fixed dielectric constant and electrode spacing, reducing the electrode area can reduce the capacitance value. Therefore, by reducing the height of the formed bit line contact structure, and consequently its area, the parasitic capacitance can be reduced.

[0092] Figures 13-18 This is a schematic diagram of the main process cross-sections in other embodiments of this application during the formation of the array region covered with a protective layer and the peripheral region with a first polysilicon layer.

[0093] like Figure 13 , 14As shown, in other embodiments, forming a protective layer 11 in the array region AA of the substrate 1 and forming a first polysilicon layer 12 in the peripheral region BB of the substrate 1 further includes the following steps:

[0094] A protective layer 11 and a first polysilicon layer 12 are stacked on the surface of the array region AA. A first polysilicon layer 12 is formed on the surface of the peripheral region BB. A first oxide layer 121 is coated on the first polysilicon layer 12 of the array region AA and the peripheral region BB. A first patterned first photoresist layer 3 is coated on the surface area of ​​the first oxide layer 121 of the peripheral region BB. The first patterned first photoresist layer 3 is a photoresist that has undergone mask exposure and development. The first oxide layer 121 on the area not covered by the first patterned first photoresist layer 3 is removed by dry etching.

[0095] like Figure 15 , 16 As shown, the first photoresist layer 3 located on the peripheral region BB is removed using a first process; more specifically, it may include removing the first photoresist layer 3 located on the peripheral region BB using a first cleaning solution, wherein the first cleaning solution mainly includes H2SO4 solution and H2O2 solution, and the temperature is controlled between 120 and 150°C. The first cleaning solution may be an SPM solution. Since the SPM solution has a high oxidation ability, a thin, incompletely oxidized oxygen-containing silicide layer 201 will be formed on the surface of the first polysilicon layer 12 in the array region AA.

[0096] Therefore, the oxygen-containing silicide layer 201 on the surface of the first polysilicon layer 12 can be removed, which may include: chemical dry etching of the oxygen-containing silicide layer 201. Chemical dry etching has excellent selectivity, and this method can avoid damage to the protective layer 11. The etching will stop after the current film is etched, without damaging the film of other materials below. The specific process parameters are: the flow rate ratio of H2 and NF3 is 8 sccm:300 sccm, the flow rate of N2 is 3600 sccm, and the power is 1200W.

[0097] This chemical dry etching process is performed at temperatures above 100 degrees Celsius. The reaction process of this chemical dry etching is as follows:

[0098] N2(g) + 3H2(g) = 2NH3(g);

[0099] NH3(g)+NF3(g)=NH4F(g)+HF(g);

[0100] NH4F(g)or NH4F.HF(g)+SiO2(s)=(NH4)2SiF6(s)+2H2O(g)

[0101] This chemical dry etching process uses H2 + N2 to generate NH3 for etching the oxygen-containing silicide layer 201. The resulting byproducts are converted into gaseous (NH4)2SiF6(s) by heating to above 100°C, and can be effectively removed. This method achieves an excellent selectivity ratio of over 100 between the oxygen-containing silicide layer and the first polysilicon layer. Therefore, the oxygen-containing silicide layer 201 located on the first polysilicon layer 12 in the array region AA can be directionally removed.

[0102] In other embodiments, a second cleaning solution can also be used to etch the oxygen-containing silicide layer 201. The second cleaning solution has a stronger oxidizing power than the first cleaning solution. The second cleaning solution can completely oxidize the oxygen-containing silicide layer 201 to form silicon dioxide. The second cleaning solution can be a DHF cleaning solution, which is mainly a mixture of HF, H2O2 and H2O. The DHF cleaning solution has a high etching rate for silicon dioxide, but an extremely low etching rate for the oxygen-containing silicide layer 201. Therefore, after the oxygen-containing silicide layer 201 is completely oxidized to form silicon dioxide, the silicon dioxide can be removed again using the DHF cleaning solution.

[0103] like Figure 16 , Figure 17 As shown, a second process is used to remove the first polysilicon layer 12 on the protective layer 11 to expose the protective layer 11;

[0104] Detailed details may include using a third cleaning solution to chemically remove the first polysilicon layer 12 on the surface of the array region AA. The third cleaning solution may be ADM cleaning solution, which is a mixture of NH4OH and H2O, specifically ADM:NH4OH:H2O = 1:40.

[0105] like Figure 18 As shown, a second cleaning solution is used to remove the first oxide layer 121 of the first polysilicon layer 12 located on the peripheral region BB.

[0106] In the above embodiment, the semiconductor structure formation method involves forming a protective layer on an array region of a substrate and a first polysilicon layer on a peripheral region during the formation of the bit line contact structure. The protective layer of the array region and the substrate below the protective layer are etched to form a contact hole that penetrates the protective layer and extends into the substrate. After the contact hole is formed, a second polysilicon layer is filled into the bottom and sidewalls of the contact hole. The filling of the second polysilicon layer is based on the area limited by the contact hole, thereby reducing the height of the second polysilicon layer within the contact hole. Simultaneously, the bit line contact structure continues to be formed on the second polysilicon layer. Therefore, the overall height of the bit line contact structure and the second polysilicon layer can be reduced. According to the capacitance calculation formula, given a fixed dielectric constant and electrode spacing, reducing the electrode area can reduce the capacitance value. Therefore, by reducing the height of the bit line contact structure and thus its area, the purpose of reducing parasitic capacitance can be achieved.

[0107] A second aspect of this application provides a semiconductor structure manufactured using a semiconductor structure formation method described in the above embodiments.

[0108] The semiconductor structure may include:

[0109] Substrate 1, wherein the substrate 1 has an array region and a peripheral region;

[0110] The surface of the array region has a protective layer 11;

[0111] The surface of the peripheral region has a first polycrystalline silicon layer 121;

[0112] The array region has a contact hole 6, which penetrates the protective layer 11 and extends into the interior of the substrate 1;

[0113] The contact hole 6 contains a second polysilicon layer 8, and the second polysilicon layer 8 has a bit line contact structure.

[0114] The bit line contact structure may include:

[0115] A conductive layer covering the protective layer and the second polysilicon layer, the conductive layer covering the protective layer and the second polysilicon layer;

[0116] An insulating layer covers the conductive layer.

[0117] In the semiconductor structure of the above embodiment, since the second polysilicon layer is limited by the contact hole, the height of the second polysilicon layer within the contact hole is reduced. Subsequently, a bit line contact structure is provided on the second polysilicon layer, which can reduce the overall height of the bit line contact structure and the second polysilicon layer. According to the capacitance calculation formula, when the dielectric constant of the material and the electrode spacing are constant, the capacitance value can be reduced by reducing the area of ​​the electrode. Therefore, by reducing the height of the bit line contact structure, its area can be reduced, thereby achieving the purpose of reducing parasitic capacitance.

[0118] The substrate material in this embodiment includes, but is not limited to, silicon or germanium crystals, silicon-on-insulator (SOI) structures or epitaxial layer structures on silicon, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium), and alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof). The protective layer material includes, but is not limited to, oxides, nitrides, or oxynitrides. In one example, the protective layer material includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0119] In a third aspect of this application, a memory is provided, including the semiconductor structure described in the above embodiments. Since the memory includes the aforementioned semiconductor structure, it also possesses the performance advantages and significant effects of the semiconductor structure. The height of the bit line contact structure of the semiconductor structure can be reduced, thereby reducing its area and ultimately reducing parasitic capacitance.

[0120] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having an array region and a peripheral region; Forming a protective layer on the surface of the array region and forming a first polysilicon layer on the surface of the peripheral region includes: forming a protective layer on the surface of the array region; forming a first polysilicon layer on the protective layer and the surface of the peripheral region; covering the first polysilicon layer in the array region and the peripheral region with a first oxide layer; forming a first photoresist layer on the first oxide layer in the peripheral region; removing the first oxide layer and the first polysilicon layer on the surface of the array region; and removing the first oxide layer and the first photoresist layer located on the first polysilicon layer in the peripheral region. Forming a contact hole in the array region, the contact hole penetrating the protective layer and extending into the substrate, includes: forming a second oxide layer covering the protective layer and the first polysilicon layer; covering the second oxide layer in the array region with a mask layer defining the location of the contact hole; etching the second oxide layer and the protective layer to form the contact hole extending into the substrate; and removing the mask layer located on the second oxide layer after the contact hole is formed. A second polysilicon layer is formed within the formed contact hole, and a bit line contact structure is formed on the second polysilicon layer.

2. The method for forming a semiconductor structure according to claim 1, wherein, Forming a second polysilicon layer within the formed contact hole includes: A second polysilicon layer is filled into the contact hole and extends to the top surface covering the second oxide layer; Remove the second polysilicon layer located on the second oxide layer, and retain the second polysilicon layer located inside the contact hole.

3. The method for forming a semiconductor structure according to claim 2, wherein, Before forming the bit line contact structure on the second polysilicon layer, the following is also included: Remove the protective layer and the second oxide layer on the surface of the first polysilicon layer.

4. The method for forming a semiconductor structure according to claim 3, wherein, Forming a bit line contact structure on the second polysilicon layer includes: A conductive layer is covered on the protective layer and the second polysilicon layer, so that the conductive layer covers the protective layer and the second polysilicon layer. An insulating layer is placed over the conductive layer; The insulating layer, the conductive layer, and the second polysilicon layer located on the sidewall of the contact hole are etched to form a bit line contact structure with a gap and equal width to the sidewall of the contact hole.

5. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having an array region and a peripheral region; Forming a protective layer on the surface of the array region and a first polysilicon layer on the surface of the peripheral region includes: stacking and forming a protective layer and a first polysilicon layer on the surface of the array region, and forming a first polysilicon layer on the surface of the peripheral region; covering the first polysilicon layer above the array region and the peripheral region with a first oxide layer, and forming a first photoresist layer on the surface of the first oxide layer in the peripheral region; removing the first oxide layer in the area not covered by the first photoresist layer; removing the first photoresist layer in the peripheral region using a first process; and removing the first polysilicon layer on the protective layer using a second process. Contact holes are formed in the array region, and the contact holes penetrate the protective layer and extend into the interior of the substrate; A second polysilicon layer is formed within the formed contact hole, and a bit line contact structure is formed on the second polysilicon layer; The removal of the first photoresist layer located on the peripheral area using the first process includes: The first photoresist layer located on the peripheral area is removed using the first cleaning solution; Remove the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region during cleaning with the first cleaning solution until the first polysilicon layer is exposed.

6. The method for forming a semiconductor structure according to claim 5, wherein, Removing the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region during cleaning with the first cleaning solution to expose the first polysilicon layer includes, The oxygen-containing silica layer is oxidized with ozone to form silica, and the silica is removed by a second cleaning solution.

7. The method for forming a semiconductor structure according to claim 5, wherein, Removing the oxygen-containing silicide layer formed on the surface of the first polysilicon layer on the array region by SPM cleaning to expose the first polysilicon layer includes: The oxygen-containing silicide layer was etched using a chemical dry etching method, with a flow rate of 3600 sccm for N2, a flow rate ratio of 8 sccm:300 sccm for H2 and NF3, and an etching power of 200 W.

8. The method for forming a semiconductor structure according to claim 7, wherein, When using chemical dry etching to etch oxygen-containing silicide layers, the temperature is maintained at or above 100°C.

9. The method for forming a semiconductor structure according to claim 5, wherein, The second process for removing the first polysilicon layer on the protective layer includes, The first polysilicon layer on the protective layer is chemically removed using a third cleaning solution until the protective layer is exposed.

10. The method for forming a semiconductor structure according to claim 5, wherein the first cleaning solution is an SPM solution.

11. The method for forming a semiconductor structure according to claim 6, wherein the second cleaning solution is a mixture of HF, H2O2 and H2O.

12. The method for forming a semiconductor structure according to claim 9, wherein the third cleaning solution is a mixture of NH4OH and H2O.

13. A semiconductor structure, wherein, The semiconductor structure is manufactured using a semiconductor structure forming method as described in any one of claims 1-12.

14. A memory, wherein, Including the semiconductor structure as described in claim 13.

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