Semiconductor devices, their fabrication methods, and 3D NAND memory

Abstract

The application provides a semiconductor device, a manufacturing method thereof and a 3D NAND memory, which comprises a substrate, an insulating layer and a conductive layer, wherein the surface of the substrate is provided with a groove, the insulating layer is located on the surface of the substrate, the bottom of the groove and the sidewall of the groove; and the conductive layer is located on the surface of the insulating layer away from the substrate. The semiconductor device of the application forms a three-dimensional pattern with multiple grooves on the substrate, so that the conductive layer covering the substrate has a three-dimensional structure, i.e., a capacitor with a three-dimensional structure is formed, which ensures that the semiconductor device has a smaller occupied area on the semiconductor device under the condition that the effective area of the semiconductor device remains unchanged, ensures that the integration density of the semiconductor device is larger, and thus relieves the limitation problem of the capacitor on the size reduction of the semiconductor device.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a semiconductor device, a method of manufacturing the same, a 3D NAND memory, and a storage system. Background Technology

[0002] In the fabrication of semiconductor devices, a portion of their area is used to form capacitors. However, the low integration density of capacitors in current technologies limits the reduction in the size of semiconductor devices.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a semiconductor device, its fabrication method, a 3D NAND memory, and a storage system to solve the problem that capacitors in existing semiconductor devices occupy a large area, which limits the size reduction of semiconductor devices.

[0005] According to one aspect of this application, a semiconductor device is provided, comprising a substrate, an insulating layer, and a conductive layer, wherein a groove is provided on the surface of the substrate; the insulating layer is located on the surface of the substrate, the bottom of the groove, and the sidewalls of the groove; and the conductive layer is located on the surface of the insulating layer away from the substrate.

[0006] Optionally, the conductive layer fills the groove, and the surface of the conductive layer away from the substrate is planar.

[0007] Optionally, the thickness of the insulating layer located at the bottom of the groove is a first thickness, and the thickness of the insulating layer located on the surface of the substrate is a second thickness, wherein the first thickness is greater than the second thickness.

[0008] Optionally, the substrate includes an isolation structure, and the groove is located in the isolation structure.

[0009] Optionally, the thickness of the insulating layer located at the bottom of the groove is a first thickness, and the thickness of the insulating layer located on the surface of the substrate is a second thickness, wherein the first thickness is equal to the second thickness.

[0010] Optionally, the conductive layer may be made of polycrystalline silicon.

[0011] According to another aspect of this application, a method for fabricating the semiconductor device is also provided, comprising: providing a substrate; forming a groove on the surface of the substrate; forming an insulating layer on the surface of the substrate, the bottom of the groove, and the sidewalls of the groove; and forming a conductive layer on the surface of the insulating layer away from the substrate.

[0012] Optionally, providing a substrate includes: providing a pre-substrate; forming a shallow trench isolation in the pre-substrate; and forming a groove on the surface of the substrate, including: removing at least a portion of the shallow trench isolation to correspondingly form the groove.

[0013] Optionally, forming a shallow trench isolation in the pre-substrate includes: forming a patterned mask layer on the exposed surface of the pre-substrate; etching the pre-substrate using the patterned mask layer as a mask to obtain trenches; depositing an isolation material on the surface of the patterned mask layer away from the pre-substrate and within the trenches, the filled isolation material forming the shallow trench isolation; and performing chemical mechanical polishing on the pre-substrate with the shallow trench isolation formed thereon to expose the patterned mask layer.

[0014] Optionally, the insulating layer is made of the same material as the insulating material.

[0015] Optionally, forming a conductive layer on the surface of the insulating layer away from the substrate includes: forming a preliminary conductive layer on the surface of the insulating layer away from the substrate, the preliminary conductive layer filling the groove; planarizing the preliminary conductive layer so that the remaining surface of the preliminary conductive layer away from the substrate is planar, thereby obtaining the conductive layer.

[0016] According to another aspect of this application, a 3D NAND memory is also provided, comprising any of the semiconductor devices described above or a semiconductor device fabricated using any of the methods described above.

[0017] According to another aspect of this application, a storage system is also provided, the storage system including a storage controller and the 3D NAND memory, the 3D NAND memory being configured to store data, and the storage controller being coupled to the 3D NAND memory and configured to control the 3D NAND memory.

[0018] According to the technical solution of this application, the semiconductor device includes a substrate, an insulating layer, and a conductive layer. The substrate has grooves on its surface, and the insulating layer covers the surface of the substrate, the bottom of the grooves, and the sidewalls of the grooves. The conductive layer is located on the surface of the insulating layer away from the substrate. Compared to the problem of large area occupation in two-dimensional planar capacitors in the prior art, the semiconductor device of this application, by forming a three-dimensional pattern with grooves on the substrate, gives the conductive layer covering the substrate a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, guaranteeing a higher integration density and alleviating the limitation of capacitors on the size reduction of semiconductor devices. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figures 1 to 6 A schematic diagram of the structure formed after different process steps according to the semiconductor process of this application is shown;

[0021] Figure 7 A schematic diagram of a semiconductor device according to an embodiment of this application is shown;

[0022] Figure 8 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown.

[0023] The above figures include the following reference numerals:

[0024] 100, Substrate; 101, Shallow trench isolation; 102, Isolation material; 200, Groove; 300, Insulating layer; 400, Conductive layer; 500, Patterned mask layer; 501, First mask layer; 502, Second mask layer. Detailed Implementation

[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0031] As described in the background section, capacitors in existing semiconductor devices occupy a large area, which limits the size reduction of semiconductor devices. In order to solve the above problems, this application proposes a semiconductor device, its fabrication method, a 3D NAND memory, and a storage system.

[0032] According to a typical embodiment of this application, a semiconductor device is provided, such as... Figure 7 As shown, the semiconductor device includes a substrate 100, an insulating layer 300, and a conductive layer 400. The substrate 100 has a groove on its surface; the insulating layer 300 is on the surface of the substrate 100, the bottom of the groove, and the sidewall of the groove; the conductive layer 400 is located on the surface of the insulating layer 300 away from the substrate 100.

[0033] The aforementioned semiconductor device includes a substrate, an insulating layer, and a conductive layer. The substrate has grooves on its surface. The insulating layer covers the surface of the substrate, the bottom of the grooves, and the sidewalls of the grooves. The conductive layer is located on the surface of the insulating layer away from the substrate. Compared to the problem of large area occupation in two-dimensional planar capacitors in the prior art, the semiconductor device of this application, by forming a three-dimensional pattern with grooves on the substrate, gives the conductive layer covering the substrate a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, guaranteeing a higher integration density and alleviating the limitation of capacitors on the size reduction of semiconductor devices.

[0034] In practical applications, there may be one or multiple grooves.

[0035] According to a specific embodiment of this application, such as Figure 7 As shown, the conductive layer 400 fills the groove, and the surface of the conductive layer 400 away from the substrate 100 is planar.

[0036] To further facilitate the formation of the subsequent conductive layer, in another specific embodiment, such as Figure 5 As shown, the thickness of the insulating layer 300 located at the bottom of the groove is a first thickness d1, and the thickness of the insulating layer 300 located on the surface of the substrate 100 is a second thickness d2. The first thickness d1 is greater than the second thickness d2.

[0037] In another specific embodiment, such as Figure 7 As shown, the substrate includes an isolation structure, and the groove is located within the isolation structure. Specifically, the substrate includes shallow trench isolation, and the groove is formed after removing a portion of the shallow trench isolation, with the remaining shallow trench isolation forming the isolation structure, which is composed of isolation material 102. In this case, the first thickness d1 can also be equal to the second thickness d2.

[0038] Of course, the relationship between the first thickness and the second thickness is not limited to the above relationship. Those skilled in the art can flexibly set the first thickness and the second thickness according to the actual situation.

[0039] In practical applications, the materials of the conductive layer, the substrate, and the insulating layer can be any feasible materials available in the prior art. Those skilled in the art can flexibly select the materials of the conductive layer, the substrate, and the insulating layer according to the actual situation. In another specific embodiment of this application, the material of the conductive layer includes polycrystalline silicon, the material of the substrate includes silicon, and the material of the insulating layer includes silicon oxide. In a more specific embodiment of this application, the material of the conductive layer is polycrystalline silicon, the material of the substrate is silicon, and the material of the insulating layer is silicon oxide.

[0040] According to another typical embodiment of this application, a method for fabricating the above-described semiconductor device is also provided. Figure 8 A flowchart illustrating a method for fabricating the above-described semiconductor device according to an embodiment of this application is shown, as follows: Figure 8 As shown, the above method includes the following steps:

[0041] Step S101: Provide a substrate;

[0042] Step S102, a groove 200 is formed on the surface of the substrate 100 to obtain the following: Figure 3 Or such as Figure 4 The structure shown;

[0043] Step S103, as follows Figure 5 or Figure 6 As shown, an insulating layer 300 is formed on the surface of the substrate 100, the bottom of the groove 200, and the sidewalls of the groove 200.

[0044] Step S104: A conductive layer 400 is formed on the surface of the insulating layer 300 away from the substrate 100, to obtain... Figure 7 The structure shown.

[0045] In the above-described method for fabricating a semiconductor device, a substrate is first provided; then, grooves are formed on the surface of the substrate; finally, an insulating layer and a conductive layer are sequentially deposited on the substrate with the grooves to obtain the semiconductor device. This method, by forming a three-dimensional pattern with grooves on a substrate, and then sequentially forming an insulating layer and a conductive layer on the surface of the substrate and within the grooves, transforms the conductive layer from a two-dimensional planar structure into a three-dimensional structure, thus obtaining a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, guaranteeing a higher integration density and alleviating the limitation of capacitors on semiconductor device size reduction.

[0046] According to another specific embodiment of this application, providing a substrate includes: providing a pre-substrate; such as Figure 1 As shown, a shallow trench isolation 101 is formed in the above-mentioned pre-substrate, as... Figure 3 or Figure 4 As shown, forming a groove on the surface of the substrate includes: removing at least a portion of the shallow trench isolation 101, correspondingly forming the groove 200, and the remaining shallow trench isolation forming an isolation structure.

[0047] To further ensure that the fabrication process of the aforementioned groove is relatively simple and easy, in another specific embodiment of this application, forming a shallow trench isolation in the aforementioned pre-substrate includes: forming a patterned mask layer 500 on the exposed surface of the aforementioned pre-substrate; etching the aforementioned pre-substrate using the patterned mask layer 500 as a mask to obtain a trench; depositing an isolation material on the surface of the patterned mask layer 500 away from the aforementioned pre-substrate and within the aforementioned trench, the filled isolation material forming the aforementioned shallow trench isolation 101; and performing chemical mechanical polishing on the aforementioned pre-substrate with the aforementioned shallow trench isolation to expose the patterned mask layer 500, resulting in... Figure 1 The structure shown. Removing at least a portion of the aforementioned shallow groove isolation to correspondingly form the aforementioned groove includes: removing at least a portion of the aforementioned shallow groove isolation 101 to obtain the structure shown. Figure 2 The structure shown is obtained by removing the patterned mask layer 500 as described above. Figure 3 Or such as Figure 4 The groove 200 shown above.

[0048] In the above embodiments, removing at least a portion of the shallow trench isolation can be done by removing all of the shallow trench isolation, resulting in... Figure 4 The structure shown can also be modified by removing part of the aforementioned shallow trench isolation, with the remaining isolation material 102 forming an isolation structure, resulting in the following: Figure 3 The structure shown.

[0049] In one specific embodiment, the trench is formed by etching the prepared substrate using a dry etching method.

[0050] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate can be selected according to the actual needs of the device and may include silicon substrates, germanium substrates, silicon-germanium composites, SOI (Silicon on Insulator) substrates, or GOI (Germanium on Insulator) substrates. In other embodiments, the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon on Germanium Insulator). Of course, other substrates feasible in the prior art may also be used.

[0051] The method for forming the patterned mask layer of this application can employ any feasible method in the prior art. Those skilled in the art can determine a suitable method to form the patterned mask layer of this application based on the actual situation. To form the patterned mask layer more simply and quickly, according to another specific embodiment of this application, forming the patterned mask layer on the exposed surface of the pre-substrate includes: sequentially forming a mask material layer and a photoresist layer on the exposed surface of the pre-substrate; patterning the photoresist layer, with the remaining photoresist layer forming a photoresist portion; etching the mask material layer using the photoresist portion as a mask to form the patterned mask layer; and removing the photoresist portion. There are also many methods for forming the photoresist layer of this application, and those skilled in the art can select a suitable method to form the photoresist layer of this application based on the actual situation.

[0052] According to another specific embodiment of this application, such as Figure 1 As shown, the patterned mask layer 500 includes a first mask layer 501 and a second mask layer 502 stacked sequentially in a direction away from the prepared substrate. The material of the first mask layer 501 includes silicon oxide, and the material of the second mask layer 502 includes silicon nitride.

[0053] Specifically, the first mask layer is made of silicon oxide, and the second mask layer is made of silicon nitride. Of course, the first and second mask layers are not limited to silicon oxide and silicon nitride. In one embodiment, to form a more stable patterned mask layer and ensure better etching results, the first mask layer is made of carbon, and the second mask layer is made of silicon oxynitride.

[0054] According to another specific embodiment of this application, forming a mask material layer on the exposed surface of the aforementioned pre-substrate includes: forming a silicon oxide layer on the exposed surface of the aforementioned pre-substrate; and forming a silicon nitride layer on the exposed surface of the aforementioned silicon oxide layer. Of course, the mask material layer of this application is not limited to the above-described formation method; other formation methods are also possible. Those skilled in the art can select appropriate materials and processes according to actual conditions to form the mask material layer described above in this application.

[0055] To further ensure that the process for obtaining the aforementioned semiconductor device is relatively simple and easy, the material of the insulating layer is the same as that of the isolation material in actual applications.

[0056] In order to obtain the conductive layer with a relatively smooth and flat surface, according to another specific embodiment of the present application, a conductive layer is formed on the surface of the insulating layer away from the substrate, including: forming a preliminary conductive layer on the surface of the insulating layer away from the substrate, the preliminary conductive layer filling the groove; planarizing the preliminary conductive layer so that the remaining surface of the preliminary conductive layer away from the substrate is a plane, thereby obtaining the conductive layer.

[0057] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0058] According to another aspect of this application, a 3D NAND memory is also provided, comprising any of the above-described semiconductor devices or semiconductor devices fabricated using any of the above-described methods.

[0059] The aforementioned 3D NAND memory includes any of the aforementioned semiconductor devices or semiconductor devices fabricated using any of the aforementioned methods. The semiconductor device includes a substrate, an insulating layer, and a conductive layer. The substrate has grooves on its surface. The insulating layer covers the surface of the substrate, the bottom of the grooves, and the sidewalls of the grooves. The conductive layer is located on the surface of the insulating layer away from the substrate. Compared to the problem of large area occupied by two-dimensional planar capacitors in the prior art, the semiconductor device of this application, by forming a three-dimensional pattern with multiple trenches on the substrate, gives the conductive layer covering the substrate a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, ensuring a higher integration density. This alleviates the limitation of capacitors on the size reduction of semiconductor devices, thereby ensuring a smaller size for the aforementioned 3D NAND memory.

[0060] In another typical embodiment of this application, a storage system is also provided, the storage system including a storage controller and the 3D NAND memory, the 3D NAND memory being configured to store data, and the storage controller being coupled to the 3D NAND memory and configured to control the 3D NAND memory.

[0061] The aforementioned storage system includes a storage controller and the aforementioned 3D NAND memory. The semiconductor devices in the aforementioned 3D NAND memory are formed by creating a three-dimensional pattern with multiple trenches on a substrate. This results in a three-dimensional structure for the conductive layer covering the substrate, forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, thus ensuring a higher integration density of the semiconductor device. This alleviates the limitation of the capacitor on the size reduction of the semiconductor device, thereby ensuring that the size of the aforementioned 3D NAND memory is small, and consequently, that the size of the entire storage system can be small.

[0062] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0063] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0064] 1) The semiconductor device described in this application includes a substrate, an insulating layer, and a conductive layer. The substrate has grooves on its surface. The insulating layer covers the surface of the substrate, the bottom of the grooves, and the sidewalls of the grooves. The conductive layer is located on the surface of the insulating layer away from the substrate. Compared to the problem of large area occupied by two-dimensional planar capacitors in the prior art, the semiconductor device of this application, by forming a three-dimensional pattern with grooves on the substrate, gives the conductive layer covering the substrate a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, ensuring a higher integration density and alleviating the limitation of capacitors on the size reduction of semiconductor devices.

[0065] 2) In the semiconductor device fabrication method described above in this application, a substrate is first provided; then, a groove is formed on the surface of the substrate; finally, an insulating layer and a conductive layer are sequentially covered on the substrate with the groove to obtain the semiconductor device. This method forms a three-dimensional pattern with grooves on the substrate, and then sequentially forms an insulating layer and a conductive layer on the surface of the substrate and within the groove. This transforms the conductive layer from a two-dimensional planar structure into a three-dimensional structure, resulting in a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, thus guaranteeing a higher integration density and alleviating the limitation of capacitors on semiconductor device size reduction.

[0066] 3) The 3D NAND memory described in this application includes any of the aforementioned semiconductor devices or semiconductor devices fabricated using any of the aforementioned methods. The semiconductor device includes a substrate, an insulating layer, and a conductive layer. The substrate has grooves on its surface. The insulating layer covers the surface of the substrate, the bottom of the grooves, and the sidewalls of the grooves. The conductive layer is located on the surface of the insulating layer away from the substrate. Compared to the problem of large area occupied by two-dimensional planar capacitors in the prior art, the semiconductor device of this application, by forming a three-dimensional pattern with multiple trenches on the substrate, gives the conductive layer covering the substrate a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a smaller area on the semiconductor device, ensuring a higher integration density. This alleviates the limitation of capacitors on the size reduction of semiconductor devices, thereby ensuring a smaller size for the 3D NAND memory.

[0067] 4) The storage system described above in this application includes a storage controller and the 3D NAND memory. The semiconductor device in the 3D NAND memory is formed by creating a three-dimensional pattern with multiple trenches on a substrate. This makes the conductive layer covering the substrate have a three-dimensional structure, thus forming a three-dimensional capacitor. This ensures that the effective area of ​​the semiconductor device remains unchanged while occupying a small area on the semiconductor device, thereby ensuring a high integration density of the semiconductor device. This alleviates the limitation of the capacitor on the size reduction of the semiconductor device, thus ensuring that the size of the 3D NAND memory is small, and consequently ensuring that the size of the entire storage system is small.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A substrate having grooves on its surface; An insulating layer is located on the surface of the substrate, the bottom of the groove, and the sidewalls of the groove; A conductive layer is located on the surface of the insulating layer away from the substrate; The substrate includes: an isolation structure, wherein the groove is located in the isolation structure; The thickness of the insulating layer located at the bottom of the groove is a first thickness, and the thickness of the insulating layer located on the surface of the substrate is a second thickness, wherein the first thickness is equal to the second thickness; The conductive layer fills the groove, and the surface of the conductive layer away from the substrate is planar.

2. The semiconductor device according to claim 1, characterized in that, The conductive layer is made of polycrystalline silicon.

3. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A groove is formed on the surface of the substrate; An insulating layer is formed on the surface of the substrate, the bottom of the groove, and the sidewalls of the groove; A conductive layer is formed on the surface of the insulating layer away from the substrate; Providing a substrate includes: providing a pre-substrate; forming a shallow trench isolation in the pre-substrate; forming a groove on the surface of the substrate, including: removing at least a portion of the shallow trench isolation to correspondingly form the groove, the remaining shallow trench isolation forming an isolation structure, wherein the thickness of the insulating layer at the bottom of the groove is a first thickness, and the thickness of the insulating layer on the surface of the substrate is a second thickness, the first thickness being equal to the second thickness.

4. The method according to claim 3, characterized in that, Forming shallow trench isolation in the prepared substrate includes: A patterned mask layer is formed on the exposed surface of the prepared substrate; The pre-substrate is etched using the patterned mask layer as a mask to obtain trenches; An isolation material is deposited on the surface of the patterned mask layer away from the pre-substrate and within the trench, and the filled isolation material forms the shallow trench isolation; The pre-substrate with the shallow trench isolation is chemically and mechanically polished to expose the patterned mask layer.

5. The method according to claim 4, characterized in that, The insulating layer is made of the same material as the insulating material.

6. The method according to any one of claims 3 to 5, characterized in that, A conductive layer is formed on the surface of the insulating layer away from the substrate, comprising: A preliminary conductive layer is formed on the surface of the insulating layer away from the substrate, the preliminary conductive layer filling the groove; The pre-conductive layer is planarized so that the remaining surface of the pre-conductive layer away from the substrate is planar, thus obtaining the conductive layer.

7. A 3D NAND memory, characterized in that, The semiconductor device includes the semiconductor device described in claim 1 or 2, or a semiconductor device manufactured using the method described in any one of claims 3 to 6.

8. A storage system, characterized in that, It includes a storage controller and a 3D NAND memory as claimed in claim 7, the 3D NAND memory being configured to store data, and the storage controller being coupled to the 3D NAND memory and configured to control the 3D NAND memory.

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