semiconductor structure

Abstract

This application provides a semiconductor structure, including a substrate, a pad structure, and a capacitor structure. Multiple metal layers are arranged from top to bottom on the substrate. The pad structure is located on the top metal layer, and the capacitor structure is located within a metal layer below the top metal layer, specifically below the pad structure. By placing the capacitor structure within the metal layer below the pad structure, this application fully utilizes the layout area of ​​the pad structure without occupying the transistor area on the substrate, which is beneficial for the miniaturization of the semiconductor structure. Furthermore, the closer proximity of the capacitor structure to the pad structure results in better voltage regulation performance.

Description

Technical Field

[0001] This application relates to, but is not limited to, a semiconductor structure. Background Technology

[0002] Because capacitors have energy storage capabilities, layout designers often need to add a large number of capacitors near the power supply in semiconductor chip circuit design to stabilize the power supply voltage. Therefore, making rational use of the limited chip area and placing a sufficient number of capacitors has always been a problem that layout designers have been striving to solve. Summary of the Invention

[0003] According to some embodiments, this application provides a semiconductor structure, including: a substrate, a pad structure, and a capacitor structure;

[0004] The substrate has multiple metal layers arranged from top to bottom. The pad structure is located on the top metal layer, and the capacitor structure is located in the metal layer below the top metal layer, with the capacitor structure located below the pad structure.

[0005] In one embodiment, the capacitor structure includes: a first upper plate, a first lower plate, a second lower plate, a capacitor pillar, and a dielectric layer;

[0006] The first upper electrode plate and the first lower electrode plate are arranged opposite to each other, and the first upper electrode plate and the second lower electrode plate are arranged opposite to each other.

[0007] There are multiple capacitor pillars, and each capacitor pillar is provided with a dielectric layer between itself and the first upper electrode plate; a capacitor pillar is provided between the first lower electrode plate and the first upper electrode plate, and a capacitor pillar is also provided between the second lower electrode plate and the first upper electrode plate.

[0008] In one embodiment, the number of capacitor pillars located between the first lower electrode and the first upper electrode is equal to the number of capacitor pillars located between the second lower electrode and the first upper electrode.

[0009] In one embodiment, a plurality of electrode holes are provided on the first upper electrode plate, and a capacitor post is provided in each electrode hole, with a dielectric layer located between the electrode hole and the capacitor post.

[0010] In one embodiment, the first lower electrode plate and the second lower electrode plate are located in the same metal layer, and the first lower electrode plate and the second lower electrode plate are arranged at an interval.

[0011] In one embodiment, the projection of the first upper electrode plate onto the substrate is located inside the projection of the pad structure onto the substrate.

[0012] In one embodiment, the capacitor structure further includes: a second upper electrode plate; the capacitor structure further includes a third lower electrode plate and a fourth lower electrode plate;

[0013] The second upper electrode plate and the third lower electrode plate are arranged opposite to each other, and the second upper electrode plate and the fourth lower electrode plate are arranged opposite to each other.

[0014] A capacitor post is provided between the third lower electrode plate and the second upper electrode plate, and a capacitor post is also provided between the fourth lower electrode plate and the second upper electrode plate.

[0015] In one embodiment, the first upper electrode plate and the second upper electrode plate are located in the same metal layer and are arranged in an array;

[0016] The first, second, third, and fourth lower electrodes are located in the same metal layer and are arranged in an array.

[0017] In one embodiment, the projection of the second upper electrode plate onto the substrate is located inside the projection of the pad structure onto the substrate.

[0018] In one embodiment, the capacitor structure further includes a third upper plate and a fourth upper plate; the capacitor structure also includes a fifth lower plate, a sixth lower plate, a seventh lower plate, and an eighth lower plate;

[0019] The third upper electrode plate and the fifth lower electrode plate are arranged opposite to each other, and the third upper electrode plate and the sixth lower electrode plate are arranged opposite to each other; a capacitor post is provided between the fifth lower electrode plate and the third upper electrode plate, and a capacitor post is also provided between the sixth lower electrode plate and the third upper electrode plate.

[0020] The fourth upper electrode plate and the seventh lower electrode plate are arranged opposite each other, and the fourth upper electrode plate and the eighth lower electrode plate are arranged opposite each other; a capacitor post is provided between the seventh lower electrode plate and the fourth upper electrode plate, and a capacitor post is also provided between the eighth lower electrode plate and the fourth upper electrode plate.

[0021] In one embodiment, the first upper electrode plate, the second upper electrode plate, the third upper electrode plate, and the fourth upper electrode plate are located in the same metal layer and are arranged in an array.

[0022] The first, second, third, fourth, fifth, sixth, seventh, and eighth lower electrodes are located in the same metal layer and are arranged in an array.

[0023] In one embodiment, the capacitor structure further includes a first contact metal and a second contact metal;

[0024] The first contact metal is located in the same layer as the first lower electrode plate; the second contact metal is located in the same layer as the first lower electrode plate;

[0025] The first contact metal is in contact with the first lower electrode plate, and the first contact metal is also in contact with the third lower electrode plate; the second contact metal is in contact with the second lower electrode plate, and the second contact metal is also in contact with the fourth lower electrode plate.

[0026] In one embodiment, the capacitor structure further includes a third contact metal and a fourth contact metal;

[0027] The third contact metal is located in the same layer as the first lower electrode plate; the fourth contact metal is located in the same layer as the first lower electrode plate;

[0028] The third contact metal is in contact with the fifth lower electrode plate, and the third contact metal is also in contact with the seventh lower electrode plate; the fourth contact metal is in contact with the sixth lower electrode plate, and the fourth contact metal is also in contact with the eighth lower electrode plate.

[0029] In one embodiment, the capacitor structure further includes a fifth contact metal;

[0030] The fifth contact metal is located in the same metal layer as the first lower electrode plate, the fifth contact metal is in contact with the second contact metal, and the fifth contact metal is also in contact with the third contact metal;

[0031] The capacitor structure also includes a sixth contact metal and a seventh contact metal; the sixth contact metal is in contact with the first contact metal and is used to connect to the first power supply terminal; the seventh contact metal is in contact with the fourth contact metal and is used to connect to the second power supply terminal.

[0032] In one embodiment, the first contact metal, the second contact metal, the third contact metal, and the fourth contact metal are arranged in an array.

[0033] The semiconductor structure provided in this application includes a pad structure, a capacitor structure, and a substrate. Multiple metal layers are disposed above the substrate, arranged sequentially from top to bottom. The pad structure is located on the top metal layer, and the capacitor structure is located within the metal layers below the top metal layer. This arrangement eliminates the need for the capacitor structure to occupy transistor area on the substrate, allowing for the placement of more transistors and improving substrate area utilization. Furthermore, the capacitor structure's location below the pad structure fully utilizes the area beneath it, contributing to semiconductor structure miniaturization in two ways. Additionally, the proximity of the capacitor structure to the pad structure improves voltage regulation for power supplied from the pad structure. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0036] Figure 2 A circuit schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0037] Figure 3 This is a top view of a capacitor structure in a semiconductor structure provided in an embodiment of this application;

[0038] Figure 4 For this application Figure 3 A cross-sectional view of the capacitor structure in the semiconductor structure provided in the illustrated embodiment;

[0039] Figure 5 This is a top view of a capacitor structure in a semiconductor structure provided in another embodiment of this application;

[0040] Figure 6 For this application Figure 5 The circuit diagram of the capacitor structure in the semiconductor structure provided in the embodiment shown;

[0041] Figure 7 This is a top view of a capacitor structure in a semiconductor structure provided in another embodiment of this application;

[0042] Figure 8 For this application Figure 7 The circuit diagram of the capacitor structure in the semiconductor structure provided in the embodiment shown.

[0043] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of this application, as shown below. Figure 1 As shown, the semiconductor structure provided in this application embodiment includes a substrate 300, a pad structure 200, and a capacitor structure 100.

[0046] The substrate 300 can be, but is not limited to, a silicon substrate 300. The pad structure 200 is located above the substrate 300. When the pad structure 200 is a power pad, it can be electrically connected to the package substrate by making leads, thereby obtaining the corresponding power supply voltage (such as VDDQ, VPP, VDD, etc.).

[0047] Several transistor regions are disposed on the substrate 300, and multiple metal layers are disposed above the substrate 300, with the multiple metal layers arranged from top to bottom. That is, the multiple metal layers are arranged from the direction away from the substrate 300 to the direction closer to the substrate 300.

[0048] The topmost metal layer is designated as the top metal layer M3. The metal layer below the top metal layer and immediately adjacent to the top metal layer M3 is designated as the second-to-top metal layer M2. The metal layer below the second-to-top metal layer M2 and immediately adjacent to the second-to-top metal layer M2 is designated as the third metal layer M1. The metal layer below the third metal layer M1 and immediately adjacent to the third metal layer M1 is designated as the fourth metal layer M0. An isolation layer is provided between the third metal layer M1 and the fourth metal layer M0 to isolate the metal layers. Metal vias are provided between any two metal layers to enable connection between them. For example, a metal via V3 is provided between the top metal layer M3 and the second-to-top metal layer M2; a metal via V2 is provided between the second-to-top metal layer M2 and the third metal layer M1; a metal via V1 is provided between the third metal layer M1 and the fourth metal layer M0; and a metal via V0 is provided between the fourth metal layer M0 and the substrate 300.

[0049] The pad structure 200 is located on the top metal layer M3 and is used to connect the power supply terminal. The capacitor structure 100 is located below the pad structure 200 and is located in the metal layer below the top metal layer M3. That is, the capacitor structure 100 is formed by the metal in the metal layer and the metal via between the two metal layers.

[0050] like Figure 2 As shown, the capacitor structure 100 located below the pad structure 200 can stabilize the power supply voltage. By placing the capacitor structure 100 below the top metal layer, the capacitor structure 100 can be formed using the metal blocks in the metal layer and the metal vias between the two metal layers. This eliminates the need to occupy the transistor area on the substrate 300, thus making reasonable use of the semiconductor structure's layout area. Furthermore, the capacitor structure 100 being located near the pad structure 200 can improve the capacitor's voltage regulation performance.

[0051] In one embodiment, reference Figure 3 and Figure 4 The capacitor structure 100 includes a first upper plate 101, a first lower plate 102, a second lower plate 103, a capacitor post 104, and a dielectric layer 105.

[0052] The first lower electrode plate 102 and the second lower electrode plate 103 are located in the same metal layer, meaning they are metal blocks on the same metal layer. For example, the first lower electrode plate 102 and the second lower electrode plate 103 are metal blocks located on an isolation layer. The first upper electrode plate 101 and the first lower electrode plate 102 are located in different metal layers, meaning they are two metal blocks located on different metal layers, serving as the first upper electrode plate 101 and the first lower electrode plate 102. For example, the first upper electrode plate 101 is a metal block located on the second-to-last metal layer M2. The first upper electrode plate 101 and the first lower electrode plate 102 are arranged opposite each other, and the first upper electrode plate 101 and the second lower electrode plate 103 are arranged opposite each other.

[0053] The capacitor post 104 is a metal through-hole located between two metal layers. There are multiple capacitor posts 104, one between the first lower electrode plate 102 and the first upper electrode plate 101, and another between the second lower electrode plate 103 and the first upper electrode plate 101. To achieve electrical isolation between the first upper electrode plate 101 and the first lower electrode plate 102, and between the first upper electrode plate 101 and the second lower electrode plate 103, a dielectric layer 105 is provided between each capacitor post 104 and the first upper electrode plate 101. This allows charge to be stored between the first upper electrode plate 101 and the two lower electrodes when the capacitor structure 100 is charged through the pad structure 200. During power fluctuations, the capacitor structure 100 can release the charge, thereby stabilizing the power supply. Furthermore, compared to transistor capacitors, capacitors formed by metal blocks and metal vias within a metal layer have a larger relative area between the two plates. Under the same area, the capacitance value of the capacitor structure provided in this application is usually more than ten times that of transistor capacitors, resulting in better voltage regulation performance.

[0054] In one embodiment, the number of capacitor posts 104 located between the first lower electrode 102 and the first upper electrode 101 is equal to the number of capacitor posts 104 located between the second lower electrode 103 and the first upper electrode 101. For example: continue to refer to Figure 3 Fourteen capacitor posts 104 are positioned between the first upper plate 101 and the first lower plate 102, and between the first upper plate 101 and the second lower plate 103. This configuration creates a symmetrical capacitor structure 100, ensuring that the dielectric strength between the first upper plate 101 and the first lower plate 102 is the same as that between the first upper plate 101 and the second lower plate 103. Compared to capacitor structures 100 with different dielectric strengths, the capacitance of the capacitor structure 100 is determined by the dielectric strength between the upper and lower plates, which has a lower dielectric strength. This structure can fully utilize the dielectric strength between the upper and lower plates, thereby improving the performance of the capacitor structure 100.

[0055] In one embodiment, the first lower electrode 102 serves as the first end of the capacitor structure 100, and the second lower electrode 103 serves as the second end of the capacitor structure 100. The first end of the capacitor structure 100 is used to connect transistors, resistors, and other devices in the pad structure 200 or the substrate 300.

[0056] In one embodiment, the first upper electrode plate 101 has a plurality of electrode holes 1011, and each electrode hole 1011 contains a capacitor post 104. That is, the upper end of the capacitor post 104 is installed inside the electrode hole 1011, and the lower end of the capacitor post 104 contacts the first lower electrode plate 102 or the second lower electrode plate 103. A dielectric layer 105 is located between the electrode holes 1011 and the capacitor post 104 to achieve electrical isolation between the capacitor post 104 and the first upper electrode plate 101. The capacitor post 104 can be a solid columnar structure or a hollow columnar structure, and the capacitor post 104 is also made of a conductive material. With this configuration, the capacitor post 104 can be fabricated using mature semiconductor drilling technology, and the upper and lower electrodes and the dielectric layer 105 can be fabricated using semiconductor deposition and patterning processes, reducing the cost of the semiconductor structure.

[0057] In one embodiment, the first lower electrode 102 and the second lower electrode 103 are located on the same metal layer, and are spaced apart from each other. The first lower electrode 102 serves as the first end of the capacitor structure 100, and the second lower electrode 103 serves as the second end of the capacitor structure 100. By arranging the first lower electrode 102 and the second lower electrode 103 spaced apart, short-circuiting of the two ends of the capacitor structure 100 can be avoided.

[0058] In one embodiment, the projection of the first upper electrode 101 onto the substrate 300 is located inside the projection of the pad structure 200 onto the substrate 300. This arrangement allows full utilization of the layout area of ​​the pad structure 200, ensuring that the chip area is completely unaffected by the capacitor structure 100, and that the capacitor structure 100 does not affect the transistor layout design within the substrate 300. These two aspects contribute to chip miniaturization.

[0059] In one embodiment, the projection of the capacitor structure 100 on the substrate 300 coincides with the projection of the pad structure 200 on the substrate 300. Under the premise of making full use of the layout area of ​​the pad structure 200, the capacitance of the capacitor structure 100 can be effectively increased, thereby improving the voltage regulation performance of the capacitor structure 100.

[0060] Figure 5 This is a top view of the capacitor structure 100 in a semiconductor structure provided in another embodiment of this application. Figure 6 For this application Figure 5 The circuit schematic of the capacitor structure 100 in the semiconductor structure provided in the embodiment shown is as follows: Figure 5As shown, the capacitor structure 100 includes a first upper plate 101, a first lower plate 102, and a second lower plate 103. The first upper plate 101 and the first lower plate 102 are arranged opposite to each other, and the first upper plate 101 and the second lower plate 103 are also arranged opposite to each other. The capacitor structure 100 further includes a second upper plate 106, a third lower plate 107, and a fourth lower plate 108. The second upper plate 106 and the third lower plate 107 are arranged opposite to each other, and the second upper plate 106 and the fourth lower plate 108 are arranged opposite to each other.

[0061] The capacitor structure 100 also includes a plurality of capacitor posts 104. A capacitor post 104 is provided between the first lower electrode plate 102 and the first upper electrode plate 101. A capacitor post 104 is also provided between the second lower electrode plate 103 and the first upper electrode plate 101. A capacitor post 104 is provided between the third lower electrode plate 107 and the second upper electrode plate 106. A capacitor post 104 is also provided between the fourth lower electrode plate 108 and the second upper electrode plate 106.

[0062] A dielectric layer 105 is provided between the capacitor post 104 on the first lower electrode plate 102 and the first upper electrode plate 101, and a dielectric layer 105 is provided between the capacitor post 104 on the second lower electrode plate 103 and the first upper electrode plate 101, to achieve electrical isolation between the first upper electrode plate 101 and the capacitor post 104, thereby achieving electrical isolation between the first upper electrode plate 101 and the first lower electrode plate 102, and electrical isolation between the first upper electrode plate 101 and the second lower electrode plate 103. The first upper electrode plate 101, the first lower electrode plate 102, the second lower electrode plate 103, and the capacitor post 104 between the upper and lower electrodes form a first capacitor unit, the capacitance of which is equivalent to C1. The first lower electrode plate 102 is the first end of the first capacitor unit, and the second lower electrode plate 103 is the second end of the first capacitor unit. The first and second ends of the first capacitor unit are used for electrical connection with other components or pad structures 200.

[0063] A dielectric layer 105 is provided between the capacitor post 104 on the third lower electrode plate 107 and the second upper electrode plate 106, and a dielectric layer 105 is provided between the capacitor post 104 on the fourth lower electrode plate 108 and the second upper electrode plate 106, to achieve electrical isolation between the second upper electrode plate 106 and the capacitor post 104, thereby achieving electrical isolation between the second upper electrode plate 106 and the third lower electrode plate 107, and between the second upper electrode plate 106 and the fourth lower electrode plate 108. The second upper electrode plate 106, the third lower electrode plate 107, the fourth lower electrode plate 108, and the capacitor post 104 between the upper and lower electrodes form a second capacitor unit, the capacitance of which is equivalent to C2. The third lower electrode plate 107 is the first end of the second capacitor unit, and the fourth lower electrode plate 108 is the second end of the second capacitor unit. The first and second ends of the second capacitor unit are used for electrical connection with other components or pad structures 200.

[0064] In the above technical solution, two upper electrode plates are provided, and two lower electrode plates are provided opposite to each upper electrode plate. Capacitor pillars 104 and a dielectric layer 105 for electrical isolation are provided between the upper and lower electrode plates to form two capacitor units. In circuit design, the two capacitor units are electrically connected to other components or pad structures 200 according to functional requirements to form a circuit structure with corresponding functions. Furthermore, the capacitor units do not occupy the transistor area on the substrate 300, thus making full use of the layout area of ​​the semiconductor structure.

[0065] In one embodiment, the first upper electrode 101 and the second upper electrode 106 are located on the same metal layer and are arranged in an array. Similarly, the first lower electrode 102, the second lower electrode 103, the third lower electrode 107, and the fourth lower electrode 108 are located on the same metal layer and are arranged in an array. This arrangement allows for a uniform distribution of metal electrodes across each metal layer, reducing the fabrication complexity of the semiconductor structure and improving its yield.

[0066] In one embodiment, the projection of the first upper electrode 101 onto the substrate 300 is located inside the projection of the pad structure 200 onto the substrate 300, and the projection of the second upper electrode 106 onto the substrate 300 is also located inside the projection of the pad structure 200 onto the substrate 300. By providing two capacitor units below the pad structure 200, the capacitance requirements of the circuit within the semiconductor structure can be met, the layout area of ​​the pad structure 200 can be fully utilized, and the capacitor structure does not occupy the transistor area on the substrate 300, which is beneficial for miniaturizing the semiconductor chip.

[0067] In one embodiment, the capacitor structure 100 further includes a first contact metal 121 and a second contact metal 122. The first lower electrode 102, the second lower electrode 103, the third lower electrode 107, and the fourth lower electrode 108 are located in the same metal layer. The first contact metal 121 is located in the same layer as the first lower electrode 102, and the second contact metal 122 is located in the same layer as the second lower electrode 103. Specifically, the first contact metal 121 is in contact with the first lower electrode 102 and also with the third lower electrode 107; the second contact metal 122 is in contact with the second lower electrode 103 and also with the fourth lower electrode 108. In the above technical solution, a capacitor unit is formed by metal blocks in a multi-layer metal layer and through holes between two metal layers. Contact metal can be arranged on the metal layer where the lower electrode plate is located to realize the interconnection between two capacitor units. Then, the capacitor unit is connected to other devices through other metal blocks on the metal layer and metal holes between two metal layers. Compared with using transistor capacitors located on the substrate 300, there is no need to lay metal through holes from the metal layer to the metal connection line of the transistor area on the substrate 300 in order to connect the transistor capacitor located on the substrate 300. In other words, the capacitor structure provided by this solution makes the connection line layout simpler.

[0068] In one embodiment, the first contact metal 121 and the second contact metal 122 are U-shaped. One end of the U-shaped first contact metal 121 contacts the first lower electrode plate 102, and the other end contacts the third lower electrode plate 107. One end of the U-shaped second contact metal 122 contacts the second lower electrode plate 103, and the other end contacts the fourth lower electrode plate 108. With this arrangement, it is not necessary to leave sufficient space between the two capacitor cells for the contact metal; that is, the layout of the contact metal does not increase the spacing between the two capacitor cells, thus increasing the density of capacitor cells located below the pad structure 200.

[0069] Figure 7 This is a top view of the capacitor structure in a semiconductor structure provided in another embodiment of this application. Figure 8 For this application Figure 7 The circuit diagram of the capacitor structure in the semiconductor structure provided in the illustrated embodiment is shown. Figure 7 and Figure 8 As shown, the capacitor structure 100 has four capacitor units, which are labeled as the first capacitor unit, the second capacitor unit, the third capacitor unit, and the fourth capacitor unit in sequence.

[0070] The first capacitor unit includes a first upper plate 101, a first lower plate 102, a second lower plate 103, and capacitor posts 104. The first upper plate 101 and the first lower plate 102 are arranged opposite to each other, as are the first upper plate 101 and the second lower plate 103. A capacitor post 104 is located between the first lower plate 102 and the first upper plate 101, and also between the second lower plate 103 and the first upper plate 101. A dielectric layer 105 is provided between the capacitor post 104 on the first lower plate 102 and the first upper plate 101, and between the capacitor post 104 on the second lower plate 103 and the first upper plate 101. This provides electrical isolation between the first upper plate 101 and the capacitor post 104, thereby achieving electrical isolation between the first upper plate 101 and the first lower plate 102, and between the first upper plate 101 and the second lower plate 103. The capacitance value of the capacitor unit is equivalent to C1. The first lower plate 102 is the first end of the first capacitor unit, and the second lower plate 103 is the second end of the first capacitor unit. The first and second ends of the first capacitor unit are used for electrical connection with other components or pad structures.

[0071] The second capacitor unit includes a second upper plate 106, a third lower plate 107, a fourth lower plate 108, and capacitor posts 104. The second upper plate 106 and the third lower plate 107 are positioned opposite each other, as are the second upper plate 106 and the fourth lower plate 108. A capacitor post 104 is positioned between the third lower plate 107 and the second upper plate 106, and also between the fourth lower plate 108 and the second upper plate 106. A dielectric layer 105 is provided between the capacitor post 104 on the third lower plate 107 and the second upper plate 106, and between the capacitor post 104 on the fourth lower plate 108 and the second upper plate 106, to achieve electrical isolation between the second upper plate 106 and the capacitor post 104, thereby achieving electrical isolation between the second upper plate 106 and the third lower plate 107, and between the second upper plate 106 and the fourth lower plate 108. The capacitance value of the second capacitor unit is equivalent to C2. The third lower electrode 107 is the first end of the capacitor unit, and the fourth lower electrode 108 is the second end of the capacitor unit. The first and second ends of the second capacitor unit are used for electrical connection with other components or pad structures.

[0072] The third capacitor unit includes a third upper plate 109, a fifth lower plate 110, a sixth lower plate 111, and capacitor posts 104. The third upper plate 109 and the fifth lower plate 110 are positioned opposite each other, as are the third upper plate 109 and the sixth lower plate 111. A capacitor post 104 is positioned between the fifth lower plate 110 and the third upper plate 109, and also between the sixth lower plate 111 and the third upper plate 109. A dielectric layer 105 is positioned between the capacitor post 104 on the fifth lower plate 110 and the third upper plate 109, and also between the capacitor post 104 on the sixth lower plate 111 and the third upper plate 109. This provides electrical isolation between the third upper plate 109 and the capacitor post 104, thereby achieving electrical isolation between the third upper plate 109 and the fifth lower plate 110. The capacitance value of the third capacitor unit is equivalent to C3. The fifth lower plate 110 is the first end of the capacitor unit, and the sixth lower plate 111 is the second end of the capacitor unit. The first and second ends of the third capacitor unit are used for electrical connection with other components or pad structures.

[0073] The fourth capacitor unit includes a fourth upper plate 112, a seventh lower plate 113, an eighth lower plate 114, and capacitor posts 104. The fourth upper plate 112 and the seventh lower plate 113 are arranged opposite to each other, and the fourth upper plate 112 and the eighth lower plate 114 are arranged opposite to each other. A capacitor post 104 is provided between the seventh lower plate 113 and the fourth upper plate 112, and a capacitor post 104 is also provided between the eighth lower plate 114 and the fourth upper plate 112. A dielectric layer 105 is provided between the capacitor post 104 on the seventh lower plate 113 and the fourth upper plate 112, and a dielectric layer 105 is provided between the capacitor post 104 on the eighth lower plate 114 and the fourth upper plate 112, so as to achieve electrical isolation between the fourth upper plate 112 and the capacitor post 104, thereby achieving electrical isolation between the fourth upper plate 112 and the seventh lower plate 113, and electrical isolation between the fourth upper plate 112 and the seventh lower plate 113. The capacitance value of the fourth capacitor unit is equivalent to C4. The seventh lower plate 113 is the first end of the capacitor unit, and the eighth lower plate 114 is the second end of the capacitor unit. The first and second ends of the fourth capacitor unit are used for electrical connection with other components or pad structures.

[0074] In the above technical solution, four upper plates are set, and two lower plates are set opposite to each upper plate. Capacitor pillars 104 are set between the upper and lower plates to form four capacitor units. According to functional requirements, two capacitor units are connected with other components or pad structures to form a circuit structure with corresponding functions. The capacitor unit does not occupy the transistor area on the substrate 300, and the layout area of ​​the semiconductor structure can be fully utilized.

[0075] It should also be noted that a greater number of capacitor units can be placed below the pad structure, depending on the functional requirements of the semiconductor structure.

[0076] In one embodiment, the first upper electrode 101, the second upper electrode 106, the third upper electrode 109, and the fourth upper electrode 112 are located on the same metal layer, and are arranged in an array. Correspondingly, the first lower electrode 102, the second lower electrode 103, the third lower electrode 107, the fourth lower electrode 108, the fifth lower electrode 110, the sixth lower electrode 111, the seventh lower electrode 113, and the eighth lower electrode 114 are located on the same metal layer, and are arranged in an array from the first lower electrode 102 to the eighth lower electrode 114. This arrangement makes the electrode layout on the metal layer more uniform, reduces the fabrication difficulty of the semiconductor structure, and improves the yield of the semiconductor structure.

[0077] In one embodiment, the capacitor structure includes a first contact metal 121 and a second contact metal 122. The first contact metal 121 and the first lower electrode 102 are located on the same layer, and the second contact metal 122 and the first lower electrode 102 are located on the same layer. The first contact metal 121 is in contact with the first lower electrode 102 and also with a third lower electrode 107. The second contact metal 122 is in contact with a second lower electrode 103 and also with a fourth lower electrode 108. With this arrangement, the first capacitor unit and the second capacitor unit can be connected in parallel, and the equivalent capacitance value after parallel connection is C1+C2. When designing the layout of the metal blocks on the metal layer where the first contact metal 121 and the second contact metal 122 are located, the lower electrode and the contact metals can be considered simultaneously. When fabricating the semiconductor structure, the lower electrode and the contact metals can be fabricated in the same step, reducing the fabrication difficulty of the semiconductor structure.

[0078] The capacitor structure includes a third contact metal 123 and a fourth contact metal 124. The third contact metal 123 is located on the same layer as the first lower electrode plate 102, and the fourth contact metal 124 is also located on the same layer as the first lower electrode plate 102. The third contact metal 123 is in contact with the fifth lower electrode plate 110 and also with the seventh lower electrode plate 113. The fourth contact metal 124 is in contact with the sixth lower electrode plate 111 and also with the eighth lower electrode plate 114. This arrangement allows for the parallel connection of the third and fourth capacitor units, resulting in an equivalent capacitance of C3 + C4.

[0079] In one embodiment, the capacitor structure includes a fifth contact metal 125, a sixth contact metal 126, and a seventh contact metal 127. The fifth contact metal 125, sixth contact metal 126, and seventh contact metal 127 are located on the same metal layer as the first lower electrode plate 102. The fifth contact metal 125 is in contact with the second contact metal 122 and also with the third contact metal 123. The sixth contact metal 126 is in contact with the first contact metal 121 and is used to connect to the first power supply terminal VSS. The seventh contact metal 127 is in contact with the fourth contact metal 124 and is used to connect to the second power supply terminal VDD. With this configuration, the first and second capacitor units can be connected in parallel, and the third and fourth capacitor units can be connected in parallel and then in series. This allows for the connection of capacitors with a capacitance value of (C1+C2)(C3+C4) / (C1+C2+C3+C4) at both power supply terminals, thus meeting the power supply's capacitance requirements.

[0080] In one embodiment, the first contact metal 121, the second contact metal 122, the third contact metal 123, and the fourth contact metal 124 are arranged in an array. This arrangement makes the electrode layout on the metal layer more uniform, reduces the fabrication difficulty of the semiconductor structure, and improves the yield of the semiconductor structure.

[0081] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0082] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, pad structure, and capacitor structure; The substrate has multiple metal layers arranged from top to bottom. The pad structure is located on the top metal layer, and the capacitor structure is located in the metal layer below the top metal layer, and the capacitor structure is located below the pad structure. The capacitor structure includes: a first upper electrode plate, a first lower electrode plate, a second lower electrode plate, a capacitor pillar, and a dielectric layer. Wherein, the first upper electrode plate and the first lower electrode plate are arranged opposite to each other, and the first upper electrode plate and the second lower electrode plate are arranged opposite to each other; The capacitor structure comprises multiple capacitor pillars, each of which has a dielectric layer between it and the first upper electrode plate; the capacitor pillar is located between the first lower electrode plate and the first upper electrode plate, and the capacitor pillar is also located between the second lower electrode plate and the first upper electrode plate; the projection of the first upper electrode plate on the substrate is located inside the projection of the pad structure on the substrate; the capacitor structure further includes a second upper electrode plate; the capacitor structure further includes a third lower electrode plate and a fourth lower electrode plate; The second upper electrode plate and the third lower electrode plate are arranged opposite to each other, and the second upper electrode plate and the fourth lower electrode plate are arranged opposite to each other; The capacitor post is provided between the third lower electrode plate and the second upper electrode plate, and the capacitor post is also provided between the fourth lower electrode plate and the second upper electrode plate; the capacitor structure also includes a third upper electrode plate and a fourth upper electrode plate; the capacitor structure also includes a fifth lower electrode plate, a sixth lower electrode plate, a seventh lower electrode plate and an eighth lower electrode plate; The third upper electrode plate and the fifth lower electrode plate are arranged opposite to each other, and the third upper electrode plate and the sixth lower electrode plate are arranged opposite to each other; the capacitor post is provided between the fifth lower electrode plate and the third upper electrode plate, and the capacitor post is also provided between the sixth lower electrode plate and the third upper electrode plate; The fourth upper electrode plate and the seventh lower electrode plate are arranged opposite to each other, and the fourth upper electrode plate and the eighth lower electrode plate are arranged opposite to each other; the capacitor column is provided between the seventh lower electrode plate and the fourth upper electrode plate, and the capacitor column is also provided between the eighth lower electrode plate and the fourth upper electrode plate; the first upper electrode plate, the second upper electrode plate, the third upper electrode plate and the fourth upper electrode plate are located in the same metal layer and are arranged in an array; The first lower electrode plate, the second lower electrode plate, the third lower electrode plate, the fourth lower electrode plate, the fifth lower electrode plate, the sixth lower electrode plate, the seventh lower electrode plate, and the eighth lower electrode plate are located in the same metal layer and are arranged in an array; the capacitor structure also includes a first contact metal and a second contact metal. The first contact metal is located in the same layer as the first lower electrode plate; the second contact metal is located in the same layer as the first lower electrode plate. The first contact metal is in contact with the first lower electrode plate, and the first contact metal is also in contact with the third lower electrode plate; the second contact metal is in contact with the second lower electrode plate, and the second contact metal is also in contact with the fourth lower electrode plate.

2. The semiconductor structure according to claim 1, characterized in that, The number of capacitor pillars located between the first lower electrode plate and the first upper electrode plate is equal to the number of capacitor pillars located between the second lower electrode plate and the first upper electrode plate.

3. The semiconductor structure according to claim 2, characterized in that, The first upper electrode plate is provided with a plurality of electrode holes, and each electrode hole contains a capacitor post, with the dielectric layer located between the electrode hole and the capacitor post.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The first lower electrode plate and the second lower electrode plate are located in the same metal layer, and the first lower electrode plate and the second lower electrode plate are arranged at intervals.

5. The semiconductor structure according to claim 1, characterized in that, The first upper electrode and the second upper electrode are located in the same metal layer and are arranged in an array; The first lower electrode plate, the second lower electrode plate, the third lower electrode plate, and the fourth lower electrode plate are located in the same metal layer and are arranged in an array.

6. The semiconductor structure according to claim 1, characterized in that, The projection of the second upper electrode on the substrate is located inside the projection of the pad structure on the substrate.

7. The semiconductor structure according to claim 1, characterized in that, The capacitor structure also includes a third contact metal and a fourth contact metal; The third contact metal is located on the same layer as the first lower electrode plate; the fourth contact metal is located on the same layer as the first lower electrode plate; The third contact metal is in contact with the fifth lower electrode plate, and the third contact metal is also in contact with the seventh lower electrode plate; the fourth contact metal is in contact with the sixth lower electrode plate, and the fourth contact metal is also in contact with the eighth lower electrode plate.

8. The semiconductor structure according to claim 7, characterized in that, The capacitor structure also includes a fifth contact metal; The fifth contact metal is located in the same metal layer as the first lower electrode plate, the fifth contact metal is in contact with the second contact metal, and the fifth contact metal is also in contact with the third contact metal; The capacitor structure further includes a sixth contact metal and a seventh contact metal; the sixth contact metal is in contact with the first contact metal and is used to connect to the first power supply terminal; the seventh contact metal is in contact with the fourth contact metal and is used to connect to the second power supply terminal.

9. The semiconductor structure according to claim 8, characterized in that, The first contact metal, the second contact metal, the third contact metal, and the fourth contact metal are arranged in an array.

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